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Notes For V3.5-0

Browse Source 
The source set has been extensively overhauled.  For correct
viewing, set Visual C++ or Emacs to have tab stops every 4
characters.

1. New Features in 3.4-1

1.1 All Ethernet devices

- Added Windows user-defined adapter names (from Timothe Litt)

1.2 Interdata, SDS, HP, PDP-8, PDP-18b terminal multiplexors

- Added support for SET <unit>n DISCONNECT

1.3 VAX

- Added latent QDSS support
- Revised autoconfigure to handle QDSS

1.4 PDP-11

- Revised autoconfigure to handle more casees

2. Bugs Fixed in 3.4-1

2.1 SCP and libraries

- Trim trailing spaces on all input (for example, attach file names)
- Fixed sim_sock spurious SIGPIPE error in Unix/Linux
- Fixed sim_tape misallocation of TPC map array for 64b simulators

2.2 1401

- Fixed bug, CPU reset was clearing SSB through SSG

2.3 PDP-11

- Fixed bug in VH vector display routine
- Fixed XU runt packet processing (found by Tim Chapman)

2.4 Interdata

- Fixed bug in SHOW PAS CONN/STATS
- Fixed potential integer overflow exception in divide

2.5 SDS

- Fixed bug in SHOW MUX CONN/STATS

2.6 HP

- Fixed bug in SHOW MUX CONN/STATS

2.7 PDP-8

- Fixed bug in SHOW TTIX CONN/STATS
- Fixed bug in SET/SHOW TTOXn LOG

2.8 PDP-18b

- Fixed bug in SHOW TTIX CONN/STATS
- Fixed bug in SET/SHOW TTOXn LOG

2.9 Nova, Eclipse

- Fixed potential integer overflow exception in divide
This commit is contained in:
Bob Supnik
2005-09-09 18:09:00 -07:00
committed by Mark Pizzolato
parent ec60bbf329
commit b7c1eae41f
257 changed files with 107140 additions and 97195 deletions
Download Patch File Download Diff File Expand all files Collapse all files

262
PDP11/pdp11_pclk.c
View File

@@ -1,6 +1,6 @@
/* pdp11_pclk.c: KW11P programmable clock simulator
Copyright (c) 1993-2004, Robert M Supnik
Copyright (c) 1993-2005, Robert M Supnik
Written by John Dundas, used with his gracious permission
Permission is hereby granted, free of charge, to any person obtaining a
@@ -20,24 +20,25 @@
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
Except as contained in this notice, the name of Robert M Supnik shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
pclk KW11P line frequency clock
*/
pclk KW11P line frequency clock
/* KW11-P Programmable Clock
07-Jul-05 RMS Removed extraneous externs
KW11-P Programmable Clock
I/O Page Registers:
CSR 17 772 540
CSB 17 772 542
CNT 17 772 544
CSR 17 772 540
CSB 17 772 542
CNT 17 772 544
Vector: 0104
Vector: 0104
Priority: BR6
Priority: BR6
** Theory of Operation **
@@ -59,11 +60,11 @@
as well as the desired clock ticking rate. Possible rates are
given in the table below.
Rate Bit 2 Bit 1
100 kHz 0 0
10 kHz 0 1
Line frequency 1 0
External 1 1
Rate Bit 2 Bit 1
100 kHz 0 0
10 kHz 0 1
Line frequency 1 0
External 1 1
I think SIMH would have a hard time actually keeping up with a 100
kHz ticking rate. I haven't tried this to verify, though.
@@ -107,32 +108,31 @@
#include "pdp11_defs.h"
#define PCLKCSR_RDMASK 0100377 /* readable */
#define PCLKCSR_WRMASK 0000137 /* writeable */
#define PCLKCSR_RDMASK 0100377 /* readable */
#define PCLKCSR_WRMASK 0000137 /* writeable */
#define UNIT_V_LINE50HZ (UNIT_V_UF + 0)
#define UNIT_LINE50HZ (1 << UNIT_V_LINE50HZ)
#define UNIT_V_LINE50HZ (UNIT_V_UF + 0)
#define UNIT_LINE50HZ (1 << UNIT_V_LINE50HZ)
/* CSR - 17772540 */
#define CSR_V_FIX 5 /* single tick */
#define CSR_V_UPDN 4 /* down/up */
#define CSR_V_MODE 3 /* single/repeat */
#define CSR_FIX (1u << CSR_V_FIX)
#define CSR_UPDN (1u << CSR_V_UPDN)
#define CSR_MODE (1u << CSR_V_MODE)
#define CSR_V_RATE 1 /* rate */
#define CSR_M_RATE 03
#define CSR_GETRATE(x) (((x) >> CSR_V_RATE) & CSR_M_RATE)
#define CSR_V_FIX 5 /* single tick */
#define CSR_V_UPDN 4 /* down/up */
#define CSR_V_MODE 3 /* single/repeat */
#define CSR_FIX (1u << CSR_V_FIX)
#define CSR_UPDN (1u << CSR_V_UPDN)
#define CSR_MODE (1u << CSR_V_MODE)
#define CSR_V_RATE 1 /* rate */
#define CSR_M_RATE 03
#define CSR_GETRATE(x) (((x) >> CSR_V_RATE) & CSR_M_RATE)
extern int32 int_req[IPL_HLVL];
extern int32 int_vec[IPL_HLVL][32];
uint32 pclk_csr = 0; /* control/status */
uint32 pclk_csb = 0; /* count set buffer */
uint32 pclk_ctr = 0; /* counter */
static uint32 rate[4] = { 100000, 10000, 60, 10 }; /* ticks per second */
static uint32 xtim[4] = { 10, 100, 16000, 100000 }; /* nominal time delay */
uint32 pclk_csr = 0; /* control/status */
uint32 pclk_csb = 0; /* count set buffer */
uint32 pclk_ctr = 0; /* counter */
static uint32 rate[4] = { 100000, 10000, 60, 10 }; /* ticks per second */
static uint32 xtim[4] = { 10, 100, 16000, 100000 }; /* nominal time delay */
DEVICE pclk_dev;
t_stat pclk_rd (int32 *data, int32 PA, int32 access);
@@ -141,69 +141,79 @@ t_stat pclk_svc (UNIT *uptr);
t_stat pclk_reset (DEVICE *dptr);
t_stat pclk_set_line (UNIT *uptr, int32 val, char *cptr, void *desc);
void pclk_tick (void);
/* PCLK data structures
pclk_dev PCLK device descriptor
pclk_unit PCLK unit descriptor
pclk_reg PCLK register list
pclk_dev PCLK device descriptor
pclk_unit PCLK unit descriptor
pclk_reg PCLK register list
*/
DIB pclk_dib = { IOBA_PCLK, IOLN_PCLK, &pclk_rd, &pclk_wr,
1, IVCL (PCLK), VEC_PCLK, { NULL } };
DIB pclk_dib = {
IOBA_PCLK, IOLN_PCLK, &pclk_rd, &pclk_wr,
1, IVCL (PCLK), VEC_PCLK, { NULL }
};
UNIT pclk_unit = { UDATA (&pclk_svc, 0, 0) };
REG pclk_reg[] = {
{ ORDATA (CSR, pclk_csr, 16) },
{ ORDATA (CSB, pclk_csb, 16) },
{ ORDATA (CNT, pclk_ctr, 16) },
{ FLDATA (INT, IREQ (PCLK), INT_V_PCLK) },
{ FLDATA (OVFL, pclk_csr, CSR_V_ERR) },
{ FLDATA (DONE, pclk_csr, CSR_V_DONE) },
{ FLDATA (IE, pclk_csr, CSR_V_IE) },
{ FLDATA (UPDN, pclk_csr, CSR_V_UPDN) },
{ FLDATA (MODE, pclk_csr, CSR_V_MODE) },
{ FLDATA (RUN, pclk_csr, CSR_V_GO) },
{ BRDATA (TIME, xtim, 10, 32, 4), REG_NZ + PV_LEFT },
{ BRDATA (TPS, rate, 10, 32, 4), REG_NZ + PV_LEFT },
{ DRDATA (CURTIM, pclk_unit.wait, 32), REG_HRO },
{ ORDATA (DEVADDR, pclk_dib.ba, 32), REG_HRO },
{ ORDATA (DEVVEC, pclk_dib.vec, 16), REG_HRO },
{ NULL } };
{ ORDATA (CSR, pclk_csr, 16) },
{ ORDATA (CSB, pclk_csb, 16) },
{ ORDATA (CNT, pclk_ctr, 16) },
{ FLDATA (INT, IREQ (PCLK), INT_V_PCLK) },
{ FLDATA (OVFL, pclk_csr, CSR_V_ERR) },
{ FLDATA (DONE, pclk_csr, CSR_V_DONE) },
{ FLDATA (IE, pclk_csr, CSR_V_IE) },
{ FLDATA (UPDN, pclk_csr, CSR_V_UPDN) },
{ FLDATA (MODE, pclk_csr, CSR_V_MODE) },
{ FLDATA (RUN, pclk_csr, CSR_V_GO) },
{ BRDATA (TIME, xtim, 10, 32, 4), REG_NZ + PV_LEFT },
{ BRDATA (TPS, rate, 10, 32, 4), REG_NZ + PV_LEFT },
{ DRDATA (CURTIM, pclk_unit.wait, 32), REG_HRO },
{ ORDATA (DEVADDR, pclk_dib.ba, 32), REG_HRO },
{ ORDATA (DEVVEC, pclk_dib.vec, 16), REG_HRO },
{ NULL }
};
MTAB pclk_mod[] = {
{ UNIT_LINE50HZ, UNIT_LINE50HZ, "50 Hz", "50HZ", &pclk_set_line },
{ UNIT_LINE50HZ, 0, "60 Hz", "60HZ", &pclk_set_line },
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
NULL, &show_addr, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
&set_vec, &show_vec, NULL },
{ 0 } };
{ UNIT_LINE50HZ, UNIT_LINE50HZ, "50 Hz", "50HZ", &pclk_set_line },
{ UNIT_LINE50HZ, 0, "60 Hz", "60HZ", &pclk_set_line },
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
NULL, &show_addr, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
&set_vec, &show_vec, NULL },
{ 0 }
};
DEVICE pclk_dev = {
"PCLK", &pclk_unit, pclk_reg, pclk_mod,
1, 0, 0, 0, 0, 0,
NULL, NULL, &pclk_reset,
NULL, NULL, NULL,
&pclk_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS };
"PCLK", &pclk_unit, pclk_reg, pclk_mod,
1, 0, 0, 0, 0, 0,
NULL, NULL, &pclk_reset,
NULL, NULL, NULL,
&pclk_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS
};
/* Clock I/O address routines */
t_stat pclk_rd (int32 *data, int32 PA, int32 access)
{
switch ((PA >> 1) & 03) {
case 00: /* CSR */
*data = pclk_csr & PCLKCSR_RDMASK; /* return CSR */
pclk_csr = pclk_csr & ~(CSR_ERR | CSR_DONE); /* clr err, done */
CLR_INT (PCLK); /* clr intr */
break;
case 01: /* buffer */
*data = 0; /* read only */
break;
case 02: /* counter */
*data = pclk_ctr & DMASK; /* return counter */
break; }
case 00: /* CSR */
*data = pclk_csr & PCLKCSR_RDMASK; /* return CSR */
pclk_csr = pclk_csr & ~(CSR_ERR | CSR_DONE); /* clr err, done */
CLR_INT (PCLK); /* clr intr */
break;
case 01: /* buffer */
*data = 0; /* read only */
break;
case 02: /* counter */
*data = pclk_ctr & DMASK; /* return counter */
break;
}
return SCPE_OK;
}
@@ -213,28 +223,34 @@ int32 old_csr = pclk_csr;
int32 rv;
switch ((PA >> 1) & 03) {
case 00: /* CSR */
pclk_csr = data & PCLKCSR_WRMASK; /* clear and write */
CLR_INT (PCLK); /* clr intr */
rv = CSR_GETRATE (pclk_csr); /* new rate */
pclk_unit.wait = xtim[rv]; /* new delay */
if ((pclk_csr & CSR_GO) == 0) { /* stopped? */
sim_cancel (&pclk_unit); /* cancel */
if (data & CSR_FIX) pclk_tick (); } /* fix? tick */
else if (((old_csr & CSR_GO) == 0) || /* run 0 -> 1? */
(rv != CSR_GETRATE (old_csr))) { /* rate change? */
sim_cancel (&pclk_unit); /* cancel */
sim_activate (&pclk_unit, /* start clock */
sim_rtcn_init (pclk_unit.wait, TMR_PCLK));
}
break;
case 01: /* buffer */
pclk_csb = pclk_ctr = data; /* store ctr */
pclk_csr = pclk_csr & ~(CSR_ERR | CSR_DONE); /* clr err, done */
CLR_INT (PCLK); /* clr intr */
break;
case 02: /* counter */
break; } /* read only */
case 00: /* CSR */
pclk_csr = data & PCLKCSR_WRMASK; /* clear and write */
CLR_INT (PCLK); /* clr intr */
rv = CSR_GETRATE (pclk_csr); /* new rate */
pclk_unit.wait = xtim[rv]; /* new delay */
if ((pclk_csr & CSR_GO) == 0) { /* stopped? */
sim_cancel (&pclk_unit); /* cancel */
if (data & CSR_FIX) pclk_tick (); /* fix? tick */
}
else if (((old_csr & CSR_GO) == 0) || /* run 0 -> 1? */
(rv != CSR_GETRATE (old_csr))) { /* rate change? */
sim_cancel (&pclk_unit); /* cancel */
sim_activate (&pclk_unit, /* start clock */
sim_rtcn_init (pclk_unit.wait, TMR_PCLK));
}
break;
case 01: /* buffer */
pclk_csb = pclk_ctr = data; /* store ctr */
pclk_csr = pclk_csr & ~(CSR_ERR | CSR_DONE); /* clr err, done */
CLR_INT (PCLK); /* clr intr */
break;
case 02: /* counter */
break; /* read only */
}
return SCPE_OK;
}
@@ -242,18 +258,20 @@ return SCPE_OK;
void pclk_tick (void)
{
if (pclk_csr & CSR_UPDN) /* up or down? */
pclk_ctr = (pclk_ctr + 1) & DMASK; /* 1 = up */
else pclk_ctr = (pclk_ctr - 1) & DMASK; /* 0 = down */
if (pclk_ctr == 0) { /* reached zero? */
if (pclk_csr & CSR_DONE) /* done already set? */
pclk_csr = pclk_csr | CSR_ERR; /* set error */
else pclk_csr = pclk_csr | CSR_DONE; /* else set done */
if (pclk_csr & CSR_IE) SET_INT (PCLK); /* if IE, set int */
if (pclk_csr & CSR_MODE) pclk_ctr = pclk_csb; /* if rpt, reload */
else {
pclk_csb = 0; /* else clr ctr */
pclk_csr = pclk_csr & ~CSR_GO; } } /* and clr go */
if (pclk_csr & CSR_UPDN) /* up or down? */
pclk_ctr = (pclk_ctr + 1) & DMASK; /* 1 = up */
else pclk_ctr = (pclk_ctr - 1) & DMASK; /* 0 = down */
if (pclk_ctr == 0) { /* reached zero? */
if (pclk_csr & CSR_DONE) /* done already set? */
pclk_csr = pclk_csr | CSR_ERR; /* set error */
else pclk_csr = pclk_csr | CSR_DONE; /* else set done */
if (pclk_csr & CSR_IE) SET_INT (PCLK); /* if IE, set int */
if (pclk_csr & CSR_MODE) pclk_ctr = pclk_csb; /* if rpt, reload */
else {
pclk_csb = 0; /* else clr ctr */
pclk_csr = pclk_csr & ~CSR_GO; /* and clr go */
}
}
return;
}
@@ -263,9 +281,9 @@ t_stat pclk_svc (UNIT *uptr)
{
int32 rv;
pclk_tick (); /* tick clock */
if ((pclk_csr & CSR_GO) == 0) return SCPE_OK; /* done? */
rv = CSR_GETRATE (pclk_csr); /* get rate */
pclk_tick (); /* tick clock */
if ((pclk_csr & CSR_GO) == 0) return SCPE_OK; /* done? */
rv = CSR_GETRATE (pclk_csr); /* get rate */
sim_activate (&pclk_unit, sim_rtcn_calb (rate[rv], TMR_PCLK));
return SCPE_OK;
}
@@ -274,12 +292,12 @@ return SCPE_OK;
t_stat pclk_reset (DEVICE *dptr)
{
pclk_csr = 0; /* clear reg */
pclk_csr = 0; /* clear reg */
pclk_csb = 0;
pclk_ctr = 0;
CLR_INT (PCLK); /* clear int */
sim_cancel (&pclk_unit); /* cancel */
pclk_unit.wait = xtim[0]; /* reset delay */
CLR_INT (PCLK); /* clear int */
sim_cancel (&pclk_unit); /* cancel */
pclk_unit.wait = xtim[0]; /* reset delay */
return SCPE_OK;
}