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PDP8/PDP11/VAX: Support high speed character input on console and other multiplexer ports instead of limiting input data rate to 1 character per clock tick.

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This commit is contained in:
Mark Pizzolato
2013-10-23 07:50:39 -07:00
parent c8ae76cb65
commit be46bac750
12 changed files with 39 additions and 48 deletions
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3
VAX/vax610_stddev.c
View File

@@ -107,7 +107,7 @@ extern int32 con_halt (int32 code, int32 cc);
DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT };
REG tti_reg[] = {
{ HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") },
@@ -238,6 +238,7 @@ int32 t = tti_unit.buf; /* char + error */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_unit.buf = tti_unit.buf & 0377; /* clr errors */
CLR_INT (TTI);
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
return t;
}

3
VAX/vax630_stddev.c
View File

@@ -82,7 +82,7 @@ extern int32 sysd_hlt_enb (void);
DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT };
REG tti_reg[] = {
{ HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") },
@@ -214,6 +214,7 @@ int32 t = tti_unit.buf; /* char + error */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_unit.buf = tti_unit.buf & 0377; /* clr errors */
CLR_INT (TTI);
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
return t;
}

3
VAX/vax730_stddev.c
View File

@@ -243,7 +243,7 @@ t_bool td_test_xfr (UNIT *uptr, int32 state);
tti_reg TTI register list
*/
UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT };
REG tti_reg[] = {
{ HRDATAD (RXDB, tti_buf, 16, "last data item processed") },
@@ -629,6 +629,7 @@ int32 t = tti_buf; /* char + error */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_buf = tti_buf & BMASK; /* clr errors */
tti_int = 0;
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
return t;
}

3
VAX/vax750_stddev.c
View File

@@ -243,7 +243,7 @@ extern int32 con_halt (int32 code, int32 cc);
tti_reg TTI register list
*/
UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT };
REG tti_reg[] = {
{ HRDATAD (RXDB, tti_buf, 16, "last data item processed") },
@@ -622,6 +622,7 @@ int32 t = tti_buf; /* char + error */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_buf = tti_buf & BMASK; /* clr errors */
tti_int = 0;
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
return t;
}

3
VAX/vax780_stddev.c
View File

@@ -259,7 +259,7 @@ extern int32 con_halt (int32 code, int32 cc);
tti_reg TTI register list
*/
UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT };
REG tti_reg[] = {
{ HRDATAD (RXDB, tti_buf, 16, "last data item processed") },
@@ -443,6 +443,7 @@ int32 t = tti_buf; /* char + error */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_buf = tti_buf & BMASK; /* clr errors */
tti_int = 0;
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
return t;
}

8
VAX/vax860_stddev.c
View File

@@ -274,10 +274,10 @@ extern int32 con_halt (int32 code, int32 cc);
*/
UNIT tti_unit[] = {
{ UDATA (&tti_svc, TT_MODE_8B, 0), 0 },
{ UDATA (&tti_svc, TT_MODE_8B, 0), 0 },
{ UDATA (&tti_svc, TT_MODE_8B, 0), 0 },
{ UDATA (&tti_svc, TT_MODE_8B, 0), 0 },
{ UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 },
{ UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 },
{ UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 },
{ UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 },
};
REG tti_reg[] = {

3
VAX/vax_stddev.c
View File

@@ -139,7 +139,7 @@ extern int32 fault_PC;
DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT };
REG tti_reg[] = {
{ HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") },
@@ -277,6 +277,7 @@ int32 t = tti_unit.buf; /* char + error */
tti_csr = tti_csr & ~CSR_DONE; /* clr done */
tti_unit.buf = tti_unit.buf & 0377; /* clr errors */
CLR_INT (TTI);
sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */
return t;
}