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ISYS8024, ISYS8030: Add initial new simulators
This commit is contained in:
Bill Beech
@@ -1,161 +0,0 @@
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/* iSBC80-30.c: Intel iSBC 80/30 Processor simulator
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Copyright (c) 2010, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of William A. Beech shall not be
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from William A. Beech.
|
||||
|
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This software was written by Bill Beech, Dec 2010, to allow emulation of Multibus
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Computer Systems.
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?? ??? 10 - Original file.
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17 May 16 - Modified for the iSBC 80/30 Processor Card.
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*/
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#include "system_defs.h"
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/* set the base I/O address for the 8259 */
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#define I8259_BASE 0xD8
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#define I8259_NUM 1
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/* set the base I/O address for the 8253 */
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#define I8253_BASE 0xDC
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#define I8253_NUM 1
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/* set the base I/O address for the 8255 */
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#define I8255_BASE_0 0xE4
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#define I8255_BASE_1 0xE8
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#define I8255_NUM 2
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/* set the base I/O address for the 8251 */
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#define I8251_BASE 0xEC
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#define I8251_NUM 1
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/* set the base and size for the EPROM */
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#define ROM_BASE 0x0000
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#define ROM_SIZE 0x1000
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/* set the base and size for the RAM */
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#define RAM_BASE 0x4000
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#define RAM_SIZE 0x2000
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/* set INTR for CPU */
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#define INTR INT_1
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/* function prototypes */
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uint16 get_mbyte(uint16 addr);
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uint8 get_mword(uint16 addr);
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void put_mbyte(uint16 addr, uint8 val);
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void put_mword(uint16 addr, uint16 val);
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t_stat i80_10_reset (DEVICE *dptr);
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/* external function prototypes */
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extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8085 emulator */
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extern int32 multibus_get_mbyte(uint16 addr);
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extern void multibus_put_mbyte(uint16 addr, uint8 val);
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extern int32 EPROM_get_mbyte(uint16 addr);
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extern int32 RAM_get_mbyte(uint16 addr);
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extern void RAM_put_mbyte(uint16, uint8 val);
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extern UNIT i8251_unit;
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extern UNIT i8253_unit;
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extern UNIT i8255_unit;
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extern UNIT i8259_unit;
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extern UNIT EPROM_unit;
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extern UNIT RAM_unit;
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extern t_stat i8259_reset (DEVICE *dptr, uint16 base);
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extern t_stat i8253_reset (DEVICE *dptr, uint16 base);
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extern t_stat i8255_reset (DEVICE *dptr, uint16 base);
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extern t_stat i8251_reset (DEVICE *dptr, uint16 base);
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extern t_stat pata_reset (DEVICE *dptr, uint16 base);
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extern t_stat EPROM_reset (DEVICE *dptr, uint16 size);
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extern t_stat RAM_reset (DEVICE *dptr, uint16 base, uint16 size);
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/* CPU reset routine
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put here to cause a reset of the entire iSBC system */
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t_stat SBC_reset (DEVICE *dptr)
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{
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sim_printf("Initializing iSBC-80/30\n");
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i8080_reset(NULL);
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i8259_reset(NULL, I8259_BASE);
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i8253_reset(NULL, I8253_BASE);
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i8255_reset(NULL, I8255_BASE_0);
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i8255_reset(NULL, I8255_BASE_1);
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i8251_reset(NULL, I8251_BASE);
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EPROM_reset(NULL, ROM_SIZE);
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RAM_reset(NULL, RAM_BASE, RAM_SIZE);
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return SCPE_OK;
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}
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/* get a byte from memory - handle RAM, ROM and Multibus memory */
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uint8 get_mbyte(uint16 addr)
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{
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int32 val, org, len;
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/* if local EPROM handle it */
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if ((i8255_unit.u6 & 0x01) && (addr >= EPROM_unit.u3) && (addr < (EPROM_unit.u3 + EPROM_unit.capac))) {
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return EPROM_get_mbyte(addr);
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} /* if local RAM handle it */
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if ((i8255_unit.u6 & 0x02) && (addr >= RAM_unit.u3) && (addr < (RAM_unit.u3 + RAM_unit.capac))) {
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return RAM_get_mbyte(addr);
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} /* otherwise, try the multibus */
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return multibus_get_mbyte(addr);
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}
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/* get a word from memory */
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uint16 get_mword(uint16 addr)
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{
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int32 val;
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val = get_mbyte(addr);
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val |= (get_mbyte(addr+1) << 8);
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return val;
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}
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/* put a byte to memory - handle RAM, ROM and Multibus memory */
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void put_mbyte(uint16 addr, uint8 val)
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{
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/* if local EPROM handle it */
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if ((i8255_unit.u6 & 0x01) && (addr >= EPROM_unit.u3) && (addr <= (EPROM_unit.u3 + EPROM_unit.capac))) {
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sim_printf("Write to R/O memory address %04X - ignored\n", addr);
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return;
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} /* if local RAM handle it */
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if ((i8255_unit.u6 & 0x02) && (addr >= RAM_unit.u3) && (addr <= (RAM_unit.u3 + RAM_unit.capac))) {
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RAM_put_mbyte(addr, val);
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return;
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} /* otherwise, try the multibus */
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multibus_put_mbyte(addr, val);
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}
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/* put a word to memory */
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void put_mword(uint16 addr, uint16 val)
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{
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put_mbyte(addr, val);
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put_mbyte(addr+1, val >> 8);
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}
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/* end of iSBC80-30.c */
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147
Intel-Systems/isys8030/isbc8030.c
Normal file
147
Intel-Systems/isys8030/isbc8030.c
Normal file
@@ -0,0 +1,147 @@
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/* iSBC80-30.c: Intel iSBC 80/30 Processor simulator
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Copyright (c) 2010, William A. Beech
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of William A. Beech shall not be
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from William A. Beech.
|
||||
|
||||
MODIFICATIONS:
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04 Nov 16 - Original file.
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NOTES:
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This software was written by Bill Beech, Nov 2016, to allow emulation of Multibus
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Computer Systems.
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||||
*/
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#include "system_defs.h"
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/* function prototypes */
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uint8 get_mbyte(uint16 addr);
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uint16 get_mword(uint16 addr);
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void put_mbyte(uint16 addr, uint8 val);
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void put_mword(uint16 addr, uint16 val);
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t_stat SBC_reset (DEVICE *dptr);
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/* external globals */
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extern uint8 i8255_C[4]; //port C byte I/O
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/* external function prototypes */
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extern uint8 multibus_get_mbyte(uint16 addr);
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extern void multibus_put_mbyte(uint16 addr, uint8 val);
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extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */
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extern int32 i8251_devnum;
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extern t_stat i8251_reset (DEVICE *dptr, uint16 base);
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extern int32 i8253_devnum;
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extern t_stat i8253_reset (DEVICE *dptr, uint16 base);
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extern int32 i8255_devnum;
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extern t_stat i8255_reset (DEVICE *dptr, uint16 base);
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extern int32 i8259_devnum;
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extern t_stat i8259_reset (DEVICE *dptr, uint16 base);
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extern uint8 EPROM_get_mbyte(uint16 addr);
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extern UNIT EPROM_unit;
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extern t_stat EPROM_reset (DEVICE *dptr, uint16 size);
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extern uint8 RAM_get_mbyte(uint16 addr);
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extern void RAM_put_mbyte(uint16 addr, uint8 val);
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extern UNIT RAM_unit;
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extern t_stat RAM_reset (DEVICE *dptr, uint16 base, uint16 size);
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/* SBC reset routine */
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t_stat SBC_reset (DEVICE *dptr)
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{
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sim_printf("Initializing iSBC-80/24:\n");
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i8080_reset (NULL);
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i8251_devnum = 0;
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i8251_reset (NULL, I8251_BASE);
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i8253_devnum = 0;
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i8253_reset (NULL, I8253_BASE);
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i8255_devnum = 0;
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i8255_reset (NULL, I8255_BASE);
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i8259_devnum = 0;
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i8259_reset (NULL, I8259_BASE);
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EPROM_reset (NULL, ROM_SIZE);
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RAM_reset (NULL, RAM_BASE, RAM_SIZE);
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return SCPE_OK;
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}
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/* get a byte from memory - handle RAM, ROM, I/O, and Multibus memory */
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uint8 get_mbyte(uint16 addr)
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{
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/* if local EPROM handle it */
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if ((ROM_DISABLE && (i8255_C[0] & 0x20)) || (ROM_DISABLE == 0)) { /* EPROM enabled */
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if ((addr >= EPROM_unit.u3) && ((uint16)addr < (EPROM_unit.u3 + EPROM_unit.capac))) {
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return EPROM_get_mbyte(addr);
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}
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} /* if local RAM handle it */
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if ((RAM_DISABLE && (i8255_C[0] & 0x10)) || (RAM_DISABLE == 0)) { /* RAM enabled */
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if ((addr >= RAM_unit.u3) && ((uint16)addr < (RAM_unit.u3 + RAM_unit.capac))) {
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return RAM_get_mbyte(addr);
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}
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} /* otherwise, try the multibus */
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return multibus_get_mbyte(addr);
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}
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/* get a word from memory */
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uint16 get_mword(uint16 addr)
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{
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uint16 val;
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val = get_mbyte(addr);
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val |= (get_mbyte(addr+1) << 8);
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return val;
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}
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/* put a byte to memory - handle RAM, ROM, I/O, and Multibus memory */
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void put_mbyte(uint16 addr, uint8 val)
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{
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/* if local EPROM handle it */
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if ((ROM_DISABLE && (i8255_C[0] & 0x20)) || (ROM_DISABLE == 0)) { /* EPROM enabled */
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if ((addr >= EPROM_unit.u3) && ((uint16)addr <= (EPROM_unit.u3 + EPROM_unit.capac))) {
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sim_printf("Write to R/O memory address %04X - ignored\n", addr);
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return;
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}
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} /* if local RAM handle it */
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if ((RAM_DISABLE && (i8255_C[0] & 0x10)) || (RAM_DISABLE == 0)) { /* RAM enabled */
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if ((addr >= RAM_unit.u3) && ((uint16)addr <= (RAM_unit.u3 + RAM_unit.capac))) {
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RAM_put_mbyte(addr, val);
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return;
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}
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} /* otherwise, try the multibus */
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multibus_put_mbyte(addr, val);
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}
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/* put a word to memory */
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void put_mword(uint16 addr, uint16 val)
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{
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put_mbyte(addr, val & 0xff);
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put_mbyte(addr+1, val >> 8);
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}
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/* end of iSBC80-30.c */
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@@ -1,41 +0,0 @@
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/* system_80_20_cfg.h: Intel System 80/20 simulator definitions
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This file holds the configuration for the System 80/20
|
||||
boards I/O and Memory.
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||||
|
||||
Copyright (c) 2010, William A. Beech
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of William A. Beech shall not be
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from William A. Beech.
|
||||
|
||||
16 Dec 12 - Original file
|
||||
*/
|
||||
|
||||
/* set the base I/O address for the iSBC 208 */
|
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#define SBC208_BASE 0x40
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|
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/* configure interrupt request line */
|
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#define SBC208_INT INT_1
|
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|
||||
/* set the base and size for the iSBC 064 */
|
||||
#define SBC064_BASE 0x0000
|
||||
#define SBC064_SIZE 0x10000
|
||||
|
||||
@@ -24,20 +24,21 @@
|
||||
in this Software without prior written authorization from William A. Beech.
|
||||
|
||||
?? ??? 10 - Original file.
|
||||
16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size.
|
||||
*/
|
||||
|
||||
#include "system_defs.h"
|
||||
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||||
extern DEVICE i8080_dev;
|
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extern REG i8080_reg[];
|
||||
extern DEVICE i8259_dev;
|
||||
extern DEVICE i8251_dev;
|
||||
extern DEVICE i8253_dev;
|
||||
extern DEVICE i8255_dev;
|
||||
extern DEVICE i8259_dev;
|
||||
extern DEVICE EPROM_dev;
|
||||
extern DEVICE RAM_dev;
|
||||
extern DEVICE multibus_dev;
|
||||
extern DEVICE isbc208_dev;
|
||||
extern DEVICE isbc201_dev;
|
||||
extern DEVICE isbc202_dev;
|
||||
extern DEVICE isbc064_dev;
|
||||
|
||||
/* SCP data structures
|
||||
@@ -49,7 +50,7 @@ extern DEVICE isbc064_dev;
|
||||
sim_stop_messages array of pointers to stop messages
|
||||
*/
|
||||
|
||||
char sim_name[] = "Intel System 80/20";
|
||||
char sim_name[] = "Intel System 80/10";
|
||||
|
||||
REG *sim_PC = &i8080_reg[0];
|
||||
|
||||
@@ -57,14 +58,16 @@ int32 sim_emax = 4;
|
||||
|
||||
DEVICE *sim_devices[] = {
|
||||
&i8080_dev,
|
||||
&i8251_dev,
|
||||
&i8253_dev,
|
||||
&i8255_dev,
|
||||
&i8259_dev,
|
||||
&EPROM_dev,
|
||||
&RAM_dev,
|
||||
&i8259_dev,
|
||||
&i8251_dev,
|
||||
&i8255_dev,
|
||||
&multibus_dev,
|
||||
&isbc064_dev,
|
||||
&isbc208_dev,
|
||||
&isbc201_dev,
|
||||
&isbc202_dev,
|
||||
NULL
|
||||
};
|
||||
|
||||
|
||||
@@ -24,14 +24,74 @@
|
||||
in this Software without prior written authorization from William A. Beech.
|
||||
|
||||
?? ??? 10 - Original file.
|
||||
16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <ctype.h>
|
||||
#include "isys8020_cfg.h" /* Intel System 80/20 configuration */
|
||||
#include "sim_defs.h" /* simulator defns */
|
||||
|
||||
#define SET_XACK(VAL) (xack = VAL)
|
||||
|
||||
//chip definitions for the iSBC-80/30
|
||||
/* set the base I/O address for the 8253/8254 */
|
||||
#define I8041_BASE 0xDC
|
||||
#define I8041_NUM 1
|
||||
|
||||
/* set the base I/O address and device count for the 8251s */
|
||||
#define I8251_BASE 0xEC
|
||||
#define I8251_NUM 1
|
||||
|
||||
/* set the base I/O address for the 8253/8254 */
|
||||
#define I8253_BASE 0xDC
|
||||
#define I8253_NUM 1
|
||||
|
||||
/* set the base I/O address and device count for the 8255s */
|
||||
#define I8255_BASE 0xE8
|
||||
#define I8255_NUM 1
|
||||
|
||||
/* set the base I/O address for the 8259 */
|
||||
#define I8259_BASE 0xDA
|
||||
#define I8259_NUM 1
|
||||
|
||||
/* set the base and size for the EPROM on the iSBC 80/30 */
|
||||
#define ROM_BASE 0x0000
|
||||
#define ROM_SIZE 0x1000
|
||||
#define ROM_DISABLE 1
|
||||
|
||||
/* set the base and size for the RAM on the iSBC 80/30 */
|
||||
#define RAM_BASE 0xF000
|
||||
#define RAM_SIZE 0x1000
|
||||
#define RAM_DISABLE 0
|
||||
|
||||
/* set INTR for CPU on the iSBC 80/30 */
|
||||
#define INTR INT_1
|
||||
|
||||
//board definitions for the multibus
|
||||
/* set the base I/O address for the iSBC 201 */
|
||||
#define SBC201_BASE 0x78
|
||||
#define SBC201_INT INT_1
|
||||
#define SBC201_NUM 0
|
||||
|
||||
/* set the base I/O address for the iSBC 202 */
|
||||
#define SBC202_BASE 0x78
|
||||
#define SBC202_INT INT_1
|
||||
#define SBC202_NUM 1
|
||||
|
||||
/* set the base for the zx-200a disk controller */
|
||||
#define ZX200A_BASE_DD 0x78
|
||||
#define ZX200A_BASE_SD 0x88
|
||||
#define ZX200A_NUM 0
|
||||
|
||||
/* set the base I/O address for the iSBC 208 */
|
||||
#define SBC208_BASE 0x40
|
||||
#define SBC208_INT INT_1
|
||||
#define SBC208_NUM 0
|
||||
|
||||
/* set the base and size for the iSBC 064 */
|
||||
#define SBC064_BASE 0x0000
|
||||
#define SBC064_SIZE 0x10000
|
||||
#define SBC064_NUM 1
|
||||
|
||||
/* multibus interrupt definitions */
|
||||
|
||||
#define INT_0 0x01
|
||||
|
||||
Reference in New Issue
Block a user