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mirror of https://github.com/simh/simh.git synced 2026-01-25 19:56:25 +00:00

PDP11: Improve idling.

This commit is contained in:
Lars Brinkhoff
2022-10-26 12:59:49 +02:00
committed by Mark Pizzolato
parent 64a9c021f3
commit da5e7f4769
4 changed files with 16 additions and 9 deletions

View File

@@ -157,7 +157,7 @@ DIB dci_dib = {
2, IVCL (DCI), VEC_AUTO, { &dci_iack, &dco_iack }, IOLN_DC,
};
UNIT dci_unit = { UDATA (&dci_svc, 0, 0), TMLN_SPD_9600_BPS };
UNIT dci_unit = { UDATA (&dci_svc, UNIT_IDLE, 0), TMLN_SPD_9600_BPS };
REG dci_reg[] = {
{ BRDATAD (BUF, dci_buf, DEV_RDX, 8, DCX_LINES, "input control/stats register") },

View File

@@ -81,8 +81,8 @@ DIB dh_dib = {
};
UNIT dh_unit[] = {
{ UDATA (&dh_input_svc, UNIT_ATTABLE, 0) },
{ UDATA (&dh_output_svc, UNIT_DIS, 0) }
{ UDATA (&dh_input_svc, UNIT_ATTABLE | UNIT_IDLE, 0) },
{ UDATA (&dh_output_svc, UNIT_DIS | UNIT_IDLE, 0) }
};
REG dh_reg[] = {

View File

@@ -58,7 +58,7 @@ DIB ng_dib = {
};
UNIT ng_unit = {
UDATA (&ng_svc, 0, 0), NG_DELAY
UDATA (&ng_svc, UNIT_IDLE, 0), NG_DELAY
};
REG ng_reg[] = {
@@ -131,8 +131,14 @@ t_stat
ng_wr(int32 data, int32 PA, int32 access)
{
switch (PA & 002) {
case 000: ng_set_csr(data); return SCPE_OK;
case 002: ng_set_reloc(data); return SCPE_OK;
case 000:
ng_set_csr(data);
if (data & 010000)
sim_activate (&ng_unit, 1);
return SCPE_OK;
case 002:
ng_set_reloc(data);
return SCPE_OK;
}
return SCPE_NXM;
}
@@ -183,7 +189,6 @@ ng_reset(DEVICE *dptr)
CLR_INT (NG);
ng_unit.wait = 100;
sim_activate (dptr->units, 1);
set_cmd (0, "DZ DISABLED"); /* Conflict with NG. */
set_cmd (0, "HK DISABLED"); /* Conflict with RF. */