Notes For V3.6-0

The save/restore format has been updated to improve its reliability.
As a result, save files prior to release 3.0 are no longer supported.

The text documentation files are obsolete and are no longer included
with the distribution.  Up-to-date PDF documentation files are
available on the SimH web site.

1. New Features

1.1 3.6-0

1.1.1 Most magnetic tapes

- Added support for limiting tape capacity to a particular size in MB

1.1.2 IBM 7090/7094

- First release

1.1.3 VAX-11/780

- Added FLOAD command, loads system file from console floppy disk

1.1.4 VAX, VAX-11/780, and PDP-11

- Added card reader support (from John Dundas)

1.1.5 PDP-11

- Added instruction history

2. Bugs Fixed

Please see the revision history on http://simh.trailing-edge.com or
in the source module sim_rev.h.

Interdata/id32_cpu.c

@@ -1,6 +1,6 @@
 /* id32_cpu.c: Interdata 32b CPU simulator
 
-   Copyright (c) 2000-2005, Robert M. Supnik
+   Copyright (c) 2000-2006, Robert M. Supnik
 
    Permission is hereby granted, free of charge, to any person obtaining a
    copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,8 @@
 
    cpu                  Interdata 32b CPU
 
+   09-Mar-06	RMS	Added 8 register bank support for 8/32
+   06-Feb-06    RMS     Fixed bug in DH (found by Mark Hittinger)
    22-Sep-05    RMS     Fixed declarations (from Sterling Garwood)
    16-Aug-05    RMS     Fixed C++ declaration and cast problems
    10-Mar-05    RMS     Fixed bug in initial memory allocation
@@ -156,7 +158,7 @@
 #define PCQ_MASK        (PCQ_SIZE - 1)
 #define PCQ_ENTRY       pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = oPC
 #define VAMASK          VAMASK32
-#define NRSETS          2                               /* 2 gen reg sets */
+#define NRSETS          8                               /* up to 8 reg sets */
 #define PSW_MASK        PSW_x32
 #define ABORT(val)      longjmp (save_env, (val))
 #define MPRO            (-1)
@@ -164,9 +166,11 @@
 #define UNIT_V_MSIZE    (UNIT_V_UF + 0)                 /* dummy mask */
 #define UNIT_V_DPFP     (UNIT_V_UF + 1)
 #define UNIT_V_832      (UNIT_V_UF + 2)
+#define UNIT_V_8RS      (UNIT_V_UF + 3)
 #define UNIT_MSIZE      (1 << UNIT_V_MSIZE)
 #define UNIT_DPFP       (1 << UNIT_V_DPFP)
 #define UNIT_832        (1 << UNIT_V_832)
+#define UNIT_8RS        (1 << UNIT_V_8RS)
 #define UNIT_TYPE       (UNIT_DPFP | UNIT_832)
 
 #define HIST_PC         0x40000000
@@ -183,6 +187,7 @@ typedef struct {
     uint32              opnd;
     } InstHistory;
 
+#define PSW_GETREG(x)   (((x) >> PSW_V_REG) & psw_reg_mask)
 #define SEXT32(x)       (((x) & SIGN32)? ((int32) ((x) | ~0x7FFFFFFF)): \
                         ((int32) ((x) & 0x7FFFFFFF)))
 #define SEXT16(x)       (((x) & SIGN16)? ((int32) ((x) | ~0x7FFF)): \
@@ -235,6 +240,7 @@ uint32 fp_in_hwre = 0;                                  /* ucode vs hwre fp */
 uint32 pawidth = PAWIDTH32;                             /* addr mask */
 uint32 hst_p = 0;                                       /* history pointer */
 uint32 hst_lnt = 0;                                     /* history length */
+uint32 psw_reg_mask = 1;                                /* PSW reg mask */
 InstHistory *hst = NULL;                                /* instruction history */
 jmp_buf save_env;                                       /* abort handler */
 struct BlockIO blk_io;                                  /* block I/O status */
@@ -565,10 +571,14 @@ MTAB cpu_mod[] = {
     { UNIT_MSIZE, 262144, NULL, "256K", &cpu_set_size },
     { UNIT_MSIZE, 524288, NULL, "512K", &cpu_set_size },
     { UNIT_MSIZE, 1048756, NULL, "1M", &cpu_set_size },
-    { UNIT_TYPE, 0, "7/32, single precision fp", "732", NULL },
+    { UNIT_8RS|UNIT_TYPE, 0, NULL, "732", NULL },
     { UNIT_DPFP, UNIT_DPFP, NULL, "DPFP", NULL },
+    { UNIT_TYPE, 0, "7/32, single precision fp", "732", NULL },
     { UNIT_TYPE, UNIT_DPFP, "7/32, double precision fp", NULL, NULL },
-    { UNIT_TYPE, UNIT_DPFP | UNIT_832, "8/32", "832", NULL },
+    { UNIT_8RS|UNIT_TYPE, UNIT_8RS|UNIT_DPFP|UNIT_832, NULL, "832", NULL },
+    { UNIT_8RS, 0, NULL, "2RS", NULL },
+    { UNIT_8RS|UNIT_TYPE, UNIT_8RS|UNIT_DPFP|UNIT_832, "832, 8 register sets", NULL, NULL },
+    { UNIT_8RS|UNIT_TYPE, UNIT_DPFP|UNIT_832, "832, 2 register sets", NULL, NULL },
     { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, NULL, "CONSINT",
       &cpu_set_consint, NULL, NULL },
     { MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY",
@@ -608,6 +618,8 @@ else {
     fp_in_hwre = 0;                                     /* fp in ucode */
     dec_flgs = OP_DPF;                                  /* sp only */
     }
+if (cpu_unit.flags & UNIT_8RS) psw_reg_mask = 7;        /* 8 register sets */
+else psw_reg_mask = 1;                                  /* 2 register sets */
 int_eval ();                                            /* eval interrupts */
 cc = newPSW (PSW & PSW_MASK);                           /* split PSW, eval wait */
 sim_rtcn_init (lfc_unit.wait, TMR_LFC);                 /* init clock */
@@ -1223,7 +1235,7 @@ while (reason == 0) {                                   /* loop until halted */
     case 0x4D:                                          /* DH - RXH */
         opnd = opnd & DMASK16;                          /* force HW opnd */
         if ((opnd == 0) ||                              /* div by zero? */
-            ((R[r1] == 0x80000000) && (opnd = 0xFFFF))) {
+            ((R[r1] == 0x80000000) && (opnd == 0xFFFF))) {
             if (PSW & PSW_AFI)                         /* div fault enabled? */
                 cc = exception (AFIPSW, cc, 0);        /* exception */
             break;