From dd31ce6e75d94e8f92167cc95eb5be4c04836bab Mon Sep 17 00:00:00 2001 From: Richard Cornwell Date: Wed, 10 Sep 2025 13:38:46 -0400 Subject: [PATCH] KA10: Update PI Panel to properly display the MI register. --- PDP10/ka10_pipanel.c | 6 ++--- PDP10/kx10_cpu.c | 62 ++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 60 insertions(+), 8 deletions(-) diff --git a/PDP10/ka10_pipanel.c b/PDP10/ka10_pipanel.c index 533843d0..57a5473c 100644 --- a/PDP10/ka10_pipanel.c +++ b/PDP10/ka10_pipanel.c @@ -341,7 +341,7 @@ void *blink(void *ptr) } /* Columns */ - for (col = 0; col < 10; col++) { + for (col = 0; col < 18; col++) { gpio_set_fsel(cols[col], GPIO_FSEL_INPUT); gpio_set_pull(cols[col], PULL_UP); } @@ -367,10 +367,10 @@ void *blink(void *ptr) switch (row) { default: case 0: - leds = (((MI_flag)? MI : MB) & MB_MASK0) >> MB_V_0; + leds = (MI & MB_MASK0) >> MB_V_0; break; case 1: - leds = (((MI_flag)? MI : MB) & MB_MASK1) >> MB_V_1; + leds = (MI & MB_MASK1) >> MB_V_1; break; case 2: if (par_stop) { diff --git a/PDP10/kx10_cpu.c b/PDP10/kx10_cpu.c index 89c1f24a..c3863f0a 100644 --- a/PDP10/kx10_cpu.c +++ b/PDP10/kx10_cpu.c @@ -778,6 +778,14 @@ DEVICE cpu_dev = { #else #define QSLAVE 0 #endif +#if PIDP10 + /* Update MI register if address matches */ +#define UPDATE_MI(a) if (!MI_flag && a == AS) { \ + MI = MB; \ + } +#else +#define UPDATE_MI(a) +#endif #define MAX_DEV 128 #if KL @@ -2280,6 +2288,7 @@ int Mem_read(int flag, int cur_context, int fetch, int mod) { } /* Check if invalid section */ MB = get_reg(AB); + UPDATE_MI(AB); } else { if (!page_lookup(AB, flag, &addr, mod, cur_context, fetch)) return 1; @@ -2294,6 +2303,7 @@ int Mem_read(int flag, int cur_context, int fetch, int mod) { MB = M[addr]; modify = mod; last_addr = addr; + UPDATE_MI(addr); } if (fetch == 0 && hst_lnt) { hst[hst_p].mb = MB; @@ -2315,11 +2325,13 @@ int Mem_write(int flag, int cur_context) { } } set_reg(AB, MB); + UPDATE_MI(AB); } else { if (modify) { if (sim_brk_summ && sim_brk_test(last_addr, SWMASK('W'))) watch_stop = 1; M[last_addr] = MB; + UPDATE_MI(last_addr); modify = 0; return 0; } @@ -2335,6 +2347,7 @@ int Mem_write(int flag, int cur_context) { watch_stop = 1; sim_interval--; M[addr] = MB; + UPDATE_MI(addr); } return 0; } @@ -2824,6 +2837,7 @@ int Mem_read(int flag, int cur_context, int fetch, int mod) { return 1; } MB = get_reg(AB); + UPDATE_MI(AB); } else { if (!page_lookup(AB, flag, &addr, mod, cur_context, fetch)) return 1; @@ -2837,6 +2851,7 @@ int Mem_read(int flag, int cur_context, int fetch, int mod) { MB = M[addr]; modify = mod; last_addr = addr; + UPDATE_MI(addr); } if (fetch == 0 && hst_lnt) { hst[hst_p].mb = MB; @@ -2867,11 +2882,13 @@ int Mem_write(int flag, int cur_context) { return 0; } set_reg(AB, MB); + UPDATE_MI(AB); } else { if (modify) { if (sim_brk_summ && sim_brk_test(last_addr, SWMASK('W'))) watch_stop = 1; M[last_addr] = MB; + UPDATE_MI(last_addr); modify = 0; return 0; } @@ -2885,6 +2902,7 @@ int Mem_write(int flag, int cur_context) { watch_stop = 1; sim_interval--; M[addr] = MB; + UPDATE_MI(addr); } return 0; } @@ -2999,6 +3017,7 @@ int Mem_read_byte(int n, uint16 *data, int byte) { need -= 8; if (need >= 0) *data |= val << need; + UPDATE_MI(addr); } return s; } @@ -3042,6 +3061,7 @@ int Mem_write_byte(int n, uint16 *data) { val |= msk & (((uint64)(dat >> (need - s))) << p); M[addr] = val; need -= s; + UPDATE_MI(addr); } return s; } @@ -3248,6 +3268,7 @@ int Mem_read(int flag, int cur_context, int fetch, int mod) { if (fetch == 0 && hst_lnt) { hst[hst_p].mb = MB; } + MB = get_reg(AB); return 0; } } @@ -3271,6 +3292,7 @@ read: if (fetch == 0 && hst_lnt) { hst[hst_p].mb = MB; } + UPDATE_MI(AB); return 0; } @@ -3297,11 +3319,13 @@ int Mem_write(int flag, int cur_context) { } } set_reg(AB, MB); + UPDATE_MI(AB); } else { if (modify) { if (sim_brk_summ && sim_brk_test(last_addr, SWMASK('W'))) watch_stop = 1; M[last_addr] = MB; + UPDATE_MI(last_addr); modify = 0; return 0; } @@ -3317,6 +3341,7 @@ write: watch_stop = 1; sim_interval--; M[addr] = MB; + UPDATE_MI(addr); } return 0; } @@ -3512,6 +3537,7 @@ int Mem_read_its(int flag, int cur_context, int fetch, int mod) { return 0; } MB = get_reg(AB); + UPDATE_MI(AB); } else { if (!page_lookup_its(AB, flag, &addr, 0, cur_context, fetch, mod)) return 1; @@ -3546,6 +3572,7 @@ int Mem_read_its(int flag, int cur_context, int fetch, int mod) { MB = M[addr]; last_addr = addr; modify = mod; + UPDATE_MI(addr); } if (fetch == 0 && hst_lnt) { hst[hst_p].mb = MB; @@ -3564,19 +3591,23 @@ int Mem_write_its(int flag, int cur_context) { if (AB < 020) { if ((xct_flag & 2) != 0 && !cur_context) { M[(ac_stack & 01777777) + AB] = MB; + UPDATE_MI((ac_stack & 01777777) + AB); return 0; } set_reg(AB, MB); + UPDATE_MI(AB); } else { if (modify) { if (sim_brk_summ && sim_brk_test(last_addr, SWMASK('W'))) watch_stop = 1; M[last_addr] = MB; + UPDATE_MI(last_addr); modify = 0; return 0; } if (!page_lookup_its(AB, flag, &addr, 1, cur_context, 0, 0)) return 1; + UPDATE_MI(addr); #if NUM_DEVS_AUXCPU > 0 if (AUXCPURANGE(addr) && QAUXCPU) { if (auxcpu_write (addr, MB)) { @@ -3606,6 +3637,7 @@ int Mem_write_its(int flag, int cur_context) { watch_stop = 1; sim_interval--; M[addr] = MB; + UPDATE_MI(addr); } return 0; } @@ -3881,6 +3913,7 @@ int Mem_read_bbn(int flag, int cur_context, int fetch, int mod) { if (fetch == 0 && hst_lnt) { hst[hst_p].mb = MB; } + UPDATE_MI(AB); return 0; } if (!page_lookup_bbn(AB, flag, &addr, mod, cur_context, fetch)) @@ -3890,6 +3923,7 @@ int Mem_read_bbn(int flag, int cur_context, int fetch, int mod) { if (fetch == 0 && hst_lnt) { hst[hst_p].mb = MB; } + UPDATE_MI(AB); return 0; } if (addr >= MEMSIZE) { @@ -3906,6 +3940,7 @@ int Mem_read_bbn(int flag, int cur_context, int fetch, int mod) { if (fetch == 0 && hst_lnt) { hst[hst_p].mb = MB; } + UPDATE_MI(addr); return 0; } @@ -3920,12 +3955,14 @@ int Mem_write_bbn(int flag, int cur_context) { /* If not doing any special access, just access register */ if (AB < 020 && ((xct_flag == 0 || cur_context || (FLAGS & USER) != 0))) { set_reg(AB, MB); + UPDATE_MI(AB); return 0; } if (modify) { if (sim_brk_summ && sim_brk_test(last_addr, SWMASK('W'))) watch_stop = 1; M[last_addr] = MB; + UPDATE_MI(AB); modify = 0; return 0; } @@ -3933,6 +3970,7 @@ int Mem_write_bbn(int flag, int cur_context) { return 1; if (addr < 020) { set_reg(AB, MB); + UPDATE_MI(AB); return 0; } if (addr >= MEMSIZE) { @@ -3944,6 +3982,7 @@ int Mem_write_bbn(int flag, int cur_context) { watch_stop = 1; sim_interval--; M[addr] = MB; + UPDATE_MI(addr); return 0; } #endif @@ -3998,6 +4037,7 @@ int Mem_read_waits(int flag, int cur_context, int fetch, int mod) { if (fetch == 0 && hst_lnt) { hst[hst_p].mb = MB; } + UPDATE_MI(addr); return 0; } if (!page_lookup_waits(AB, flag, &addr, mod, cur_context, fetch)) @@ -4016,6 +4056,7 @@ int Mem_read_waits(int flag, int cur_context, int fetch, int mod) { if (fetch == 0 && hst_lnt) { hst[hst_p].mb = MB; } + UPDATE_MI(addr); return 0; } @@ -4031,6 +4072,7 @@ int Mem_write_waits(int flag, int cur_context) { /* If not doing any special access, just access register */ if (AB < 020 && ((xct_flag == 0 || cur_context || (FLAGS & USER) != 0))) { set_reg(AB, MB); + UPDATE_MI(AB); return 0; } if (modify) { @@ -4038,6 +4080,7 @@ int Mem_write_waits(int flag, int cur_context) { watch_stop = 1; M[last_addr] = MB; modify = 0; + UPDATE_MI(AB); return 0; } if (!page_lookup_waits(AB, flag, &addr, 1, cur_context, 0)) @@ -4051,6 +4094,7 @@ int Mem_write_waits(int flag, int cur_context) { watch_stop = 1; sim_interval--; M[addr] = MB; + UPDATE_MI(addr); return 0; } #endif @@ -4081,7 +4125,7 @@ int page_lookup_ka(t_addr addr, int flag, t_addr *loc, int wr, int cur_context, } int Mem_read_ka(int flag, int cur_context, int fetch, int mod) { - t_addr addr; + t_addr addr = AB; if (AB < 020) { MB = get_reg(AB); @@ -4101,6 +4145,7 @@ int Mem_read_ka(int flag, int cur_context, int fetch, int mod) { if (fetch == 0 && hst_lnt) { hst[hst_p].mb = MB; } + UPDATE_MI(addr); return 0; } @@ -4111,7 +4156,7 @@ int Mem_read_ka(int flag, int cur_context, int fetch, int mod) { */ int Mem_write_ka(int flag, int cur_context) { - t_addr addr; + t_addr addr = AB; if (AB < 020) { set_reg(AB, MB); @@ -4128,6 +4173,7 @@ int Mem_write_ka(int flag, int cur_context) { sim_interval--; M[addr] = MB; } + UPDATE_MI(addr); return 0; } @@ -4251,7 +4297,7 @@ int page_lookup(t_addr addr, int flag, t_addr *loc, int wr, int cur_context, int } int Mem_read(int flag, int cur_context, int fetch, int mod) { - t_addr addr; + t_addr addr = AB; sim_interval--; if (AB < 020) { @@ -4271,6 +4317,7 @@ int Mem_read(int flag, int cur_context, int fetch, int mod) { if (fetch == 0 && hst_lnt) { hst[hst_p].mb = MB; } + UPDATE_MI(addr); return 0; } @@ -4281,7 +4328,7 @@ int Mem_read(int flag, int cur_context, int fetch, int mod) { */ int Mem_write(int flag, int cur_context) { - t_addr addr; + t_addr addr = AB; sim_interval--; if (AB < 020) { @@ -4298,6 +4345,7 @@ int Mem_write(int flag, int cur_context) { watch_stop = 1; M[addr] = MB; } + UPDATE_MI(addr); return 0; } #endif @@ -4323,6 +4371,7 @@ int Mem_read_nopage() { } sim_interval--; MB = M[AB]; + UPDATE_MI(AB); return 0; } @@ -4347,6 +4396,7 @@ int Mem_write_nopage() { } sim_interval--; M[AB] = MB; + UPDATE_MI(AB); return 0; } @@ -4909,7 +4959,7 @@ st_pi: #if PIDP10 if (xct_sw) { /* Handle Front panel xct switch */ xct_sw = 0; - } else + } else #endif f_pc_inh = 0; #if KL | KS @@ -13931,6 +13981,8 @@ if (cptr == NULL) { } #if KI lnt = (int32) get_uint (cptr, 10, 001777, &r); +#elif KS +lnt = (int32) get_uint (cptr, 10, 077777, &r); #else lnt = (int32) get_uint (cptr, 10, 007777, &r); #endif