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Notes For V2.9-11
1. New Features 1.1 GRI-909 - This is a new simulator for the GRI-909. - It has been hand-tested; so far, no software has been discovered. 1.2 VAX - SET CPU CONHALT will cause a HALT instruction to return to the boot ROM console rather than to SIMH. SET CPU SIMHALT restores the default behavior. - BRB/W self at IPL 1F stops the simulator. This is the default behavior of VMS at exit. 1.3 PDP-18b - ATTACH -A PTR/PTP attaches the reader and punch in ASCII mode. In ASCII mode, the reader automatically sets the high order bit of incoming alphabetic data, and the punch clears the high order bit of outgoing data. 1.4 SCP - DO -V echoes commands from the file as they are executed. - Under Windows, execution priority is set BELOW_NORMAL when the simulator is running. 2. Release Notes 2.1 Bugs Fixed - PDP-11 CPU: fixed updating of MMR0 on a memory management error. - VAX FPA: changed function names to avoid conflict with C math library. - 1401 MT: read end of record generates group mark without word mark. - 1401 DP: fixed address generation and checking. - SCP: an EXIT within a DO command will cause the simulator to exit. 3. In Progress - Interdata 16b/32b: coded, not tested. - SDS 940: coded, not tested. - IBM 1620: coded, not tested. If you would like to help with the debugging of the untested simulators, they can be made available by special request.
This commit is contained in:
committed by
Mark Pizzolato
parent
701f0fe028
commit
df6475181c
@@ -1,6 +1,6 @@
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/* pdp1_cpu.c: PDP-1 CPU simulator
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Copyright (c) 1993-2001, Robert M. Supnik
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Copyright (c) 1993-2002, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -25,6 +25,7 @@
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cpu PDP-1 central processor
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30-Dec-01 RMS Added old PC queue
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07-Dec-01 RMS Revised to use breakpoint package
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30-Nov-01 RMS Added extended SET/SHOW support
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16-Dec-00 RMS Fixed bug in XCT address calculation
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@@ -214,6 +215,9 @@
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#include "pdp1_defs.h"
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#define PCQ_SIZE 64 /* must be 2**n */
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#define PCQ_MASK (PCQ_SIZE - 1)
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#define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = PC
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#define UNIT_V_MDV (UNIT_V_UF) /* mul/div */
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#define UNIT_MDV (1 << UNIT_V_MDV)
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#define UNIT_V_MSIZE (UNIT_V_UF+1) /* dummy mask */
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@@ -237,7 +241,9 @@ int32 extm_init = 0; /* ext mem startup */
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int32 stop_inst = 0; /* stop on rsrv inst */
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int32 xct_max = 16; /* nested XCT limit */
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int32 ind_max = 16; /* nested ind limit */
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int32 old_PC = 0; /* old PC */
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uint16 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
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int32 pcq_p = 0; /* PC queue ptr */
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REG *pcq_r = NULL; /* PC queue reg ptr */
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extern UNIT *sim_clock_queue;
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extern int32 sim_int_char;
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extern int32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
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@@ -313,7 +319,8 @@ REG cpu_reg[] = {
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{ FLDATA (SBIP, sbs, SB_V_IP) },
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{ FLDATA (IOH, ioh, 0) },
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{ FLDATA (IOC, ioc, 0) },
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{ ORDATA (OLDPC, old_PC, ASIZE), REG_RO },
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{ BRDATA (PCQ, pcq, 8, ASIZE, PCQ_SIZE), REG_RO+REG_CIRC },
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{ ORDATA (PCQP, pcq_p, 6), REG_HRO },
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{ FLDATA (STOP_INST, stop_inst, 0) },
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{ FLDATA (SBS_INIT, sbs_init, SB_V_ON) },
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{ FLDATA (EXTM_INIT, extm_init, 0) },
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@@ -369,7 +376,7 @@ if (sim_interval <= 0) { /* check clock queue */
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if (sbs == (SB_ON | SB_RQ)) { /* interrupt? */
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sbs = SB_ON | SB_IP; /* set in prog flag */
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old_PC = PC; /* save old PC */
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PCQ_ENTRY; /* save old PC */
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M[0] = AC; /* save state */
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M[1] = EPC_WORD;
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M[2] = IO;
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@@ -392,7 +399,7 @@ sim_interval = sim_interval - 1;
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xct_instr: /* label for XCT */
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if ((IR == 0610001) && ((MA & EPCMASK) == 0) && (sbs & SB_ON)) {
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sbs = sbs & ~SB_IP; /* seq debreak */
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old_PC = PC; /* save old PC */
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PCQ_ENTRY; /* save old PC */
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OV = (M[1] >> 17) & 1; /* restore OV */
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extm = (M[1] >> 16) & 1; /* restore ext mode */
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PC = M[1] & AMASK; /* JMP I 1 */
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@@ -433,7 +440,7 @@ case 004: /* XCT */
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goto xct_instr; /* go execute */
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case 007: /* CAL, JDA */
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MA = (PC & EPCMASK) | ((IR & IA)? (IR & DAMASK): 0100);
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old_PC = PC;
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PCQ_ENTRY;
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M[MA] = AC;
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AC = EPC_WORD;
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PC = INCR_ADDR (MA);
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@@ -509,12 +516,12 @@ case 025: /* SAS */
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if (AC == M[MA]) PC = INCR_ADDR (PC);
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break;
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case 030: /* JMP */
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old_PC = PC;
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PCQ_ENTRY;
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PC = MA;
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break;
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case 031: /* JSP */
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AC = EPC_WORD;
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old_PC = PC;
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PCQ_ENTRY;
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PC = MA;
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break;
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case 034: /* LAW */
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@@ -724,6 +731,7 @@ default: /* undefined */
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reason = STOP_RSRV; /* halt */
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break; } /* end switch opcode */
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} /* end while */
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pcq_r -> qptr = pcq_p; /* update pc q ptr */
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return reason;
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}
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@@ -736,6 +744,9 @@ extm = extm_init;
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ioh = ioc = 0;
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OV = 0;
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PF = 0;
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pcq_r = find_reg ("PCQ", NULL, dptr);
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if (pcq_r) pcq_r -> qptr = 0;
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else return SCPE_IERR;
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sim_brk_types = sim_brk_dflt = SWMASK ('E');
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return SCPE_OK;
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}
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@@ -1,6 +1,6 @@
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/* pdp1_defs.h: 18b PDP simulator definitions
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Copyright (c) 1993-2001, Robert M. Supnik
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Copyright (c) 1993-2002, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -1,14 +1,14 @@
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To: Users
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From: Bob Supnik
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Subj: PDP-1 Simulator Usage
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Date: 1-Dec-01
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Date: 15-Jun-02
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COPYRIGHT NOTICE
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The following copyright notice applies to both the SIMH source and binary:
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Original code published in 1993-2001, written by Robert M Supnik
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Copyright (c) 1993-2001, Robert M Supnik
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Original code published in 1993-2002, written by Robert M Supnik
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Copyright (c) 1993-2002, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -114,7 +114,8 @@ control registers for the interrupt system.
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SBIP 1 sequence break in progress
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IOH 1 I/O halt in progress
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IOC 1 I/O continue
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OLDPC 16 PC prior to last transfer
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PCQ[0:63] 16 PC prior to last jump or interrupt;
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most recent PC change first
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STOP_INST 1 stop on undefined instruction
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SBS_INIT 1 initial state of sequence break enable
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EXTM_INIT 1 initial state of extend mode
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@@ -138,7 +139,7 @@ The paper tape reader implements these registers:
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BUF 8 last data item processed
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DONE 1 device done flag
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RPLS 1 return restart pulse flag
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POS 31 position in the input file
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POS 32 position in the input file
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TIME 24 time from I/O initiation to interrupt
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STOP_IOE 1 stop on I/O error
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@@ -167,7 +168,7 @@ The paper tape punch implements these registers:
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BUF 8 last data item processed
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DONE 1 device done flag
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RPLS 1 return restart pulse flag
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POS 31 position in the output file
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POS 32 position in the output file
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TIME 24 time from I/O initiation to interrupt
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STOP_IOE 1 stop on I/O error
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@@ -189,7 +190,7 @@ implements these registers:
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BUF 8 last data item processed
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DONE 1 device done flag
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POS 31 number of characters input
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POS 32 number of characters input
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TIME 24 keyboard polling interval
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2.2.4 Terminal Output (TTO)
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@@ -202,7 +203,7 @@ It implements these registers:
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BUF 8 last data item processed
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DONE 1 device done flag
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RPLS 1 return restart pulse flag
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POS 31 number of characters output
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POS 32 number of characters output
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TIME 24 time from I/O initiation to interrupt
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2.2.5 Type 62 Line Printer (LPT)
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@@ -220,7 +221,7 @@ The line printer implements these registers:
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SPC 1 spacing done flag
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RPLS 1 return restart pulse flag
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BPTR 6 print buffer pointer
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POS 31 position in the output file
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POS 32 position in the output file
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TIME 24 time from I/O initiation to interrupt
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STOP_IOE 1 stop on I/O error
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LBUF[0:119] 8 line buffer
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@@ -1,6 +1,6 @@
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/* pdp1_lp.c: PDP-1 line printer simulator
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Copyright (c) 1993-2001, Robert M. Supnik
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Copyright (c) 1993-2002, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -25,6 +25,7 @@
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lpt Type 62 line printer for the PDP-1
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30-May-02 RMS Widened POS to 32b
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13-Apr-01 RMS Revised for register arrays
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*/
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@@ -55,7 +56,7 @@ REG lpt_reg[] = {
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{ FLDATA (RPLS, lpt_rpls, 0) },
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{ DRDATA (BPTR, bptr, 6) },
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{ ORDATA (LPT_STATE, lpt_iot, 6), REG_HRO },
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{ DRDATA (POS, lpt_unit.pos, 31), PV_LEFT },
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{ DRDATA (POS, lpt_unit.pos, 32), PV_LEFT },
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{ DRDATA (TIME, lpt_unit.wait, 24), PV_LEFT },
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{ FLDATA (STOP_IOE, lpt_stopioe, 0) },
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{ BRDATA (LBUF, lpt_buf, 8, 8, LPT_BSIZE) },
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@@ -1,6 +1,6 @@
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/* pdp1_stddev.c: PDP-1 standard devices
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Copyright (c) 1993-2001, Robert M. Supnik
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Copyright (c) 1993-2002, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -28,6 +28,7 @@
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tti keyboard
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tto teleprinter
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30-May-02 RMS Widened POS to 32b
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29-Nov-01 RMS Added read only unit support
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07-Sep-01 RMS Moved function prototypes
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10-Jun-01 RMS Fixed comment
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@@ -112,7 +113,7 @@ REG ptr_reg[] = {
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{ FLDATA (DONE, iosta, IOS_V_PTR) },
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{ FLDATA (RPLS, ptr_rpls, 0) },
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{ ORDATA (STATE, ptr_state, 5), REG_HRO },
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{ DRDATA (POS, ptr_unit.pos, 31), PV_LEFT },
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{ DRDATA (POS, ptr_unit.pos, 32), PV_LEFT },
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{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },
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{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
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{ NULL } };
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@@ -137,7 +138,7 @@ REG ptp_reg[] = {
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{ ORDATA (BUF, ptp_unit.buf, 8) },
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{ FLDATA (DONE, iosta, IOS_V_PTP) },
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{ FLDATA (RPLS, ptp_rpls, 0) },
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{ DRDATA (POS, ptp_unit.pos, 31), PV_LEFT },
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{ DRDATA (POS, ptp_unit.pos, 32), PV_LEFT },
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{ DRDATA (TIME, ptp_unit.wait, 24), PV_LEFT },
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{ FLDATA (STOP_IOE, ptp_stopioe, 0) },
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{ NULL } };
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@@ -161,7 +162,7 @@ REG tti_reg[] = {
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{ ORDATA (BUF, tti_unit.buf, 6) },
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{ FLDATA (DONE, iosta, IOS_V_TTI) },
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{ ORDATA (STATE, tti_state, 10), REG_HRO },
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{ DRDATA (POS, tti_unit.pos, 31), PV_LEFT },
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{ DRDATA (POS, tti_unit.pos, 32), PV_LEFT },
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{ DRDATA (TIME, tti_unit.wait, 24), REG_NZ + PV_LEFT },
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{ NULL } };
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@@ -185,7 +186,7 @@ REG tto_reg[] = {
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{ FLDATA (DONE, iosta, IOS_V_TTO) },
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{ FLDATA (RPLS, tto_rpls, 0) },
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{ ORDATA (STATE, tto_state, 10), REG_HRO },
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{ DRDATA (POS, tto_unit.pos, 31), PV_LEFT },
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{ DRDATA (POS, tto_unit.pos, 32), PV_LEFT },
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{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },
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{ NULL } };
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@@ -1,6 +1,6 @@
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/* pdp1_sys.c: PDP-1 simulator interface
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Copyright (c) 1993-2001, Robert M. Supnik
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Copyright (c) 1993-2002, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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