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Notes For V2.9-11
1. New Features 1.1 GRI-909 - This is a new simulator for the GRI-909. - It has been hand-tested; so far, no software has been discovered. 1.2 VAX - SET CPU CONHALT will cause a HALT instruction to return to the boot ROM console rather than to SIMH. SET CPU SIMHALT restores the default behavior. - BRB/W self at IPL 1F stops the simulator. This is the default behavior of VMS at exit. 1.3 PDP-18b - ATTACH -A PTR/PTP attaches the reader and punch in ASCII mode. In ASCII mode, the reader automatically sets the high order bit of incoming alphabetic data, and the punch clears the high order bit of outgoing data. 1.4 SCP - DO -V echoes commands from the file as they are executed. - Under Windows, execution priority is set BELOW_NORMAL when the simulator is running. 2. Release Notes 2.1 Bugs Fixed - PDP-11 CPU: fixed updating of MMR0 on a memory management error. - VAX FPA: changed function names to avoid conflict with C math library. - 1401 MT: read end of record generates group mark without word mark. - 1401 DP: fixed address generation and checking. - SCP: an EXIT within a DO command will cause the simulator to exit. 3. In Progress - Interdata 16b/32b: coded, not tested. - SDS 940: coded, not tested. - IBM 1620: coded, not tested. If you would like to help with the debugging of the untested simulators, they can be made available by special request.
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
701f0fe028
commit
df6475181c
@@ -1,6 +1,6 @@
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/* pdp10_cpu.c: PDP-10 CPU simulator
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Copyright (c) 1993-2001, Robert M. Supnik
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Copyright (c) 1993-2002, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -25,6 +25,7 @@
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cpu KS10 central processor
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30-Dec-01 RMS Added old PC queue
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25-Dec-01 RMS Cleaned up sim_inst declarations
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07-Dec-01 RMS Revised to use new breakpoint package
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21-Nov-01 RMS Implemented ITS 1-proceed hack
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@@ -128,6 +129,9 @@
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#include "pdp10_defs.h"
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#include <setjmp.h>
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#define PCQ_SIZE 64 /* must be 2**n */
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#define PCQ_MASK (PCQ_SIZE - 1)
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#define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = PC
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#define UNIT_V_MSIZE (UNIT_V_T20V41 + 1) /* dummy mask */
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#define UNIT_MSIZE (1 << UNIT_V_MSIZE)
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@@ -169,7 +173,9 @@ int32 stop_op0 = 0; /* stop on 0 */
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int32 rlog = 0; /* extend fixup log */
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int32 ind_max = 32; /* nested ind limit */
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int32 xct_max = 32; /* nested XCT limit */
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a10 old_PC = 0; /* old PC */
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a10 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
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int32 pcq_p = 0; /* PC queue ptr */
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REG *pcq_r = NULL; /* PC queue reg ptr */
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jmp_buf save_env;
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extern int32 sim_int_char;
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@@ -351,7 +357,8 @@ REG cpu_reg[] = {
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{ ORDATA (APRLVL, apr_lvl, 3) },
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{ ORDATA (RLOG, rlog, 10) },
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{ FLDATA (F1PR, its_1pr, 0) },
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{ ORDATA (OLDPC, old_PC, VASIZE), REG_RO },
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{ BRDATA (PCQ, pcq, 8, VASIZE, PCQ_SIZE), REG_RO+REG_CIRC },
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{ ORDATA (PCQP, pcq_p, 6), REG_HRO },
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{ DRDATA (INDMAX, ind_max, 8), PV_LEFT + REG_NZ },
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{ DRDATA (XCTMAX, xct_max, 8), PV_LEFT + REG_NZ },
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{ FLDATA (ITS, cpu_unit.flags, UNIT_V_ITS), REG_HRO },
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@@ -434,7 +441,7 @@ static t_stat jrst_tab[16] = {
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#define IM ((d10) ea)
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#define IMS (((d10) ea) << 18)
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#define JUMP(x) old_PC = PC, PC = ((a10) (x)) & AMASK
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#define JUMP(x) PCQ_ENTRY, PC = ((a10) (x)) & AMASK
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#define SUBJ(x) CLRF (F_AFI | F_FPD | F_TR); JUMP (x)
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#define INCPC PC = INCA (PC)
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@@ -572,7 +579,7 @@ static t_stat jrst_tab[16] = {
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t_stat sim_instr (void)
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{
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a10 PC;
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a10 PC; /* set by setjmp */
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int abortval = 0; /* abort value */
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/* Restore register state */
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@@ -598,6 +605,7 @@ if ((abortval > 0) || pager_pi) { /* stop or pi err? */
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abortval = STOP_PAGINT; /* stop for pi err */
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saved_PC = pager_PC & AMASK; /* failing instr PC */
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set_ac_display (ac_cur); /* set up AC display */
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pcq_r -> qptr = pcq_p; /* update pc q ptr */
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return abortval; } /* return to SCP */
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/* Page fail - checked against KS10 ucode
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@@ -2035,6 +2043,9 @@ set_ac_display (ac_cur);
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pi_eval ();
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if (M == NULL) M = calloc (MAXMEMSIZE, sizeof (d10));
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if (M == NULL) return SCPE_MEM;
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pcq_r = find_reg ("PCQ", NULL, dptr);
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if (pcq_r) pcq_r -> qptr = 0;
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else return SCPE_IERR;
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sim_brk_types = sim_brk_dflt = SWMASK ('E');
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return SCPE_OK;
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}
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@@ -1,6 +1,6 @@
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/* pdp10_defs.h: PDP-10 simulator definitions
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Copyright (c) 1993-2001, Robert M Supnik
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Copyright (c) 1993-2002, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -23,8 +23,10 @@
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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22-Apr-02 RMS Removed magtape record length error
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20-Jan-02 RMS Added multiboard DZ11 support
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23-Oct-01 RMS New IO page address constants
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19-Oct-01 RMS Added DZ definitions
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19-Oct-01 RMS Added DZ11 definitions
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07-Sep-01 RMS Revised for PDP-11 multi-level interrupts
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31-Aug-01 RMS Changed int64 to t_int64 for Windoze
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29-Aug-01 RMS Corrected models and dates (found by Lars Brinkhoff)
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@@ -93,9 +95,8 @@ typedef t_int64 d10; /* PDP-10 data (36b) */
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#define STOP_IND 8 /* indirection loop */
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#define STOP_XCT 9 /* XCT loop */
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#define STOP_ILLIOC 10 /* invalid UBA num */
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#define STOP_MTRLNT 11 /* invalid mt rec lnt */
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#define STOP_ASTOP 12 /* address stop */
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#define STOP_UNKNOWN 13 /* unknown stop */
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#define STOP_ASTOP 11 /* address stop */
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#define STOP_UNKNOWN 12 /* unknown stop */
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#define PAGE_FAIL -1 /* page fail */
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#define INTERRUPT -2 /* interrupt */
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#define ABORT(x) longjmp (save_env, (x)) /* abort */
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@@ -573,30 +574,51 @@ typedef t_int64 d10; /* PDP-10 data (36b) */
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#define IO_UBA3 (3 << IO_V_UBA)
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#define GET_IOUBA(x) (((x) >> IO_V_UBA) & IO_M_UBA)
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/* Device information block */
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struct pdp_dib {
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uint32 enb; /* enabled */
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uint32 ba; /* base addr */
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uint32 lnt; /* length */
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t_stat (*rd)(int32 *dat, int32 ad, int32 md);
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t_stat (*wr)(int32 dat, int32 ad, int32 md); };
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typedef struct pdp_dib DIB;
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/* DZ11 parameters */
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#define DZ_MUXES 1 /* # of muxes */
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#define DZ_MUXES 4 /* max # of muxes */
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#define DZ_LINES 8 /* lines per mux */
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/* I/O page layout */
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#define IOBA_DZ 0760010 /* DZ11 */
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#define IOLN_DZ (010 * DZ_MUXES)
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#define IOBA_TCU 0760770 /* TCU150 */
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#define IOLN_TCU 006
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#define IOBA_UBMAP 0763000 /* Unibus map */
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#define IOLN_UBMAP 0100
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#define IOBA_UBCS 0763100 /* Unibus c/s reg */
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#define IOLN_UBCS 001
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#define IOBA_UBMNT 0763101 /* Unibus maint reg */
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#define IOLN_UBMNT 001
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#define IOBA_TU 0772440 /* RH11/tape */
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#define IOLN_TU 034
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#define IOBA_RP 0776700 /* RH11/disk */
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#define IOPAGEBASE 0760000 /* I/O page base */
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#define IOBA_UBMAP 0763000
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#define IOBA_UBMAP1 (IO_UBA1 + IOBA_UBMAP) /* Unibus 1 map */
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#define IOLN_UBMAP1 0100
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#define IOBA_UBCS1 (IO_UBA1 + 0763100) /* Unibus 1 c/s reg */
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#define IOLN_UBCS1 001
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#define IOBA_UBMNT1 (IO_UBA1 + 0763101) /* Unibus 1 maint reg */
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#define IOLN_UBMNT1 001
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#define IOBA_RP (IO_UBA1 + 0776700) /* RH11/disk */
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#define IOLN_RP 050
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#define IOBA_LP20 0775400 /* LP20 */
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#define IOBA_DZ (IO_UBA3 + 0760010) /* DZ11 */
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#define IOLN_DZ 010
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#define IOBA_TCU (IO_UBA3 + 0760770) /* TCU150 */
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#define IOLN_TCU 006
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#define IOBA_UBMAP3 (IO_UBA3 + IOBA_UBMAP) /* Unibus 3 map */
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#define IOLN_UBMAP3 0100
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#define IOBA_UBCS3 (IO_UBA3 + 0763100) /* Unibus 3 c/s reg */
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#define IOLN_UBCS3 001
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#define IOBA_UBMNT3 (IO_UBA3 + 0763101) /* Unibus 3 maint reg */
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#define IOLN_UBMNT3 001
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#define IOBA_TU (IO_UBA3 + 0772440) /* RH11/tape */
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#define IOLN_TU 034
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#define IOBA_LP20 (IO_UBA3 + 0775400) /* LP20 */
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#define IOLN_LP20 020
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#define IOBA_PT 0777550 /* PC11 */
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#define IOBA_PT (IO_UBA3 + 0777550) /* PC11 */
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#define IOLN_PT 010
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/* Common Unibus CSR flags */
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@@ -664,3 +686,10 @@ typedef t_int64 d10; /* PDP-10 data (36b) */
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#define IREQ(dv) int_req
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#define SET_INT(dv) IREQ(dv) = IREQ(dv) | (INT_##dv)
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#define CLR_INT(dv) IREQ(dv) = IREQ(dv) & ~(INT_##dv)
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/* Function prototypes */
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t_stat set_addr (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat show_addr (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat set_enbdis (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_bool dev_conflict (uint32 nba, DIB *curr);
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@@ -1,14 +1,14 @@
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To: Users
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From: Bob Supnik
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Subj: PDP-10 Simulator Usage
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Date: 1-Dec-01
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Date: 15-Jun-2002
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COPYRIGHT NOTICE
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The following copyright notice applies to both the SIMH source and binary:
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Original code published in 1993-2001, written by Robert M Supnik
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Copyright (c) 1993-2001, Robert M Supnik
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Original code published in 1993-2002, written by Robert M Supnik
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Copyright (c) 1993-2002, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -76,13 +76,14 @@ UBA Unibus adapters (translation maps)
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FE console
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TIM timer
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PTR,PTP PC11 paper tape reader/punch
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DZ DZ11 8-line terminal multiplexor
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DZ DZ11 8-line terminal multiplexor (up to 4)
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LP20 LP20 line printer
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RP RH11/RP04/RP05/RP06/RP07/RM03/RM05/RM80 controller with
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eight drives
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TU RH11/TM02/TU45 controller with eight drives
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The PTR/PTP are initially DISABLEd. The DZ11 can also be DISABLEd.
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The PTR/PTP are initially set DISABLED. The DZ11 and LP20 can also be
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set DISABLED.
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The PDP-10 simulator implements several unique stop condition:
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@@ -99,7 +100,7 @@ The PDP-10 loader supports RIM10B format paper tapes, SAV binary files, and
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EXE binary files. LOAD switches -r, -s, -e specify RIM10, SAV, EXE format,
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respectively. If no switch is specified, the LOAD command checks the file
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extension; .RIM, .SAV, .EXE specify RIM10, SAV, EXE format, respectively.
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If no switch specified, and no extension matches, the LOAD command checks
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If no switch is specified, and no extension matches, the LOAD command checks
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the file format to try to determine the file type.
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2.1 CPU
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@@ -146,7 +147,8 @@ control registers for the interrupt system.
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APRLVL 3 PI level for APR interrupt
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IND_MAX 8 indirect address nesting limit
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XCT_MAX 8 execute chaining limit
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OLDPC 18 PC prior to last transfer instruction
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PCQ[0:63] 18 PC prior to last jump or interrupt;
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most recent PC change first
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WRU 8 interrupt character
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REG[0:127] 36 fast memory blocks
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@@ -173,7 +175,7 @@ The Unibus adapters link the system I/O devices to the CPU. Unibus
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adapter 1 (UBA1) is unit 0, and Unibus adapter 3 is unit 1. The
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adapter's Unibus map is the memory space of the corresponding unit.
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The Unibus Adapter has the following registers:
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The Unibus adapter has the following registers:
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name size comments
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@@ -194,10 +196,10 @@ The front end has the following registers:
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name size comments
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IBUF 8 input buffer
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ICOUNT 31 count of input characters
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ICOUNT 32 count of input characters
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ITIME 24 keyboard polling interval
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OBUF 8 output buffer
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OCOUNT 31 count of output characters
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OCOUNT 32 count of output characters
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OTIME 24 console output response time
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2.5 Timer (TIM)
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@@ -205,7 +207,7 @@ The front end has the following registers:
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The timer (TIM) implements the system timer, the interval timer, and
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the time of day clock used to get the date and time at system startup.
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Because most PDP-10 software is not Y2K compliant, the timer implements
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one option
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one option:
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SET TIM NOY2K software not Y2K compliant, limit time
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of day clock to 1999 (default)
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@@ -243,7 +245,7 @@ The paper tape reader implements these registers:
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BUSY 1 busy flag (CSR<11>)
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DONE 1 device done flag (CSR<7>)
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IE 1 interrupt enable flag (CSR<6>)
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POS 31 position in the input file
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POS 32 position in the input file
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TIME 24 time from I/O initiation to interrupt
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STOP_IOE 1 stop on I/O error
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@@ -276,7 +278,7 @@ The paper tape punch implements these registers:
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ERR 1 error flag (CSR<15>)
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DONE 1 device done flag (CSR<7>)
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IE 1 interrupt enable flag (CSR<6>)
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POS 31 position in the input or output file
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POS 32 position in the input or output file
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TIME 24 time from I/O initiation to interrupt
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STOP_IOE 1 stop on I/O error
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@@ -291,11 +293,18 @@ Error handling is as follows:
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2.8 DZ11 Terminal Multiplexor (DZ)
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The DZ11 is an 8-line terminal multiplexor. The terminal lines perform
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input and output through Telnet sessions connected to a user-specified
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port. The ATTACH command specifies the port to be used:
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The DZ11 is an 8-line terminal multiplexor. Up to 4 DZ11's (32 lines)
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are supported. The number of lines can be changed with the command
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ATTACH {-am} DZ <port>(cr) -- set up listening port
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SET DZ LINES=n set line count to n
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The line count must be a multiple of 8, with a maximum of 32.
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The terminal lines perform input and output through Telnet sessions
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connected to a user-specified port. The ATTACH command specifies
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the port to be used:
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ATTACH {-am} DZ <port> set up listening port
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where port is a decimal number between 1 and 65535 that is not being used
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for other TCP/IP activities. The optional switch -m turns on the DZ11's
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@@ -305,25 +314,28 @@ modem controls; the optional switch -a turns on active disconnects
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Once the DZ is attached and the simulator is running, the DZ will listen
|
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for connections on the specified port. It assumes that the incoming
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connections are Telnet connections. The connection remains open until
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disconnected either by the simulated program or by the Telnet client.
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disconnected by the simulated program, the Telnet client, a SET DZ
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DISCONNECT command, or a DETACH DZ command.
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The SHOW DZ LINESTATUS command displays the current connections to the DZ.
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The SHOW DZ CONNECTIONS command displays the current connections to the DZ.
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The SHOW DZ STATISTICS command displays statistics for active connections.
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The SET DZ DISCONNECT=linenumber disconnects the specified line.
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The DZ11 implements these registers:
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name size comments
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CSR 16 control/status register
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RBUF 16 receive buffer
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LPR 16 line parameter register
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TCR 16 transmission control register
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MSR 16 modem status register
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TDR 16 transmit data register
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SAENB 1 silo alarm enabled
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CSR[0:3] 16 control/status register, boards 0-3
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RBUF[0:3] 16 receive buffer, boards 0-3
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LPR[0:3] 16 line parameter register, boards 0-3
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TCR[0:3] 16 transmission control register, boards 0-3
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MSR[0:3] 16 modem status register, boards 0-3
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TDR[0:3] 16 transmit data register, boards 0-3
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SAENB[0:3] 1 silo alarm enabled, boards 0-3
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RXINT 4 receive interrupts, boards 3..0
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TXINT 4 transmit interrupts, boards 3..0
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MDMTCL 1 modem control enabled
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AUTODS 1 autodisconnect enabled
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RPOS0..7 32 count of characters received
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TPOS0..7 32 count of characters transmitted
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The DZ11 does not support save and restore. All open connections are
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lost when the simulator shuts down or the DZ is detached.
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@@ -340,7 +352,7 @@ RP options include the ability to set units write enabled or write locked,
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to set the drive type to one of six disk types, or autosize:
|
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|
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SET RPn LOCKED set unit n write locked
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SET RPn ENABLED set unit n write enabled
|
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SET RPn WRITEENABLED set unit n write enabled
|
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SET RPn RM03 set type to RM03
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SET RPn RM05 set type to RM05
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SET RPn RM80 set type to RM80
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@@ -350,8 +362,9 @@ to set the drive type to one of six disk types, or autosize:
|
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SET RPn AUTOSIZE set type based on file size at attach
|
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|
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The type options can be used only when a unit is not attached to a file.
|
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Note that TOPS-10 V7.03 only supported the RP06 and RM03; V7.04 added
|
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support for the RP07. Units can be REMOVEd or ADDed to the configuration.
|
||||
Note that TOPS-10 V7.03 supported only the RP06 and RM03; V7.04 added
|
||||
support for the RP07. TOPS-20 V4.1 also supported only the RP06 and
|
||||
RM03. Units can be set ONLINE or OFFLINE.
|
||||
|
||||
The RP controller implements these registers:
|
||||
|
||||
@@ -399,9 +412,9 @@ TM02 formatter and up to eight TU45 drives. Magnetic tape options include
|
||||
the ability to make units write enabled or locked.
|
||||
|
||||
SET TUn LOCKED set unit n write locked
|
||||
SET TUn ENABLED set unit n write enabled
|
||||
SET TUn WRITEENABLED set unit n write enabled
|
||||
|
||||
Units can also be REMOVEd or ADDed to the configuration.
|
||||
Units can also be set ONLINE or OFFLINE.
|
||||
|
||||
The magnetic tape controller implements these registers:
|
||||
|
||||
@@ -424,7 +437,7 @@ The magnetic tape controller implements these registers:
|
||||
STOP_IOE 1 stop on I/O error
|
||||
TIME 24 delay
|
||||
UST[0:7] 16 unit status, units 0-7
|
||||
POS[0:7] 31 position, units 0-7
|
||||
POS[0:7] 32 position, units 0-7
|
||||
|
||||
Error handling is as follows:
|
||||
|
||||
@@ -440,7 +453,7 @@ Error handling is as follows:
|
||||
2.11 LP20 DMA Line Printer (LP20)
|
||||
|
||||
The LP20 is a DMA-based line printer controller. There is one
|
||||
line printer option to clear the vertical forms unit (VFU).
|
||||
line printer option to clear the vertical forms unit (VFU):
|
||||
|
||||
SET LP20 VFUCLEAR clear the vertical forms unit
|
||||
|
||||
@@ -464,7 +477,7 @@ The LP20 implements these registers:
|
||||
ERR 1 error flag
|
||||
DONE 1 done flag
|
||||
IE 1 interrupt enable flag
|
||||
POS 31 position in output file
|
||||
POS 32 position in output file
|
||||
TIME 24 response time
|
||||
STOP_IOE 1 stop on I/O error
|
||||
TXRAM[0:255] 12 translation RAM
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* pdp10_dz.c: DZ11 terminal multiplexor simulator
|
||||
|
||||
Copyright (c) 1993-2001, Robert M Supnik
|
||||
Copyright (c) 1993-2002, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* pdp10_fe.c: PDP-10 front end (console terminal) simulator
|
||||
|
||||
Copyright (c) 1993-2001, Robert M Supnik
|
||||
Copyright (c) 1993-2002, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -25,6 +25,7 @@
|
||||
|
||||
fe KS10 console front end
|
||||
|
||||
30-May-02 RMS Widened COUNT to 32b
|
||||
30-Nov-01 RMS Added extended SET/SHOW support
|
||||
23-Oct-01 RMS New IO page address constants
|
||||
07-Sep-01 RMS Moved function prototypes
|
||||
@@ -57,10 +58,10 @@ UNIT fe_unit[] = {
|
||||
|
||||
REG fe_reg[] = {
|
||||
{ ORDATA (IBUF, fei_unit.buf, 8) },
|
||||
{ DRDATA (ICOUNT, fei_unit.pos, 31), REG_RO + PV_LEFT },
|
||||
{ DRDATA (ICOUNT, fei_unit.pos, 32), REG_RO + PV_LEFT },
|
||||
{ DRDATA (ITIME, fei_unit.wait, 24), REG_NZ + PV_LEFT },
|
||||
{ ORDATA (OBUF, feo_unit.buf, 8) },
|
||||
{ DRDATA (OCOUNT, feo_unit.pos, 31), REG_RO + PV_LEFT },
|
||||
{ DRDATA (OCOUNT, feo_unit.pos, 32), REG_RO + PV_LEFT },
|
||||
{ DRDATA (OTIME, feo_unit.wait, 24), REG_NZ + PV_LEFT },
|
||||
{ NULL } };
|
||||
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* pdp10_ksio.c: PDP-10 KS10 I/O subsystem simulator
|
||||
|
||||
Copyright (c) 1993-2001, Robert M Supnik
|
||||
Copyright (c) 1993-2002, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -25,6 +25,8 @@
|
||||
|
||||
uba Unibus adapters
|
||||
|
||||
25-Jan-02 RMS Revised for multiple DZ11's
|
||||
06-Jan-02 RMS Revised enable/disable support
|
||||
23-Sep-01 RMS New IO page address constants
|
||||
07-Sep-01 RMS Revised device disable mechanism
|
||||
25-Aug-01 RMS Enabled DZ11
|
||||
@@ -94,26 +96,17 @@ extern d10 *ac_cur;
|
||||
extern d10 pager_word;
|
||||
extern int32 flags, pi_l2bit[8];
|
||||
extern UNIT cpu_unit;
|
||||
extern FILE *sim_log;
|
||||
extern jmp_buf save_env;
|
||||
|
||||
extern d10 Read (a10 ea);
|
||||
extern void pi_eval ();
|
||||
extern t_stat dz_rd (int32 *data, int32 addr, int32 access);
|
||||
extern t_stat dz_wr (int32 data, int32 addr, int32 access);
|
||||
extern int32 dz_enb;
|
||||
extern t_stat pt_rd (int32 *data, int32 addr, int32 access);
|
||||
extern t_stat pt_wr (int32 data, int32 addr, int32 access);
|
||||
extern int32 pt_enb;
|
||||
extern t_stat lp20_rd (int32 *data, int32 addr, int32 access);
|
||||
extern t_stat lp20_wr (int32 data, int32 addr, int32 access);
|
||||
extern int32 lp20_inta (void);
|
||||
extern t_stat rp_rd (int32 *data, int32 addr, int32 access);
|
||||
extern t_stat rp_wr (int32 data, int32 addr, int32 access);
|
||||
extern DIB dz_dib, pt_dib, lp20_dib, rp_dib, tu_dib, tcu_dib;
|
||||
extern int32 rp_inta (void);
|
||||
extern t_stat tu_rd (int32 *data, int32 addr, int32 access);
|
||||
extern t_stat tu_wr (int32 data, int32 addr, int32 access);
|
||||
extern int32 tu_inta (void);
|
||||
extern t_stat tcu_rd (int32 *data, int32 addr, int32 access);
|
||||
extern int32 lp20_inta (void);
|
||||
extern int32 dz_rxinta (void);
|
||||
extern int32 dz_txinta (void);
|
||||
t_stat ubmap_rd (int32 *data, int32 addr, int32 access);
|
||||
t_stat ubmap_wr (int32 data, int32 addr, int32 access);
|
||||
t_stat ubs_rd (int32 *data, int32 addr, int32 access);
|
||||
@@ -125,6 +118,7 @@ t_stat uba_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
|
||||
t_stat uba_reset (DEVICE *dptr);
|
||||
d10 ReadIO (a10 ea);
|
||||
void WriteIO (a10 ea, d10 val, int32 mode);
|
||||
t_bool dev_conflict (uint32 nba, DIB *curr);
|
||||
|
||||
/* Unibus adapter data structures
|
||||
|
||||
@@ -133,6 +127,14 @@ void WriteIO (a10 ea, d10 val, int32 mode);
|
||||
uba_reg UBA register list
|
||||
*/
|
||||
|
||||
DIB ubmp1_dib = { 1, IOBA_UBMAP1, IOLN_UBMAP1, &ubmap_rd, &ubmap_wr };
|
||||
DIB ubmp3_dib = { 1, IOBA_UBMAP3, IOLN_UBMAP3, &ubmap_rd, &ubmap_wr };
|
||||
DIB ubcs1_dib = { 1, IOBA_UBCS1, IOLN_UBCS1, &ubs_rd, &ubs_wr };
|
||||
DIB ubcs3_dib = { 1, IOBA_UBCS3, IOLN_UBCS3, &ubs_rd, &ubs_wr };
|
||||
DIB ubmn1_dib = { 1, IOBA_UBMNT1, IOLN_UBMNT1, &rd_zro, &wr_nop };
|
||||
DIB ubmn3_dib = { 1, IOBA_UBMNT3, IOLN_UBMNT3, &rd_zro, &wr_nop };
|
||||
DIB msys_dib = { 1, 00100000, 00100001, &rd_zro, &wr_nop };
|
||||
|
||||
UNIT uba_unit[] = {
|
||||
{ UDATA (NULL, UNIT_FIX, UMAP_MEMSIZE) },
|
||||
{ UDATA (NULL, UNIT_FIX, UMAP_MEMSIZE) } };
|
||||
@@ -151,50 +153,28 @@ DEVICE uba_dev = {
|
||||
|
||||
/* PDP-11 I/O structures */
|
||||
|
||||
struct iolink { /* I/O page linkage */
|
||||
int32 low; /* low I/O addr */
|
||||
int32 high; /* high I/O addr */
|
||||
int32 *enb; /* enable flag */
|
||||
t_stat (*read)(); /* read routine */
|
||||
t_stat (*write)(); }; /* write routine */
|
||||
|
||||
/* Table of I/O devices and corresponding read/write routines
|
||||
The expected Unibus adapter number is included as the high 2 bits */
|
||||
|
||||
struct iolink iotable[] = {
|
||||
{ IO_UBA1+IOBA_RP, IO_UBA1+IOBA_RP+IOLN_RP,
|
||||
NULL, &rp_rd, &rp_wr }, /* disk */
|
||||
{ IO_UBA3+IOBA_TU, IO_UBA3+IOBA_TU+IOLN_TU,
|
||||
NULL, &tu_rd, &tu_wr }, /* mag tape */
|
||||
{ IO_UBA3+IOBA_DZ, IO_UBA3+IOBA_DZ+IOLN_DZ,
|
||||
&dz_enb, &dz_rd, &dz_wr }, /* terminal mux */
|
||||
{ IO_UBA3+IOBA_LP20, IO_UBA3+IOBA_LP20+IOLN_LP20,
|
||||
NULL, &lp20_rd, &lp20_wr }, /* line printer */
|
||||
{ IO_UBA3+IOBA_PT, IO_UBA3+IOBA_PT+IOLN_PT,
|
||||
&pt_enb, &pt_rd, &pt_wr }, /* paper tape */
|
||||
{ IO_UBA1+IOBA_UBMAP, IO_UBA1+IOBA_UBMAP+IOLN_UBMAP,
|
||||
NULL, &ubmap_rd, &ubmap_wr }, /* Unibus 1 map */
|
||||
{ IO_UBA3+IOBA_UBMAP, IO_UBA3+IOBA_UBMAP+IOLN_UBMAP,
|
||||
NULL, &ubmap_rd, &ubmap_wr }, /* Unibus 3 map */
|
||||
{ IO_UBA1+IOBA_UBCS, IO_UBA1+IOBA_UBCS+IOLN_UBCS,
|
||||
NULL, &ubs_rd, &ubs_wr }, /* Unibus 1 c/s */
|
||||
{ IO_UBA3+IOBA_UBCS, IO_UBA3+IOBA_UBCS+IOLN_UBCS,
|
||||
NULL, &ubs_rd, &ubs_wr }, /* Unibus 3 c/s */
|
||||
{ IO_UBA1+IOBA_UBMNT, IO_UBA1+IOBA_UBMNT+IOLN_UBMNT,
|
||||
NULL, &rd_zro, &wr_nop }, /* Unibus 1 maint */
|
||||
{ IO_UBA3+IOBA_UBMNT, IO_UBA3+IOBA_UBMNT+IOLN_UBMNT,
|
||||
NULL, &rd_zro, &wr_nop }, /* Unibus 3 maint */
|
||||
{ IO_UBA3+IOBA_TCU, IO_UBA3+IOBA_TCU+IOLN_TCU,
|
||||
NULL, &tcu_rd, &wr_nop }, /* TCU150 */
|
||||
{ 00100000, 00100000, NULL, &rd_zro, &wr_nop }, /* Mem sys stat */
|
||||
{ 0, 0, 0, NULL, NULL } };
|
||||
DIB *dib_tab[] = {
|
||||
&rp_dib,
|
||||
&tu_dib,
|
||||
&dz_dib,
|
||||
&lp20_dib,
|
||||
&pt_dib,
|
||||
&tcu_dib,
|
||||
&ubmp1_dib,
|
||||
&ubmp3_dib,
|
||||
&ubcs1_dib,
|
||||
&ubcs3_dib,
|
||||
&ubmn1_dib,
|
||||
&ubmn3_dib,
|
||||
&msys_dib,
|
||||
NULL };
|
||||
|
||||
/* Interrupt request to interrupt action map */
|
||||
|
||||
int32 (*int_ack[32])() = { /* int ack routines */
|
||||
NULL, NULL, NULL, NULL, NULL, NULL, &rp_inta, &tu_inta,
|
||||
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
&dz_rxinta, &dz_txinta, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
NULL, NULL, &lp20_inta, NULL, NULL, NULL, NULL, NULL };
|
||||
|
||||
/* Interrupt request to vector map */
|
||||
@@ -393,14 +373,14 @@ return;
|
||||
|
||||
d10 ReadIO (a10 ea)
|
||||
{
|
||||
int32 n, pa, val;
|
||||
struct iolink *p;
|
||||
uint32 pa = (uint32) ea;
|
||||
int32 i, n, val;
|
||||
DIB *dibp;
|
||||
|
||||
pa = (int32) ea; /* cvt addr to 32b */
|
||||
for (p = &iotable[0]; p -> low != 0; p++ ) {
|
||||
if ((pa >= p -> low) && (pa < p -> high) &&
|
||||
((p -> enb == NULL) || *p -> enb)) {
|
||||
p -> read (&val, pa, READ);
|
||||
for (i = 0; dibp = dib_tab[i]; i++ ) {
|
||||
if (dibp -> enb && (pa >= dibp -> ba) &&
|
||||
(pa < (dibp -> ba + dibp -> lnt))) {
|
||||
dibp -> rd (&val, pa, READ);
|
||||
pi_eval ();
|
||||
return ((d10) val); } }
|
||||
UBNXM_FAIL (pa, READ);
|
||||
@@ -408,14 +388,14 @@ UBNXM_FAIL (pa, READ);
|
||||
|
||||
void WriteIO (a10 ea, d10 val, int32 mode)
|
||||
{
|
||||
int32 n, pa;
|
||||
struct iolink *p;
|
||||
uint32 pa = (uint32) ea;
|
||||
int32 i, n;
|
||||
DIB *dibp;
|
||||
|
||||
pa = (int32) ea; /* cvt addr to 32b */
|
||||
for (p = &iotable[0]; p -> low != 0; p++ ) {
|
||||
if ((pa >= p -> low) && (pa < p -> high) &&
|
||||
((p -> enb == NULL) || *p -> enb)) {
|
||||
p -> write ((int32) val, pa, mode);
|
||||
for (i = 0; dibp = dib_tab[i]; i++ ) {
|
||||
if (dibp -> enb && (pa >= dibp -> ba) &&
|
||||
(pa < (dibp -> ba + dibp -> lnt))) {
|
||||
dibp -> wr ((int32) val, pa, mode);
|
||||
pi_eval ();
|
||||
return; } }
|
||||
UBNXM_FAIL (pa, mode);
|
||||
@@ -549,3 +529,87 @@ for (uba = 0; uba < UBANUM; uba++) {
|
||||
pi_eval ();
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Change device number for a device */
|
||||
|
||||
t_stat set_addr (UNIT *uptr, int32 val, char *cptr, void *desc)
|
||||
{
|
||||
DIB *dibp;
|
||||
uint32 newba;
|
||||
t_stat r;
|
||||
|
||||
if (cptr == NULL) return SCPE_ARG;
|
||||
if ((val == 0) || (desc == NULL)) return SCPE_IERR;
|
||||
dibp = (DIB *) desc;
|
||||
newba = (uint32) get_uint (cptr, 8, PAMASK, &r); /* get new */
|
||||
if ((r != SCPE_OK) || (newba == dibp -> ba)) return r;
|
||||
if ((newba & AMASK) <= IOPAGEBASE) return SCPE_ARG; /* must be > 0 */
|
||||
if (newba % ((uint32) val)) return SCPE_ARG; /* check modulus */
|
||||
if (GET_IOUBA (newba) != GET_IOUBA (dibp -> ba)) return SCPE_ARG;
|
||||
if (dev_conflict (newba, dibp)) return SCPE_OK;
|
||||
dibp -> ba = newba; /* store */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Show device address */
|
||||
|
||||
t_stat show_addr (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||
{
|
||||
DIB *dibp;
|
||||
|
||||
if (desc == NULL) return SCPE_IERR;
|
||||
dibp = (DIB *) desc;
|
||||
if (dibp -> ba <= IOPAGEBASE) return SCPE_IERR;
|
||||
fprintf (st, "address=%07o", dibp -> ba);
|
||||
if (dibp -> lnt > 1)
|
||||
fprintf (st, "-%07o", dibp -> ba + dibp -> lnt - 1);
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Enable or disable a device */
|
||||
|
||||
t_stat set_enbdis (UNIT *uptr, int32 val, char *cptr, void *desc)
|
||||
{
|
||||
int32 i;
|
||||
DEVICE *dptr;
|
||||
DIB *dibp;
|
||||
UNIT *up;
|
||||
|
||||
if (cptr != NULL) return SCPE_ARG;
|
||||
if ((uptr == NULL) || (desc == NULL)) return SCPE_IERR;
|
||||
dptr = find_dev_from_unit (uptr); /* find device */
|
||||
if (dptr == NULL) return SCPE_IERR;
|
||||
dibp = (DIB *) desc;
|
||||
if ((val ^ dibp -> enb) == 0) return SCPE_OK; /* enable chg? */
|
||||
if (val) { /* enable? */
|
||||
if (dev_conflict (dibp -> ba, dibp)) return SCPE_OK; }
|
||||
else { /* disable */
|
||||
for (i = 0; i < dptr -> numunits; i++) { /* check units */
|
||||
up = (dptr -> units) + i;
|
||||
if ((up -> flags & UNIT_ATT) || sim_is_active (up))
|
||||
return SCPE_NOFNC; } }
|
||||
dibp -> enb = val;
|
||||
if (dptr -> reset) return dptr -> reset (dptr);
|
||||
else return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Test for conflict in device addresses */
|
||||
|
||||
t_bool dev_conflict (uint32 nba, DIB *curr)
|
||||
{
|
||||
uint32 i, end;
|
||||
DIB *dibp;
|
||||
|
||||
end = nba + curr -> lnt - 1; /* get end */
|
||||
for (i = 0; dibp = dib_tab[i]; i++) { /* loop thru dev */
|
||||
if (!dibp -> enb || (dibp == curr)) continue; /* skip disabled */
|
||||
if (((nba >= dibp -> ba) &&
|
||||
(nba < (dibp -> ba + dibp -> lnt))) ||
|
||||
((end >= dibp -> ba) &&
|
||||
(end < (dibp -> ba + dibp -> lnt)))) {
|
||||
printf ("Device address conflict at %07o\n", dibp -> ba);
|
||||
if (sim_log) fprintf (sim_log,
|
||||
"Device number conflict at %07o\n", dibp -> ba);
|
||||
return TRUE; } }
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* pdp10_lp20.c: PDP-10 LP20 line printer simulator
|
||||
|
||||
Copyright (c) 1993-2001, Robert M Supnik
|
||||
Copyright (c) 1993-2002, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -25,6 +25,8 @@
|
||||
|
||||
lp20 line printer
|
||||
|
||||
30-May-02 RMS Widened POS to 32b
|
||||
06-Jan-02 RMS Added enable/disable support
|
||||
30-Nov-01 RMS Added extended SET/SHOW support
|
||||
*/
|
||||
|
||||
@@ -150,6 +152,9 @@ int32 lp20_irq = 0; /* int request */
|
||||
int32 lp20_stopioe = 0; /* stop on error */
|
||||
int16 txram[TX_SIZE] = { 0 }; /* translation RAM */
|
||||
int16 davfu[DV_SIZE] = { 0 }; /* DAVFU */
|
||||
|
||||
t_stat lp20_rd (int32 *data, int32 pa, int32 access);
|
||||
t_stat lp20_wr (int32 data, int32 pa, int32 access);
|
||||
t_stat lp20_svc (UNIT *uptr);
|
||||
t_stat lp20_reset (DEVICE *dptr);
|
||||
t_stat lp20_attach (UNIT *uptr, char *ptr);
|
||||
@@ -167,6 +172,8 @@ void update_lpcs (int32 flg);
|
||||
lp20_reg LPT register list
|
||||
*/
|
||||
|
||||
DIB lp20_dib = { 1, IOBA_LP20, IOLN_LP20, &lp20_rd, &lp20_wr };
|
||||
|
||||
UNIT lp20_unit = {
|
||||
UDATA (&lp20_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_OUT_WAIT };
|
||||
|
||||
@@ -188,7 +195,7 @@ REG lp20_reg[] = {
|
||||
{ FLDATA (ERR, lpcsa, CSR_V_ERR) },
|
||||
{ FLDATA (DONE, lpcsa, CSR_V_DONE) },
|
||||
{ FLDATA (IE, lpcsa, CSR_V_IE) },
|
||||
{ DRDATA (POS, lp20_unit.pos, 31), PV_LEFT },
|
||||
{ DRDATA (POS, lp20_unit.pos, 32), PV_LEFT },
|
||||
{ DRDATA (TIME, lp20_unit.wait, 24), PV_LEFT },
|
||||
{ FLDATA (STOP_IOE, lp20_stopioe, 0) },
|
||||
{ BRDATA (TXRAM, txram, 8, 12, TX_SIZE) },
|
||||
@@ -197,6 +204,12 @@ REG lp20_reg[] = {
|
||||
|
||||
MTAB lp20_mod[] = {
|
||||
{ UNIT_DUMMY, 0, NULL, "VFUCLEAR", &lp20_clear_vfu },
|
||||
{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", "ADDRESS",
|
||||
&set_addr, &show_addr, &lp20_dib },
|
||||
{ MTAB_XTD|MTAB_VDV, 1, NULL, "ENABLED",
|
||||
&set_enbdis, NULL, &lp20_dib },
|
||||
{ MTAB_XTD|MTAB_VDV, 0, NULL, "DISABLED",
|
||||
&set_enbdis, NULL, &lp20_dib },
|
||||
{ 0 } };
|
||||
|
||||
DEVICE lp20_dev = {
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* pdp10_mdfp.c: PDP-10 multiply/divide and floating point simulator
|
||||
|
||||
Copyright (c) 1993-2001, Robert M Supnik
|
||||
Copyright (c) 1993-2002, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* pdp10_pag.c: PDP-10 paging subsystem simulator
|
||||
|
||||
Copyright (c) 1993-2001, Robert M Supnik
|
||||
Copyright (c) 1993-2002, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* pdp10_pt.c: PDP-10 Unibus paper tape reader/punch simulator
|
||||
|
||||
Copyright (c) 1993-2001, Robert M Supnik
|
||||
Copyright (c) 1993-2002, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -26,6 +26,8 @@
|
||||
ptr paper tape reader
|
||||
ptp paper tape punch
|
||||
|
||||
30-May-02 RMS Widened POS to 32b
|
||||
06-Jan-02 RMS Revised enable/disable support
|
||||
29-Nov-01 RMS Added read only unit support
|
||||
07-Sep-01 RMS Revised disable mechanism
|
||||
*/
|
||||
@@ -42,7 +44,9 @@ int32 ptr_csr = 0; /* control/status */
|
||||
int32 ptr_stopioe = 0; /* stop on error */
|
||||
int32 ptp_csr = 0; /* control/status */
|
||||
int32 ptp_stopioe = 0; /* stop on error */
|
||||
int32 pt_enb = 0; /* device enable */
|
||||
|
||||
t_stat pt_rd (int32 *data, int32 PA, int32 access);
|
||||
t_stat pt_wr (int32 data, int32 PA, int32 access);
|
||||
t_stat ptr_svc (UNIT *uptr);
|
||||
t_stat ptp_svc (UNIT *uptr);
|
||||
t_stat ptr_reset (DEVICE *dptr);
|
||||
@@ -59,6 +63,8 @@ t_stat ptp_detach (UNIT *uptr);
|
||||
ptr_reg PTR register list
|
||||
*/
|
||||
|
||||
DIB pt_dib = { 0, IOBA_PT, IOLN_PT, &pt_rd, &pt_wr };
|
||||
|
||||
UNIT ptr_unit = {
|
||||
UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0),
|
||||
SERIAL_IN_WAIT };
|
||||
@@ -71,14 +77,23 @@ REG ptr_reg[] = {
|
||||
{ FLDATA (BUSY, ptr_csr, CSR_V_BUSY) },
|
||||
{ FLDATA (DONE, ptr_csr, CSR_V_DONE) },
|
||||
{ FLDATA (IE, ptr_csr, CSR_V_IE) },
|
||||
{ DRDATA (POS, ptr_unit.pos, 31), PV_LEFT },
|
||||
{ DRDATA (POS, ptr_unit.pos, 32), PV_LEFT },
|
||||
{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },
|
||||
{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
|
||||
{ FLDATA (*DEVENB, pt_enb, 0), REG_HRO },
|
||||
{ FLDATA (*DEVENB, pt_dib.enb, 0), REG_HRO },
|
||||
{ NULL } };
|
||||
|
||||
MTAB ptr_mod[] = {
|
||||
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
|
||||
NULL, &show_addr, &pt_dib },
|
||||
{ MTAB_XTD|MTAB_VDV, 1, NULL, "ENABLED",
|
||||
&set_enbdis, NULL, &pt_dib },
|
||||
{ MTAB_XTD|MTAB_VDV, 0, NULL, "DISABLED",
|
||||
&set_enbdis, NULL, &pt_dib },
|
||||
{ 0 } };
|
||||
|
||||
DEVICE ptr_dev = {
|
||||
"PTR", &ptr_unit, ptr_reg, NULL,
|
||||
"PTR", &ptr_unit, ptr_reg, ptr_mod,
|
||||
1, 10, 31, 1, 8, 8,
|
||||
NULL, NULL, &ptr_reset,
|
||||
NULL, &ptr_attach, &ptr_detach };
|
||||
@@ -100,14 +115,23 @@ REG ptp_reg[] = {
|
||||
{ FLDATA (ERR, ptp_csr, CSR_V_ERR) },
|
||||
{ FLDATA (DONE, ptp_csr, CSR_V_DONE) },
|
||||
{ FLDATA (IE, ptp_csr, CSR_V_IE) },
|
||||
{ DRDATA (POS, ptp_unit.pos, 31), PV_LEFT },
|
||||
{ DRDATA (POS, ptp_unit.pos, 32), PV_LEFT },
|
||||
{ DRDATA (TIME, ptp_unit.wait, 24), PV_LEFT },
|
||||
{ FLDATA (STOP_IOE, ptp_stopioe, 0) },
|
||||
{ FLDATA (*DEVENB, pt_enb, 0), REG_HRO },
|
||||
{ FLDATA (*DEVENB, pt_dib.enb, 0), REG_HRO },
|
||||
{ NULL } };
|
||||
|
||||
MTAB ptp_mod[] = {
|
||||
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
|
||||
NULL, &show_addr, &pt_dib },
|
||||
{ MTAB_XTD|MTAB_VDV, 1, NULL, "ENABLED",
|
||||
&set_enbdis, NULL, &pt_dib },
|
||||
{ MTAB_XTD|MTAB_VDV, 0, NULL, "DISABLED",
|
||||
&set_enbdis, NULL, &pt_dib },
|
||||
{ 0 } };
|
||||
|
||||
DEVICE ptp_dev = {
|
||||
"PTP", &ptp_unit, ptp_reg, NULL,
|
||||
"PTP", &ptp_unit, ptp_reg, ptp_mod,
|
||||
1, 10, 31, 1, 8, 8,
|
||||
NULL, NULL, &ptp_reset,
|
||||
NULL, &ptp_attach, &ptp_detach };
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* pdp10_rp.c - RH11/RP04/05/06/07 RM02/03/05/80 "Massbus" disk controller
|
||||
|
||||
Copyright (c) 1993-2001, Robert M Supnik
|
||||
Copyright (c) 1993-2002, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -339,14 +339,16 @@ int reg_in_drive[32] = {
|
||||
0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 1, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
|
||||
|
||||
void update_rpcs (int32 flags, int32 drv);
|
||||
void rp_go (int32 drv, int32 fnc);
|
||||
t_stat rp_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||
t_stat rp_rd (int32 *data, int32 PA, int32 access);
|
||||
t_stat rp_wr (int32 data, int32 PA, int32 access);
|
||||
t_stat rp_svc (UNIT *uptr);
|
||||
t_stat rp_reset (DEVICE *dptr);
|
||||
t_stat rp_boot (int32 unitno);
|
||||
t_stat rp_attach (UNIT *uptr, char *cptr);
|
||||
t_stat rp_detach (UNIT *uptr);
|
||||
void update_rpcs (int32 flags, int32 drv);
|
||||
void rp_go (int32 drv, int32 fnc);
|
||||
t_stat rp_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||
|
||||
/* RP data structures
|
||||
|
||||
@@ -356,6 +358,8 @@ t_stat rp_detach (UNIT *uptr);
|
||||
rp_mod RP modifier list
|
||||
*/
|
||||
|
||||
DIB rp_dib = { 1, IOBA_RP, IOLN_RP, &rp_rd, &rp_wr };
|
||||
|
||||
UNIT rp_unit[] = {
|
||||
{ UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
|
||||
UNIT_ROABLE+(RP06_DTYPE << UNIT_V_DTYPE), RP06_SIZE) },
|
||||
@@ -406,7 +410,7 @@ REG rp_reg[] = {
|
||||
{ NULL } };
|
||||
|
||||
MTAB rp_mod[] = {
|
||||
{ UNIT_WLK, 0, "write enabled", "ENABLED", NULL },
|
||||
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
|
||||
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
|
||||
{ (UNIT_DTYPE+UNIT_ATT), (RM03_DTYPE << UNIT_V_DTYPE) + UNIT_ATT,
|
||||
"RM03", NULL, NULL },
|
||||
@@ -446,6 +450,8 @@ MTAB rp_mod[] = {
|
||||
NULL, "RM05", &rp_set_size },
|
||||
{ (UNIT_AUTO+UNIT_DTYPE), (RP07_DTYPE << UNIT_V_DTYPE),
|
||||
NULL, "RP07", &rp_set_size },
|
||||
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
|
||||
NULL, &show_addr, &rp_dib },
|
||||
{ 0 } };
|
||||
|
||||
DEVICE rp_dev = {
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* pdp10_sys.c: PDP-10 simulator interface
|
||||
|
||||
Copyright (c) 1993-2001, Robert M Supnik
|
||||
Copyright (c) 1993-2002, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -23,6 +23,7 @@
|
||||
be used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from Robert M Supnik.
|
||||
|
||||
22-Apr-02 RMS Removed magtape record length error
|
||||
17-Sep-01 RMS Removed multiconsole support
|
||||
25-Aug-01 RMS Enabled DZ11
|
||||
27-May-01 RMS Added multiconsole support
|
||||
@@ -72,9 +73,9 @@ DEVICE *sim_devices[] = {
|
||||
&ptr_dev,
|
||||
&ptp_dev,
|
||||
&lp20_dev,
|
||||
&dz_dev,
|
||||
&rp_dev,
|
||||
&tu_dev,
|
||||
&dz_dev,
|
||||
NULL };
|
||||
|
||||
const char *sim_stop_messages[] = {
|
||||
@@ -89,7 +90,6 @@ const char *sim_stop_messages[] = {
|
||||
"Nested indirect address limit exceeded",
|
||||
"Nested XCT limit exceeded",
|
||||
"Invalid I/O controller",
|
||||
"Invalid magtape record length",
|
||||
"Address stop",
|
||||
"Panic stop" };
|
||||
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* pdp10_tim.c: PDP-10 tim subsystem simulator
|
||||
|
||||
Copyright (c) 1993-2001, Robert M Supnik
|
||||
Copyright (c) 1993-2002, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -25,6 +25,7 @@
|
||||
|
||||
tim timer subsystem
|
||||
|
||||
06-Jan-02 RMS Added enable/disable support
|
||||
02-Dec-01 RMS Fixed bug in ITS PC sampling (found by Dave Conroy)
|
||||
31-Aug-01 RMS Changed int64 to t_int64 for Windoze
|
||||
17-Jul-01 RMS Moved function prototype
|
||||
@@ -54,6 +55,8 @@ d10 quant = 0; /* ITS quantum */
|
||||
int32 diagflg = 0; /* diagnostics? */
|
||||
int32 tmxr_poll = TIM_DELAY * DZ_MULT; /* term mux poll */
|
||||
|
||||
t_stat tcu_rd (int32 *data, int32 PA, int32 access);
|
||||
extern t_stat wr_nop (int32 data, int32 PA, int32 access);
|
||||
t_stat tim_svc (UNIT *uptr);
|
||||
t_stat tim_reset (DEVICE *dptr);
|
||||
extern d10 Read (a10 ea, int32 prv);
|
||||
@@ -69,6 +72,8 @@ extern int32 pi_eval (void);
|
||||
tim_reg TIM register list
|
||||
*/
|
||||
|
||||
DIB tcu_dib = { 1, IOBA_TCU, IOLN_TCU, &tcu_rd, &wr_nop };
|
||||
|
||||
UNIT tim_unit = { UDATA (&tim_svc, 0, 0), TIM_DELAY };
|
||||
|
||||
REG tim_reg[] = {
|
||||
@@ -84,6 +89,12 @@ REG tim_reg[] = {
|
||||
MTAB tim_mod[] = {
|
||||
{ UNIT_Y2K, 0, "non Y2K OS", "NOY2K", NULL },
|
||||
{ UNIT_Y2K, UNIT_Y2K, "Y2K OS", "Y2K", NULL },
|
||||
{ MTAB_XTD|MTAB_VDV, 000, "ADDRESS", NULL,
|
||||
NULL, &show_addr, &tcu_dib },
|
||||
{ MTAB_XTD|MTAB_VDV, 1, NULL, "ENABLED",
|
||||
&set_enbdis, NULL, &tcu_dib },
|
||||
{ MTAB_XTD|MTAB_VDV, 0, NULL, "DISABLED",
|
||||
&set_enbdis, NULL, &tcu_dib },
|
||||
{ 0 } };
|
||||
|
||||
DEVICE tim_dev = {
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* pdp10_tu.c - PDP-10 RH11/TM03/TU45 magnetic tape simulator
|
||||
|
||||
Copyright (c) 1993-2001, Robert M Supnik
|
||||
Copyright (c) 1993-2002, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -25,6 +25,9 @@
|
||||
|
||||
tu RH11/TM03/TU45 magtape
|
||||
|
||||
30-May-02 RMS Widened POS to 32b
|
||||
22-Apr-02 RMS Changed record length error code
|
||||
06-Jan-02 RMS Revised enable/disable support
|
||||
30-Nov-01 RMS Added read only unit, extended SET/SHOW support
|
||||
24-Nov-01 RMS Changed POS, FLG, UST to arrays
|
||||
23-Oct-01 RMS Fixed bug in error interrupts
|
||||
@@ -296,6 +299,8 @@ int fmt_test[16] = { /* fmt bytes/10 wd */
|
||||
int den_test[8] = { /* valid densities */
|
||||
0, 0, 0, 1, 1, 0, 0, 0 };
|
||||
|
||||
t_stat tu_rd (int32 *data, int32 PA, int32 access);
|
||||
t_stat tu_wr (int32 data, int32 PA, int32 access);
|
||||
t_stat tu_svc (UNIT *uptr);
|
||||
t_stat tu_reset (DEVICE *dptr);
|
||||
t_stat tu_attach (UNIT *uptr, char *cptr);
|
||||
@@ -313,6 +318,8 @@ t_stat tu_vlock (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||
tu_mod TU modifier list
|
||||
*/
|
||||
|
||||
DIB tu_dib = { 1, IOBA_TU, IOLN_TU, &tu_rd, &tu_wr };
|
||||
|
||||
UNIT tu_unit[] = {
|
||||
{ UDATA (&tu_svc, UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE, 0) },
|
||||
{ UDATA (&tu_svc, UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE, 0) },
|
||||
@@ -342,7 +349,7 @@ REG tu_reg[] = {
|
||||
{ FLDATA (STOP_IOE, tu_stopioe, 0) },
|
||||
{ DRDATA (TIME, tu_time, 24), PV_LEFT },
|
||||
{ URDATA (UST, tu_unit[0].USTAT, 8, 17, 0, TU_NUMDR, 0) },
|
||||
{ URDATA (POS, tu_unit[0].pos, 8, 31, 0,
|
||||
{ URDATA (POS, tu_unit[0].pos, 8, 32, 0,
|
||||
TU_NUMDR, PV_LEFT | REG_RO) },
|
||||
{ URDATA (FLG, tu_unit[0].flags, 8, UNIT_W_UF, UNIT_V_UF - 1,
|
||||
TU_NUMDR, REG_HRO) },
|
||||
@@ -350,8 +357,10 @@ REG tu_reg[] = {
|
||||
{ NULL } };
|
||||
|
||||
MTAB tu_mod[] = {
|
||||
{ UNIT_WLK, 0, "write enabled", "ENABLED", &tu_vlock },
|
||||
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", &tu_vlock },
|
||||
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", &tu_vlock },
|
||||
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
|
||||
NULL, &show_addr, &tu_dib },
|
||||
{ 0 } };
|
||||
|
||||
DEVICE tu_dev = {
|
||||
@@ -763,7 +772,7 @@ case FNC_WCHKF: /* wcheck = read */
|
||||
tufs = tufs | FS_TMK;
|
||||
uptr -> pos = uptr -> pos + sizeof (t_mtrlnt);
|
||||
break; }
|
||||
if (tbc > XBUFLNT) return STOP_MTRLNT; /* bad rec length? */
|
||||
if (tbc > XBUFLNT) return SCPE_MTRLNT; /* bad rec length? */
|
||||
i = fxread (xbuf, sizeof (int8), tbc, uptr -> fileref);
|
||||
for ( ; i < tbc + 4; i++) xbuf[i] = 0; /* fill/pad with 0's */
|
||||
err = ferror (uptr -> fileref);
|
||||
@@ -825,7 +834,7 @@ case FNC_WCHKR: /* wcheck = read */
|
||||
tufs = tufs | FS_TMK;
|
||||
uptr -> pos = uptr -> pos - sizeof (t_mtrlnt);
|
||||
break; }
|
||||
if (tbc > XBUFLNT) return STOP_MTRLNT; /* bad rec length? */
|
||||
if (tbc > XBUFLNT) return SCPE_MTRLNT; /* bad rec length? */
|
||||
fseek (uptr -> fileref, uptr -> pos - sizeof (t_mtrlnt)
|
||||
- ((tbc + 1) & ~1), SEEK_SET);
|
||||
fxread (xbuf + 4, sizeof (int8), tbc, uptr -> fileref);
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* pdp10_xtnd.c: PDP-10 extended instruction simulator
|
||||
|
||||
Copyright (c) 1993-2001, Robert M Supnik
|
||||
Copyright (c) 1993-2002, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
|
||||
Reference in New Issue
Block a user