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Code Releases Activity

Notes For V2.9-11

Browse Source 
1. New Features

1.1 GRI-909

- This is a new simulator for the GRI-909.
- It has been hand-tested; so far, no software has been discovered.

1.2 VAX

- SET CPU CONHALT will cause a HALT instruction to return to the
  boot ROM console rather than to SIMH.  SET CPU SIMHALT restores
  the default behavior.
- BRB/W self at IPL 1F stops the simulator.  This is the default
  behavior of VMS at exit.

1.3 PDP-18b

- ATTACH -A PTR/PTP attaches the reader and punch in ASCII mode.
  In ASCII mode, the reader automatically sets the high order bit
  of incoming alphabetic data, and the punch clears the high order
  bit of outgoing data.

1.4 SCP

- DO -V echoes commands from the file as they are executed.
- Under Windows, execution priority is set BELOW_NORMAL when the
  simulator is running.

2. Release Notes

2.1 Bugs Fixed

- PDP-11 CPU: fixed updating of MMR0 on a memory management error.
- VAX FPA: changed function names to avoid conflict with C math library.
- 1401 MT: read end of record generates group mark without word mark.
- 1401 DP: fixed address generation and checking.
- SCP: an EXIT within a DO command will cause the simulator to exit.

3. In Progress

- Interdata 16b/32b: coded, not tested.
- SDS 940: coded, not tested.
- IBM 1620: coded, not tested.

If you would like to help with the debugging of the untested simulators,
they can be made available by special request.
This commit is contained in:
Bob Supnik
2002-07-14 15:20:00 -07:00
committed by Mark Pizzolato
parent 701f0fe028
commit df6475181c
179 changed files with 36441 additions and 4464 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
PDP8/pdp8_clk.c
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@@ -1,6 +1,6 @@
/* pdp8_clk.c: PDP-8 real-time clock simulator
Copyright (c) 1993-2001, Robert M Supnik
Copyright (c) 1993-2002, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
clk real time clock
30-Dec-01 RMS Removed for generalized timers
05-Sep-01 RMS Added terminal multiplexor support
17-Jul-01 RMS Moved function prototype
05-Mar-01 RMS Added clock calibration support
@@ -109,7 +110,7 @@ int32 t;
dev_done = dev_done | INT_CLK; /* set done */
int_req = INT_UPDATE; /* update interrupts */
t = sim_rtc_calb (clk_tps); /* calibrate clock */
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate (&clk_unit, t); /* reactivate unit */
tmxr_poll = t; /* set mux poll */
return SCPE_OK;
@@ -123,6 +124,5 @@ dev_done = dev_done & ~INT_CLK; /* clear done, int */
int_req = int_req & ~INT_CLK;
int_enable = int_enable & ~INT_CLK; /* clear enable */
sim_activate (&clk_unit, clk_unit.wait); /* activate unit */
tmxr_poll = clk_unit.wait; /* set mux poll */
return SCPE_OK;
}

138
PDP8/pdp8_cpu.c
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@@ -1,6 +1,6 @@
/* pdp8_cpu.c: PDP-8 CPU simulator
Copyright (c) 1993-2001, Robert M Supnik
Copyright (c) 1993-2002, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,8 @@
cpu central processor
06-Jan-02 RMS Added device enable/disable routines
30-Dec-01 RMS Added old PC queue
16-Dec-01 RMS Fixed bugs in EAE
07-Dec-01 RMS Revised to use new breakpoint package
30-Nov-01 RMS Added RL8A, extended SET/SHOW support
@@ -179,6 +181,9 @@
#include "pdp8_defs.h"
#define PCQ_SIZE 64 /* must be 2**n */
#define PCQ_MASK (PCQ_SIZE - 1)
#define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = PC
#define UNIT_V_NOEAE (UNIT_V_UF) /* EAE absent */
#define UNIT_NOEAE (1 << UNIT_V_NOEAE)
#define UNIT_V_MSIZE (UNIT_V_UF+1) /* dummy mask */
@@ -197,19 +202,47 @@ int32 SC = 0; /* EAE shift count */
int32 UB = 0; /* User mode Buffer */
int32 UF = 0; /* User mode Flag */
int32 OSR = 0; /* Switch Register */
int32 old_PC = 0; /* old PC */
int16 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
int32 pcq_p = 0; /* PC queue ptr */
REG *pcq_r = NULL; /* PC queue reg ptr */
int32 dev_done = 0; /* dev done flags */
int32 int_enable = INT_INIT_ENABLE; /* intr enables */
int32 int_req = 0; /* intr requests */
int32 dev_enb = -1 & ~INT_DF & ~INT_RL; /* device enables */
int32 stop_inst = 0; /* trap on ill inst */
extern int32 sim_interval;
extern int32 sim_int_char;
extern int32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern UNIT clk_unit, ttix_unit;
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_reset (DEVICE *dptr);
t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
extern int32 tti (int32 pulse, int32 AC);
extern int32 tto (int32 pulse, int32 AC);
extern int32 ptr (int32 pulse, int32 AC);
extern int32 ptp (int32 pulse, int32 AC);
extern int32 clk (int32 pulse, int32 AC);
extern int32 lpt (int32 pulse, int32 AC);
extern int32 ttix (int32 inst, int32 AC);
extern int32 ttox (int32 inst, int32 AC);
extern int32 rk (int32 pulse, int32 AC);
extern int32 rx (int32 pulse, int32 AC);
extern int32 df60 (int32 pulse, int32 AC);
extern int32 df61 (int32 pulse, int32 AC);
extern int32 df62 (int32 pulse, int32 AC);
extern int32 rf60 (int32 pulse, int32 AC);
extern int32 rf61 (int32 pulse, int32 AC);
extern int32 rf62 (int32 pulse, int32 AC);
extern int32 rf64 (int32 pulse, int32 AC);
extern int32 rl60 (int32 pulse, int32 AC);
extern int32 rl61 (int32 pulse, int32 AC);
extern int32 mt70 (int32 pulse, int32 AC);
extern int32 mt71 (int32 pulse, int32 AC);
extern int32 mt72 (int32 pulse, int32 AC);
extern int32 dt76 (int32 pulse, int32 AC);
extern int32 dt77 (int32 pulse, int32 AC);
/* CPU data structures
@@ -245,7 +278,8 @@ REG cpu_reg[] = {
{ ORDATA (DONE, dev_done, INT_V_DIRECT), REG_RO },
{ ORDATA (ENABLE, int_enable, INT_V_DIRECT), REG_RO },
{ FLDATA (NOEAE, cpu_unit.flags, UNIT_V_NOEAE), REG_HRO },
{ ORDATA (OLDPC, old_PC, 15), REG_RO },
{ BRDATA (PCQ, pcq, 8, 15, PCQ_SIZE), REG_RO+REG_CIRC },
{ ORDATA (PCQP, pcq_p, 6), REG_HRO },
{ FLDATA (STOP_INST, stop_inst, 0) },
{ ORDATA (WRU, sim_int_char, 8) },
{ ORDATA (DEVENB, dev_enb, 32), REG_HRO },
@@ -272,36 +306,10 @@ DEVICE cpu_dev = {
t_stat sim_instr (void)
{
extern int32 sim_interval;
int32 IR, MB, IF, DF, LAC, MQ;
t_addr PC, MA;
int32 device, pulse, temp, iot_data;
t_stat reason;
extern UNIT clk_unit;
extern int32 tti (int32 pulse, int32 AC);
extern int32 tto (int32 pulse, int32 AC);
extern int32 ptr (int32 pulse, int32 AC);
extern int32 ptp (int32 pulse, int32 AC);
extern int32 clk (int32 pulse, int32 AC);
extern int32 lpt (int32 pulse, int32 AC);
extern int32 ttix (int32 inst, int32 AC);
extern int32 ttox (int32 inst, int32 AC);
extern int32 rk (int32 pulse, int32 AC);
extern int32 rx (int32 pulse, int32 AC);
extern int32 df60 (int32 pulse, int32 AC);
extern int32 df61 (int32 pulse, int32 AC);
extern int32 df62 (int32 pulse, int32 AC);
extern int32 rf60 (int32 pulse, int32 AC);
extern int32 rf61 (int32 pulse, int32 AC);
extern int32 rf62 (int32 pulse, int32 AC);
extern int32 rf64 (int32 pulse, int32 AC);
extern int32 rl60 (int32 pulse, int32 AC);
extern int32 rl61 (int32 pulse, int32 AC);
extern int32 mt70 (int32 pulse, int32 AC);
extern int32 mt71 (int32 pulse, int32 AC);
extern int32 mt72 (int32 pulse, int32 AC);
extern int32 dt76 (int32 pulse, int32 AC);
extern int32 dt77 (int32 pulse, int32 AC);
/* Restore register state */
@@ -312,7 +320,8 @@ LAC = saved_LAC & 017777;
MQ = saved_MQ & 07777;
int_req = INT_UPDATE;
reason = 0;
sim_rtc_init (clk_unit.wait); /* init calibration */
sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init clk calib */
sim_rtcn_init (ttix_unit.wait, TMR_TTX); /* init ttx calib */
/* Main instruction fetch/decode loop */
@@ -324,7 +333,8 @@ if (int_req > INT_PENDING) { /* interrupt? */
int_req = int_req & ~INT_ION; /* interrupts off */
SF = (UF << 6) | (IF >> 9) | (DF >> 12); /* form save field */
IF = IB = DF = UF = UB = 0; /* clear mem ext */
old_PC = M[0] = PC; /* save PC in 0 */
PCQ_ENTRY; /* save old PC */
M[0] = PC; /* save PC in 0 */
PC = 1; } /* fetch next from 1 */
MA = IF | PC; /* form PC */
@@ -469,7 +479,7 @@ case 020: /* JMS, dir, zero */
ZERO_PAGE_J;
CHANGE_FIELD;
MA = IF | MA;
old_PC = PC;
PCQ_ENTRY;
if (MEM_ADDR_OK (MA)) M[MA] = PC;
PC = (MA + 1) & 07777;
break;
@@ -477,7 +487,7 @@ case 021: /* JMS, dir, curr */
CURR_PAGE_J;
CHANGE_FIELD;
MA = IF | MA;
old_PC = PC;
PCQ_ENTRY;
if (MEM_ADDR_OK (MA)) M[MA] = PC;
PC = (MA + 1) & 07777;
break;
@@ -486,7 +496,7 @@ case 022: /* JMS, indir, zero */
INDIRECT_J;
CHANGE_FIELD;
MA = IF | MA;
old_PC = PC;
PCQ_ENTRY;
if (MEM_ADDR_OK (MA)) M[MA] = PC;
PC = (MA + 1) & 07777;
break;
@@ -495,7 +505,7 @@ case 023: /* JMS, indir, curr */
INDIRECT_J;
CHANGE_FIELD;
MA = IF | MA;
old_PC = PC;
PCQ_ENTRY;
if (MEM_ADDR_OK (MA)) M[MA] = PC;
PC = (MA + 1) & 07777;
break;
@@ -505,27 +515,27 @@ case 023: /* JMS, indir, curr */
case 024: /* JMP, dir, zero */
ZERO_PAGE_J;
CHANGE_FIELD;
old_PC = PC;
PCQ_ENTRY;
PC = MA;
break;
case 025: /* JMP, dir, curr */
CURR_PAGE_J;
CHANGE_FIELD;
old_PC = PC;
PCQ_ENTRY;
PC = MA;
break;
case 026: /* JMP, indir, zero */
ZERO_PAGE;
INDIRECT_J;
CHANGE_FIELD;
old_PC = PC;
PCQ_ENTRY;
PC = MA;
break;
case 027: /* JMP, indir, curr */
CURR_PAGE;
INDIRECT_J;
CHANGE_FIELD;
old_PC = PC;
PCQ_ENTRY;
PC = MA;
break;
@@ -1022,11 +1032,13 @@ case 030:case 031:case 032:case 033: /* IOT */
case 013: /* CLK */
iot_data = clk (pulse, iot_data);
break;
case 040: case 042: case 044: case 046: /* KL8A in */
iot_data = ttix (IR, iot_data);
case 040: case 042: case 044: case 046: /* KL8JA in */
if (dev_enb & INT_TTI1) iot_data = ttix (IR, iot_data);
else reason = stop_inst;
break;
case 041: case 043: case 045: case 047: /* KL8A out */
iot_data = ttox (IR, iot_data);
case 041: case 043: case 045: case 047: /* KL8JA out */
if (dev_enb & INT_TTI1) iot_data = ttox (IR, iot_data);
else reason = stop_inst;
break;
case 060: /* DF32/RF08 */
if (dev_enb & INT_DF) iot_data = df60 (pulse, iot_data);
@@ -1091,6 +1103,7 @@ saved_PC = IF | (PC & 07777); /* save copies */
saved_DF = DF & 070000;
saved_LAC = LAC & 017777;
saved_MQ = MQ & 07777;
pcq_r -> qptr = pcq_p; /* update pc q ptr */
return reason;
} /* end sim_instr */
@@ -1101,6 +1114,9 @@ t_stat cpu_reset (DEVICE *dptr)
int_req = (int_req & ~INT_ION) | INT_NO_CIF_PENDING;
saved_DF = IB = saved_PC & 070000;
UF = UB = gtf = emode = 0;
pcq_r = find_reg ("PCQ", NULL, dptr);
if (pcq_r) pcq_r -> qptr = 0;
else return SCPE_IERR;
sim_brk_types = sim_brk_dflt = SWMASK ('E');
return SCPE_OK;
}
@@ -1139,3 +1155,39 @@ MEMSIZE = val;
for (i = MEMSIZE; i < MAXMEMSIZE; i++) M[i] = 0;
return SCPE_OK;
}
/* Device enable routine */
t_stat set_enb (UNIT *uptr, int32 val, char *cptr, void *desc)
{
DEVICE *dptr;
if (cptr != NULL) return SCPE_ARG;
if ((uptr == NULL) || (val == 0)) return SCPE_IERR;
dptr = find_dev_from_unit (uptr);
if (dptr == NULL) return SCPE_IERR;
dev_enb = dev_enb | val;
if (dptr -> reset) dptr -> reset (dptr);
return SCPE_OK;
}
/* Device disable routine */
t_stat set_dsb (UNIT *uptr, int32 val, char *cptr, void *desc)
{
int32 i;
DEVICE *dptr;
UNIT *up;
if (cptr != NULL) return SCPE_ARG;
if ((uptr == NULL) || (val == 0)) return SCPE_IERR;
dptr = find_dev_from_unit (uptr);
if (dptr == NULL) return SCPE_IERR;
for (i = 0; i < dptr -> numunits; i++) { /* check units */
up = (dptr -> units) + i;
if ((up -> flags & UNIT_ATT) || sim_is_active (up))
return SCPE_NOFNC; }
dev_enb = dev_enb & ~val;
if (dptr -> reset) dptr -> reset (dptr);
return SCPE_OK;
}

17
PDP8/pdp8_defs.h
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@@ -1,6 +1,6 @@
/* pdp8_defs.h: PDP-8 simulator definitions
Copyright (c) 1993-2001, Robert M Supnik
Copyright (c) 1993-2002, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -23,6 +23,7 @@
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
20-Jan-02 RMS Fixed bug in TTx interrupt enable initialization
25-Nov-01 RMS Added RL8A support
16-Sep-01 RMS Added multiple KL support
18-Mar-01 RMS Added DF32 support
@@ -57,6 +58,11 @@
#define IOT_SKP (1 << IOT_V_SKP)
#define IOT_REASON (1 << IOT_V_REASON)
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* stop on error */
/* Timers */
#define TMR_CLK 0 /* timer 0 = clock */
#define TMR_TTX 1 /* timer 1 = TTx */
/* Interrupt flags
@@ -138,6 +144,13 @@
#define INT_ION (1 << INT_V_ION)
#define INT_DEV_ENABLE ((1 << INT_V_DIRECT) - 1) /* devices w/enables */
#define INT_ALL ((1 << INT_V_OVHD) - 1) /* all interrupts */
#define INT_INIT_ENABLE (INT_TTI+INT_TTO+INT_PTR+INT_PTP+INT_LPT)
#define INT_INIT_ENABLE (INT_TTI+INT_TTO+INT_PTR+INT_PTP+INT_LPT) | \
(INT_TTI1+INT_TTI2+INT_TTI3+INT_TTI4) | \
(INT_TTO1+INT_TTO2+INT_TTO3+INT_TTO4)
#define INT_PENDING (INT_ION+INT_NO_CIF_PENDING+INT_NO_ION_PENDING)
#define INT_UPDATE ((int_req & ~INT_DEV_ENABLE) | (dev_done & int_enable))
/* Function prototypes */
t_stat set_enb (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat set_dsb (UNIT *uptr, int32 val, char *cptr, void *desc);

9
PDP8/pdp8_df.c
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@@ -1,6 +1,6 @@
/* pdp8_df.c: DF32 fixed head disk simulator
Copyright (c) 1993-2001, Robert M Supnik
Copyright (c) 1993-2002, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -118,8 +118,13 @@ REG df_reg[] = {
{ FLDATA (*DEVENB, dev_enb, INT_V_DF), REG_HRO },
{ NULL } };
MTAB df_mod[] = {
{ MTAB_XTD|MTAB_VDV, INT_DF, NULL, "ENABLED", &set_enb },
{ MTAB_XTD|MTAB_VDV, INT_DF, NULL, "DISABLED", &set_dsb },
{ 0 } };
DEVICE df_dev = {
"DF", &df_unit, df_reg, NULL,
"DF", &df_unit, df_reg, df_mod,
1, 8, 17, 1, 8, 12,
NULL, NULL, &df_reset,
&df_boot, NULL, NULL };

121
PDP8/pdp8_doc.txt
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@@ -1,14 +1,14 @@
To: Users
From: Bob Supnik
Subj: PDP-8 Simulator Usage
Date: 1-Dec-01
Date: 15-Jun-2002
COPYRIGHT NOTICE
The following copyright notice applies to both the SIMH source and binary:
Original code published in 1993-2001, written by Robert M Supnik
Copyright (c) 1993-2001, Robert M Supnik
Original code published in 1993-2002, written by Robert M Supnik
Copyright (c) 1993-2002, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -67,12 +67,12 @@ The PDP-8 simulator is configured as follows:
device simulates
name(s)
CPU PDP-8/E CPU with 32KW of memory
CPU PDP-8/E CPU with 4KW-32KW of memory
- KE8E extended arithmetic element (EAE)
- KM8E memory management and timeshare control
PTR,PTP PC8E paper tape reader/punch
TTI,TTO KL8E console terminal
TTI1-4,TTO1-4 KL8JA additional terminals
TTIX,TTOX KL8JA additional terminals
LPT LE8E line printer
CLK DK8E line frequency clock (also PDP-8/A compatible)
RK RK8E/RK05 cartridge disk controller with four drives
@@ -83,14 +83,14 @@ RX RX8E/RX01 floppy disk controller with two drives
DT TC08/TU56 DECtape controller with eight drives
MT TM8E/TU10 magnetic tape controller with eight drives
The RK, RF, DF, RL, RX, DT, and MT devices can be DISABLEd. The PDP-8
can support only one of the set {DF32, RF08, RL8A},since they use the same
IOT's. The simulator defaults to the RF08. To change the disk at device
addresses 60-61:
The RK, RF, DF, RL, RX, DT, MT, and TTIX/TTOX devices can be set DISABLEd.
The PDP-8 can support only one of the set {DF32, RF08, RL8A}, since they
use the same IOT's. The simulator defaults to the RF08. To change the
disk at device addresses 60-61:
ENABLE DF enable DF32, disable RF08 and RL8A
ENABLE RF enable RF08, disable DF32 and RL8A
ENABLE RL enable RL8A, disable DF32 and RF08
SET RF DISABLED disable RF08
SET DF ENABLED, or enable DF32
SET RL ENABLED enable RL8A
The PDP-8 simulator implements one unique stop condition: if an undefined
instruction (unimplemented IOT or OPR) is decoded, and register STOP_INST
@@ -149,7 +149,8 @@ control registers for the interrupt system.
INT 15 interrupt pending flags
DONE 15 device done flags
ENABLE 15 device interrupt enable flags
OLDPC 15 PC prior to last JMP, JMS, or interrupt
PCQ[0:63] 15 PC prior to last JMP, JMS, or interrupt;
most recent PC change first
STOP_INST 1 stop on undefined instruction
WRU 8 interrupt character
@@ -172,7 +173,7 @@ The paper tape reader implements these registers:
DONE 1 device done flag
ENABLE 1 interrupt enable flag
INT 1 interrupt pending flag
POS 31 position in the input file
POS 32 position in the input file
TIME 24 time from I/O initiation to interrupt
STOP_IOE 1 stop on I/O error
@@ -202,7 +203,7 @@ The paper tape punch implements these registers:
DONE 1 device done flag
ENABLE 1 interrupt enable flag
INT 1 interrupt pending flag
POS 31 position in the output file
POS 32 position in the output file
TIME 24 time from I/O initiation to interrupt
STOP_IOE 1 stop on I/O error
@@ -229,7 +230,7 @@ The terminal input implements these registers:
DONE 1 device done flag
ENABLE 1 interrupt enable flag
INT 1 interrupt pending flag
POS 31 number of characters input
POS 32 number of characters input
TIME 24 keyboard polling interval
2.2.4 KL8E Terminal Output (TTO)
@@ -243,7 +244,7 @@ implements these registers:
DONE 1 device done flag
ENABLE 1 interrupt enable flag
INT 1 interrupt pending flag
POS 31 number of characters output
POS 32 number of characters output
TIME 24 time from I/O initiation to interrupt
2.2.5 LE8E Line Printer (LPT)
@@ -261,7 +262,7 @@ The line printer implements these registers:
DONE 1 device done flag
ENABLE 1 interrupt enable flag
INT 1 interrupt pending flag
POS 31 position in the output file
POS 32 position in the output file
TIME 24 time from I/O initiation to interrupt
Error handling is as follows:
@@ -288,51 +289,58 @@ The real-time clock (CLK) implements these registers:
The real-time clock autocalibrates; the clock interval is adjusted up or
down so that the clock tracks actual elapsed time.
2.2.7 KL8JA Additional Terminals (TTI1-4, TTO1-4)
2.2.7 KL8JA Additional Terminals (TTIX, TTOX)
Each additional terminal consists of two independent devices, TTIn and
TTOn. The entire set is modelled as a terminal multiplexor, with TTI1
The additional terminals consist of two independent devices, TTIX and
TTOX. The entire set is modelled as a terminal multiplexor, with TTIX
as the master unit. The additional terminals perform input and output
through Telnet sessions connected to a user-specified port. The ATTACH
command specifies the port to be used:
ATTACH TTI1 <port>(cr) -- set up listening port
ATTACH TTIX <port> set up listening port
where port is a decimal number between 1 and 65535 that is not being used
for other TCP/IP activities.
Once TTI1 is attached and the simulator is running, the terminals listen
The additional terminals have one option, UC; when set, lower case input
characters are automatically converted to upper case. This is required
by TSS/8 and is on by default for all lines.
Once TTIX is attached and the simulator is running, the terminals listen
for connections on the specified port. They assume that the incoming
connections are Telnet connections. The connections remain open until
disconnected either by the Telnet client, or by a DETACH TTI1 command.
disconnected either by the Telnet client, a SET TTIX DISCONNECT command,
or a DETACH TTIX command.
The SHOW TTI1 LINESTATUS command displays the current connections to the
additional terminals.
The SHOW TTIX CONNECTIONS command displays the current connections to the
extra terminals. The SHOW TTIX STATISTICS command displays statistics for
active connections. The SET TTIX DISCONNECT=linenumber disconnects the
specified line.
The input devices (TTI1-4) implement these registers:
The input device (TTIX) implements these registers:
name size comments
BUF 8 last data item processed
DONE 1 device done flag
ENABLE 1 interrupt enable flag
INT 1 interrupt pending flag
POS 31 number of characters input
TIME 24 keyboard polling interval
BUF[0:3] 8 input buffer, lines 0-3
DONE 4 device done flags (line 0 rightmost)
ENABLE 4 interrupt enable flag
INT 4 interrupt pending flag
TIME 24 initial polling interval
TPS 10 polls per second after calibration
The output devices (TTO1-4) implement these registers:
The output device (TTOX) implements these registers:
name size comments
BUF 8 last data item processed
DONE 1 device done flag
ENABLE 1 interrupt enable flag
INT 1 interrupt pending flag
POS 31 number of characters output
TIME 24 time from I/O initiation to interrupt
BUF[0:3] 8 last data item processed, lines 0-3
DONE 4 device done flag (line 0 rightmost)
ENABLE 4 interrupt enable flag
INT 4 interrupt pending flag
TIME[0:3] 24 time from I/O initiation to interrupt,
lines 0-3
The additional terminals do not support save and restore. All open
connections are lost when the simulator shuts down or TTI1 is detached.
connections are lost when the simulator shuts down or TTIX is detached.
2.3 Moving Head Disks
@@ -341,10 +349,9 @@ connections are lost when the simulator shuts down or TTI1 is detached.
RK8E options include the ability to make units write enabled or write locked:
SET RKn LOCKED set unit n write locked
SET RKn ENABLED set unit n write enabled
SET RKn WRITEENABLED set unit n write enabled
Units can also be REMOVEd or ADDed to the configuration. The RK8E supports
the BOOT command.
Units can also be set ONLINE or OFFLINE. The RK8E supports the BOOT command.
The RK8E implements these registers:
@@ -375,11 +382,10 @@ Error handling is as follows:
RL8A options include the ability to make units write enabled or write locked:
SET RKn LOCKED set unit n write locked
SET RKn ENABLED set unit n write enabled
SET RLn LOCKED set unit n write locked
SET RLn WRITEENABLED set unit n write enabled
Units can also be REMOVEd or ADDed to the configuration. The RK8E supports
the BOOT command.
Units can also be set ONLINE or OFFILE. The RL8A supports the BOOT command.
The RL8A implements these registers:
@@ -418,7 +424,7 @@ Error handling is as follows:
RX8E options include the ability to set units write enabled or write locked:
SET RXn LOCKED set unit n write locked
SET RXn ENABLED set unit n write enabled
SET RXn WRITEENABLED set unit n write enabled
The RX8E supports the BOOT command.
@@ -534,17 +540,16 @@ DECtape options include the ability to make units write enabled or write
locked.
SET DTn LOCKED set unit n write locked
SET DTn ENABLED set unit n write enabled
SET DTn WRITEENABLED set unit n write enabled
Units can also be REMOVEd or ADDed to the configuration. The TC08 supports
the BOOT command.
Units can also be set ONLINE or OFFLINE. The TC08 supports the BOOT command.
The TC08 supports both PDP-8 format and PDP-9/11/15 format DECtape images.
ATTACH tries to determine the tape format from the DECtape image; the user
can force a particular format with switches:
-f foreign (PDP-9/11/15) format
-n native (PDP-8) format
-f foreign (PDP-9/11/15) format
-n native (PDP-8) format
The DECtape controller is a data-only simulator; the timing and mark
track, and block header and trailer, are not stored. Thus, the WRITE
@@ -568,7 +573,7 @@ The DECtape controller implements these registers:
ACTIME 31 time to accelerate to full speed
DCTIME 31 time to decelerate to a full stop
SUBSTATE 2 read/write command substate
POS[0:7] 31 position, in lines, units 0-7
POS[0:7] 32 position, in lines, units 0-7
STATT[0:7] 31 unit state, units 0-7
It is critically important to maintain certain timing relationships
@@ -585,9 +590,9 @@ Magnetic tape options include the ability to make units write enabled or
or write locked.
SET MTn LOCKED set unit n write locked
SET MTn ENABLED set unit n write enabled
SET MTn WRITEENABLED set unit n write enabled
Units can also be REMOVEd or ADDed to the configuration.
Units can also be set ONLINE or OFFLINE.
The magnetic tape controller implements these registers:
@@ -605,7 +610,7 @@ The magnetic tape controller implements these registers:
STOP_IOE 1 stop on I/O error
TIME 24 record delay
UST[0:7] 24 unit status, units 0-7
POS[0:7] 31 position, units 0-7
POS[0:7] 32 position, units 0-7
Error handling is as follows:

10
PDP8/pdp8_dt.c
View File

@@ -1,6 +1,6 @@
/* pdp8_dt.c: PDP-8 DECtape simulator
Copyright (c) 1993-2001, Robert M Supnik
Copyright (c) 1993-2002, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,8 @@
dt TC08/TU56 DECtape
30-May-02 RMS Widened POS to 32b
06-Jan-02 RMS Changed enable/disable support
30-Nov-01 RMS Added read only unit, extended SET/SHOW support
24-Nov-01 RMS Changed POS, STATT, LASTT, FLG to arrays
29-Aug-01 RMS Added casts to PDP-18b packup routine
@@ -305,7 +307,7 @@ REG dt_reg[] = {
{ ORDATA (SUBSTATE, dt_substate, 2) },
{ ORDATA (LOG, dt_log, 4), REG_HIDDEN },
{ DRDATA (LBLK, dt_logblk, 12), REG_HIDDEN },
{ URDATA (POS, dt_unit[0].pos, 10, 31, 0,
{ URDATA (POS, dt_unit[0].pos, 10, 32, 0,
DT_NUMDR, PV_LEFT | REG_RO) },
{ URDATA (STATT, dt_unit[0].STATE, 8, 18, 0,
DT_NUMDR, REG_RO) },
@@ -317,10 +319,12 @@ REG dt_reg[] = {
{ NULL } };
MTAB dt_mod[] = {
{ UNIT_WLK, 0, "write enabled", "ENABLED", NULL },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ UNIT_8FMT, 0, "16b/18b", NULL, NULL },
{ UNIT_8FMT, UNIT_8FMT, "12b", NULL, NULL },
{ MTAB_XTD|MTAB_VDV, INT_DTA, NULL, "ENABLED", &set_enb },
{ MTAB_XTD|MTAB_VDV, INT_DTA, NULL, "DISABLED", &set_dsb },
{ 0 } };
DEVICE dt_dev = {

6
PDP8/pdp8_lp.c
View File

@@ -1,6 +1,6 @@
/* pdp8_lp.c: PDP-8 line printer simulator
Copyright (c) 1993-2001, Robert M Supnik
Copyright (c) 1993-2002, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -24,6 +24,8 @@
in this Software without prior written authorization from Robert M Supnik.
lpt LP8E line printer
30-May-02 RMS Widened POS to 32b
*/
#include "pdp8_defs.h"
@@ -52,7 +54,7 @@ REG lpt_reg[] = {
{ FLDATA (DONE, dev_done, INT_V_LPT) },
{ FLDATA (ENABLE, int_enable, INT_V_LPT) },
{ FLDATA (INT, int_req, INT_V_LPT) },
{ DRDATA (POS, lpt_unit.pos, 31), PV_LEFT },
{ DRDATA (POS, lpt_unit.pos, 32), PV_LEFT },
{ DRDATA (TIME, lpt_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, lpt_stopioe, 0) },
{ NULL } };

15
PDP8/pdp8_mt.c
View File

@@ -1,6 +1,6 @@
/* pdp8_mt.c: PDP-8 magnetic tape simulator
Copyright (c) 1993-2001, Robert M Supnik
Copyright (c) 1993-2002, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,9 @@
mt TM8E/TU10 magtape
30-May-02 RMS Widened POS to 32b
22-Apr-02 RMS Added maximum record length test
06-Jan-02 RMS Changed enable/disable support
30-Nov-01 RMS Added read only unit, extended SET/SHOW support
24-Nov-01 RMS Changed UST, POS, FLG to arrays
25-Apr-01 RMS Added device enable/disable support
@@ -55,6 +58,7 @@
#define UNIT_W_UF 2 /* saved user flags */
#define USTAT u3 /* unit status */
#define UNUM u4 /* unit number */
#define MT_MAXFR (1 << 16) /* max record lnt */
#define DBSIZE (1 << 12) /* max data cmd */
#define DBMASK (SBSIZE - 1)
#define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protect */
@@ -173,7 +177,7 @@ REG mt_reg[] = {
{ FLDATA (STOP_IOE, mt_stopioe, 0) },
{ DRDATA (TIME, mt_time, 24), PV_LEFT },
{ URDATA (UST, mt_unit[0].USTAT, 8, 16, 0, MT_NUMDR, 0) },
{ URDATA (POS, mt_unit[0].pos, 10, 31, 0,
{ URDATA (POS, mt_unit[0].pos, 10, 32, 0,
MT_NUMDR, PV_LEFT | REG_RO) },
{ URDATA (FLG, mt_unit[0].flags, 8, UNIT_W_UF, UNIT_V_UF - 1,
MT_NUMDR, REG_HRO) },
@@ -181,8 +185,10 @@ REG mt_reg[] = {
{ NULL } };
MTAB mt_mod[] = {
{ UNIT_WLK, 0, "write enabled", "ENABLED", &mt_vlock },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", &mt_vlock },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", &mt_vlock },
{ MTAB_XTD|MTAB_VDV, INT_MT, NULL, "ENABLED", &set_enb },
{ MTAB_XTD|MTAB_VDV, INT_MT, NULL, "DISABLED", &set_dsb },
{ 0 } };
DEVICE mt_dev = {
@@ -365,8 +371,9 @@ case FN_CMPARE: /* read/compare */
uptr -> USTAT = uptr -> USTAT | STA_EOF | STA_RLE;
uptr -> pos = uptr -> pos + sizeof (t_mtrlnt);
break; }
cbc = (mt_cu & CU_UNPAK)? wc: wc * 2; /* expected bc */
tbc = MTRL (tbc); /* ignore error flag */
if (tbc > MT_MAXFR) return SCPE_MTRLNT; /* record too long? */
cbc = (mt_cu & CU_UNPAK)? wc: wc * 2; /* expected bc */
if (tbc != cbc) mt_sta = mt_sta | STA_RLE; /* wrong size? */
if (tbc < cbc) { /* record small? */
cbc = tbc; /* use smaller */

9
PDP8/pdp8_pt.c
View File

@@ -1,6 +1,6 @@
/* pdp8_pt.c: PDP-8 paper tape reader/punch simulator
Copyright (c) 1993-2001, Robert M Supnik
Copyright (c) 1993-2002, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
ptr,ptp PC8E paper tape reader/punch
30-May-02 RMS Widened POS to 32b
30-Nov-01 RMS Added read only unit support
30-Mar-98 RMS Added RIM loader as PTR bootstrap
*/
@@ -55,7 +56,7 @@ REG ptr_reg[] = {
{ FLDATA (DONE, dev_done, INT_V_PTR) },
{ FLDATA (ENABLE, int_enable, INT_V_PTR) },
{ FLDATA (INT, int_req, INT_V_PTR) },
{ DRDATA (POS, ptr_unit.pos, 31), PV_LEFT },
{ DRDATA (POS, ptr_unit.pos, 32), PV_LEFT },
{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
{ NULL } };
@@ -81,7 +82,7 @@ REG ptp_reg[] = {
{ FLDATA (DONE, dev_done, INT_V_PTP) },
{ FLDATA (ENABLE, int_enable, INT_V_PTP) },
{ FLDATA (INT, int_req, INT_V_PTP) },
{ DRDATA (POS, ptp_unit.pos, 31), PV_LEFT },
{ DRDATA (POS, ptp_unit.pos, 32), PV_LEFT },
{ DRDATA (TIME, ptp_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, ptp_stopioe, 0) },
{ NULL } };
@@ -209,7 +210,7 @@ return SCPE_OK;
/* Bootstrap routine */
#define BOOT_START 07756
#define BOOT_LEN (sizeof (boot_rom) / sizeof (int))
#define BOOT_LEN (sizeof (boot_rom) / sizeof (int32))
static const int32 boot_rom[] = {
06014, /* 7756, RFC */

10
PDP8/pdp8_rf.c
View File

@@ -1,6 +1,6 @@
/* pdp8_rf.c: RF08 fixed head disk simulator
Copyright (c) 1993-2001, Robert M Supnik
Copyright (c) 1993-2002, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
rf RF08 fixed head disk
06-Nov-02 RMS Changed enable/disable support
28-Nov-01 RMS Added RL8A support
25-Apr-01 RMS Added device enable/disable support
19-Mar-01 RMS Added disk monitor bootstrap, fixed IOT decoding
@@ -131,8 +132,13 @@ REG rf_reg[] = {
{ FLDATA (*DEVENB, dev_enb, INT_V_RF), REG_HRO },
{ NULL } };
MTAB rf_mod[] = {
{ MTAB_XTD|MTAB_VDV, INT_RF, NULL, "ENABLED", &set_enb },
{ MTAB_XTD|MTAB_VDV, INT_RF, NULL, "DISABLED", &set_dsb },
{ 0 } };
DEVICE rf_dev = {
"RF", &rf_unit, rf_reg, NULL,
"RF", &rf_unit, rf_reg, rf_mod,
1, 8, 20, 1, 8, 12,
NULL, NULL, &rf_reset,
&rf_boot, NULL, NULL };

7
PDP8/pdp8_rk.c
View File

@@ -1,6 +1,6 @@
/* pdp8_rk.c: RK8E cartridge disk simulator
Copyright (c) 1993-2001, Robert M Supnik
Copyright (c) 1993-2002, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
rk RK8E/RK05 cartridge disk
06-Jan-02 RMS Changed enable/disable support
30-Nov-01 RMS Added read only unit, extended SET/SHOW support
24-Nov-01 RMS Converted FLG to array, made register names consistent
25-Apr-01 RMS Added device enable/disable support
@@ -170,8 +171,10 @@ REG rk_reg[] = {
{ NULL } };
MTAB rk_mod[] = {
{ UNIT_HWLK, 0, "write enabled", "ENABLED", NULL },
{ UNIT_HWLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_HWLK, UNIT_HWLK, "write locked", "LOCKED", NULL },
{ MTAB_XTD|MTAB_VDV, INT_RK, NULL, "ENABLED", &set_enb },
{ MTAB_XTD|MTAB_VDV, INT_RK, NULL, "DISABLED", &set_dsb },
{ 0 } };
DEVICE rk_dev = {

7
PDP8/pdp8_rl.c
View File

@@ -1,6 +1,6 @@
/* pdp8_rl.c: RL8A cartridge disk simulator
Copyright (c) 1993-2001, Robert M Supnik
Copyright (c) 1993-2002, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
rl RL8A cartridge disk
06-Jan-02 RMS Changed enable/disable support
30-Nov-01 RMS Cloned from RL11
The RL8A is a four drive cartridge disk subsystem. An RL01 drive
@@ -218,7 +219,7 @@ REG rl_reg[] = {
{ NULL } };
MTAB rl_mod[] = {
{ UNIT_WLK, 0, "write enabled", "ENABLED", NULL },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ UNIT_DUMMY, 0, NULL, "BADBLOCK", &rl_set_bad },
{ (UNIT_RL02+UNIT_ATT), UNIT_ATT, "RL01", NULL, NULL },
@@ -229,6 +230,8 @@ MTAB rl_mod[] = {
{ UNIT_AUTO, UNIT_AUTO, NULL, "AUTOSIZE", NULL },
{ (UNIT_AUTO+UNIT_RL02), 0, NULL, "RL01", &rl_set_size },
{ (UNIT_AUTO+UNIT_RL02), UNIT_RL02, NULL, "RL02", &rl_set_size },
{ MTAB_XTD|MTAB_VDV, INT_RL, NULL, "ENABLED", &set_enb },
{ MTAB_XTD|MTAB_VDV, INT_RL, NULL, "DISABLED", &set_dsb },
{ 0 } };
DEVICE rl_dev = {

7
PDP8/pdp8_rx.c
View File

@@ -1,6 +1,6 @@
/* pdp8_rx.c: RX8E/RX01 floppy disk simulator
Copyright (c) 1993-2001, Robert M Supnik
Copyright (c) 1993-2002, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
rx RX8E/RX01 floppy disk
06-Jan-02 RMS Changed enable/disable support
30-Nov-01 RMS Added read only unit, extended SET/SHOW support
24-Nov-01 RMS Converted FLG to array
17-Jul-01 RMS Fixed warning from VC++ 6
@@ -146,8 +147,10 @@ REG rx_reg[] = {
{ NULL } };
MTAB rx_mod[] = {
{ UNIT_WLK, 0, "write enabled", "ENABLED", NULL },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ MTAB_XTD|MTAB_VDV, INT_RX, NULL, "ENABLED", &set_enb },
{ MTAB_XTD|MTAB_VDV, INT_RX, NULL, "DISABLED", &set_dsb },
{ 0 } };
DEVICE rx_dev = {

13
PDP8/pdp8_sys.c
View File

@@ -1,6 +1,6 @@
/* pdp8_sys.c: PDP-8 simulator interface
Copyright (c) 1993-2001, Robert M Supnik
Copyright (c) 1993-2002, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -23,6 +23,7 @@
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
30-Dec-01 RMS Revised for new TTX
26-Nov-01 RMS Added RL8A support
17-Sep-01 RMS Removed multiconsole support
16-Sep-01 RMS Added TSS/8 packed char support, added KL8A support
@@ -48,10 +49,7 @@ extern DEVICE rk_dev, rl_dev;
extern DEVICE rx_dev;
extern DEVICE df_dev, rf_dev;
extern DEVICE dt_dev, mt_dev;
extern DEVICE tti1_dev, tto1_dev;
extern DEVICE tti2_dev, tto2_dev;
extern DEVICE tti3_dev, tto3_dev;
extern DEVICE tti4_dev, tto4_dev;
extern DEVICE ttix_dev, ttox_dev;
extern REG cpu_reg[];
extern uint16 M[];
extern int32 sim_switches;
@@ -77,10 +75,7 @@ DEVICE *sim_devices[] = {
&cpu_dev,
&ptr_dev, &ptp_dev,
&tti_dev, &tto_dev,
&tti1_dev, &tto1_dev,
&tti2_dev, &tto2_dev,
&tti3_dev, &tto3_dev,
&tti4_dev, &tto4_dev,
&ttix_dev, &ttox_dev,
&clk_dev, &lpt_dev,
&rk_dev, &rl_dev,
&rx_dev,

7
PDP8/pdp8_tt.c
View File

@@ -1,6 +1,6 @@
/* pdp8_tt.c: PDP-8 console terminal simulator
Copyright (c) 1993-2001, Robert M Supnik
Copyright (c) 1993-2002, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
tti,tto KL8E terminal input/output
30-May-02 RMS Widened POS to 32b
07-Sep-01 RMS Moved function prototypes
*/
@@ -54,7 +55,7 @@ REG tti_reg[] = {
{ FLDATA (DONE, dev_done, INT_V_TTI) },
{ FLDATA (ENABLE, int_enable, INT_V_TTI) },
{ FLDATA (INT, int_req, INT_V_TTI) },
{ DRDATA (POS, tti_unit.pos, 31), PV_LEFT },
{ DRDATA (POS, tti_unit.pos, 32), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), REG_NZ + PV_LEFT },
{ FLDATA (UC, tti_unit.flags, UNIT_V_UC), REG_HRO },
{ NULL } };
@@ -84,7 +85,7 @@ REG tto_reg[] = {
{ FLDATA (DONE, dev_done, INT_V_TTO) },
{ FLDATA (ENABLE, int_enable, INT_V_TTO) },
{ FLDATA (INT, int_req, INT_V_TTO) },
{ DRDATA (POS, tto_unit.pos, 31), PV_LEFT },
{ DRDATA (POS, tto_unit.pos, 32), PV_LEFT },
{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },
{ NULL } };

333
PDP8/pdp8_ttx.c
View File

@@ -1,6 +1,6 @@
/* pdp8_ttx.c: PDP-8 additional terminals simulator
Copyright (c) 1993-2001, Robert M Supnik
Copyright (c) 1993-2002, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,8 @@
ttix,ttox PT08/KL8JA terminal input/output
06-Jan-02 RMS Added device enable/disable support
30-Dec-01 RMS Complete rebuild
30-Nov-01 RMS Added extended SET/SHOW support
This module implements four individual serial interfaces similar in function
@@ -44,15 +46,13 @@
#define UNIT_UC (1 << UNIT_V_UC)
#define TTX_GETLN(x) (((x) >> 4) & TTX_MASK)
extern int32 int_req, int_enable, dev_done, stop_inst;
extern int32 tmxr_poll; /* calibrated poll */
TMLN tt1_ldsc = { 0 }; /* line descriptors */
TMLN tt2_ldsc = { 0 }; /* line descriptors */
TMLN tt3_ldsc = { 0 }; /* line descriptors */
TMLN tt4_ldsc = { 0 }; /* line descriptors */
extern int32 int_req, int_enable, dev_done, dev_enb, stop_inst;
uint8 ttix_buf[TTX_LINES] = { 0 }; /* input buffers */
uint8 ttox_buf[TTX_LINES] = { 0 }; /* output buffers */
int32 ttx_tps = 100; /* polls per second */
TMLN ttx_ldsc[TTX_LINES] = { 0 }; /* line descriptors */
TMXR ttx_desc = { /* mux descriptor */
TTX_LINES, 0, &tt1_ldsc, &tt2_ldsc, &tt3_ldsc, &tt4_ldsc };
TTX_LINES, 0, &ttx_ldsc[0], &ttx_ldsc[1], &ttx_ldsc[2], &ttx_ldsc[3] };
t_stat ttix_svc (UNIT *uptr);
t_stat ttix_reset (DEVICE *dptr);
@@ -60,7 +60,8 @@ t_stat ttox_svc (UNIT *uptr);
t_stat ttox_reset (DEVICE *dptr);
t_stat ttx_attach (UNIT *uptr, char *cptr);
t_stat ttx_detach (UNIT *uptr);
t_stat ttx_status (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat ttx_summ (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat ttx_show (FILE *st, UNIT *uptr, int32 val, void *desc);
/* TTIx data structures
@@ -70,89 +71,36 @@ t_stat ttx_status (FILE *st, UNIT *uptr, int32 val, void *desc);
ttix_mod TTIx modifiers list
*/
MTAB ttix_mod[] = {
{ UNIT_UC, 0, "lower case", "LC", NULL },
{ UNIT_UC, UNIT_UC, "upper case", "UC", NULL },
{ UNIT_ATT, UNIT_ATT, "line status", NULL, NULL, &ttx_status },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "LINESTATUS", NULL,
NULL, &ttx_status, NULL },
{ 0 } };
UNIT ttix_unit = { UDATA (&ttix_svc, UNIT_ATTABLE, 0), KBD_POLL_WAIT };
UNIT ttix_unit[] = {
{ UDATA (&ttix_svc, UNIT_ATTABLE+UNIT_UC, 0), KBD_POLL_WAIT },
{ UDATA (&ttix_svc, UNIT_UC, 0), KBD_POLL_WAIT },
{ UDATA (&ttix_svc, UNIT_UC, 0), KBD_POLL_WAIT },
{ UDATA (&ttix_svc, UNIT_UC, 0), KBD_POLL_WAIT } };
#define tti1_unit ttix_unit[0]
#define tti2_unit ttix_unit[1]
#define tti3_unit ttix_unit[2]
#define tti4_unit ttix_unit[3]
REG tti1_reg[] = {
{ ORDATA (BUF, tti1_unit.buf, 8) },
{ FLDATA (DONE, dev_done, INT_V_TTI1) },
{ FLDATA (ENABLE, int_enable, INT_V_TTI1) },
{ FLDATA (INT, int_req, INT_V_TTI1) },
{ DRDATA (POS, tt1_ldsc.rxcnt, 32), PV_LEFT },
{ DRDATA (TIME, tti1_unit.wait, 24), REG_NZ + PV_LEFT },
{ FLDATA (UC, tti1_unit.flags, UNIT_V_UC), REG_HRO },
REG ttix_reg[] = {
{ BRDATA (BUF, ttix_buf, 8, 8, TTX_LINES) },
{ GRDATA (DONE, dev_done, 8, TTX_LINES, INT_V_TTI1) },
{ GRDATA (ENABLE, int_enable, 8, TTX_LINES, INT_V_TTI1) },
{ GRDATA (INT, int_req, 8, TTX_LINES, INT_V_TTI1) },
{ DRDATA (TIME, ttix_unit.wait, 24), REG_NZ + PV_LEFT },
{ DRDATA (TPS, ttx_tps, 10), REG_NZ + PV_LEFT },
{ FLDATA (*DEVENB, dev_enb, INT_V_TTI1), REG_HRO },
{ NULL } };
DEVICE tti1_dev = {
"TTI1", &tti1_unit, tti1_reg, ttix_mod,
MTAB ttix_mod[] = {
{ UNIT_ATT, UNIT_ATT, "summary", NULL, NULL, &ttx_summ },
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &ttx_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &ttx_show, NULL },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
NULL, &ttx_show, NULL },
{ MTAB_XTD|MTAB_VDV, INT_TTI1, NULL, "ENABLED", &set_enb },
{ MTAB_XTD|MTAB_VDV, INT_TTI1, NULL, "DISABLED", &set_dsb },
{ 0 } };
DEVICE ttix_dev = {
"TTIX", &ttix_unit, ttix_reg, ttix_mod,
1, 10, 31, 1, 8, 8,
&tmxr_ex, &tmxr_dep, &ttix_reset,
NULL, &ttx_attach, &ttx_detach };
REG tti2_reg[] = {
{ ORDATA (BUF, tti2_unit.buf, 8) },
{ FLDATA (DONE, dev_done, INT_V_TTI2) },
{ FLDATA (ENABLE, int_enable, INT_V_TTI2) },
{ FLDATA (INT, int_req, INT_V_TTI2) },
{ DRDATA (POS, tt2_ldsc.rxcnt, 32), PV_LEFT },
{ DRDATA (TIME, tti2_unit.wait, 24), REG_NZ + PV_LEFT },
{ FLDATA (UC, tti2_unit.flags, UNIT_V_UC), REG_HRO },
{ NULL } };
DEVICE tti2_dev = {
"TTI2", &tti2_unit, tti2_reg, ttix_mod,
1, 10, 31, 1, 8, 8,
NULL, NULL, &ttix_reset,
NULL, NULL, NULL };
REG tti3_reg[] = {
{ ORDATA (BUF, tti3_unit.buf, 8) },
{ FLDATA (DONE, dev_done, INT_V_TTI3) },
{ FLDATA (ENABLE, int_enable, INT_V_TTI3) },
{ FLDATA (INT, int_req, INT_V_TTI3) },
{ DRDATA (POS, tt3_ldsc.rxcnt, 32), PV_LEFT },
{ DRDATA (TIME, tti3_unit.wait, 24), REG_NZ + PV_LEFT },
{ FLDATA (UC, tti3_unit.flags, UNIT_V_UC), REG_HRO },
{ NULL } };
DEVICE tti3_dev = {
"TTI3", &tti3_unit, tti3_reg, ttix_mod,
1, 10, 31, 1, 8, 8,
NULL, NULL, &ttix_reset,
NULL, NULL, NULL };
REG tti4_reg[] = {
{ ORDATA (BUF, tti4_unit.buf, 8) },
{ FLDATA (DONE, dev_done, INT_V_TTI4) },
{ FLDATA (ENABLE, int_enable, INT_V_TTI4) },
{ FLDATA (INT, int_req, INT_V_TTI4) },
{ DRDATA (POS, tt4_ldsc.rxcnt, 32), PV_LEFT },
{ DRDATA (TIME, tti4_unit.wait, 24), REG_NZ + PV_LEFT },
{ FLDATA (UC, tti4_unit.flags, UNIT_V_UC), REG_HRO },
{ NULL } };
DEVICE tti4_dev = {
"TTI4", &tti4_unit, tti4_reg, ttix_mod,
1, 10, 31, 1, 8, 8,
NULL, NULL, &ttix_reset,
NULL, NULL, NULL };
/* TTOx data structures
ttox_dev TTOx device descriptor
@@ -161,73 +109,31 @@ DEVICE tti4_dev = {
*/
UNIT ttox_unit[] = {
{ UDATA (&ttox_svc, 0, 0), SERIAL_OUT_WAIT },
{ UDATA (&ttox_svc, 0, 0), SERIAL_OUT_WAIT },
{ UDATA (&ttox_svc, 0, 0), SERIAL_OUT_WAIT },
{ UDATA (&ttox_svc, 0, 0), SERIAL_OUT_WAIT } };
{ UDATA (&ttox_svc, UNIT_UC, 0), SERIAL_OUT_WAIT },
{ UDATA (&ttox_svc, UNIT_UC, 0), SERIAL_OUT_WAIT },
{ UDATA (&ttox_svc, UNIT_UC, 0), SERIAL_OUT_WAIT },
{ UDATA (&ttox_svc, UNIT_UC, 0), SERIAL_OUT_WAIT } };
#define tto1_unit ttox_unit[0]
#define tto2_unit ttox_unit[0]
#define tto3_unit ttox_unit[0]
#define tto4_unit ttox_unit[0]
REG tto1_reg[] = {
{ ORDATA (BUF, tto1_unit.buf, 8) },
{ FLDATA (DONE, dev_done, INT_V_TTO1) },
{ FLDATA (ENABLE, int_enable, INT_V_TTO1) },
{ FLDATA (INT, int_req, INT_V_TTO1) },
{ DRDATA (POS, tt1_ldsc.txcnt, 32), PV_LEFT },
{ DRDATA (TIME, tto1_unit.wait, 24), PV_LEFT },
REG ttox_reg[] = {
{ BRDATA (BUF, ttox_buf, 8, 8, TTX_LINES) },
{ GRDATA (DONE, dev_done, 8, TTX_LINES, INT_V_TTO1) },
{ GRDATA (ENABLE, int_enable, 8, TTX_LINES, INT_V_TTO1) },
{ GRDATA (INT, int_req, 8, TTX_LINES, INT_V_TTO1) },
{ URDATA (TIME, ttox_unit[0].wait, 10, 24, 0,
TTX_LINES, PV_LEFT) },
{ URDATA (FLGS, ttox_unit[0].flags, 8, 1, UNIT_V_UC,
TTX_LINES, REG_HRO) },
{ FLDATA (*DEVENB, dev_enb, INT_V_TTI1), REG_HRO },
{ NULL } };
DEVICE tto1_dev = {
"TTO1", &tto1_unit, tto1_reg, NULL,
1, 10, 31, 1, 8, 8,
NULL, NULL, &ttox_reset,
NULL, NULL, NULL };
MTAB ttox_mod[] = {
{ UNIT_UC, 0, "lower case", "LC", NULL },
{ UNIT_UC, UNIT_UC, "upper case", "UC", NULL },
{ 0 } };
REG tto2_reg[] = {
{ ORDATA (BUF, tto2_unit.buf, 8) },
{ FLDATA (DONE, dev_done, INT_V_TTO2) },
{ FLDATA (ENABLE, int_enable, INT_V_TTO2) },
{ FLDATA (INT, int_req, INT_V_TTO2) },
{ DRDATA (POS, tt2_ldsc.txcnt, 32), PV_LEFT },
{ DRDATA (TIME, tto2_unit.wait, 24), PV_LEFT },
{ NULL } };
DEVICE tto2_dev = {
"TTO2", &tto2_unit, tto2_reg, NULL,
1, 10, 31, 1, 8, 8,
NULL, NULL, &ttox_reset,
NULL, NULL, NULL };
REG tto3_reg[] = {
{ ORDATA (BUF, tto3_unit.buf, 8) },
{ FLDATA (DONE, dev_done, INT_V_TTO3) },
{ FLDATA (ENABLE, int_enable, INT_V_TTO3) },
{ FLDATA (INT, int_req, INT_V_TTO3) },
{ DRDATA (POS, tt3_ldsc.txcnt, 32), PV_LEFT },
{ DRDATA (TIME, tto3_unit.wait, 24), PV_LEFT },
{ NULL } };
DEVICE tto3_dev = {
"TTO3", &tto3_unit, tto3_reg, NULL,
1, 10, 31, 1, 8, 8,
NULL, NULL, &ttox_reset,
NULL, NULL, NULL };
REG tto4_reg[] = {
{ ORDATA (BUF, tto4_unit.buf, 8) },
{ FLDATA (DONE, dev_done, INT_V_TTO4) },
{ FLDATA (ENABLE, int_enable, INT_V_TTO4) },
{ FLDATA (INT, int_req, INT_V_TTO4) },
{ DRDATA (POS, tt4_ldsc.txcnt, 32), PV_LEFT },
{ DRDATA (TIME, tto4_unit.wait, 24), PV_LEFT },
{ NULL } };
DEVICE tto4_dev = {
"TTO4", &tto4_unit, tto4_reg, NULL,
1, 10, 31, 1, 8, 8,
DEVICE ttox_dev = {
"TTOX", ttox_unit, ttox_reg, ttox_mod,
4, 10, 31, 1, 8, 8,
NULL, NULL, &ttox_reset,
NULL, NULL, NULL };
@@ -252,7 +158,7 @@ case 2: /* KCC */
int_req = int_req & ~itti;
return 0; /* clear AC */
case 4: /* KRS */
return (AC | ttix_unit[ln].buf); /* return buf */
return (AC | ttix_buf[ln]); /* return buf */
case 5: /* KIE */
if (AC & 1) int_enable = int_enable | (itti + itto);
else int_enable = int_enable & ~(itti + itto);
@@ -261,7 +167,7 @@ case 5: /* KIE */
case 6: /* KRB */
dev_done = dev_done & ~itti; /* clear flag */
int_req = int_req & ~itti;
return ttix_unit[ln].buf; /* return buf */
return ttix_buf[ln]; /* return buf */
default:
return (stop_inst << IOT_V_REASON) + AC; } /* end switch */
return AC;
@@ -271,26 +177,24 @@ return AC;
t_stat ttix_svc (UNIT *uptr)
{
int32 temp, newln;
int32 ln = uptr - ttix_unit; /* line # */
int32 itti = (INT_TTI1 << ln); /* rx intr */
int32 ln, c, temp;
if (ttx_desc.ldsc[ln] -> conn) { /* connected? */
tmxr_poll_rx (&ttx_desc); /* poll for input */
if (temp = tmxr_getc_ln (ttx_desc.ldsc[ln])) { /* get char */
temp = temp & 0177; /* mask to 7b */
if ((uptr -> flags & UNIT_UC) && islower (temp))
temp = toupper (temp);
uptr -> buf = temp | 0200; /* Teletype code */
dev_done = dev_done | itti; /* set done */
int_req = INT_UPDATE; } /* update intr */
sim_activate (uptr, uptr -> wait); } /* continue poll */
if (uptr -> flags & UNIT_ATT) { /* attached? */
newln = tmxr_poll_conn (&ttx_desc, uptr); /* poll connect */
if (newln >= 0) { /* got one? */
sim_activate (&ttix_unit[newln], ttix_unit[newln].wait);
ttx_desc.ldsc[newln] -> rcve = 1; } /* rcv enabled */
sim_activate (uptr, tmxr_poll); } /* sched poll */
if ((uptr -> flags & UNIT_ATT) == 0) return SCPE_OK; /* attached? */
temp = sim_rtcn_calb (ttx_tps, TMR_TTX); /* calibrate */
sim_activate (uptr, temp); /* continue poll */
ln = tmxr_poll_conn (&ttx_desc, uptr); /* look for connect */
if (ln >= 0) { /* got one? */
ttx_ldsc[ln].rcve = 1; } /* rcv enabled */
tmxr_poll_rx (&ttx_desc); /* poll for input */
for (ln = 0; ln < TTX_LINES; ln++) { /* loop thru lines */
if (ttx_ldsc[ln].conn) { /* connected? */
if (temp = tmxr_getc_ln (&ttx_ldsc[ln])) { /* get char */
c = temp & 0177;
if ((ttox_unit[ln].flags & UNIT_UC) && islower (c))
c = toupper (c);
ttix_buf[ln] = c;
dev_done = dev_done | (INT_TTI1 << ln);
int_req = INT_UPDATE; } } }
return SCPE_OK;
}
@@ -298,20 +202,19 @@ return SCPE_OK;
t_stat ttix_reset (DEVICE *dptr)
{
UNIT *uptr = dptr -> units; /* unit */
int32 ln = uptr - ttix_unit; /* line # */
int32 itti = (INT_TTI1 << ln); /* rx intr */
int32 t, ln, itto;
uptr -> buf = 0; /* clr buf */
dev_done = dev_done & ~itti; /* clr done, int */
int_req = int_req & ~itti;
int_enable = int_enable | itti; /* set enable */
if (ttx_desc.ldsc[ln] -> conn) { /* if conn, */
sim_activate (uptr, uptr -> wait); /* activate, */
ttx_desc.ldsc[ln] -> rcve = 1; } /* enable */
else if (uptr -> flags & UNIT_ATT) /* if attached, */
sim_activate (uptr, tmxr_poll); /* activate */
else sim_cancel (uptr); /* else stop */
if (ttix_unit.flags & UNIT_ATT) { /* if attached, */
if (!sim_is_active (&ttix_unit)) {
t = sim_rtcn_init (ttix_unit.wait, TMR_TTX);
sim_activate (&ttix_unit, t); } } /* activate */
else sim_cancel (&ttix_unit); /* else stop */
for (ln = 0; ln < TTX_LINES; ln++) { /* for all lines */
ttix_buf[ln] = 0; /* clear buf, */
itto = (INT_TTI1 << ln); /* interrupt */
dev_done = dev_done & ~itto; /* clr done, int */
int_req = int_req & ~itto;
int_enable = int_enable | itto; } /* set enable */
return SCPE_OK;
}
@@ -342,7 +245,7 @@ case 6: /* TLS */
int_req = int_req & ~itto; /* clear int req */
case 4: /* TPC */
sim_activate (&ttox_unit[ln], ttox_unit[ln].wait); /* activate */
ttox_unit[ln].buf = AC & 0377; /* load buffer */
ttox_buf[ln] = AC & 0377; /* load buffer */
break;
default:
return (stop_inst << IOT_V_REASON) + AC; } /* end switch */
@@ -353,18 +256,20 @@ return AC;
t_stat ttox_svc (UNIT *uptr)
{
int32 ln = uptr - ttox_unit; /* line # */
int32 itto = (INT_TTO1 << ln); /* tx intr */
int32 c, ln = uptr - ttox_unit; /* line # */
if (ttx_desc.ldsc[ln] -> conn) { /* connected? */
if (ttx_desc.ldsc[ln] -> xmte) { /* tx enabled? */
TMLN *lp = ttx_desc.ldsc[ln]; /* get line */
tmxr_putc_ln (lp, uptr -> buf & 0177); /* output char */
c = ttox_buf[ln] & 0177; /* get char */
if ((ttox_unit[ln].flags & UNIT_UC) && islower (c))
c = toupper (c);
tmxr_putc_ln (lp, c); /* output char */
tmxr_poll_tx (&ttx_desc); } /* poll xmt */
else { tmxr_poll_tx (&ttx_desc); /* poll xmt */
sim_activate (uptr, tmxr_poll); /* wait */
sim_activate (uptr, ttox_unit[ln].wait); /* wait */
return SCPE_OK; } }
dev_done = dev_done | itto; /* set done */
dev_done = dev_done | (INT_TTO1 << ln); /* set done */
int_req = INT_UPDATE; /* update intr */
return SCPE_OK;
}
@@ -373,15 +278,15 @@ return SCPE_OK;
t_stat ttox_reset (DEVICE *dptr)
{
UNIT *uptr = dptr -> units; /* unit */
int32 ln = uptr - ttox_unit; /* line # */
int32 itto = (INT_TTO1 << ln); /* tx intr */
int32 ln, itto;
uptr -> buf = 0; /* clr buf */
dev_done = dev_done & ~itto; /* clr done, int */
int_req = int_req & ~itto;
int_enable = int_enable | itto; /* set enable */
sim_cancel (uptr); /* deactivate */
for (ln = 0; ln < TTX_LINES; ln++) { /* for all lines */
ttox_buf[ln] = 0; /* clear buf */
itto = (INT_TTO1 << ln); /* interrupt */
dev_done = dev_done & ~itto; /* clr done, int */
int_req = int_req & ~itto;
int_enable = int_enable | itto; /* set enable */
sim_cancel (&ttox_unit[ln]); } /* deactivate */
return SCPE_OK;
}
@@ -389,11 +294,13 @@ return SCPE_OK;
t_stat ttx_attach (UNIT *uptr, char *cptr)
{
int32 t;
t_stat r;
r = tmxr_attach (&ttx_desc, uptr, cptr); /* attach */
if (r != SCPE_OK) return r; /* error */
sim_activate (uptr, tmxr_poll); /* start poll */
t = sim_rtcn_init (ttix_unit.wait, TMR_TTX); /* init calib */
sim_activate (uptr, t); /* start poll */
return SCPE_OK;
}
@@ -407,22 +314,34 @@ t_stat r;
r = tmxr_detach (&ttx_desc, uptr); /* detach */
for (i = 0; i < TTX_LINES; i++) { /* all lines, */
ttx_desc.ldsc[i] -> rcve = 0; /* disable rcv */
sim_cancel (&ttix_unit[i]); } /* stop poll */
sim_cancel (&ttox_unit[i]); } /* stop poll */
return SCPE_OK;
}
/* Status */
/* Show summary processor */
t_stat ttx_status (FILE *st, UNIT *uptr, int32 val, void *desc)
t_stat ttx_summ (FILE *st, UNIT *uptr, int32 val, void *desc)
{
int32 i, t;
for (i = t = 0; i < TTX_LINES; i++) t = t + (ttx_ldsc[i].conn != 0);
if (t == 1) fprintf (st, "1 connection");
else fprintf (st, "%d connections", t);
return SCPE_OK;
}
/* SHOW CONN/STAT processor */
t_stat ttx_show (FILE *st, UNIT *uptr, int32 val, void *desc)
{
int32 i;
fprintf (st, "line status:");
for (i = 0; (i < TTX_LINES) && (ttx_desc.ldsc[i] -> conn == 0); i++) ;
for (i = 0; (i < TTX_LINES) && (ttx_ldsc[i].conn == 0); i++) ;
if (i < TTX_LINES) {
for (i = 0; i < TTX_LINES; i++) {
if (ttx_desc.ldsc[i] -> conn)
tmxr_fstatus (st, ttx_desc.ldsc[i], i); } }
else fprintf (st, " all disconnected");
for (i = 0; i < TTX_LINES; i++) {
if (ttx_ldsc[i].conn)
if (val) tmxr_fconns (st, &ttx_ldsc[i], i);
else tmxr_fstats (st, &ttx_ldsc[i], i); } }
else fprintf (st, "all disconnected\n");
return SCPE_OK;
}