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Notes For V3.2-1
RESTRICTION: The PDP-15 FPP is only partially debugged. Do NOT enable this feature for normal operations. 1. New Features in 3.2-1 1.1 SCP and libraries - Added SET CONSOLE subhierarchy. - Added SHOW CONSOLE subhierarchy. - Added limited keyboard mapping capability. 1.2 HP2100 (new features from Dave Bryan) - Added instruction printout to HALT message. - Added M and T internal registers. - Added N, S, and U breakpoints. 1.3 PDP-11 and VAX - Added DHQ11 support (from John Dundas) 2. Bugs Fixed in 3.2-1 2.1 HP2100 (most fixes from Dave Bryan) - SBT increments B after store. - DMS console map must check dms_enb. - SFS x,C and SFC x,C work. - MP violation clears automatically on interrupt. - SFS/SFC 5 is not gated by protection enabled. - DMS enable does not disable mem prot checks. - DMS status inconsistent at simulator halt. - Examine/deposit are checking wrong addresses. - Physical addresses are 20b not 15b. - Revised DMS to use memory rather than internal format. - Revised IBL facility to conform to microcode. - Added DMA EDT I/O pseudo-opcode. - Separated DMA SRQ (service request) from FLG. - Revised peripherals to make SFS x,C and SFC x,C work. - Revised boot ROMs to use IBL facility. - Revised IBL treatment of SR to preserve SR<5:3>. - Fixed LPS, LPT timing. - Fixed DP boot interpretation of SR<0>. - Revised DR boot code to use IBL algorithm. - Fixed TTY input behavior during typeout for RTE-IV. - Suppressed nulls on TTY output for RTE-IV. - Added SFS x,C and SFC x,C to print/parse routines. - Fixed spurious timing error in magtape reads. 2.2 All DEC console devices - Removed SET TTI CTRL-C option. 2.3 PDP-11/VAX peripherals - Fixed bug in TQ reporting write protect status (reported by Lyle Bickley). - Fixed TK70 model number and media ID (found by Robert Schaffrath). - Fixed bug in autoconfigure (found by John Dundas). 2.4 VAX - Fixed bug in DIVBx and DIVWx (reported by Peter Trimmel).
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
26aa6de663
commit
e2ba672610
@@ -35,6 +35,9 @@
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The drum control channel does not have any of the traditional flip-flops.
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26-Apr-04 RMS Fixed SFS x,C and SFC x,C
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Revised boot rom to use IBL algorithm
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Implemented DMA SRQ (follows FLG)
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27-Jul-03 RMS Fixed drum sizes
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Fixed variable capacity interaction with SAVE/RESTORE
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10-Nov-02 RMS Added BOOT command
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@@ -110,7 +113,7 @@
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extern UNIT cpu_unit;
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extern uint16 *M;
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extern uint32 PC;
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extern uint32 dev_cmd[2], dev_ctl[2], dev_flg[2], dev_fbf[2];
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extern uint32 dev_cmd[2], dev_ctl[2], dev_flg[2], dev_fbf[2], dev_srq[2];
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int32 drc_cw = 0; /* fnc, addr */
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int32 drc_sta = 0; /* status */
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@@ -142,8 +145,8 @@ t_stat dr_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
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*/
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DIB dr_dib[] = {
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{ DRD, 0, 0, 0, 0, &drdio },
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{ DRC, 0, 0, 0, 0, &drcio } };
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{ DRD, 0, 0, 0, 0, 0, &drdio },
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{ DRC, 0, 0, 0, 0, 0, &drcio } };
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#define drd_dib dr_dib[0]
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#define drc_dib dr_dib[1]
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@@ -157,6 +160,7 @@ REG drd_reg[] = {
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{ FLDATA (CTL, drd_dib.ctl, 0) },
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{ FLDATA (FLG, drd_dib.flg, 0) },
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{ FLDATA (FBF, drd_dib.fbf, 0) },
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{ FLDATA (SRQ, drd_dib.srq, 0) },
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{ ORDATA (BPTR, drd_ptr, 6) },
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{ ORDATA (DEVNO, drd_dib.devno, 6), REG_HRO },
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{ NULL } };
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@@ -192,6 +196,7 @@ REG drc_reg[] = {
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{ FLDATA (CTL, drc_dib.ctl, 0) },
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{ FLDATA (FLG, drc_dib.flg, 0) },
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{ FLDATA (FBF, drc_dib.fbf, 0) },
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{ FLDATA (SRQ, drc_dib.srq, 0) },
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{ DRDATA (TIME, dr_time, 24), REG_NZ + PV_LEFT },
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{ FLDATA (STOP_IOE, dr_stopioe, 0) },
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{ ORDATA (DEVNO, drc_dib.devno, 6), REG_HRO },
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@@ -242,11 +247,11 @@ case ioLIX: /* load */
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case ioCTL: /* control clear/set */
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if (IR & I_AB) { /* CLC */
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clrCMD (devd); /* clr "ctl" */
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clrFLG (devd); /* clr flg */
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clrFSR (devd); /* clr flg */
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drc_sta = drc_sta & ~DRS_SAC; } /* clear SAC flag */
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else if (!CMD (devd)) { /* STC, not set? */
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setCMD (devd); /* set "ctl" */
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if (drc_cw & CW_WR) { setFLG (devd); } /* prime DMA */
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if (drc_cw & CW_WR) { setFSR (devd); } /* prime DMA */
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drc_sta = 0; /* clear errors */
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drd_ptr = 0; /* clear sec ptr */
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sim_cancel (&drc_unit); /* cancel curr op */
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@@ -256,7 +261,7 @@ case ioCTL: /* control clear/set */
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break;
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default:
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break; }
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if (IR & I_HC) { clrFLG (devd); } /* H/C option */
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if (IR & I_HC) { clrFSR (devd); } /* H/C option */
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return dat;
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}
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@@ -267,7 +272,7 @@ int32 st;
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switch (inst) { /* case on opcode */
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case ioSFC: /* skip flag clear */
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PC = (PC + 1) & VAMASK;
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return dat;
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break;
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case ioOTX: /* output */
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drc_cw = dat;
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break;
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@@ -310,7 +315,7 @@ if (drc_cw & CW_WR) { /* write? */
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uptr->hwmark = da + drd_ptr + 1; }
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drd_ptr = dr_incda (trk, sec, drd_ptr); /* inc disk addr */
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if (CMD (devd)) { /* dch active? */
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setFLG (devd); /* set dch flg */
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setFSR (devd); /* set dch flg */
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sim_activate (uptr, dr_time); } /* sched next word */
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else if (drd_ptr) { /* done, need to fill? */
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for ( ; drd_ptr < DR_NUMWD; drd_ptr++)
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@@ -321,7 +326,7 @@ else { /* read */
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if ((da >= uptr->capac) || (sec >= DR_NUMSC)) drd_ibuf = 0;
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else drd_ibuf = bptr[da + drd_ptr];
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drd_ptr = dr_incda (trk, sec, drd_ptr);
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setFLG (devd); /* set dch flg */
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setFSR (devd); /* set dch flg */
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sim_activate (uptr, dr_time); } /* sched next word */
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}
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return SCPE_OK;
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@@ -354,6 +359,7 @@ drc_dib.cmd = drd_dib.cmd = 0; /* clear cmd */
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drc_dib.ctl = drd_dib.ctl = 0; /* clear ctl */
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drc_dib.fbf = drd_dib.fbf = 0; /* clear fbf */
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drc_dib.flg = drd_dib.flg = 0; /* clear flg */
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drc_dib.srq = drd_dib.srq = 0; /* srq follows flg */
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sim_cancel (&drc_unit);
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return SCPE_OK;
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}
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@@ -384,18 +390,17 @@ return SCPE_OK;
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/* Fixed head disk/drum bootstrap routine (disc subset of disc/paper tape loader) */
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#define CHANGE_DEV (1 << 24)
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#define BOOT_BASE 056
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#define BOOT_START 060
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static const int32 dboot[IBL_LNT - BOOT_BASE] = {
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0020000+CHANGE_DEV, /*DMA 20000+DC */
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static const uint16 dr_rom[IBL_LNT - BOOT_BASE] = {
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0020010, /*DMA 20000+DC */
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0000000, /* 0 */
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0107700, /* CLC 0,C */
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0063756, /* LDA DMA ; DMA ctrl */
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0102606, /* OTA 6 */
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0002700, /* CLA,CCE */
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0102601+CHANGE_DEV, /* OTA CC ; trk = sec = 0 */
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0102611, /* OTA CC ; trk = sec = 0 */
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0001500, /* ERA ; A = 100000 */
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0102602, /* OTA 2 ; DMA in, addr */
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0063777, /* LDA M64 */
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@@ -404,21 +409,25 @@ static const int32 dboot[IBL_LNT - BOOT_BASE] = {
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0103706, /* STC 6,C ; start DMA */
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0067776, /* LDB JSF ; get JMP . */
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0074077, /* STB 77 ; in base page */
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0102700+CHANGE_DEV, /* STC DC ; start disc */
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0102710, /* STC DC ; start disc */
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0024077, /*JSF JMP 77 ; go wait */
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0177700 }; /*M64 -100 */
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t_stat drc_boot (int32 unitno, DEVICE *dptr)
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{
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int32 i, dev, ad;
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uint16 wd;
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if (unitno != 0) return SCPE_NOFNC; /* only unit 0 */
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dev = drd_dib.devno; /* get data chan dev */
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ad = ((MEMSIZE - 1) & ~IBL_MASK) & VAMASK; /* start at mem top */
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for (i = 0; i < (IBL_LNT - BOOT_BASE); i++) { /* copy bootstrap */
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if (dboot[i] & CHANGE_DEV) /* IO instr? */
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M[ad + BOOT_BASE + i] = (dboot[i] + dev) & DMASK;
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else M[ad + BOOT_BASE + i] = dboot[i]; }
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for (i = BOOT_BASE; i < IBL_LNT; i++) { /* copy bootstrap */
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wd = dr_rom[i - BOOT_BASE]; /* get word */
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if (((wd & I_NMRMASK) == I_IO) && /* IO instruction? */
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((wd & I_DEVMASK) >= 010) && /* dev >= 10? */
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(I_GETIOOP (wd) != ioHLT)) /* not a HALT? */
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M[ad + i] = (wd + (dev - 010)) & DMASK;
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else M[ad + i] = wd; }
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PC = ad + BOOT_START;
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return SCPE_OK;
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}
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