mirror of
https://github.com/simh/simh.git
synced 2026-01-26 12:02:14 +00:00
Notes For V3.2-1
RESTRICTION: The PDP-15 FPP is only partially debugged. Do NOT enable this feature for normal operations. 1. New Features in 3.2-1 1.1 SCP and libraries - Added SET CONSOLE subhierarchy. - Added SHOW CONSOLE subhierarchy. - Added limited keyboard mapping capability. 1.2 HP2100 (new features from Dave Bryan) - Added instruction printout to HALT message. - Added M and T internal registers. - Added N, S, and U breakpoints. 1.3 PDP-11 and VAX - Added DHQ11 support (from John Dundas) 2. Bugs Fixed in 3.2-1 2.1 HP2100 (most fixes from Dave Bryan) - SBT increments B after store. - DMS console map must check dms_enb. - SFS x,C and SFC x,C work. - MP violation clears automatically on interrupt. - SFS/SFC 5 is not gated by protection enabled. - DMS enable does not disable mem prot checks. - DMS status inconsistent at simulator halt. - Examine/deposit are checking wrong addresses. - Physical addresses are 20b not 15b. - Revised DMS to use memory rather than internal format. - Revised IBL facility to conform to microcode. - Added DMA EDT I/O pseudo-opcode. - Separated DMA SRQ (service request) from FLG. - Revised peripherals to make SFS x,C and SFC x,C work. - Revised boot ROMs to use IBL facility. - Revised IBL treatment of SR to preserve SR<5:3>. - Fixed LPS, LPT timing. - Fixed DP boot interpretation of SR<0>. - Revised DR boot code to use IBL algorithm. - Fixed TTY input behavior during typeout for RTE-IV. - Suppressed nulls on TTY output for RTE-IV. - Added SFS x,C and SFC x,C to print/parse routines. - Fixed spurious timing error in magtape reads. 2.2 All DEC console devices - Removed SET TTI CTRL-C option. 2.3 PDP-11/VAX peripherals - Fixed bug in TQ reporting write protect status (reported by Lyle Bickley). - Fixed TK70 model number and media ID (found by Robert Schaffrath). - Fixed bug in autoconfigure (found by John Dundas). 2.4 VAX - Fixed bug in DIVBx and DIVWx (reported by Peter Trimmel).
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
26aa6de663
commit
e2ba672610
@@ -26,6 +26,7 @@
|
||||
The author gratefully acknowledges the help of Max Burnet, Megan Gentry,
|
||||
and John Wilson in resolving questions about the PDP-11
|
||||
|
||||
28-May-04 RMS Added DHQ support
|
||||
25-Jan-04 RMS Removed local debug logging support
|
||||
22-Dec-03 RMS Added second DEUNA/DELUA support
|
||||
18-Oct-03 RMS Added DECtape off reel message
|
||||
@@ -74,6 +75,8 @@
|
||||
#define UNIMEMSIZE 001000000 /* 2**18 */
|
||||
#define UNIMASK (UNIMEMSIZE - 1) /* 2**18 - 1 */
|
||||
#define IOPAGEBASE 017760000 /* 2**22 - 2**13 */
|
||||
#define IOPAGESIZE 000020000 /* 2**13 */
|
||||
#define IOPAGEMASK (IOPAGESIZE - 1) /* 2**13 - 1 */
|
||||
#define MAXMEMSIZE 020000000 /* 2**22 */
|
||||
#define PAMASK (MAXMEMSIZE - 1) /* 2**22 - 1 */
|
||||
#define MEMSIZE (cpu_unit.capac)
|
||||
@@ -308,8 +311,9 @@ typedef struct fpac fpac_t;
|
||||
|
||||
/* IO parameters */
|
||||
|
||||
#define DZ_MUXES 4 /* max # of muxes */
|
||||
#define DZ_LINES 8 /* lines per mux */
|
||||
#define DZ_MUXES 4 /* max # of DZ muxes */
|
||||
#define DZ_LINES 8 /* lines per DZ mux */
|
||||
#define VH_MUXES 4 /* max # of VH muxes */
|
||||
#define MT_MAXFR (1 << 16) /* magtape max rec */
|
||||
#define AUTO_LNT 34 /* autoconfig ranks */
|
||||
#define DIB_MAX 100 /* max DIBs */
|
||||
@@ -359,6 +363,8 @@ typedef struct pdp_dib DIB;
|
||||
#define IOLN_RQC 004
|
||||
#define IOBA_RQD (IOPAGEBASE + IOBA_RQC + IOLN_RQC)
|
||||
#define IOLN_RQD 004
|
||||
#define IOBA_VH (IOPAGEBASE + 000440) /* DHQ11 */
|
||||
#define IOLN_VH 020
|
||||
#define IOBA_UBM (IOPAGEBASE + 010200) /* Unibus map */
|
||||
#define IOLN_UBM (UBM_LNT_LW * sizeof (int32))
|
||||
#define IOBA_RQ (IOPAGEBASE + 012150) /* RQDX3 */
|
||||
@@ -446,7 +452,9 @@ typedef struct pdp_dib DIB;
|
||||
#define INT_V_PTR 2
|
||||
#define INT_V_PTP 3
|
||||
#define INT_V_LPT 4
|
||||
#define INT_V_PIR4 5
|
||||
#define INT_V_VHRX 5
|
||||
#define INT_V_VHTX 6
|
||||
#define INT_V_PIR4 7
|
||||
|
||||
#define INT_V_PIR3 0 /* BR3 */
|
||||
#define INT_V_PIR2 0 /* BR2 */
|
||||
@@ -477,6 +485,8 @@ typedef struct pdp_dib DIB;
|
||||
#define INT_TTI (1u << INT_V_TTI)
|
||||
#define INT_TTO (1u << INT_V_TTO)
|
||||
#define INT_LPT (1u << INT_V_LPT)
|
||||
#define INT_VHRX (1u << INT_V_VHRX)
|
||||
#define INT_VHTX (1u << INT_V_VHTX)
|
||||
#define INT_PIR4 (1u << INT_V_PIR4)
|
||||
#define INT_PIR3 (1u << INT_V_PIR3)
|
||||
#define INT_PIR2 (1u << INT_V_PIR2)
|
||||
@@ -504,6 +514,8 @@ typedef struct pdp_dib DIB;
|
||||
#define IPL_TTI 4
|
||||
#define IPL_TTO 4
|
||||
#define IPL_LPT 4
|
||||
#define IPL_VHRX 4
|
||||
#define IPL_VHTX 4
|
||||
|
||||
#define IPL_PIR7 7
|
||||
#define IPL_PIR6 6
|
||||
@@ -539,6 +551,8 @@ typedef struct pdp_dib DIB;
|
||||
#define VEC_RY 0264
|
||||
#define VEC_DZRX 0300
|
||||
#define VEC_DZTX 0304
|
||||
#define VEC_VHRX 0310
|
||||
#define VEC_VHTX 0314
|
||||
|
||||
/* Autoconfigure ranks */
|
||||
|
||||
@@ -548,6 +562,7 @@ typedef struct pdp_dib DIB;
|
||||
#define RANK_XU 25
|
||||
#define RANK_RQ 26
|
||||
#define RANK_TQ 30
|
||||
#define RANK_VH 32
|
||||
|
||||
/* Interrupt macros */
|
||||
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
To: Users
|
||||
From: Bob Supnik
|
||||
Subj: PDP-11 Simulator Usage
|
||||
Date: 04-Apr-2004
|
||||
Date: 15-Jun-2004
|
||||
|
||||
COPYRIGHT NOTICE
|
||||
|
||||
@@ -84,6 +84,7 @@ sim/pdp11/ pdp11_defs.h
|
||||
pdp11_tc.c
|
||||
pdp11_tm.c
|
||||
pdp11_ts.c
|
||||
pdp11_vh.c
|
||||
pdp11_xq.c
|
||||
pdp11_xu.c
|
||||
|
||||
@@ -103,6 +104,7 @@ LPT LP11 line printer
|
||||
CLK line frequency clock
|
||||
PCLK KW11P programmable clock
|
||||
DZ DZ11 8-line terminal multiplexor (up to 4)
|
||||
VH DHQ11 8-line terminal multiplexor (up to 4)
|
||||
RK RK11/RK05 cartridge disk controller with eight drives
|
||||
HK RK611/RK06(7) cartridge disk controller with eight drives
|
||||
RL RLV12/RL01(2) cartridge disk controller with four drives
|
||||
@@ -144,12 +146,12 @@ The CPU options include CPU mapping configuration (18b Unibus, 22b Unibus
|
||||
with RH70-style controllers, 22b Unibus with RH11 style controllers, and
|
||||
22b Qbus), the CIS instruction set, and the size of main memory.
|
||||
|
||||
SET CPU 18B 18b addressing, no I/O map
|
||||
SET CPU URH11 22b addresssing, Unibus I/O map,
|
||||
SET CPU U18 Unibus, no I/O map, 18b addressing
|
||||
SET CPU URH11 Unibus, I/O map with 22b addressing,
|
||||
18b mapped RH11 controller
|
||||
SET CPU URH70 22b addressing, Unibus I/O map,
|
||||
SET CPU URH70 Unibus, I/O map with 22b addressing,
|
||||
22b unmapped RH70 controller
|
||||
SET CPU 22B 22b addressing, no I/O map (Qbus)
|
||||
SET CPU Q22 Qbus, no I/O map, 22b addressing
|
||||
SET CPU NOCIS disable CIS instructions (default)
|
||||
SET CPU CIS enable CIS instructions
|
||||
SET CPU 16K set memory size = 16KB
|
||||
@@ -395,12 +397,6 @@ implements these registers:
|
||||
POS 32 number of characters input
|
||||
TIME 24 keyboard polling interval
|
||||
|
||||
If the simulator is compiled under Windows Visual C++, typing ^C to the
|
||||
terminal input causes a fatal run-time error. Use the following command
|
||||
to simulate typing ^C:
|
||||
|
||||
SET TTI CTRL-C
|
||||
|
||||
2.3.4 DL11 Terminal Output (TTO)
|
||||
|
||||
The terminal output (TTO) writes to the simulator console window. It
|
||||
@@ -499,81 +495,6 @@ up or down so that the clock tracks actual elapsed time. Operation at
|
||||
the highest clock rate (100Khz) is not recommended. The programmable
|
||||
clock is disabled by default.
|
||||
|
||||
2.3.8 DZ11 Terminal Multiplexor (DZ)
|
||||
|
||||
The DZ11 is an 8-line terminal multiplexor. Up to 4 DZ11's (32 lines)
|
||||
are supported. The number of lines can be changed with the command
|
||||
|
||||
SET DZ LINES=n set line count to n
|
||||
|
||||
The line count must be a multiple of 8, with a maximum of 32.
|
||||
|
||||
The DZ11 supports 8-bit input and output of characters. 8-bit output
|
||||
may be incompatible with certain operating systems. The command
|
||||
|
||||
SET DZ 7B
|
||||
|
||||
forces output characters (only) to be masked to 7 bits.
|
||||
|
||||
The DZ11 supports logging on a per-line basis. The command
|
||||
|
||||
SET DZ LOG=line=filename
|
||||
|
||||
enables logging for the specified line to the indicated file. The
|
||||
command
|
||||
|
||||
SET DZ NOLOG=line
|
||||
|
||||
disables logging for the specified line and closes any open log file.
|
||||
Finally, the command
|
||||
|
||||
SHOW DZ LOG
|
||||
|
||||
displays logging information for all DZ lines.
|
||||
|
||||
The terminal lines perform input and output through Telnet sessions
|
||||
connected to a user-specified port. The ATTACH command specifies
|
||||
the port to be used:
|
||||
|
||||
ATTACH {-am} DZ <port> set up listening port
|
||||
|
||||
where port is a decimal number between 1 and 65535 that is not being used
|
||||
for other TCP/IP activities. The optional switch -m turns on the DZ11's
|
||||
modem controls; the optional switch -a turns on active disconnects
|
||||
(disconnect session if computer clears Data Terminal Ready). Without
|
||||
modem control, the DZ behaves as though terminals were directly connected;
|
||||
disconnecting the Telnet session does not cause any operating system-
|
||||
visible change in line status.
|
||||
|
||||
Once the DZ is attached and the simulator is running, the DZ will listen
|
||||
for connections on the specified port. It assumes that the incoming
|
||||
connections are Telnet connections. The connection remains open until
|
||||
disconnected by the simulated program, the Telnet client, a SET DZ
|
||||
DISCONNECT command, or a DETACH DZ command.
|
||||
|
||||
The SHOW DZ CONNECTIONS command displays the current connections to the DZ.
|
||||
The SHOW DZ STATISTICS command displays statistics for active connections.
|
||||
The SET DZ DISCONNECT=linenumber disconnects the specified line.
|
||||
|
||||
The DZ11 implements these registers:
|
||||
|
||||
name size comments
|
||||
|
||||
CSR[0:3] 16 control/status register, boards 0..3
|
||||
RBUF[0:3] 16 receive buffer, boards 0..3
|
||||
LPR[0:3] 16 line parameter register, boards 0..3
|
||||
TCR[0:3] 16 transmission control register, boards 0..3
|
||||
MSR[0:3] 16 modem status register, boards 0..3
|
||||
TDR[0:3] 16 transmit data register, boards 0..3
|
||||
SAENB[0:3] 1 silo alarm enabled, boards 0..3
|
||||
RXINT 4 receive interrupts, boards 3..0
|
||||
TXINT 4 transmit interrupts, boards 3..0
|
||||
MDMTCL 1 modem control enabled
|
||||
AUTODS 1 autodisconnect enabled
|
||||
|
||||
The DZ11 does not support save and restore. All open connections are
|
||||
lost when the simulator shuts down or the DZ is detached.
|
||||
|
||||
2.4 Floppy Disk Drives
|
||||
|
||||
2.4.1 RX11/RX01 Floppy Disk (RX)
|
||||
@@ -1217,7 +1138,166 @@ Error handling is as follows:
|
||||
|
||||
OS I/O error fatal tape error
|
||||
|
||||
2.10 DELQA/DEQNA Qbus Ethernet Controllers (XQ, XQB)
|
||||
2.10 Communications Devices
|
||||
|
||||
2.10.1 DZ11 Terminal Multiplexor (DZ)
|
||||
|
||||
The DZ11 is an 8-line terminal multiplexor. Up to 4 DZ11's (32 lines)
|
||||
are supported. The number of lines can be changed with the command
|
||||
|
||||
SET DZ LINES=n set line count to n
|
||||
|
||||
The line count must be a multiple of 8, with a maximum of 32.
|
||||
|
||||
The DZ11 supports 8-bit input and output of characters. 8-bit output
|
||||
may be incompatible with certain operating systems. The command
|
||||
|
||||
SET DZ 7B
|
||||
|
||||
forces output characters (only) to be masked to 7 bits.
|
||||
|
||||
The DZ11 supports logging on a per-line basis. The command
|
||||
|
||||
SET DZ LOG=line=filename
|
||||
|
||||
enables logging for the specified line to the indicated file. The
|
||||
command
|
||||
|
||||
SET DZ NOLOG=line
|
||||
|
||||
disables logging for the specified line and closes any open log file.
|
||||
Finally, the command
|
||||
|
||||
SHOW DZ LOG
|
||||
|
||||
displays logging information for all DZ lines.
|
||||
|
||||
The terminal lines perform input and output through Telnet sessions
|
||||
connected to a user-specified port. The ATTACH command specifies
|
||||
the port to be used:
|
||||
|
||||
ATTACH {-am} DZ <port> set up listening port
|
||||
|
||||
where port is a decimal number between 1 and 65535 that is not being used
|
||||
for other TCP/IP activities. The optional switch -m turns on the DZ11's
|
||||
modem controls; the optional switch -a turns on active disconnects
|
||||
(disconnect session if computer clears Data Terminal Ready). Without
|
||||
modem control, the DZ behaves as though terminals were directly connected;
|
||||
disconnecting the Telnet session does not cause any operating system-
|
||||
visible change in line status.
|
||||
|
||||
Once the DZ is attached and the simulator is running, the DZ will listen
|
||||
for connections on the specified port. It assumes that the incoming
|
||||
connections are Telnet connections. The connection remains open until
|
||||
disconnected by the simulated program, the Telnet client, a SET DZ
|
||||
DISCONNECT command, or a DETACH DZ command.
|
||||
|
||||
The SHOW DZ CONNECTIONS command displays the current connections to the DZ.
|
||||
The SHOW DZ STATISTICS command displays statistics for active connections.
|
||||
The SET DZ DISCONNECT=linenumber disconnects the specified line.
|
||||
|
||||
The DZ11 implements these registers:
|
||||
|
||||
name size comments
|
||||
|
||||
CSR[0:3] 16 control/status register, boards 0..3
|
||||
RBUF[0:3] 16 receive buffer, boards 0..3
|
||||
LPR[0:3] 16 line parameter register, boards 0..3
|
||||
TCR[0:3] 16 transmission control register, boards 0..3
|
||||
MSR[0:3] 16 modem status register, boards 0..3
|
||||
TDR[0:3] 16 transmit data register, boards 0..3
|
||||
SAENB[0:3] 1 silo alarm enabled, boards 0..3
|
||||
RXINT 4 receive interrupts, boards 3..0
|
||||
TXINT 4 transmit interrupts, boards 3..0
|
||||
MDMTCL 1 modem control enabled
|
||||
AUTODS 1 autodisconnect enabled
|
||||
|
||||
The DZ11 does not support save and restore. All open connections are
|
||||
lost when the simulator shuts down or the DZ is detached.
|
||||
|
||||
2.10.2 DHQ11 Terminal Multiplexor (VH)
|
||||
|
||||
The DHQ11 is an 8-line terminal multiplexor for Qbus systems. Up
|
||||
to 4 DHQ11's are supported.
|
||||
|
||||
The DHQ11 is a programmable asynchronous terminal multiplexor. It
|
||||
has two programming modes: DHV11 and DHU11. The register sets are
|
||||
compatible with these devices. For transmission, the DHQ11 can be
|
||||
used in either DMA or programmed I/O mode. For reception, there
|
||||
is a 256-entry FIFO for received characters, dataset status changes,
|
||||
and diagnostic information, and a programmable input interrupt
|
||||
timer (in DHU mode). The device supports 16-, 18-, and 22-bit
|
||||
addressing. The DHQ11 can be programmed to filter and/or handle
|
||||
XON/XOFF characters independently of the processor. The DHQ11
|
||||
supports programmable bit width (between 5 and 8) for the input
|
||||
and output of characters.
|
||||
|
||||
The DHQ11 has a rocker switch for determining the programming mode.
|
||||
By default, the DHV11 mode is selected, though DHU11 mode is
|
||||
recommended for applications that can support it. The VH controller
|
||||
may be adjusted on a per controller basis as follows:
|
||||
|
||||
SET VHn DHU use the DHU programming mode and registers
|
||||
SET VHn DHV use the DHV programming mode and registers
|
||||
|
||||
DMA output is supported. In a real DHQ11, DMA is not initiated
|
||||
immediately upon receipt of TX.DMA.START but is dependent upon some
|
||||
internal processes. The VH controller mimics this behavior by default.
|
||||
It may be desirable to alter this and start immediately, though
|
||||
this may not be compatible with all operating systems and diagnostics.
|
||||
You can change the behavior of the VH controller as follows:
|
||||
|
||||
SET VHn NORMAL use normal DMA procedures
|
||||
SET VHn FASTDMA set DMA to initiate immediately
|
||||
|
||||
The terminal lines perform input and output through Telnet sessions
|
||||
connected to a user-specified port. The ATTACH command specifies
|
||||
the port to be used:
|
||||
|
||||
ATTACH VH <port> set up listening port
|
||||
DETACH VH
|
||||
|
||||
where port is a decimal number between 1 and 65535 that is not
|
||||
being used for other TCP/IP activities. This port is the point of
|
||||
entry for al lines on all VH controllers.
|
||||
|
||||
Modem and auto-disconnect support may be set on an individual
|
||||
controller basis. The SET MODEM command directs the controller to
|
||||
report modem status changes to the computer. The SET HANGUP command
|
||||
turns on active disconnects (disconnect session if computer clears
|
||||
Data Terminal Ready).
|
||||
|
||||
SET VHn [NO]MODEM disable/enable modem control
|
||||
SET VHn [NO]HANGUP disable/enable disconnect on DTR drop
|
||||
|
||||
Once the VH is attached and the simulator is running, the VH will
|
||||
listen for connections on the specified port. It assumes that the
|
||||
incoming connections are Telnet connections. The connection remains
|
||||
open until disconnected by the simulated program, the Telnet client,
|
||||
a SET VH DISCONNECT command, or a DETACH VH command.
|
||||
|
||||
The SHOW VH CONNECTIONS command displays the current connections to the VH.
|
||||
The SHOW VH STATISTICS command displays statistics for active connections.
|
||||
The SET VH DISCONNECT=linenumber disconnects the specified line.
|
||||
|
||||
The DHQ11 implements these registers, though not all can be examined
|
||||
from SCP:
|
||||
|
||||
name size comments
|
||||
|
||||
CSR[0:3] 16 control/status register, boards 0..3
|
||||
RBUF[0:3] 16 receive buffer, boards 0..3
|
||||
LPR[0:3] 16 line parameter register, boards 0..3
|
||||
RXINT 4 receive interrupts, boards 3..0
|
||||
TXINT 4 transmit interrupts, boards 3..0
|
||||
[more to be described...]
|
||||
|
||||
The DHQ11 does not support save and restore. All open connections
|
||||
are lost when the simulator shuts down or the VH is detached.
|
||||
|
||||
2.11 Ethernet Controllers
|
||||
|
||||
2.11.1 DELQA/DEQNA Qbus Ethernet Controllers (XQ, XQB)
|
||||
|
||||
The simulator implements two DELQA/DEQNA Qbus Ethernet controllers (XQ,
|
||||
XQB). Initially, XQ is enabled, and XQB is disabled. Options allow
|
||||
@@ -1301,10 +1381,10 @@ not limited to the ~1.5Mbit/sec of the real DEQNA/DELQA controllers,
|
||||
nor the 10Mbit/sec of a standard Ethernet. Attach it to a Fast Ethernet
|
||||
(100 Mbit/sec) card, and "Feel the Power!" :-)
|
||||
|
||||
2.11 DEUNA/DELUA Unibus Ethernet Controller (XU)
|
||||
2.11.2 DEUNA/DELUA Unibus Ethernet Controller (XU)
|
||||
|
||||
XU simulates the DEUNA/DELUA Unibus Ethernet controller. THe current
|
||||
implementation is a stub and is permanently disabled.
|
||||
XU simulates the DEUNA/DELUA Unibus Ethernet controller. Its operation
|
||||
is analagous to the DELQA/DEQNA controller.
|
||||
|
||||
2.12 Symbolic Display and Input
|
||||
|
||||
|
||||
244
PDP11/pdp11_io.c
244
PDP11/pdp11_io.c
@@ -23,6 +23,7 @@
|
||||
be used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from Robert M Supnik.
|
||||
|
||||
28-May-04 RMS Revised I/O dispatching (from John Dundas)
|
||||
25-Jan-04 RMS Removed local debug logging support
|
||||
21-Dec-03 RMS Fixed bug in autoconfigure vector assignment; added controls
|
||||
21-Nov-03 RMS Added check for interrupt slot conflict (found by Dave Hittner)
|
||||
@@ -42,13 +43,13 @@
|
||||
extern uint16 *M;
|
||||
extern int32 int_req[IPL_HLVL];
|
||||
extern int32 ub_map[UBM_LNT_LW];
|
||||
extern UNIT cpu_unit;
|
||||
extern int32 cpu_bme, cpu_18b, cpu_ubm;
|
||||
extern int32 trap_req, ipl;
|
||||
extern int32 cpu_log;
|
||||
extern int32 autcon_enb;
|
||||
extern FILE *sim_log;
|
||||
extern DEVICE *sim_devices[];
|
||||
extern DEVICE *sim_devices[], cpu_dev;
|
||||
extern UNIT cpu_unit;
|
||||
|
||||
int32 calc_ints (int32 nipl, int32 trq);
|
||||
|
||||
@@ -57,7 +58,9 @@ extern DIB cpu3_dib, cpu4_dib, ubm_dib;
|
||||
|
||||
/* I/O data structures */
|
||||
|
||||
DIB *dib_tab[DIB_MAX]; /* run time DIBs */
|
||||
static t_stat (*iodispR[IOPAGESIZE >> 1])(int32 *dat, int32 ad, int32 md);
|
||||
static t_stat (*iodispW[IOPAGESIZE >> 1])(int32 dat, int32 ad, int32 md);
|
||||
static DIB *iodibp[IOPAGESIZE >> 1];
|
||||
|
||||
int32 int_vec[IPL_HLVL][32]; /* int req to vector */
|
||||
|
||||
@@ -71,9 +74,9 @@ static DIB *std_dib[] = { /* standard DIBs */
|
||||
&cpu4_dib,
|
||||
NULL };
|
||||
|
||||
static int32 pirq_vloc[7] = {
|
||||
IVCL (PIR7), IVCL (PIR6), IVCL (PIR5), IVCL (PIR4),
|
||||
IVCL (PIR3), IVCL (PIR2), IVCL (PIR1) };
|
||||
static const int32 pirq_bit[7] = {
|
||||
INT_V_PIR1, INT_V_PIR2, INT_V_PIR3, INT_V_PIR4,
|
||||
INT_V_PIR5, INT_V_PIR6, INT_V_PIR7 };
|
||||
|
||||
/* I/O page lookup and linkage routines
|
||||
|
||||
@@ -88,31 +91,27 @@ static int32 pirq_vloc[7] = {
|
||||
|
||||
t_stat iopageR (int32 *data, uint32 pa, int32 access)
|
||||
{
|
||||
int32 i;
|
||||
DIB *dibp;
|
||||
int32 idx;
|
||||
t_stat stat;
|
||||
|
||||
for (i = 0; dibp = dib_tab[i]; i++ ) {
|
||||
if ((pa >= dibp->ba) &&
|
||||
(pa < (dibp->ba + dibp->lnt))) {
|
||||
stat = dibp->rd (data, pa, access);
|
||||
trap_req = calc_ints (ipl, trap_req);
|
||||
return stat; } }
|
||||
idx = (pa & IOPAGEMASK) >> 1;
|
||||
if (iodispR[idx]) {
|
||||
stat = iodispR[idx] (data, pa, access);
|
||||
trap_req = calc_ints (ipl, trap_req);
|
||||
return stat; }
|
||||
return SCPE_NXM;
|
||||
}
|
||||
|
||||
t_stat iopageW (int32 data, uint32 pa, int32 access)
|
||||
{
|
||||
int32 i;
|
||||
DIB *dibp;
|
||||
int32 idx;
|
||||
t_stat stat;
|
||||
|
||||
for (i = 0; dibp = dib_tab[i]; i++ ) {
|
||||
if ((pa >= dibp->ba) &&
|
||||
(pa < (dibp->ba + dibp->lnt))) {
|
||||
stat = dibp->wr (data, pa, access);
|
||||
trap_req = calc_ints (ipl, trap_req);
|
||||
return stat; } }
|
||||
idx = (pa & IOPAGEMASK) >> 1;
|
||||
if (iodispW[idx]) {
|
||||
stat = iodispW[idx] (data, pa, access);
|
||||
trap_req = calc_ints (ipl, trap_req);
|
||||
return stat; }
|
||||
return SCPE_NXM;
|
||||
}
|
||||
|
||||
@@ -422,123 +421,126 @@ else { fprintf (st, "vector=%o", vec);
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Test for conflict in device addresses */
|
||||
/* Build dispatch tables */
|
||||
|
||||
t_bool dev_conflict (DIB *curr)
|
||||
t_stat build_dsp_tab (DEVICE *dptr, DIB *dibp)
|
||||
{
|
||||
uint32 i, end;
|
||||
DEVICE *dptr;
|
||||
DIB *dibp;
|
||||
uint32 i, idx;
|
||||
|
||||
end = curr->ba + curr->lnt - 1; /* get end */
|
||||
for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */
|
||||
dibp = (DIB *) dptr->ctxt; /* get DIB */
|
||||
if ((dibp == NULL) || (dibp == curr) ||
|
||||
(dptr->flags & DEV_DIS)) continue;
|
||||
if (((curr->ba >= dibp->ba) && /* overlap start? */
|
||||
(curr->ba < (dibp->ba + dibp->lnt))) ||
|
||||
((end >= dibp->ba) && /* overlap end? */
|
||||
(end < (dibp->ba + dibp->lnt)))) {
|
||||
printf ("Device %s address conflict at %08o\n",
|
||||
sim_dname (dptr), dibp->ba);
|
||||
if (sim_log) fprintf (sim_log,
|
||||
"Device %s address conflict at %08o\n",
|
||||
sim_dname (dptr), dibp->ba);
|
||||
return TRUE; } }
|
||||
return FALSE;
|
||||
if ((dptr == NULL) || (dibp == NULL)) return SCPE_IERR; /* validate args */
|
||||
for (i = 0; i < dibp->lnt; i = i + 2) { /* create entries */
|
||||
idx = ((dibp->ba + i) & IOPAGEMASK) >> 1; /* index into disp */
|
||||
if ((iodispR[idx] && dibp->rd && /* conflict? */
|
||||
(iodispR[idx] != dibp->rd)) ||
|
||||
(iodispW[idx] && dibp->wr &&
|
||||
(iodispW[idx] != dibp->wr))) {
|
||||
printf ("Device %s address conflict at %08o\n",
|
||||
sim_dname (dptr), dibp->ba);
|
||||
if (sim_log) fprintf (sim_log,
|
||||
"Device %s address conflict at %08o\n",
|
||||
sim_dname (dptr), dibp->ba);
|
||||
return SCPE_STOP;
|
||||
}
|
||||
if (dibp->rd) iodispR[idx] = dibp->rd; /* set rd dispatch */
|
||||
if (dibp->wr) iodispW[idx] = dibp->wr; /* set wr dispatch */
|
||||
iodibp[idx] = dibp; /* remember DIB */
|
||||
}
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Build interrupt tables */
|
||||
|
||||
t_bool build_int_vec (int32 vloc, int32 ivec, int32 (*iack)(void) )
|
||||
t_stat build_int_vec (DEVICE *dptr, DIB *dibp)
|
||||
{
|
||||
int32 ilvl = vloc / 32;
|
||||
int32 ibit = vloc % 32;
|
||||
int32 i, idx, vec, ilvl, ibit;
|
||||
|
||||
if (iack != NULL) {
|
||||
if (int_ack[ilvl][ibit] &&
|
||||
(int_ack[ilvl][ibit] != iack)) return TRUE;
|
||||
int_ack[ilvl][ibit] = iack; }
|
||||
else if (ivec != 0) {
|
||||
if (int_vec[ilvl][ibit] &&
|
||||
(int_vec[ilvl][ibit] != ivec)) return TRUE;
|
||||
int_vec[ilvl][ibit] = ivec; }
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/* Build dib_tab from device list */
|
||||
|
||||
t_stat build_dib_tab (int32 ubm)
|
||||
{
|
||||
int32 i, j, k;
|
||||
DEVICE *dptr;
|
||||
DIB *dibp;
|
||||
|
||||
for (i = 0; i < IPL_HLVL; i++) { /* clear int tables */
|
||||
for (j = 0; j < 32; j++) {
|
||||
int_vec[i][j] = 0;
|
||||
int_ack[i][j] = NULL; } }
|
||||
for (i = j = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */
|
||||
dibp = (DIB *) dptr->ctxt; /* get DIB */
|
||||
if (dibp && !(dptr->flags & DEV_DIS)) { /* defined, enabled? */
|
||||
if (dibp->vnum > VEC_DEVMAX) return SCPE_IERR;
|
||||
for (k = 0; k < dibp->vnum; k++) { /* loop thru vec */
|
||||
if (build_int_vec (dibp->vloc + k, /* add vector */
|
||||
dibp->vec + (k * 4), dibp->ack[k])) {
|
||||
printf ("Device %s interrupt slot conflict at %d\n",
|
||||
sim_dname (dptr), dibp->vloc + k);
|
||||
if (sim_log) fprintf (sim_log,
|
||||
"Device %s interrupt slot conflict at %d\n",
|
||||
sim_dname (dptr), dibp->vloc + k);
|
||||
return SCPE_IERR; } }
|
||||
if (dibp->lnt != 0) { /* I/O addresses? */
|
||||
dib_tab[j++] = dibp; /* add DIB to dib_tab */
|
||||
if (j >= DIB_MAX) return SCPE_IERR; } /* too many? */
|
||||
} /* end if enabled */
|
||||
} /* end for */
|
||||
for (i = 0; (dibp = std_dib[i]) != NULL; i++) { /* loop thru std */
|
||||
dib_tab[j++] = dibp; /* add to dib_tab */
|
||||
if (j >= DIB_MAX) return SCPE_IERR; } /* too many? */
|
||||
if (ubm) { /* Unibus map? */
|
||||
dib_tab[j++] = &ubm_dib; /* add to dib_tab */
|
||||
if (j >= DIB_MAX) return SCPE_IERR; } /* too many? */
|
||||
dib_tab[j] = NULL; /* end with NULL */
|
||||
for (i = 0; i < 7; i++) /* add PIRQ intr */
|
||||
build_int_vec (pirq_vloc[i], VEC_PIRQ, NULL);
|
||||
for (i = 0; (dibp = dib_tab[i]) != NULL; i++) { /* test built dib_tab */
|
||||
if (dev_conflict (dibp)) {
|
||||
return SCPE_STOP; } } /* for conflicts */
|
||||
if ((dptr == NULL) || (dibp == NULL)) return SCPE_IERR; /* validate args */
|
||||
if (dibp->vnum > VEC_DEVMAX) return SCPE_IERR;
|
||||
for (i = 0; i < dibp->vnum; i++) { /* loop thru vec */
|
||||
idx = dibp->vloc + i; /* vector index */
|
||||
vec = dibp->vec? (dibp->vec + (i * 4)): 0; /* vector addr */
|
||||
ilvl = idx / 32;
|
||||
ibit = idx % 32;
|
||||
if ((int_ack[ilvl][ibit] && dibp->ack[i] && /* conflict? */
|
||||
(int_ack[ilvl][ibit] != dibp->ack[i])) ||
|
||||
(int_vec[ilvl][ibit] && vec &&
|
||||
(int_vec[ilvl][ibit] != vec))) {
|
||||
printf ("Device %s interrupt slot conflict at %d\n",
|
||||
sim_dname (dptr), idx);
|
||||
if (sim_log) fprintf (sim_log,
|
||||
"Device %s interrupt slot conflict at %d\n",
|
||||
sim_dname (dptr), idx);
|
||||
return SCPE_STOP;
|
||||
}
|
||||
if (dibp->ack[i]) int_ack[ilvl][ibit] = dibp->ack[i];
|
||||
else if (vec) int_vec[ilvl][ibit] = vec;
|
||||
}
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Show dib_tab */
|
||||
/* Build tables from device list */
|
||||
|
||||
t_stat build_dib_tab (int32 ubm)
|
||||
{
|
||||
int32 i, j;
|
||||
DEVICE *dptr;
|
||||
DIB *dibp;
|
||||
t_stat r;
|
||||
|
||||
for (i = 0; i < IPL_HLVL; i++) { /* clear intr tab */
|
||||
for (j = 0; j < 32; j++) {
|
||||
int_vec[i][j] = 0;
|
||||
int_ack[i][j] = NULL; } }
|
||||
for (i = 0; i < (IOPAGESIZE >> 1); i++) { /* clear dispatch tab */
|
||||
iodispR[i] = NULL;
|
||||
iodispW[i] = NULL;
|
||||
iodibp[i] = NULL; }
|
||||
for (i = 0; i < 7; i++) /* seed PIRQ intr */
|
||||
int_vec[i + 1][pirq_bit[i]] = VEC_PIRQ;
|
||||
for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */
|
||||
dibp = (DIB *) dptr->ctxt; /* get DIB */
|
||||
if (dibp && !(dptr->flags & DEV_DIS)) { /* defined, enabled? */
|
||||
if (r = build_int_vec (dptr, dibp)) /* add to intr tab */
|
||||
return r;
|
||||
if (r = build_dsp_tab (dptr, dibp)) /* add to dispatch tab */
|
||||
return r;
|
||||
} /* end if enabled */
|
||||
} /* end for */
|
||||
for (i = 0; std_dib[i] != NULL; i++) { /* loop thru std */
|
||||
if (r = build_dsp_tab (&cpu_dev, std_dib[i])) /* add to dispatch tab */
|
||||
return r;
|
||||
}
|
||||
if (ubm) { /* Unibus map? */
|
||||
if (r = build_dsp_tab (&cpu_dev, &ubm_dib)) /* add to dispatch tab */
|
||||
return r;
|
||||
}
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Show IO space */
|
||||
|
||||
t_stat show_iospace (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||
{
|
||||
int32 i, j, done = 0;
|
||||
uint32 i, j;
|
||||
DEVICE *dptr;
|
||||
DIB *dibt;
|
||||
DIB *dibp;
|
||||
|
||||
build_dib_tab (cpu_ubm); /* build table */
|
||||
while (done == 0) { /* sort ascending */
|
||||
done = 1; /* assume done */
|
||||
for (i = 0; dib_tab[i + 1] != NULL; i++) { /* check table */
|
||||
if (dib_tab[i]->ba > dib_tab[i + 1]->ba) { /* out of order? */
|
||||
dibt = dib_tab[i]; /* interchange */
|
||||
dib_tab[i] = dib_tab[i + 1];
|
||||
dib_tab[i + 1] = dibt;
|
||||
done = 0; } } /* not done */
|
||||
} /* end while */
|
||||
for (i = 0; dib_tab[i] != NULL; i++) { /* print table */
|
||||
for (j = 0, dptr = NULL; sim_devices[j] != NULL; j++) {
|
||||
if (((DIB*) sim_devices[j]->ctxt) == dib_tab[i]) {
|
||||
dptr = sim_devices[j];
|
||||
break; } }
|
||||
fprintf (st, "%08o - %08o%c\t%s\n", dib_tab[i]->ba,
|
||||
dib_tab[i]->ba + dib_tab[i]->lnt - 1,
|
||||
if (build_dib_tab (cpu_ubm)) return SCPE_OK; /* build IO page */
|
||||
for (i = 0, dibp = NULL; i < (IOPAGESIZE >> 1); i++) { /* loop thru entries */
|
||||
if (iodibp[i] && (iodibp[i] != dibp)) { /* new block? */
|
||||
dibp = iodibp[i]; /* DIB for block */
|
||||
for (j = 0, dptr = NULL; sim_devices[j] != NULL; j++) {
|
||||
if (((DIB*) sim_devices[j]->ctxt) == dibp) {
|
||||
dptr = sim_devices[j]; /* locate device */
|
||||
break;
|
||||
} /* end if */
|
||||
} /* end for j */
|
||||
fprintf (st, "%08o - %08o%c\t%s\n", /* print block entry */
|
||||
dibp->ba, dibp->ba + dibp->lnt - 1,
|
||||
(dptr && (dptr->flags & DEV_FLTA))? '*': ' ',
|
||||
dptr? sim_dname (dptr): "CPU");
|
||||
}
|
||||
} /* end if */
|
||||
} /* end for i */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
@@ -593,7 +595,7 @@ struct auto_con auto_tab[AUTO_LNT + 1] = {
|
||||
{ 0xf, 0x3 }, /* VS100 */
|
||||
{ 0x3, 0x3, AUTO_DYN|AUTO_VEC, 0, IOBA_TQ, { "TQ", "TQB" } },
|
||||
{ 0xf, 0x7 }, /* KMV11 */
|
||||
{ 0xf, 0x7 }, /* DHU11/DHQ11 */
|
||||
{ 0x1f, 0x7, AUTO_VEC, VH_MUXES, 0, { "VH" } }, /* DHU11/DHQ11 */
|
||||
|
||||
{ 0x1f, 0x7 }, /* DMZ32 */
|
||||
{ 0x1f, 0x7 }, /* CP132 */
|
||||
|
||||
@@ -26,6 +26,7 @@
|
||||
tti,tto DL11 terminal input/output
|
||||
clk KW11L line frequency clock
|
||||
|
||||
28-May-04 RMS Removed SET TTI CTRL-C
|
||||
29-Dec-03 RMS Added console backpressure support
|
||||
25-Apr-03 RMS Revised for extended file support
|
||||
01-Mar-03 RMS Added SET/SHOW CLOCK FREQ, SET TTI CTRL-C
|
||||
@@ -80,7 +81,6 @@ t_stat tto_rd (int32 *data, int32 PA, int32 access);
|
||||
t_stat tto_wr (int32 data, int32 PA, int32 access);
|
||||
t_stat tto_svc (UNIT *uptr);
|
||||
t_stat tto_reset (DEVICE *dptr);
|
||||
t_stat tti_set_ctrlc (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||
t_stat tty_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||
t_stat clk_rd (int32 *data, int32 PA, int32 access);
|
||||
t_stat clk_wr (int32 data, int32 PA, int32 access);
|
||||
@@ -115,8 +115,6 @@ REG tti_reg[] = {
|
||||
MTAB tti_mod[] = {
|
||||
{ UNIT_8B, 0 , "7b" , "7B" , &tty_set_mode },
|
||||
{ UNIT_8B, UNIT_8B , "8b" , "8B" , &tty_set_mode },
|
||||
{ MTAB_XTD|MTAB_VDV|MTAB_VUN, 0, NULL, "CTRL-C",
|
||||
&tti_set_ctrlc, NULL, NULL },
|
||||
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
|
||||
NULL, &show_addr, NULL },
|
||||
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
|
||||
@@ -267,18 +265,6 @@ CLR_INT (TTI);
|
||||
sim_activate (&tti_unit, tti_unit.wait); /* activate unit */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Set control-C */
|
||||
|
||||
t_stat tti_set_ctrlc (UNIT *uptr, int32 val, char *cptr, void *desc)
|
||||
{
|
||||
if (cptr) return SCPE_ARG;
|
||||
uptr->buf = 003;
|
||||
uptr->pos = uptr->pos + 1;
|
||||
tti_csr = tti_csr | CSR_DONE;
|
||||
if (tti_csr & CSR_IE) SET_INT (TTI);
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Terminal output address routines */
|
||||
|
||||
|
||||
@@ -57,6 +57,7 @@ extern DEVICE tti_dev, tto_dev;
|
||||
extern DEVICE lpt_dev;
|
||||
extern DEVICE clk_dev, pclk_dev;
|
||||
extern DEVICE dz_dev;
|
||||
extern DEVICE vh_dev;
|
||||
extern DEVICE rk_dev, rl_dev;
|
||||
extern DEVICE hk_dev;
|
||||
extern DEVICE rx_dev, ry_dev;
|
||||
@@ -98,6 +99,7 @@ DEVICE *sim_devices[] = {
|
||||
&clk_dev,
|
||||
&pclk_dev,
|
||||
&dz_dev,
|
||||
&vh_dev,
|
||||
&rk_dev,
|
||||
&rl_dev,
|
||||
&hk_dev,
|
||||
|
||||
@@ -25,6 +25,8 @@
|
||||
|
||||
tq TQK50 tape controller
|
||||
|
||||
12-Jun-04 RMS Fixed bug in reporting write protect (reported by Lyle Bickley)
|
||||
18-Apr-04 RMS Fixed TQK70 media ID and model byte (found by Robert Schaffrath)
|
||||
26-Mar-04 RMS Fixed warnings with -std=c99
|
||||
25-Jan-04 RMS Revised for device debug support
|
||||
19-May-03 RMS Revised for new conditional compilation scheme
|
||||
@@ -87,7 +89,7 @@ extern int32 cpu_18b, cpu_ubm;
|
||||
#define pktq u4 /* packet queue */
|
||||
#define uf buf /* settable unit flags */
|
||||
#define objp wait /* object position */
|
||||
#define TQ_WPH(u) (sim_tape_wrp (u))
|
||||
#define TQ_WPH(u) ((sim_tape_wrp (u))? UF_WPH: 0)
|
||||
|
||||
#define CST_S1 0 /* init stage 1 */
|
||||
#define CST_S1_WR 1 /* stage 1 wrap */
|
||||
@@ -144,8 +146,8 @@ struct tqpkt {
|
||||
#define TQ7_TYPE 1 /* TK70 */
|
||||
#define TQ7_UQPM 14 /* UQ port ID */
|
||||
#define TQ7_CMOD 14 /* ctrl ID */
|
||||
#define TQ7_UMOD 11 /* unit ID */
|
||||
#define TQ7_MED 0x6A68B046 /* media ID */
|
||||
#define TQ7_UMOD 14 /* unit ID */
|
||||
#define TQ7_MED 0x6D68B046 /* media ID */
|
||||
#define TQ7_CREV ((1 << 8) | 5) /* ctrl revs */
|
||||
#define TQ7_FREV 0 /* formatter revs */
|
||||
#define TQ7_UREV 0 /* unit revs */
|
||||
|
||||
1367
PDP11/pdp11_vh.c
Normal file
1367
PDP11/pdp11_vh.c
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user