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Notes For V3.2-1

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RESTRICTION: The PDP-15 FPP is only partially debugged.  Do NOT
enable this feature for normal operations.

1. New Features in 3.2-1

1.1 SCP and libraries

- Added SET CONSOLE subhierarchy.
- Added SHOW CONSOLE subhierarchy.
- Added limited keyboard mapping capability.

1.2 HP2100 (new features from Dave Bryan)

- Added instruction printout to HALT message.
- Added M and T internal registers.
- Added N, S, and U breakpoints.

1.3 PDP-11 and VAX

- Added DHQ11 support (from John Dundas)

2. Bugs Fixed in 3.2-1

2.1 HP2100 (most fixes from Dave Bryan)

- SBT increments B after store.
- DMS console map must check dms_enb.
- SFS x,C and SFC x,C work.
- MP violation clears automatically on interrupt.
- SFS/SFC 5 is not gated by protection enabled.
- DMS enable does not disable mem prot checks.
- DMS status inconsistent at simulator halt.
- Examine/deposit are checking wrong addresses.
- Physical addresses are 20b not 15b.
- Revised DMS to use memory rather than internal format.
- Revised IBL facility to conform to microcode.
- Added DMA EDT I/O pseudo-opcode.
- Separated DMA SRQ (service request) from FLG.
- Revised peripherals to make SFS x,C and SFC x,C work.
- Revised boot ROMs to use IBL facility.
- Revised IBL treatment of SR to preserve SR<5:3>.
- Fixed LPS, LPT timing.
- Fixed DP boot interpretation of SR<0>.
- Revised DR boot code to use IBL algorithm.
- Fixed TTY input behavior during typeout for RTE-IV.
- Suppressed nulls on TTY output for RTE-IV.
- Added SFS x,C and SFC x,C to print/parse routines.
- Fixed spurious timing error in magtape reads.

2.2 All DEC console devices

- Removed SET TTI CTRL-C option.

2.3 PDP-11/VAX peripherals

- Fixed bug in TQ reporting write protect status (reported by Lyle Bickley).
- Fixed TK70 model number and media ID (found by Robert Schaffrath).
- Fixed bug in autoconfigure (found by John Dundas).

2.4 VAX

- Fixed bug in DIVBx and DIVWx (reported by Peter Trimmel).
This commit is contained in:
Bob Supnik
2004-07-10 06:13:00 -07:00
committed by Mark Pizzolato
parent 26aa6de663
commit e2ba672610
75 changed files with 14174 additions and 2343 deletions
Download Patch File Download Diff File Expand all files Collapse all files

35
VAX/vax_cpu.c
View File

@@ -25,6 +25,8 @@
cpu CVAX central processor
28-Jun-04 RMS Fixed bug in DIVBx, DIVWx (reported by Peter Trimmel)
18-Apr-04 RMS Added octaword macros
25-Jan-04 RMS Removed local debug logging support
RMS,MP Added extended physical memory support
31-Dec-03 RMS Fixed bug in set_cpu_hist
@@ -155,7 +157,7 @@
#define UNIT_MSIZE (1u << UNIT_V_MSIZE)
#define GET_CUR acc = ACC_MASK (PSL_GETCUR (PSL))
#define OPND_SIZE 10
#define OPND_SIZE 20
#define op0 opnd[0]
#define op1 opnd[1]
#define op2 opnd[2]
@@ -167,6 +169,7 @@
#define op8 opnd[8]
#define CHECK_FOR_PC if (rn == nPC) RSVD_ADDR_FAULT
#define CHECK_FOR_SP if (rn >= nSP) RSVD_ADDR_FAULT
#define CHECK_FOR_AP if (rn >= nAP) RSVD_ADDR_FAULT
#define RECW(l) ((l) << 4) | rn
#define WRITE_B(r) if (spec > (GRN | nPC)) Write (va, r, L_BYTE, WA); \
else R[rn] = (R[rn] & ~BMASK) | ((r) & BMASK)
@@ -174,11 +177,24 @@
else R[rn] = (R[rn] & ~WMASK) | ((r) & WMASK)
#define WRITE_L(r) if (spec > (GRN | nPC)) Write (va, r, L_LONG, WA); \
else R[rn] = (r)
#define WRITE_Q(rl,rh) if (spec > (GRN | nPC)) { \
if (Test (va + 7, WA, &mstat) >= 0) \
Write (va, rl, L_LONG, WA); \
Write (va + 4, rh, L_LONG, WA); } \
else { R[rn] = rl; R[rnplus1] = rh; }
#define WRITE_Q(rl,rh) if (spec > (GRN | nPC)) { \
if (Test (va + 7, WA, &mstat) >= 0) \
Write (va, rl, L_LONG, WA); \
Write (va + 4, rh, L_LONG, WA); } \
else { \
R[rn] = rl; \
R[rnplus1] = rh; }
#define WRITE_O(rl,rm2,rm1,rh) if (spec > (GRN | nPC)) { \
if (Test (va + 15, WA, &mstat) >= 0) \
Write (va, rl, L_LONG, WA); \
Write (va + 4, rm2, L_LONG, WA); \
Write (va + 8, rm1, L_LONG, WA); \
Write (va + 12, rh, L_LONG, WA); } \
else { \
R[rn] = rl; \
R[(rn + 1) & 0xF] = rm2; \
R[(rn + 2) & 0xF] = rm1; \
R[(rn + 3) & 0xF] = rh; }
#define HIST_MIN 128
#define HIST_MAX 65536
@@ -1343,6 +1359,7 @@ case DIVB2: case DIVB3:
else {
r = SXTB (op1) / SXTB (op0); /* ok, divide */
temp = 0; }
r = r & BMASK; /* mask to result */
WRITE_B (r); /* write result */
CC_IIZZ_B (r); /* set cc's */
cc = cc | temp; /* error? set V */
@@ -1359,6 +1376,7 @@ case DIVW2: case DIVW3:
else {
r = SXTW (op1) / SXTW (op0); /* ok, divide */
temp = 0; }
r = r & WMASK; /* mask to result */
WRITE_W (r); /* write result */
CC_IIZZ_W (r); /* set cc's */
cc = cc | temp; /* error? set V */
@@ -1375,6 +1393,7 @@ case DIVL2: case DIVL3:
else {
r = op1 / op0; /* ok, divide */
temp = 0; }
r = r & LMASK; /* mask to result */
WRITE_L (r); /* write result */
CC_IIZZ_L (r); /* set cc's */
cc = cc | temp; /* error? set V */
@@ -1460,7 +1479,7 @@ case ROTL:
case ASHL:
if (op0 & BSIGN) { /* right shift? */
temp = 0x100 - op0; /* get |shift| */
if (temp > 31) r = (op1 & LSIGN)? -1: 0; /* sc > 31? */
if (temp > 31) r = (op1 & LSIGN)? LMASK: 0; /* sc > 31? */
else r = op1 >> temp; /* shift */
WRITE_L (r); /* store result */
CC_IIZZ_L (r); /* set cc's */
@@ -1468,7 +1487,7 @@ case ASHL:
else {
if (op0 > 31) r = temp = 0; /* sc > 31? */
else {
r = ((uint32) op1) << op0; /* shift */
r = (((uint32) op1) << op0) & LMASK; /* shift */
temp = r >> op0; } /* shift back */
WRITE_L (r); /* store result */
CC_IIZZ_L (r); /* set cc's */

9
VAX/vax_cpu1.c
View File

@@ -730,15 +730,6 @@ return 0; /* q can't be empty */
#define MVC_FILL 3 /* must be 3 */
#define MVC_M_STATE 3
#define MVC_V_CC 2
#define STR_V_DPC 24
#define STR_M_DPC 0xFF
#define STR_V_CHR 16
#define STR_M_CHR 0xFF
#define STR_LNMASK 0xFFFF
#define STR_GETDPC(x) (((x) >> STR_V_DPC) & STR_M_DPC)
#define STR_GETCHR(x) (((x) >> STR_V_CHR) & STR_M_CHR)
#define STR_PACK(m,x) ((((PC - fault_PC) & STR_M_DPC) << STR_V_DPC) | \
(((m) & STR_M_CHR) << STR_V_CHR) | ((x) & STR_LNMASK))
/* MOVC3, MOVC5

47
VAX/vax_defs.h
View File

@@ -26,6 +26,7 @@
The author gratefully acknowledges the help of Stephen Shirron, Antonio
Carlini, and Kevin Peterson in providing specifications for the Qbus VAX's
18-Apr-04 RMS Added octa, fp, string definitions
19-May-03 RMS Revised for new conditional compilation scheme
14-Jul-02 RMS Added infinite loop message
30-Apr-02 RMS Added CLR_TRAPS macro
@@ -96,6 +97,32 @@
#define NUM_INST 512 /* one byte+two byte */
#define MAX_SPEC 6 /* max spec/instr */
/* Floating point formats */
#define FD_V_EXP 7 /* f/d exponent */
#define FD_M_EXP 0xFF
#define FD_BIAS 0x80 /* f/d bias */
#define FD_EXP (FD_M_EXP << FD_V_EXP)
#define FD_HB (1 << FD_V_EXP) /* f/d hidden bit */
#define FD_GUARD (15 - FD_V_EXP) /* # guard bits */
#define FD_GETEXP(x) (((x) >> FD_V_EXP) & FD_M_EXP)
#define G_V_EXP 4 /* g exponent */
#define G_M_EXP 0x7FF
#define G_BIAS 0x400 /* g bias */
#define G_EXP (G_M_EXP << G_V_EXP)
#define G_HB (1 << G_V_EXP) /* g hidden bit */
#define G_GUARD (15 - G_V_EXP) /* # guard bits */
#define G_GETEXP(x) (((x) >> G_V_EXP) & G_M_EXP)
#define H_V_EXP 0 /* h exponent */
#define H_M_EXP 0x7FFF
#define H_BIAS 0x4000 /* h bias */
#define H_EXP (H_M_EXP << H_V_EXP)
#define H_HB (1 << H_V_EXP) /* h hidden bit */
#define H_GUARD (15 - H_V_EXP) /* # guard bits */
#define H_GETEXP(x) (((x) >> H_V_EXP) & H_M_EXP)
/* Memory management modes */
#define KERN 0
@@ -458,6 +485,18 @@ enum opcodes {
#define SETPC(d) PC = (d), FLUSH_ISTR
#define FLUSH_ISTR ibcnt = 0, ppc = -1
/* Character string instructions */
#define STR_V_DPC 24 /* delta PC */
#define STR_M_DPC 0xFF
#define STR_V_CHR 16 /* char argument */
#define STR_M_CHR 0xFF
#define STR_LNMASK 0xFFFF /* string length */
#define STR_GETDPC(x) (((x) >> STR_V_DPC) & STR_M_DPC)
#define STR_GETCHR(x) (((x) >> STR_V_CHR) & STR_M_CHR)
#define STR_PACK(m,x) ((((PC - fault_PC) & STR_M_DPC) << STR_V_DPC) | \
(((m) & STR_M_CHR) << STR_V_CHR) | ((x) & STR_LNMASK))
/* Read and write */
#define RA (acc)
@@ -488,6 +527,10 @@ enum opcodes {
if ((rh) & LSIGN) cc = CC_N; \
else if (((rl) | (rh)) == 0) cc = CC_Z; \
else cc = 0
#define CC_IIZZ_O(rl,rm2,rm1,rh) \
if ((rh) & LSIGN) cc = CC_N; \
else if (((rl) | (rm2) | (rm1) | (rh)) == 0) cc = CC_Z; \
else cc = 0
#define CC_IIZZ_FP CC_IIZZ_W
#define CC_IIZP_B(r) \
@@ -506,6 +549,10 @@ enum opcodes {
if ((rh) & LSIGN) cc = CC_N | (cc & CC_C); \
else if (((rl) | (rh)) == 0) cc = CC_Z | (cc & CC_C); \
else cc = cc & CC_C
#define CC_IIZP_O(rl,rm2,rm1,rh) \
if ((rh) & LSIGN) cc = CC_N | (cc & CC_C); \
else if (((rl) | (rm2) | (rm1) | (rh)) == 0) cc = CC_Z | (cc & CC_C); \
else cc = cc & CC_C
#define CC_IIZP_FP CC_IIZP_W
#define V_ADD_B(r,s1,s2) \

251
VAX/vax_doc.txt
View File

@@ -1,7 +1,7 @@
To: Users
From: Bob Supnik
Subj: VAX Simulator Usage
Date: 04-Apr-2004
Date: 15-Jun-2004
COPYRIGHT NOTICE
@@ -82,7 +82,8 @@ sim/pdp11/ pdp11_mscp.h
pdp11_rq.c
pdp11_tq.c
pdp11_ts.c
pdp11_xp.c
pdp11_vh.c
pdp11_xq.c
Additional files are:
@@ -108,6 +109,7 @@ TTI,TTO console terminal
LPT LPV11 line printer
CLK real-time clock
DZ DZV11 4-line terminal multiplexor (up to 4)
VH DHQ11 8-line terminal multiplexor (up to 4)
RL RLV12/RL01(2) cartridge disk controller with four drives
RQ RQDX3 MSCP controller with four drives
RQB second RQDX3 MSCP controller with four drives
@@ -476,12 +478,6 @@ implements these registers:
POS 32 number of characters input
TIME 24 keyboard polling interval
If the simulator is compiled under Windows Visual C++, typing ^C to the
terminal input causes a fatal run-time error. Use the following command
to simulate typing ^C:
SET TTI CTRL-C
2.3.4 Terminal Output (TTO)
The terminal output (TTO) writes to the simulator console window. It
@@ -544,81 +540,6 @@ The clock (CLK) implements these registers:
The real-time clock autocalibrates; the clock interval is adjusted up or
down so that the clock tracks actual elapsed time.
2.3.7 DZV11 Terminal Multiplexor (DZ)
The DZV11 is an 4-line terminal multiplexor. Up to 4 DZ11's (16 lines)
are supported. The number of lines can be changed with the command
SET DZ LINES=n set line count to n
The line count must be a multiple of 4, with a maximum of 16.
The DZV11 supports 8-bit input and output of characters. 8-bit output
may be incompatible with certain operating systems. The command
SET DZ 7B
forces output characters to be masked to 7 bits.
The DZ11 supports logging on a per-line basis. The command
SET DZ LOG=line=filename
enables logging for the specified line to the indicated file. The
command
SET DZ NOLOG=line
disables logging for the specified line and closes any open log file.
Finally, the command
SHOW DZ LOG
displays logging information for all DZ lines.
The terminal lines perform input and output through Telnet sessions
connected to a user-specified port. The ATTACH command specifies
the port to be used:
ATTACH {-am} DZ <port> set up listening port
where port is a decimal number between 1 and 65535 that is not being used
for other TCP/IP activities. The optional switch -m turns on the DZV11's
modem controls; the optional switch -a turns on active disconnects
(disconnect session if computer clears Data Terminal Ready). Without
modem control, the DZ behaves as though terminals were directly connected;
disconnecting the Telnet session does not cause any operating system-
visible change in line status.
Once the DZ is attached and the simulator is running, the DZ will listen
for connections on the specified port. It assumes that the incoming
connections are Telnet connections. The connection remains open until
disconnected by the simulated program, the Telnet client, a SET DZ
DISCONNECT command, or a DETACH DZ command.
The SHOW DZ CONNECTIONS command displays the current connections to the DZ.
The SHOW DZ STATISTICS command displays statistics for active connections.
The SET DZ DISCONNECT=linenumber disconnects the specified line.
The DZV11 implements these registers:
name size comments
CSR[0:3] 16 control/status register, boards 0-3
RBUF[0:3] 16 receive buffer, boards 0-3
LPR[0:3] 16 line parameter register, boards 0-3
TCR[0:3] 16 transmission control register, boards 0-3
MSR[0:3] 16 modem status register, boards 0-3
TDR[0:3] 16 transmit data register, boards 0-3
SAENB[0:3] 1 silo alarm enabled, boards 0-3
RXINT 4 receive interrupts, boards 3..0
TXINT 4 transmit interrupts, boards 3..0
MDMTCL 1 modem control enabled
AUTODS 1 autodisconnect enabled
The DZV11 does not support save and restore. All open connections are
lost when the simulator shuts down or the DZ is detached.
2.4 RLV12/RL01,RL02 Cartridge Disk (RL)
RLV12 options include the ability to set units write enabled or write locked,
@@ -685,13 +606,12 @@ of many disk types:
SET RQn RA72 set type to RA72
SET RQn RA90 set type to RA90
SET RQn RA92 set type to RA92
SET RQn RAUSER{=n} set type to RA81 with n LBN's
SET RQn RAUSER{=n} set type to RA81 with n MB's
The type options can be used only when a unit is not attached to a file.
RAUSER is a "user specified" disk; the user can specify the size of the
disk in logical block numbers (LBN's, 512 bytes each). The minimum size
is 50MB. The maximum size is 2GB if the simulator is compiled without
64b addressing, 1000GB with 64b addressing.
disk in megabytes. The minimum size is 50MB. The maximum size is 2GB if
the simulator is compiled without 64b addressing, 1000GB with 64b addressing.
Units can also be set ONLINE or OFFLINE.
@@ -912,6 +832,163 @@ Error handling is as follows:
OS I/O error report error and stop
2.8 Communications Devices
2.8.1 DZV11 Terminal Multiplexor (DZ)
The DZV11 is an 4-line terminal multiplexor. Up to 4 DZ11's (16 lines)
are supported. The number of lines can be changed with the command
SET DZ LINES=n set line count to n
The line count must be a multiple of 4, with a maximum of 16.
The DZV11 supports 8-bit input and output of characters. 8-bit output
may be incompatible with certain operating systems. The command
SET DZ 7B
forces output characters to be masked to 7 bits.
The DZ11 supports logging on a per-line basis. The command
SET DZ LOG=line=filename
enables logging for the specified line to the indicated file. The
command
SET DZ NOLOG=line
disables logging for the specified line and closes any open log file.
Finally, the command
SHOW DZ LOG
displays logging information for all DZ lines.
The terminal lines perform input and output through Telnet sessions
connected to a user-specified port. The ATTACH command specifies
the port to be used:
ATTACH {-am} DZ <port> set up listening port
where port is a decimal number between 1 and 65535 that is not being used
for other TCP/IP activities. The optional switch -m turns on the DZV11's
modem controls; the optional switch -a turns on active disconnects
(disconnect session if computer clears Data Terminal Ready). Without
modem control, the DZ behaves as though terminals were directly connected;
disconnecting the Telnet session does not cause any operating system-
visible change in line status.
Once the DZ is attached and the simulator is running, the DZ will listen
for connections on the specified port. It assumes that the incoming
connections are Telnet connections. The connection remains open until
disconnected by the simulated program, the Telnet client, a SET DZ
DISCONNECT command, or a DETACH DZ command.
The SHOW DZ CONNECTIONS command displays the current connections to the DZ.
The SHOW DZ STATISTICS command displays statistics for active connections.
The SET DZ DISCONNECT=linenumber disconnects the specified line.
The DZV11 implements these registers:
name size comments
CSR[0:3] 16 control/status register, boards 0-3
RBUF[0:3] 16 receive buffer, boards 0-3
LPR[0:3] 16 line parameter register, boards 0-3
TCR[0:3] 16 transmission control register, boards 0-3
MSR[0:3] 16 modem status register, boards 0-3
TDR[0:3] 16 transmit data register, boards 0-3
SAENB[0:3] 1 silo alarm enabled, boards 0-3
RXINT 4 receive interrupts, boards 3..0
TXINT 4 transmit interrupts, boards 3..0
MDMTCL 1 modem control enabled
AUTODS 1 autodisconnect enabled
The DZV11 does not support save and restore. All open connections are
lost when the simulator shuts down or the DZ is detached.
2.8.2 DHQ11 Terminal Multiplexor (VH)
The DHQ11 is an 8-line terminal multiplexor for Qbus systems. Up
to 4 DHQ11's are supported.
The DHQ11 is a programmable asynchronous terminal multiplexor. It
has two programming modes: DHV11 and DHU11. The register sets are
compatible with these devices. For transmission, the DHQ11 can be
used in either DMA or programmed I/O mode. For reception, there
is a 256-entry FIFO for received characters, dataset status changes,
and diagnostic information, and a programmable input interrupt
timer (in DHU mode). The device supports 16-, 18-, and 22-bit
addressing. The DHQ11 can be programmed to filter and/or handle
XON/XOFF characters independently of the processor. The DHQ11
supports programmable bit width (between 5 and 8) for the input
and output of characters.
The DHQ11 has a rocker switch for determining the programming mode.
By default, the DHV11 mode is selected, though DHU11 mode is
recommended for applications that can support it. The VH controller
may be adjusted on a per controller basis as follows:
SET VHn DHU use the DHU programming mode and registers
SET VHn DHV use the DHV programming mode and registers
DMA output is supported. In a real DHQ11, DMA is not initiated
immediately upon receipt of TX.DMA.START but is dependent upon some
internal processes. The VH controller mimics this behavior by default.
It may be desirable to alter this and start immediately, though
this may not be compatible with all operating systems and diagnostics.
You can change the behavior of the VH controller as follows:
SET VHn NORMAL use normal DMA procedures
SET VHn FASTDMA set DMA to initiate immediately
The terminal lines perform input and output through Telnet sessions
connected to a user-specified port. The ATTACH command specifies
the port to be used:
ATTACH VH <port> set up listening port
DETACH VH
where port is a decimal number between 1 and 65535 that is not
being used for other TCP/IP activities. This port is the point of
entry for al lines on all VH controllers.
Modem and auto-disconnect support may be set on an individual
controller basis. The SET MODEM command directs the controller to
report modem status changes to the computer. The SET HANGUP command
turns on active disconnects (disconnect session if computer clears
Data Terminal Ready).
SET VHn [NO]MODEM disable/enable modem control
SET VHn [NO]HANGUP disable/enable disconnect on DTR drop
Once the VH is attached and the simulator is running, the VH will
listen for connections on the specified port. It assumes that the
incoming connections are Telnet connections. The connection remains
open until disconnected by the simulated program, the Telnet client,
a SET VH DISCONNECT command, or a DETACH VH command.
The SHOW VH CONNECTIONS command displays the current connections to the VH.
The SHOW VH STATISTICS command displays statistics for active connections.
The SET VH DISCONNECT=linenumber disconnects the specified line.
The DHQ11 implements these registers, though not all can be examined
from SCP:
name size comments
CSR[0:3] 16 control/status register, boards 0..3
RBUF[0:3] 16 receive buffer, boards 0..3
LPR[0:3] 16 line parameter register, boards 0..3
RXINT 4 receive interrupts, boards 3..0
TXINT 4 transmit interrupts, boards 3..0
[more to be described...]
The DHQ11 does not support save and restore. All open connections
are lost when the simulator shuts down or the VH is detached.
2.9 DELQA/DEQNA Qbus Ethernet Controllers (XQ, XQB)
The simulator implements two DELQA/DEQNA Qbus Ethernet controllers (XQ,

17
VAX/vax_fpa.c
View File

@@ -23,6 +23,7 @@
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
18-Apr-04 RMS Moved format definitions to vax_defs.h
19-Jun-03 RMS Simplified add algorithm
16-May-03 RMS Fixed bug in floating to integer convert overflow
Fixed multiple bugs in EMODx
@@ -43,22 +44,6 @@
#define M32 0xFFFFFFFF /* 32b */
#define M16 0x0000FFFF
#define FD_V_EXP 7 /* f/d exponent */
#define FD_M_EXP 0xFF
#define FD_BIAS 0x80 /* f/d bias */
#define FD_EXP (FD_M_EXP << FD_V_EXP)
#define FD_HB (1 << FD_V_EXP) /* f/d hidden bit */
#define FD_GUARD (15 - FD_V_EXP) /* # guard bits */
#define FD_GETEXP(x) (((x) >> FD_V_EXP) & FD_M_EXP)
#define G_V_EXP 4 /* g exponent */
#define G_M_EXP 0x7FF
#define G_BIAS 0x400 /* g bias */
#define G_EXP (G_M_EXP << G_V_EXP)
#define G_HB (1 << G_V_EXP) /* g hidden bit */
#define G_GUARD (15 - G_V_EXP) /* # guard bits */
#define G_GETEXP(x) (((x) >> G_V_EXP) & G_M_EXP)
extern int32 R[16];
extern int32 PSL;
extern int32 p1;

182
VAX/vax_io.c
View File

@@ -25,6 +25,7 @@
qba Qbus adapter
28-May-04 RMS Revised I/O dispatching (from John Dundas)
21-Mar-04 RMS Added RXV21 support
21-Dec-03 RMS Fixed bug in autoconfigure vector assignment; added controls
21-Nov-03 RMS Added check for interrupt slot conflict (found by Dave Hittner)
@@ -154,9 +155,11 @@ DEVICE qba_dev = {
NULL, NULL, NULL,
&qba_dib, DEV_QBUS };
/* IO page addresses */
/* IO page dispatches */
DIB *dib_tab[DIB_MAX]; /* DIB table */
static t_stat (*iodispR[IOPAGESIZE >> 1])(int32 *dat, int32 ad, int32 md);
static t_stat (*iodispW[IOPAGESIZE >> 1])(int32 dat, int32 ad, int32 md);
static DIB *iodibp[IOPAGESIZE >> 1];
/* Interrupt request to interrupt action map */
@@ -174,14 +177,12 @@ int32 int_vec[IPL_HLVL][32]; /* int req to vector */
int32 ReadQb (uint32 pa)
{
int32 i, val;
DIB *dibp;
int32 idx, val;
for (i = 0; dibp = dib_tab[i]; i++ ) {
if ((pa >= dibp->ba) &&
(pa < (dibp->ba + dibp->lnt))) {
dibp->rd (&val, pa, READ);
return val; } }
idx = (pa & IOPAGEMASK) >> 1;
if (iodispR[idx]) {
iodispR[idx] (&val, pa, READ);
return val; }
cq_merr (pa);
MACH_CHECK (MCHK_READ);
return 0;
@@ -189,14 +190,12 @@ return 0;
void WriteQb (uint32 pa, int32 val, int32 mode)
{
int32 i;
DIB *dibp;
int32 idx;
for (i = 0; dibp = dib_tab[i]; i++ ) {
if ((pa >= dibp->ba) &&
(pa < (dibp->ba + dibp->lnt))) {
dibp->wr (val, pa, mode);
return; } }
idx = (pa & IOPAGEMASK) >> 1;
if (iodispW[idx]) {
iodispW[idx] (val, pa, mode);
return; }
cq_merr (pa);
mem_err = 1;
return;
@@ -781,114 +780,117 @@ else { fprintf (st, "vector=%X", vec);
return SCPE_OK;
}
/* Test for conflict in device addresses */
/* Build dispatch tables */
t_bool dev_conflict (DIB *curr)
t_stat build_dsp_tab (DEVICE *dptr, DIB *dibp)
{
uint32 i, end;
DEVICE *dptr;
DIB *dibp;
uint32 i, idx;
end = curr->ba + curr->lnt - 1; /* get end */
for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */
dibp = (DIB *) dptr->ctxt; /* get DIB */
if ((dibp == NULL) || (dibp == curr) ||
(dptr->flags & DEV_DIS)) continue;
if (((curr->ba >= dibp->ba) && /* overlap start? */
(curr->ba < (dibp->ba + dibp->lnt))) ||
((end >= dibp->ba) && /* overlap end? */
(end < (dibp->ba + dibp->lnt)))) {
printf ("Device %s address conflict at %08X\n",
sim_dname (dptr), dibp->ba);
if (sim_log) fprintf (sim_log,
"Device %s address conflict at %08X\n",
sim_dname (dptr), dibp->ba);
return TRUE; } }
return FALSE;
if ((dptr == NULL) || (dibp == NULL)) return SCPE_IERR; /* validate args */
for (i = 0; i < dibp->lnt; i = i + 2) { /* create entries */
idx = ((dibp->ba + i) & IOPAGEMASK) >> 1; /* index into disp */
if ((iodispR[idx] && dibp->rd && /* conflict? */
(iodispR[idx] != dibp->rd)) ||
(iodispW[idx] && dibp->wr &&
(iodispW[idx] != dibp->wr))) {
printf ("Device %s address conflict at %08o\n",
sim_dname (dptr), dibp->ba);
if (sim_log) fprintf (sim_log,
"Device %s address conflict at %08o\n",
sim_dname (dptr), dibp->ba);
return SCPE_STOP;
}
if (dibp->rd) iodispR[idx] = dibp->rd; /* set rd dispatch */
if (dibp->wr) iodispW[idx] = dibp->wr; /* set wr dispatch */
iodibp[idx] = dibp; /* remember DIB */
}
return SCPE_OK;
}
/* Build interrupt tables */
t_bool build_int_vec (int32 vloc, int32 ivec, int32 (*iack)(void) )
t_stat build_int_vec (DEVICE *dptr, DIB *dibp)
{
int32 ilvl = vloc / 32;
int32 ibit = vloc % 32;
int32 i, idx, vec, ilvl, ibit;
if (iack != NULL) {
if (int_ack[ilvl][ibit] &&
(int_ack[ilvl][ibit] != iack)) return TRUE;
int_ack[ilvl][ibit] = iack; }
else if (ivec != 0) {
if (int_vec[ilvl][ibit] &&
(int_vec[ilvl][ibit] != ivec)) return TRUE;
int_vec[ilvl][ibit] = ivec; }
return FALSE;
if ((dptr == NULL) || (dibp == NULL)) return SCPE_IERR; /* validate args */
if (dibp->vnum > VEC_DEVMAX) return SCPE_IERR;
for (i = 0; i < dibp->vnum; i++) { /* loop thru vec */
idx = dibp->vloc + i; /* vector index */
vec = dibp->vec? (dibp->vec + (i * 4)): 0; /* vector addr */
ilvl = idx / 32;
ibit = idx % 32;
if ((int_ack[ilvl][ibit] && dibp->ack[i] && /* conflict? */
(int_ack[ilvl][ibit] != dibp->ack[i])) ||
(int_vec[ilvl][ibit] && vec &&
(int_vec[ilvl][ibit] != vec))) {
printf ("Device %s interrupt slot conflict at %d\n",
sim_dname (dptr), idx);
if (sim_log) fprintf (sim_log,
"Device %s interrupt slot conflict at %d\n",
sim_dname (dptr), idx);
return SCPE_STOP;
}
if (dibp->ack[i]) int_ack[ilvl][ibit] = dibp->ack[i];
else if (vec) int_vec[ilvl][ibit] = vec;
}
return SCPE_OK;
}
/* Build dib_tab from device list */
t_stat build_dib_tab (void)
{
int32 i, j, k;
int32 i, j;
DEVICE *dptr;
DIB *dibp;
t_stat r;
for (i = 0; i < IPL_HLVL; i++) { /* clear int tables */
for (j = 0; j < 32; j++) {
int_vec[i][j] = 0;
int_ack[i][j] = NULL; } }
for (i = j = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */
for (i = 0; i < (IOPAGESIZE >> 1); i++) { /* clear dispatch tab */
iodispR[i] = NULL;
iodispW[i] = NULL;
iodibp[i] = NULL; }
for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */
dibp = (DIB *) dptr->ctxt; /* get DIB */
if (dibp && !(dptr->flags & DEV_DIS)) { /* defined, enabled? */
if (dibp->vnum > VEC_DEVMAX) return SCPE_IERR;
for (k = 0; k < dibp->vnum; k++) { /* loop thru vec */
if (build_int_vec (dibp->vloc + k, /* add vector */
dibp->vec + (k * 4), dibp->ack[k])) {
printf ("Device %s interrupt slot conflict at %d\n",
sim_dname (dptr), dibp->vloc + k);
if (sim_log) fprintf (sim_log,
"Device %s interrupt slot conflict at %d\n",
sim_dname (dptr), dibp->vloc + k);
return SCPE_IERR; } }
if (dibp->lnt != 0) { /* I/O addresses? */
dib_tab[j++] = dibp; /* add DIB to dib_tab */
if (j >= DIB_MAX) return SCPE_IERR; } /* too many? */
if (r = build_int_vec (dptr, dibp)) /* add to intr tab */
return r;
if (r = build_dsp_tab (dptr, dibp)) /* add to dispatch tab */
return r;
} /* end if enabled */
} /* end for */
dib_tab[j] = NULL; /* end with NULL */
for (i = 0; (dibp = dib_tab[i]) != NULL; i++) { /* test built dib_tab */
if (dev_conflict (dibp)) return SCPE_STOP; } /* for conflicts */
return FALSE;
return SCPE_OK;
}
/* Show dib_tab */
/* Show IO space */
t_stat show_iospace (FILE *st, UNIT *uptr, int32 val, void *desc)
{
int32 i, j, done = 0;
uint32 i, j;
DEVICE *dptr;
DIB *dibt;
DIB *dibp;
build_dib_tab (); /* build table */
while (done == 0) { /* sort ascending */
done = 1; /* assume done */
for (i = 0; dib_tab[i + 1] != NULL; i++) { /* check table */
if (dib_tab[i]->ba > dib_tab[i + 1]->ba) { /* out of order? */
dibt = dib_tab[i]; /* interchange */
dib_tab[i] = dib_tab[i + 1];
dib_tab[i + 1] = dibt;
done = 0; } } /* not done */
} /* end while */
for (i = 0; dib_tab[i] != NULL; i++) { /* print table */
for (j = 0, dptr = NULL; sim_devices[j] != NULL; j++) {
if (((DIB*) sim_devices[j]->ctxt) == dib_tab[i]) {
dptr = sim_devices[j];
break; } }
fprintf (st, "%08X - %08X%c\t%s\n", dib_tab[i]->ba,
dib_tab[i]->ba + dib_tab[i]->lnt - 1,
if (build_dib_tab ()) return SCPE_OK; /* build IO page */
for (i = 0, dibp = NULL; i < (IOPAGESIZE >> 1); i++) { /* loop thru entries */
if (iodibp[i] && (iodibp[i] != dibp)) { /* new block? */
dibp = iodibp[i]; /* DIB for block */
for (j = 0, dptr = NULL; sim_devices[j] != NULL; j++) {
if (((DIB*) sim_devices[j]->ctxt) == dibp) {
dptr = sim_devices[j]; /* locate device */
break;
} /* end if */
} /* end for j */
fprintf (st, "%08X - %08X%c\t%s\n", dibp->ba,
dibp->ba + dibp->lnt - 1,
(dptr && (dptr->flags & DEV_FLTA))? '*': ' ',
dptr? sim_dname (dptr): "CPU");
}
} /* end if */
} /* end for i */
return SCPE_OK;
}
@@ -943,7 +945,7 @@ struct auto_con auto_tab[AUTO_LNT + 1] = {
{ 0xf, 0x3 }, /* VS100 */
{ 0x3, 0x3, AUTO_DYN|AUTO_VEC, 0, IOBA_TQ, { "TQ", "TQB" } },
{ 0xf, 0x7 }, /* KMV11 */
{ 0xf, 0x7 }, /* DHU11/DHQ11 */
{ 0x1f, 0x7, AUTO_VEC, VH_MUXES, 0, { "VH" } }, /* DHU11/DHQ11 */
{ 0x1f, 0x7 }, /* DMZ32 */
{ 0x1f, 0x7 }, /* CP132 */

6
VAX/vax_mmu.c
View File

@@ -194,7 +194,7 @@ if (lnt >= L_LONG) { /* lw unaligned? */
sc = bo << 3;
wl = ReadL (pa); /* read both lw */
wh = ReadL (pa1); /* extract */
return (((wl >> sc) & align[bo]) | (wh << (32 - sc))); }
return ((((wl >> sc) & align[bo]) | (wh << (32 - sc))) & LMASK); }
else if (bo == 1) return ((ReadL (pa) >> 8) & WMASK);
else { wl = ReadL (pa); /* word cross lw */
wh = ReadL (pa1); /* read, extract */
@@ -248,7 +248,7 @@ wl = ReadL (pa);
if (lnt >= L_LONG) {
sc = bo << 3;
wh = ReadL (pa1);
wl = (wl & insert[bo]) | (val << sc);
wl = (wl & insert[bo]) | ((val << sc) & LMASK);
wh = (wh & ~insert[bo]) | ((val >> (32 - sc)) & insert[bo]);
WriteL (pa, wl);
WriteL (pa1, wh); }
@@ -256,7 +256,7 @@ else if (bo == 1) {
wl = (wl & 0xFF0000FF) | (val << 8);
WriteL (pa, wl); }
else { wh = ReadL (pa1);
wl = (wl & 0x00FFFFFF) | (val << 24);
wl = (wl & 0x00FFFFFF) | ((val & 0xFF) << 24);
wh = (wh & 0xFFFFFF00) | ((val >> 8) & 0xFF);
WriteL (pa, wl);
WriteL (pa1, wh); }

16
VAX/vax_stddev.c
View File

@@ -27,6 +27,7 @@
tto terminal output
clk 100Hz and TODR clock
28-May-04 RMS Removed SET TTI CTRL-C
29-Dec-03 RMS Added console backpressure support
25-Apr-03 RMS Revised for extended file support
02-Mar-02 RMS Added SET TTI CTRL-C
@@ -74,7 +75,6 @@ t_stat clk_svc (UNIT *uptr);
t_stat tti_reset (DEVICE *dptr);
t_stat tto_reset (DEVICE *dptr);
t_stat clk_reset (DEVICE *dptr);
t_stat tti_set_ctrlc (UNIT *uptr, int32 val, char *cptr, void *desc);
extern int32 sysd_hlt_enb (void);
@@ -102,8 +102,6 @@ REG tti_reg[] = {
MTAB tti_mod[] = {
{ UNIT_8B, UNIT_8B, "8b", "8B", NULL },
{ UNIT_8B, 0 , "7b", "7B", NULL },
{ MTAB_XTD|MTAB_VDV|MTAB_VUN, 0, NULL, "CTRL-C",
&tti_set_ctrlc, NULL, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
NULL, &show_vec, NULL },
{ 0 } };
@@ -292,18 +290,6 @@ CLR_INT (TTI);
sim_activate (&tti_unit, tti_unit.wait); /* activate unit */
return SCPE_OK;
}
/* Set control-C */
t_stat tti_set_ctrlc (UNIT *uptr, int32 val, char *cptr, void *desc)
{
if (cptr) return SCPE_ARG;
uptr->buf = 003;
uptr->pos = uptr->pos + 1;
tti_csr = tti_csr | CSR_DONE;
if (tti_csr & CSR_IE) SET_INT (TTI);
return SCPE_OK;
}
/* Terminal output routines

3
VAX/vax_sys.c
View File

@@ -23,6 +23,7 @@
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
16-Jun-04 RMS Added DHQ11 support
21-Mar-04 RMS Added RXV21 support
06-May-03 RMS Added support for second DELQA
12-Oct-02 RMS Added multiple RQ controller support
@@ -52,6 +53,7 @@ extern DEVICE ry_dev;
extern DEVICE ts_dev;
extern DEVICE tq_dev;
extern DEVICE dz_dev;
extern DEVICE vh_dev;
extern DEVICE xq_dev, xqb_dev;
extern UNIT cpu_unit;
extern REG cpu_reg[];
@@ -104,6 +106,7 @@ DEVICE *sim_devices[] = {
&ptp_dev,
&lpt_dev,
&dz_dev,
&vh_dev,
&rl_dev,
&rq_dev,
&rqb_dev,

21
VAX/vaxmod_defs.h
View File

@@ -23,6 +23,7 @@
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
16-Jun-04 RMS Added DHQ11 support
21-Mar-04 RMS Added RXV21 support
25-Jan-04 RMS Removed local debug logging support
RMS,MP Added "KA655X" support
@@ -204,8 +205,9 @@
/* I/O system definitions */
#define DZ_MUXES 4 /* max # of muxes */
#define DZ_LINES 4 /* (DZV) lines per mux */
#define DZ_MUXES 4 /* max # of DZV muxes */
#define DZ_LINES 4 /* lines per DZV mux */
#define VH_MUXES 4 /* max # of DHQ muxes */
#define MT_MAXFR (1 << 16) /* magtape max rec */
#define AUTO_LNT 34 /* autoconfig ranks */
#define DIB_MAX 100 /* max DIBs */
@@ -250,6 +252,8 @@ typedef struct pdp_dib DIB;
#define IOLN_RQC 004
#define IOBA_RQD (IOPAGEBASE + IOBA_RQC + IOLN_RQC)
#define IOLN_RQD 004
#define IOBA_VH (IOPAGEBASE + 000440) /* DHQ11 */
#define IOLN_VH 020
#define IOBA_RQ (IOPAGEBASE + 012150) /* RQDX3 */
#define IOLN_RQ 004
#define IOBA_TS (IOPAGEBASE + 012520) /* TS11 */
@@ -297,6 +301,7 @@ typedef struct pdp_dib DIB;
#define INT_V_TS 5 /* TS11/TSV05 */
#define INT_V_TQ 6 /* TMSCP */
#define INT_V_XQ 7 /* DEQNA/DELQA */
#define INT_V_RY 8 /* RXV21 */
/* IPL 14 */
@@ -309,7 +314,8 @@ typedef struct pdp_dib DIB;
#define INT_V_CSO 6
#define INT_V_TMR0 7 /* SSC timers */
#define INT_V_TMR1 8
#define INT_V_RY 9 /* RXV21 */
#define INT_V_VHRX 9 /* DHQ11 */
#define INT_V_VHTX 10
#define INT_CLK (1u << INT_V_CLK)
#define INT_RQ (1u << INT_V_RQ)
@@ -320,6 +326,7 @@ typedef struct pdp_dib DIB;
#define INT_TS (1u << INT_V_TS)
#define INT_TQ (1u << INT_V_TQ)
#define INT_XQ (1u << INT_V_XQ)
#define INT_RY (1u << INT_V_RY)
#define INT_TTI (1u << INT_V_TTI)
#define INT_TTO (1u << INT_V_TTO)
#define INT_PTR (1u << INT_V_PTR)
@@ -329,7 +336,8 @@ typedef struct pdp_dib DIB;
#define INT_CSO (1u << INT_V_CSO)
#define INT_TMR0 (1u << INT_V_TMR0)
#define INT_TMR1 (1u << INT_V_TMR1)
#define INT_RY (1u << INT_V_RY)
#define INT_VHRX (1u << INT_V_VHRX)
#define INT_VHTX (1u << INT_V_VHTX)
#define IPL_CLK (0x16 - IPL_HMIN) /* relative IPL */
#define IPL_RQ (0x15 - IPL_HMIN)
@@ -350,6 +358,8 @@ typedef struct pdp_dib DIB;
#define IPL_CSO (0x14 - IPL_HMIN)
#define IPL_TMR0 (0x14 - IPL_HMIN)
#define IPL_TMR1 (0x14 - IPL_HMIN)
#define IPL_VHRX (0x14 - IPL_HMIN)
#define IPL_VHTX (0x14 - IPL_HMIN)
#define IPL_HMAX 0x17 /* highest hwre level */
#define IPL_HMIN 0x14 /* lowest hwre level */
@@ -371,6 +381,8 @@ typedef struct pdp_dib DIB;
#define VEC_RY (VEC_Q + 0264)
#define VEC_DZRX (VEC_Q + 0300)
#define VEC_DZTX (VEC_Q + 0304)
#define VEC_VHRX (VEC_Q + 0310)
#define VEC_VHTX (VEC_Q + 0314)
/* Autoconfigure ranks */
@@ -379,6 +391,7 @@ typedef struct pdp_dib DIB;
#define RANK_RX 18
#define RANK_RQ 26
#define RANK_TQ 30
#define RANK_VH 32
/* Interrupt macros */