From e4f8313262bb6c0780a7af0f51f2d94e0e256cdc Mon Sep 17 00:00:00 2001 From: Bob Supnik Date: Mon, 15 Apr 2019 21:37:15 -0700 Subject: [PATCH] VAX: Add C & V condition code support for MTPR and MFPR opcodes As originally specified, both MTPR and MFPR set N,Z based on the transmitted/received longword data, cleared V, and left C untouched. The simulator hardwired this (except for the standardized TBCHK register) based on the CVAX microcode. In the 8200, accessing the RXCD register sets V for character sent/received. (The VAX vector MxPRs also return non-standard values for the condition codes.) This is one of the reasons that, in 1986, the VAX architecture spec was changed to make the condition codes UNPREDICTABLE following MTPR or MFPR. Accordingly, I've added a "hook" to support the 8200 and other non-standard MxPRs: global variable mxpr_cc_vc. At the start of MTPR or MFPR (only), this variable is set to 000. MTPR will set N and Z based on the transmitted operand and clear V and C. MFPR will set N and Z based on the received data and clear V and C. Then, at the end, mxpr_cc_vc, masked down to V & C, is ORed into the condition codes. Thus, if an IPR write or read does nothing special, MTPR and MFPR will get the canonical results. N,Z set, V cleared, C preserved. However, an IPR routine can now specify a non-standard value for V and/or C by modifying mxpr_cc_vc. This tweak required changes only in vax_cpu.c. None of the model- specific IPR routines need to be changed, except for Matt's 8200 RXCD code. Anyone attempting implementation of further models (or VAX vectors) should be aware of this new capability. --- VAX/vax_cpu.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/VAX/vax_cpu.c b/VAX/vax_cpu.c index 62d051a1..bbacdbb2 100644 --- a/VAX/vax_cpu.c +++ b/VAX/vax_cpu.c @@ -1,6 +1,6 @@ /* vax_cpu.c: VAX CPU - Copyright (c) 1998-2017, Robert M Supnik + Copyright (c) 1998-2019, Robert M Supnik Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,7 @@ cpu VAX central processor + 14-Apr-19 RMS Added hook for non-standard MxPR CC's 31-Mar-17 RMS Fixed uninitialized variable on FPD path (COVERITY) 13-Mar-17 RMS Fixed dangling else in show_opnd (COVERITY) 29-Dec-16 RMS Removed delay in invoking sim_idle (Mark Pizzolato) @@ -271,6 +272,7 @@ int32 mem_err = 0; int32 crd_err = 0; int32 p1 = 0, p2 = 0; /* fault parameters */ int32 fault_PC; /* fault PC */ +int32 mxpr_cc_vc = 0; /* MxPR V,C bits */ int32 pcq_p = 0; /* PC queue ptr */ int32 hst_p = 0; /* history pointer */ int32 hst_lnt = 0; /* history length */ @@ -3003,14 +3005,18 @@ for ( ;; ) { break; case MTPR: - cc = (cc & CC_C) | op_mtpr (opnd); + mxpr_cc_vc = cc & CC_C; /* std: V=0, C unchgd */ + cc = op_mtpr (opnd); + cc = cc | (mxpr_cc_vc & (CC_V|CC_C)); /* or in V,C */ SET_IRQL; /* update intreq */ break; case MFPR: + mxpr_cc_vc = cc & CC_C; /* std: V=0, C unchgd */ r = op_mfpr (opnd); WRITE_L (r); - CC_IIZP_L (r); + CC_IIZZ_L (r); /* set NV, clr VC */ + cc = cc | (mxpr_cc_vc & (CC_V|CC_C)); /* or in V,C */ break; /* CIS or emulated instructions */