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Notes For V3.0-1
RESTRICTION: The FP15 and XVM features of the PDP-15 are only partially debugged. Do NOT enable these features for normal operations. 1. New Features in 3.0-1 1.1 PDP-1 - Added block loader format support to LOAD. - Changed BOOT PTR to allow loading of all of the first bank of memory. 1.2 PDP-18b Family - Added PDP-4 EAE support. - Added PDP-15 FP15 support. - Added PDP-15 XVM support. - Added PDP-15 "re-entrancy ECO". - Added PDP-7, PDP-9, PDP-15 hardware RIM loader support in BOOT PTR. 2. Bugs Fixed in 3.0-1 2.1 PDP-11/VAX - Fixed bug in user disk size (found by Chaskiel M Grundman). 2.2 PDP-1 - Updated CPU, line printer, standard devices to detect indefinite I/O wait. - Fixed incorrect logical, missing activate, break in drum simulator. - Fixed bugs in instruction decoding, overprinting for line printer. 2.3 PDP-10 - Fixed bug in RP read header. 2.4 PDP-18b Family - Fixed bug in PDP-4 line printer overprinting. - Fixed bug in PDP-15 memory protect/skip interaction. - Fixed bug in RF set size routine. - Increased PTP TIME for PDP-15 operating systems. 2.5 PDP-8 - Fixed bug in DF, RF set size routine. 2.6 Nova - Fixed bug in DSK set size routine. 2.7 1401 - Revised fetch to model hardware more closely. 2.8 Ibm1130 - Fixed bugs found by APL 1130. 2.9 Altairz80 - Fixed bug in real-time clock on Windows host. 2.10 HP2100 -- Fixed DR drum sizes. -- Fixed DR variable capacity interaction with SAVE/RESTORE. 3. New Features in 3.0 vs prior releases 3.1 SCP and Libraries - Added ASSIGN/DEASSIGN (logical name) commands. - Changed RESTORE to unconditionally detach files. - Added E11 and TPC format support to magtape library. - Fixed bug in SHOW CONNECTIONS. - Added USE_ADDR64 support 3.2 All magtapes - Magtapes support SIMH format, E11 format, and TPC format (read only). - SET <tape_unit> FORMAT=format sets the specified tape unit's format. - SHOW <tape_unit> FORMAT displays the specified tape unit's format. - Tape format can also be set as part of the ATTACH command, using the -F switch. 3.3 VAX - VAX can be compiled without USE_INT64. - If compiled with USE_INT64 and USE_ADDR64, RQ and TQ controllers support files > 2GB. - VAX ROM has speed control (SET ROM DELAY/NODELAY). 4. Bugs Fixed in 3.0 vs prior releases 4.1 VAX - Fixed CVTfi bug: integer overflow not set if exponent out of range - Fixed EMODx bugs: o First and second operands reversed o Separated fraction received wrong exponent o Overflow calculation on separated integer incorrect o Fraction not set to zero if exponent out of range - Fixed interval timer and ROM access to pass power-up self-test even on very fast host processors (fixes from Mark Pizzolato). 4.2 1401 - Fixed mnemonic, instruction lengths, and reverse scan length check bug for MCS. - Fixed MCE bug, BS off by 1 if zero suppress. - Fixed chaining bug, D lost if return to SCP. - Fixed H branch, branch occurs after continue. - Added check for invalid 8 character MCW, LCA. - Fixed magtape load-mode end of record response. 4.3 Nova - Fixed DSK variable size interaction with restore. 4.4 PDP-1 - Fixed DT variable size interaction with restore. 4.5 PDP-11 - Fixed DT variable size interaction with restore. - Fixed bug in MMR1 update (found by Tim Stark). - Added XQ features and fixed bugs: o Corrected XQ interrupts on IE state transition (code by Tom Evans). o Added XQ interrupt clear on soft reset. o Removed XQ interrupt when setting XL or RL (multiple people). o Added SET/SHOW XQ STATS. o Added SHOW XQ FILTERS. o Added ability to split received packet into multiple buffers. o Added explicit runt and giant packet processing. 4.6 PDP-18B - Fixed DT, RF variable size interaction with restore. - Fixed MT bug in MTTR. 4.7 PDP-8 - Fixed DT, DF, RF, RX variable size interaction with restore. - Fixed MT bug in SKTR. 4.8 HP2100 - Fixed bug in DP (13210A controller only), DQ read status. - Fixed bug in DP, DQ seek complete. 4.9 GRI - Fixed bug in SC queue pointer management.
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
4ffd3be790
commit
f9564b81b9
@@ -23,6 +23,8 @@
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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30-Jul-03 RMS Fixed FPM class mask
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18-Jul-03 RMS Added FP15 support
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02-Mar-03 RMS Split loaders apart for greater flexibility
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09-Feb-03 RMS Fixed bug in FMTASC (found by Hans Pufal)
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31-Jan-03 RMS Added support for RB09
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@@ -47,6 +49,9 @@
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#include <ctype.h>
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extern DEVICE cpu_dev;
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#if defined (PDP15)
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extern DEVICE fpp_dev;
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#endif
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extern DEVICE ptr_dev, ptp_dev;
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extern DEVICE tti_dev, tto_dev;
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extern UNIT tti_unit, tto_unit;
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@@ -87,7 +92,7 @@ extern UNIT cpu_unit;
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extern REG cpu_reg[];
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extern int32 M[];
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extern int32 memm;
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extern int32 saved_PC;
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extern int32 PC;
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/* SCP data structures and interface routines
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@@ -111,9 +116,13 @@ char sim_name[] = "PDP-15";
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REG *sim_PC = &cpu_reg[0];
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int32 sim_emax = 3;
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int32 sim_emax = 2;
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DEVICE *sim_devices[] = { &cpu_dev,
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DEVICE *sim_devices[] = {
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&cpu_dev,
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#if defined (PDP15)
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&fpp_dev,
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#endif
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&ptr_dev,
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&ptp_dev,
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&tti_dev,
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@@ -159,7 +168,8 @@ const char *sim_stop_messages[] = {
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"Breakpoint",
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"Nested XCT's",
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"Invalid API interrupt",
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"Non-standard device number" };
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"Non-standard device number",
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"Memory management error" };
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/* Binary loaders */
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@@ -202,7 +212,7 @@ for (;;) {
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if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
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if (MEM_ADDR_OK (origin)) M[origin++] = val; }
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else if ((val & 0760000) == OP_JMP) { /* JMP? */
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saved_PC = ((origin - 1) & 060000) | (val & 017777);
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PC = ((origin - 1) & 060000) | (val & 017777);
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return SCPE_OK; }
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else if (val == OP_HLT) return SCPE_OK; /* HLT? */
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else return SCPE_FMT; } /* error */
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@@ -226,7 +236,7 @@ t_stat r;
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if (*cptr != 0) { /* more input? */
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cptr = get_glyph (cptr, gbuf, 0); /* get origin */
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origin = get_uint (gbuf, 8, ADDRMASK, &r);
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origin = get_uint (gbuf, 8, AMASK, &r);
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if (r != SCPE_OK) return r;
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if (*cptr != 0) return SCPE_ARG; } /* no more */
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else origin = 0200; /* default 200 */
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@@ -234,7 +244,7 @@ else origin = 0200; /* default 200 */
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for (;;) { /* word loop */
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if ((val = getword (fileref, &bits)) < 0) return SCPE_FMT;
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if (bits & 1) { /* end of tape? */
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if ((val & 0760000) == OP_JMP) saved_PC =
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if ((val & 0760000) == OP_JMP) PC =
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((origin - 1) & 060000) | (val & 017777);
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else if (val != OP_HLT) return SCPE_FMT;
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break; }
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@@ -258,16 +268,16 @@ return SCPE_OK;
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t_stat bin_load_915 (FILE *fileref, char *cptr)
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{
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int32 i, val, origin, count, cksum;
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int32 i, val, bits, origin, count, cksum;
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if (*cptr != 0) return SCPE_2MARG; /* no arguments */
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do { val = getc (fileref); } /* find end RIM */
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while (((val & 0100) == 0) && (val != EOF));
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if (val == EOF) rewind (fileref); /* no RIM? rewind */
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do { val = getword (fileref, & bits); } /* find end RIM */
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while ((val >= 0) && ((bits & 1) == 0));
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if (val < 0) rewind (fileref); /* no RIM? rewind */
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for (;;) { /* block loop */
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if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
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if (val & SIGN) {
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if (val != DMASK) saved_PC = val & 077777;
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if (val != DMASK) PC = val & 077777;
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break; }
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cksum = origin = val; /* save origin */
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if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
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@@ -328,23 +338,30 @@ return bin_load_915 (fileref, cptr); /* must be BIN */
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#define I_V_EST 8 /* EAE setup */
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#define I_V_ESH 9 /* EAE shift */
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#define I_V_EMD 10 /* EAE mul-div */
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#define I_NPN (I_V_NPN << I_V_FL) /* no operand */
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#define I_NPI (I_V_NPI << I_V_FL) /* no operand IOT */
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#define I_IOT (I_V_IOT << I_V_FL) /* IOT */
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#define I_MRF (I_V_MRF << I_V_FL) /* memory reference */
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#define I_OPR (I_V_OPR << I_V_FL) /* OPR */
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#define I_LAW (I_V_LAW << I_V_FL) /* LAW */
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#define I_XR (I_V_XR << I_V_FL) /* index */
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#define I_XR9 (I_V_XR9 << I_V_FL) /* index literal */
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#define I_EST (I_V_EST << I_V_FL) /* EAE setup */
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#define I_ESH (I_V_ESH << I_V_FL) /* EAE shift */
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#define I_EMD (I_V_EMD << I_V_FL) /* EAE mul-div */
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#define I_V_FPM 11 /* FP15 mem ref */
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#define I_V_FPI 12 /* FP15 indirect */
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#define I_V_FPN 13 /* FP15 no operand */
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#define I_NPN (I_V_NPN << I_V_FL)
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#define I_NPI (I_V_NPI << I_V_FL)
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#define I_IOT (I_V_IOT << I_V_FL)
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#define I_MRF (I_V_MRF << I_V_FL)
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#define I_OPR (I_V_OPR << I_V_FL)
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#define I_LAW (I_V_LAW << I_V_FL)
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#define I_XR (I_V_XR << I_V_FL)
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#define I_XR9 (I_V_XR9 << I_V_FL)
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#define I_EST (I_V_EST << I_V_FL)
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#define I_ESH (I_V_ESH << I_V_FL)
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#define I_EMD (I_V_EMD << I_V_FL)
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#define I_FPM (I_V_FPM << I_V_FL)
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#define I_FPI (I_V_FPI << I_V_FL)
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#define I_FPN (I_V_FPN << I_V_FL)
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#define MD(x) ((I_EMD) + ((x) << I_V_DC))
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static const int32 masks[] = {
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0777777, 0777767, 0740000, 0760000,
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0777777, 0777767, 0770000, 0760000,
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0763730, 0760000, 0777000, 0777000,
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0740700, 0760700, 0777700 };
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0740700, 0760700, 0777700, 0777777,
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0777777, 0777777 };
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static const char *opcode[] = {
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"CAL", "DAC", "JMS", "DZM", /* mem refs */
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@@ -452,9 +469,75 @@ static const char *opcode[] = {
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#if defined (PDP15)
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"SPCO", "SKP15", "RES",
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"SBA", "DBA", "EBA",
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"ORMM", "RDMM", "LDMM", "MPLR",
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"ENB", "INH", "MPRC", "IPFH",
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"AAS", "PAX", "PAL", "AAC",
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"PXA", "AXS", "PXL", "PLA",
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"PLX", "CLAC","CLX", "CLLR", "AXR",
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"FPT", /* FP15 */
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"ISB", "ESB", /* mem ref */
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"FSB", "URFSB", "UNFSB", "UUFSB",
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"DSB", "URDSB", "UNDSB", "UUDSB",
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"IRS", "ERS",
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"FRS", "URFRS", "UNFRS", "UUFRS",
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"DRS", "URDRS", "UNDRS", "UUDRS",
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"IMP", "EMP",
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"FMP", "URFMP", "UNFMP", "UUFMP",
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"DMP", "URDMP", "UNDMP", "UUDMP",
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"IDV", "EDV",
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"FDV", "URFDV", "UNFDV", "UUFDV",
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"DDV", "URDDV", "UNDDV", "UUDDV",
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"IRD", "ERD",
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"FRD", "URFRD", "UNFRD", "UUFRD",
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"DRD", "URDRD", "UNDRD", "UUDRD",
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"ILD", "ELD",
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"FLD", "UNFLD", "DLD", "UNDLD",
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"IST", "EST",
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"FST", "URFST", "UNFST", "UUFST",
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"DST", "UNDST",
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"ILF", "UNILF", "ELF", "UNELF",
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"FLX", "URFLX", "DLX", "URDLX",
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"ILQ", "ELQ",
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"FLQ", "UNFLQ", "DLQ", "UNDLQ",
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"LJE", "SJE",
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"IAD", "EAD",
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"FAD", "URFAD", "UNFAD", "UUFAD",
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"DAD", "URDAD", "UNDAD", "UUDAD",
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"BZA", "BMA", "BLE", "BPA",
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"BRU", "BNA", "BAC",
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"ISB*", "ESB*", /* indirect */
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"FSB*", "URFSB*", "UNFSB*", "UUFSB*",
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"DSB*", "URDSB*", "UNDSB*", "UUDSB*",
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"IRS*", "ERS*",
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"FRS*", "URFRS*", "UNFRS*", "UUFRS*",
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"DRS*", "URDRS*", "UNDRS*", "UUDRS*",
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"IMP*", "EMP*",
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"FMP*", "URFMP*", "UNFMP*", "UUFMP*",
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"DMP*", "URDMP*", "UNDMP*", "UUDMP*",
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"IDV*", "EDV*",
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"FDV*", "URFDV*", "UNFDV*", "UUFDV*",
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"DDV*", "URDDV*", "UNDDV*", "UUDDV*",
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"IRD*", "ERD",
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"FRD*", "URFRD*", "UNFRD*", "UUFRD*",
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"DRD*", "URDRD*", "UNDRD*", "UUDRD*",
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"ILD*", "ELD",
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"FLD*", "UNFLD*", "DLD*", "UNDLD*",
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"IST*", "EST",
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"FST*", "URFST*", "UNFST*", "UUFST*",
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"DST*", "UNDST*",
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"ILF*", "UNILF*", "ELF*", "UNELF*",
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"FLX*", "URFLX*", "DLX*", "URDLX*",
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"ILQ*", "ELQ*",
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"FLQ*", "UNFLQ*", "DLQ*", "UNDLQ*",
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"LJE*", "SJE*",
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"IAD*", "EAD*",
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"FAD*", "URFAD*", "UNFAD*", "UUFAD*",
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"DAD*", "URDAD*", "UNDAD*", "UUDAD*",
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"FLA", "UNFLA", "FXA", "URFXA", /* no operand */
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"SWQ", "UNSWQ", "FZR",
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"FAB", "FNG", "FCM", "FNM",
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#endif
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#if defined (PDP9) || defined (PDP15)
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"MPSK", "MPSNE", "MPCV", "MPEU",
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@@ -617,9 +700,74 @@ static const int32 opc_val[] = {
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#if defined (PDP15)
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0703341+I_NPI, 0707741+I_NPI, 0707742+I_NPI,
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0707761+I_NPI, 0707762+I_NPI, 0707764+I_NPI,
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0700022+I_NPI, 0700032+I_NPN, 0700024+I_NPI, 0701724+I_NPI,
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0705521+I_NPI, 0705522+I_NPI, 0701722+I_NPI, 0701764+I_NPI,
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0720000+I_XR9, 0721000+I_XR, 0722000+I_XR, 0723000+I_XR9,
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0724000+I_XR, 0725000+I_XR9, 0726000+I_XR, 0730000+I_XR,
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0731000+I_XR, 0734000+I_XR, 0735000+I_XR, 0736000+I_XR, 0737000+I_XR9,
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0710314+I_FPN,
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0710400+I_FPM, 0710500+I_FPM,
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0710440+I_FPM, 0710450+I_FPM, 0710460+I_FPM, 0710470+I_FPM,
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0710540+I_FPM, 0710550+I_FPM, 0710560+I_FPM, 0710570+I_FPM,
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0711000+I_FPM, 0711100+I_FPM,
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0711040+I_FPM, 0711050+I_FPM, 0711060+I_FPM, 0711070+I_FPM,
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0711140+I_FPM, 0711150+I_FPM, 0711160+I_FPM, 0711170+I_FPM,
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0711400+I_FPM, 0711500+I_FPM,
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0711440+I_FPM, 0711450+I_FPM, 0711460+I_FPM, 0711470+I_FPM,
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0711540+I_FPM, 0711550+I_FPM, 0711560+I_FPM, 0711570+I_FPM,
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0712000+I_FPM, 0712100+I_FPM,
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0712040+I_FPM, 0712050+I_FPM, 0712060+I_FPM, 0712070+I_FPM,
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0712140+I_FPM, 0712150+I_FPM, 0712160+I_FPM, 0712170+I_FPM,
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0712400+I_FPM, 0712500+I_FPM,
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0712440+I_FPM, 0712450+I_FPM, 0712460+I_FPM, 0712470+I_FPM,
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0712540+I_FPM, 0712550+I_FPM, 0712560+I_FPM, 0712570+I_FPM,
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0713000+I_FPM, 0713100+I_FPM,
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0713050+I_FPM, 0713070+I_FPM, 0713150+I_FPM, 0713170+I_FPM,
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0713600+I_FPM, 0713700+I_FPM,
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0713640+I_FPM, 0713650+I_FPM, 0713660+I_FPM, 0713670+I_FPM,
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0713750+I_FPM, 0713770+I_FPM,
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0714010+I_FPM, 0714030+I_FPM, 0714110+I_FPM, 0714130+I_FPM,
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0714460+I_FPM, 0714470+I_FPM, 0714560+I_FPM, 0714570+I_FPM,
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0715000+I_FPM, 0715100+I_FPM,
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0715050+I_FPM, 0715070+I_FPM, 0715150+I_FPM, 0715170+I_FPM,
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0715400+I_FPM, 0715600+I_FPM,
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0716000+I_FPM, 0716100+I_FPM,
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0716040+I_FPM, 0716050+I_FPM, 0716060+I_FPM, 0716070+I_FPM,
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0716140+I_FPM, 0716150+I_FPM, 0716160+I_FPM, 0716170+I_FPM,
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0716601+I_FPM, 0716602+I_FPM, 0716603+I_FPM,
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0716604+I_FPM, 0716606+I_FPM, 0716610+I_FPM, 0716620+I_FPM,
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0710400+I_FPI, 0710500+I_FPI, /* indirect */
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0710440+I_FPI, 0710450+I_FPI, 0710460+I_FPI, 0710470+I_FPI,
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0710540+I_FPI, 0710550+I_FPI, 0710560+I_FPI, 0710570+I_FPI,
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0711000+I_FPI, 0711100+I_FPI,
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0711040+I_FPI, 0711050+I_FPI, 0711060+I_FPI, 0711070+I_FPI,
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0711140+I_FPI, 0711150+I_FPI, 0711160+I_FPI, 0711170+I_FPI,
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0711400+I_FPI, 0711500+I_FPI,
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0711440+I_FPI, 0711450+I_FPI, 0711460+I_FPI, 0711470+I_FPI,
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0711540+I_FPI, 0711550+I_FPI, 0711560+I_FPI, 0711570+I_FPI,
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0712000+I_FPI, 0712100+I_FPI,
|
||||
0712040+I_FPI, 0712050+I_FPI, 0712060+I_FPI, 0712070+I_FPI,
|
||||
0712140+I_FPI, 0712150+I_FPI, 0712160+I_FPI, 0712170+I_FPI,
|
||||
0712400+I_FPI, 0712500+I_FPI,
|
||||
0712440+I_FPI, 0712450+I_FPI, 0712460+I_FPI, 0712470+I_FPI,
|
||||
0712540+I_FPI, 0712550+I_FPI, 0712560+I_FPI, 0712570+I_FPI,
|
||||
0713000+I_FPI, 0713100+I_FPI,
|
||||
0713050+I_FPI, 0713070+I_FPI, 0713150+I_FPI, 0713170+I_FPI,
|
||||
0713600+I_FPI, 0713700+I_FPI,
|
||||
0713640+I_FPI, 0713650+I_FPI, 0713660+I_FPI, 0713670+I_FPI,
|
||||
0713750+I_FPI, 0713770+I_FPI,
|
||||
0714010+I_FPI, 0714030+I_FPI, 0714110+I_FPI, 0714130+I_FPI,
|
||||
0714460+I_FPI, 0714470+I_FPI, 0714560+I_FPI, 0714570+I_FPI,
|
||||
0715000+I_FPI, 0715100+I_FPI,
|
||||
0715050+I_FPI, 0715070+I_FPI, 0715150+I_FPI, 0715170+I_FPI,
|
||||
0715400+I_FPI, 0715600+I_FPI,
|
||||
0716000+I_FPI, 0716100+I_FPI,
|
||||
0716040+I_FPI, 0716050+I_FPI, 0716060+I_FPI, 0716070+I_FPI,
|
||||
0716140+I_FPI, 0716150+I_FPI, 0716160+I_FPI, 0716170+I_FPI,
|
||||
0714210+I_FPN, 0714230+I_FPN, 0714660+I_FPN, 0714670+I_FPN,
|
||||
0715250+I_FPN, 0715270+I_FPN, 0711200+I_FPN,
|
||||
0713271+I_FPN, 0713272+I_FPN, 0713273+I_FPN, 0713250+I_FPN,
|
||||
#endif
|
||||
#if defined (PDP9) || defined (PDP15)
|
||||
0701701+I_NPI, 0701741+I_NPI, 0701702+I_NPI, 0701742+I_NPI,
|
||||
@@ -741,7 +889,7 @@ if (!(sw & SWMASK ('M'))) return SCPE_ARG;
|
||||
|
||||
for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
|
||||
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
|
||||
if ((opc_val[i] & 0777777) == (inst & masks[j])) { /* match? */
|
||||
if ((opc_val[i] & DMASK) == (inst & masks[j])) { /* match? */
|
||||
|
||||
switch (j) { /* case on class */
|
||||
case I_V_NPN: /* no operands */
|
||||
@@ -758,17 +906,17 @@ for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
|
||||
case I_V_MRF: /* mem ref */
|
||||
#if defined (PDP15)
|
||||
if (memm) {
|
||||
disp = inst & 017777;
|
||||
ma = (addr & 0760000) | disp; }
|
||||
disp = inst & B_DAMASK;
|
||||
ma = (addr & (AMASK & ~B_DAMASK)) | disp; }
|
||||
else {
|
||||
disp = inst & 007777;
|
||||
ma = (addr & 0770000) | disp; }
|
||||
fprintf (of, "%s %-o", opcode[i], (cflag? ma & ADDRMASK: disp));
|
||||
if (!memm && (inst & 0010000)) fprintf (of, ",X");
|
||||
disp = inst & P_DAMASK;
|
||||
ma = (addr & (AMASK & ~P_DAMASK)) | disp; }
|
||||
fprintf (of, "%s %-o", opcode[i], (cflag? ma & AMASK: disp));
|
||||
if (!memm && (inst & I_IDX)) fprintf (of, ",X");
|
||||
#else
|
||||
disp = inst & 017777;
|
||||
ma = (addr & 0760000) | disp;
|
||||
fprintf (of, "%s %-o", opcode[i], (cflag? ma & ADDRMASK: disp));
|
||||
disp = inst & B_DAMASK;
|
||||
ma = (addr & (AMASK & ~B_DAMASK)) | disp;
|
||||
fprintf (of, "%s %-o", opcode[i], (cflag? ma & AMASK: disp));
|
||||
#endif
|
||||
break;
|
||||
case I_V_OPR: /* operate */
|
||||
@@ -796,7 +944,15 @@ for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
|
||||
if (disp == k) fprintf (of, "%s", opcode[i]);
|
||||
else if (disp < k) fprintf (of, "%s -%-o", opcode[i], k - disp);
|
||||
else fprintf (of, "%s +%-o", opcode[i], disp - k);
|
||||
break; } /* end case */
|
||||
break;
|
||||
case I_V_FPM: case I_V_FPI: /* FP15 mem ref */
|
||||
fprintf (of, "%s", opcode[i]);
|
||||
if (val[1] & SIGN) fputc ('*', of);
|
||||
fprintf (of, " %-o", val[1] & ~SIGN);
|
||||
return -1;
|
||||
case I_V_FPN: /* FP15 no operand */
|
||||
fprintf (of, "%s", opcode[i]);
|
||||
return -1; } /* end case */
|
||||
return SCPE_OK; } /* end if */
|
||||
} /* end for */
|
||||
return SCPE_ARG;
|
||||
@@ -838,8 +994,8 @@ return get_uint (cptr, 8, 0777777, status);
|
||||
|
||||
t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
|
||||
{
|
||||
int32 cflag, d, i, j, k, sign, dmask, epcmask;
|
||||
t_stat r;
|
||||
int32 cflag, d, i, j, k, sign, damask, epcmask;
|
||||
t_stat r, sta = SCPE_OK;
|
||||
char gbuf[CBUFSIZE];
|
||||
|
||||
cflag = (uptr == NULL) || (uptr == &cpu_unit);
|
||||
@@ -895,31 +1051,31 @@ case I_V_LAW: /* law */
|
||||
break;
|
||||
case I_V_MRF: /* mem ref */
|
||||
#if defined (PDP15)
|
||||
if (memm) dmask = 017777;
|
||||
else dmask = 07777;
|
||||
if (memm) damask = B_DAMASK;
|
||||
else damask = P_DAMASK;
|
||||
cptr = get_glyph (cptr, gbuf, ','); /* get glyph */
|
||||
#else
|
||||
dmask = 017777;
|
||||
damask = B_DAMASK;
|
||||
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
||||
#endif
|
||||
#if defined (PDP4) || defined (PDP7)
|
||||
if (strcmp (gbuf, "I") == 0) { /* indirect? */
|
||||
val[0] = val[0] | 020000;
|
||||
val[0] = val[0] | I_IND;
|
||||
cptr = get_glyph (cptr, gbuf, 0); }
|
||||
#endif
|
||||
epcmask = ADDRMASK & ~dmask; /* get ePC */
|
||||
d = get_uint (gbuf, 8, ADDRMASK, &r); /* get addr */
|
||||
epcmask = AMASK & ~damask; /* get ePC */
|
||||
d = get_uint (gbuf, 8, AMASK, &r); /* get addr */
|
||||
if (r != SCPE_OK) return SCPE_ARG;
|
||||
if (d <= dmask) val[0] = val[0] | d; /* fit in 12/13b? */
|
||||
if (d <= damask) val[0] = val[0] | d; /* fit in 12/13b? */
|
||||
else if (cflag && (((addr ^ d) & epcmask) == 0))
|
||||
val[0] = val[0] | (d & dmask); /* hi bits = ePC? */
|
||||
val[0] = val[0] | (d & damask); /* hi bits = ePC? */
|
||||
else return SCPE_ARG;
|
||||
#if defined (PDP15)
|
||||
if (!memm) {
|
||||
cptr = get_glyph (cptr, gbuf, 0);
|
||||
if (gbuf[0] != 0) {
|
||||
if (strcmp (gbuf, "X") != 0) return SCPE_ARG;
|
||||
val[0] = val[0] | 010000; } }
|
||||
val[0] = val[0] | I_IDX; } }
|
||||
#endif
|
||||
break;
|
||||
case I_V_EMD: /* or'able */
|
||||
@@ -940,7 +1096,23 @@ case I_V_NPN: case I_V_NPI: case I_V_IOT: case I_V_OPR:
|
||||
if (sign > 0) val[0] = val[0] + d;
|
||||
else if (sign < 0) val[0] = val[0] - d;
|
||||
else val[0] = val[0] | d; } }
|
||||
break;
|
||||
case I_V_FPM: /* FP15 mem ref */
|
||||
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
||||
val[1] = get_uint (gbuf, 8, AMASK, &r); /* get addr */
|
||||
if (r != SCPE_OK) return SCPE_ARG;
|
||||
sta = -1;
|
||||
break;
|
||||
case I_V_FPI: /* FP15 ind mem ref */
|
||||
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
||||
val[1] = get_uint (gbuf, 8, AMASK, &r) | SIGN; /* get @addr */
|
||||
if (r != SCPE_OK) return SCPE_ARG;
|
||||
sta = -1;
|
||||
break;
|
||||
case I_V_FPN: /* FP15 no operand */
|
||||
val[1] = 0;
|
||||
sta = -1;
|
||||
break; } /* end case */
|
||||
if (*cptr != 0) return SCPE_ARG; /* junk at end? */
|
||||
return SCPE_OK;
|
||||
return sta;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user