This is the initial release of the Altair8800 simulator.
Why another Altair simulator? AltairZ80 has been described as a
“software simulator”, where the intent is to run software designed
specifically for executing under a simulator. Altair8800 is intended
to accurately simulate the Altair hardware and execute software
that will run unchanged on real hardware. Software and disk images
can be moved between the Altair8800 simulator and real Altair and
other S-100 hardware without any changes. The Altair8800 simulator
is a tool that can assist with the restoration of vintage Altair
and other S-100 hardware and software along with the development
of new hardware and software. The accomplish this, the following
are major differences between AltairZ80 and Altair8800.
* The monolithic design where devices access other devices directly
through external variables and functions is no longer supported.
All devices exchange data through a new BUS device. Memory and I/O
address decoding and transfers are now handled by the BUS device.
All interrupt requests are handled by the BUS device.
* System RAM was moved from the CPU device to a new RAM device and
managed by the BUS device.
* Banked RAM was moved from the CPU device to a new BRAM device.
* Banked RAM can only be accessed through the BUS device. Memory in
banks that are not currently selected cannot be accessed. The AZ80
“banked” RAM was removed.
* ROMs were moved from the CPU and DSK devices to the new ROM device.
Mike Douglas’ Altmon Monitor is also available through the ROM
device. The custom AltairZ80 ALTAIRROM, which is not compatible
with original Altair disk images, is also available.
* The custom ALTAIRROM boot loader was replaced with the original
MITS Disk Boot Loader as the default ROM.
* The monolithic Multiple-CPU/RAM/ROM/IO/BankedRAM CPU device has
been replaced with a generic CPU device that provides an abstraction
layer between SIMH and the supported CPU architectures (currently
8080 and Z80). All IO is handled through the BUS device. RAM, Banked
RAM, and ROM are each handled by their own independent devices.
* The AltairZ80 SIO device was replaced with the M2SIO0 and M2SIO1
devices. The M2SIO devices fully support TMXR.
* A new SIO device was added to provide generic, programmable, Serial
IO. TMXR is not supported on this device.
* The Altair 8800 did not have PTR or PTP hardware devices. They have
been removed and replaced with the M2SIO1 device. PTR and PTP devices
are defined by software executing on the simulator.
* Contention between multiple enabled serial devices checking the
single host keyboard for input is now handled by the BUS device.
Port 0xFF sense switches was moved to a new SSW device and IMSAI
programmed output was moved to a new PO device.
* The SIMH pseudo device no longer uses the removed PTR and PTP
devices. The SIMH device has its own IO system. To avoid conflicts
with other devices and remain compatible with the R and W utilities
written for AltairZ80, SIMH “borrows” I/O ports 12H and 13H during
file transfers. Only SIMH commands needed to support R and W file
transfers are supported. All other SIMH commands were removed.
* AltairZ80-specific versions of CP/M are not supported by Altair8800.
* PC queue was removed from CPU device and replaced with CPU HISTORY.
* The Altair8800 simulator only supports 16-bit address and 8-bit
data buses. 8086 and 68K CPU architectures were removed.
* All CPU timing (clockFrequency) and “sleeps” (SIO SLEEP) have been
removed. SIMH THROTTLE is fully supported and is the recommended
way to manage simulator speed and host CPU utilization. Executing
“SET THROTTLE 100K/1”, for example, should provide ample speed
without tasking the host CPU.
* HEXLOAD and HEXSAVE commands were added. The LOAD “-h” option has
been removed. Intel Hex and sRecord (coming soon) formats are
supported.
* The WD179X device was converted to an API.
* A new DSK API was added to provide a consistent way to manage soft
sector raw disk images.
* Support for the proprietary IMD disk image format was removed. Only
RAW disk images are supported.
The following devices are supported by this initial release:
BUS - Altair (S-100) Bus
CPU - Intel 8080 / Zilog Z80
RAM - 64K RAM
ROM - ROMs
BRAM - Banked RAM
DSK - MITS 88-DCDD Floppy Disk Controller
M2SIO0 - MITS 88-2SIO Port 0
M2SIO1 - MITS 88-2SIO Port 1
SSW - Sense Switches
PO - Programmed Output
SIO - Generic Serial I/O
SBC200 - SD Systems SBC-200
TARBELL - Tarbell SD and DD Floppy Disk Controller
VFII - SD Systems VersaFloppy II
SIMH - SIMH Pseudo Device
The original SET CONSOLE SPEED=nnn was added to a allow direct wired
terminal connected to a host system serial port to be a simulator's console.
The current change generalizes all console I/O such that speed is a reliable
option for direct console connections as well as serial and telnet connections.
The simple recipe to get well behaved console output speed is:
1) call tmxr_set_console_units() in the reset routine of the console DEVICE.
2) In the code path that engages console output do something similar
to this as appropriate for the system being simulated:
void txdb_wr (int32 data)
{
tto_unit.buf = data & 0377;
tto_csr = tto_csr & ~CSR_DONE;
CLR_INT (TTO);
sim_activate (&tto_unit, tto_unit.wait);
}
3) In the output unit's service routine the console output unit's service
routine do something similar to this as appropriate for the system
being simulated:
t_stat tto_svc (UNIT *uptr)
{
int32 c;
c = sim_tt_outcvt (tto_unit.buf, TT_GET_MODE (uptr->flags));
if (c >= 0) {
t_stat r;
if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */
sim_activate (uptr, uptr->wait); /* retry */
return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */
}
}
tto_csr = tto_csr | CSR_DONE;
if (tto_csr & CSR_IE)
SET_INT (TTO);
}
The almost all of the current simh simulators already are implemented
with logic like the above example. These will work just fine with the
newly regulated console speed.
This fixes the H flag handling for the 8080 CPU and corrects the parity
flag computation for the Z80 CPU for INI, OUTI, IND, OUTD, INIR, OTIR,
INDR and OTDR instructions. It is based on Thomas Eberhardt's work.
- Add common system includes used in may places which are allowed
and thus added directly in sim_defs.h.
- Separate completely private system data structures and system APIs
for use only by SCP library routines into sim_scp_private.h.
- Update README to describe differences with open-simh
- Allow SET NOAUTOSIZE and SET AUTOSIZE
- Document deprecation and possibly non functionality of MinGW
Windows build support
- bounds check accesses in get_rval and put_rval for circular registers
- extend unit tests for REGister sanity checks to include all macros
- add sanity checks for new REGister macros
Historically, if a configuration file explicitly set either a DEVICE's
ADDRESS or VECTOR, autoconfiguration was immediately disabled.
This change defers disabling autoconfigure until an explicitly setting
of a DEVICE address or VECTOR actually changes what had been previously
configured by autoconfigure.
- General cleanup of codebase
- Fixed condition codes m6800.c from Roberto Sancho Villa
- Add additional FDC lfd-400 from Roberto Sancho Villa
- Add additional OS's (FLEX 1.0, FDOS 1.0, DOS68, MiniDOS, and MiniDOS-MPX)
to software support
- Add additional disk formats to software support dc-4.c from Roberto
Sancho Villa
- Add CPU history
- Fix LOAD/DUMP to support binary and hex
- Fix fprintf_sym to disassemble 6800 code correctly
- Add EXAMINE/DEPOSIT to CPU Memory
- Fixed disasm to space the register
- Add SET_FLAG(IF) to IRQ – fixed error in handling IRQ from
Roberto Sancho Villa
Some simulators and/or devices may want to provide specific testing
activities outside of full simulator execution which often will require
external, potentially complicated setup.
Added KS10 support.
CPU Redid instruction decode to improve performance
Triple-I display cleanup.
Normalized end of line to DOS/Unix.
KL10 FE, Cleanup issues with TTY devices hanging simulator..
Fixed errors in RH20 device.
RP and TU drives more independent of RH controller.
The key change is the addition of:
When a simulator starts execution, the following sequence of simh command
files are executed if they are found:
1. If a file named simh.ini is located in your HOME directory, it is
executed.
2. If the simh.ini file in your HOME directory isn’t found, a file named
simh.ini in your current working directory is executed if it exists.
3. If the simulator is invoked with any arguments, then the arguments are
presumed to be a command file and possible arguments to that command
file which is executed.
4. If the simulator is invoked without any arguments, then a command file
with the same name as the simulator binary with .ini appended that is
located in the current working directory is executed.
Note, that up to 2 separate command files may be executed on simulator
startup. The simh.ini file allows the user to define local user
preferences that align with their personal goals for simulator execution
across all simulators that may be used on their system.
Steps 3 and 4 were inherited from simh v3.x. Steps 1 and 2 was inspired
by conversations with J. David Bryan in April of 2012. Some how it
never got documented.
- Added a specific drive type RP05 which is the same size as the RP04
but can be distringuished by OS software.
- Restrict SET rpn BADBLOCK to only disk types which actually supported
the DEC Standard 144 bad block table.
- Fixed typo's in help and comments about DEC 044 vs DEC 144 and also
in pdp11_doc and vax780_doc documentation files.
As discussed in #1065
The new REG_DEPOSIT register flag bit indicates that updates to a
REGister with this flag specified will invoke the sim_vm_reg_update
routine after the data has been updated.
This avoids a potential invalid pointer dereference when formatting
the return value from sim_instr() if it is < SCPE_BASE but greater
than the previously defined static array size.sizeof
Update simh.doc to reflect this generic change.
