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This is the initial release of the Altair8800 simulator. Why another Altair simulator? AltairZ80 has been described as a “software simulator”, where the intent is to run software designed specifically for executing under a simulator. Altair8800 is intended to accurately simulate the Altair hardware and execute software that will run unchanged on real hardware. Software and disk images can be moved between the Altair8800 simulator and real Altair and other S-100 hardware without any changes. The Altair8800 simulator is a tool that can assist with the restoration of vintage Altair and other S-100 hardware and software along with the development of new hardware and software. The accomplish this, the following are major differences between AltairZ80 and Altair8800. * The monolithic design where devices access other devices directly through external variables and functions is no longer supported. All devices exchange data through a new BUS device. Memory and I/O address decoding and transfers are now handled by the BUS device. All interrupt requests are handled by the BUS device. * System RAM was moved from the CPU device to a new RAM device and managed by the BUS device. * Banked RAM was moved from the CPU device to a new BRAM device. * Banked RAM can only be accessed through the BUS device. Memory in banks that are not currently selected cannot be accessed. The AZ80 “banked” RAM was removed. * ROMs were moved from the CPU and DSK devices to the new ROM device. Mike Douglas’ Altmon Monitor is also available through the ROM device. The custom AltairZ80 ALTAIRROM, which is not compatible with original Altair disk images, is also available. * The custom ALTAIRROM boot loader was replaced with the original MITS Disk Boot Loader as the default ROM. * The monolithic Multiple-CPU/RAM/ROM/IO/BankedRAM CPU device has been replaced with a generic CPU device that provides an abstraction layer between SIMH and the supported CPU architectures (currently 8080 and Z80). All IO is handled through the BUS device. RAM, Banked RAM, and ROM are each handled by their own independent devices. * The AltairZ80 SIO device was replaced with the M2SIO0 and M2SIO1 devices. The M2SIO devices fully support TMXR. * A new SIO device was added to provide generic, programmable, Serial IO. TMXR is not supported on this device. * The Altair 8800 did not have PTR or PTP hardware devices. They have been removed and replaced with the M2SIO1 device. PTR and PTP devices are defined by software executing on the simulator. * Contention between multiple enabled serial devices checking the single host keyboard for input is now handled by the BUS device. Port 0xFF sense switches was moved to a new SSW device and IMSAI programmed output was moved to a new PO device. * The SIMH pseudo device no longer uses the removed PTR and PTP devices. The SIMH device has its own IO system. To avoid conflicts with other devices and remain compatible with the R and W utilities written for AltairZ80, SIMH “borrows” I/O ports 12H and 13H during file transfers. Only SIMH commands needed to support R and W file transfers are supported. All other SIMH commands were removed. * AltairZ80-specific versions of CP/M are not supported by Altair8800. * PC queue was removed from CPU device and replaced with CPU HISTORY. * The Altair8800 simulator only supports 16-bit address and 8-bit data buses. 8086 and 68K CPU architectures were removed. * All CPU timing (clockFrequency) and “sleeps” (SIO SLEEP) have been removed. SIMH THROTTLE is fully supported and is the recommended way to manage simulator speed and host CPU utilization. Executing “SET THROTTLE 100K/1”, for example, should provide ample speed without tasking the host CPU. * HEXLOAD and HEXSAVE commands were added. The LOAD “-h” option has been removed. Intel Hex and sRecord (coming soon) formats are supported. * The WD179X device was converted to an API. * A new DSK API was added to provide a consistent way to manage soft sector raw disk images. * Support for the proprietary IMD disk image format was removed. Only RAW disk images are supported. The following devices are supported by this initial release: BUS - Altair (S-100) Bus CPU - Intel 8080 / Zilog Z80 RAM - 64K RAM ROM - ROMs BRAM - Banked RAM DSK - MITS 88-DCDD Floppy Disk Controller M2SIO0 - MITS 88-2SIO Port 0 M2SIO1 - MITS 88-2SIO Port 1 SSW - Sense Switches PO - Programmed Output SIO - Generic Serial I/O SBC200 - SD Systems SBC-200 TARBELL - Tarbell SD and DD Floppy Disk Controller VFII - SD Systems VersaFloppy II SIMH - SIMH Pseudo Device
61 lines
2.5 KiB
C
61 lines
2.5 KiB
C
/* s100_sio.h
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Copyright (c) 2025 Patrick A. Linstruth
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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PETER SCHORN BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Patrick Linstruth shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Patrick Linstruth.
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History:
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11/07/25 Initial version
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*/
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#ifndef _S100_SIO_H
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#define _S100_SIO_H
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#define UNIT_SIO_V_VERBOSE (UNIT_V_UF+0)
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#define UNIT_SIO_VERBOSE (1 << UNIT_SIO_V_VERBOSE)
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#define UNIT_SIO_V_CONSOLE (UNIT_V_UF+1)
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#define UNIT_SIO_CONSOLE (1 << UNIT_SIO_V_CONSOLE)
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typedef struct {
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uint8 type; /* Type Value */
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char *name; /* Name */
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char *desc; /* Description */
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int32 base; /* Base Port */
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int32 stat; /* Status Port Offset */
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int32 data; /* Data Port Offset */
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int32 rdre; /* Receive Data Register Empty Mask */
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int32 rdrf; /* Receive Data Register Full Mask */
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int32 tdre; /* Transmit Data Register Empty Mask */
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int32 tdrf; /* Transmit Data Register Full Mask */
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} SIO;
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typedef struct {
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uint8 type; /* Board SIO Configuration Type */
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char *name; /* Board Name */
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char *desc; /* Board Description */
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int32 base; /* Board Base I/O Address */
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} SIO_BOARD;
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#endif
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