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simh.simh/AltairZ80/s100_selchan.c
Mark Pizzolato 3071894c78 Notes For V3.9
The makefile now works for Linux and most Unix's. However, for Solaris
and MacOS, you must first export the OSTYPE environment variable:

> export OSTYPE
> make

Otherwise, you will get build errors.

1. New Features

1.1 3.9-0

1.1.1 SCP and libraries

	- added *nix READLINE support (Mark Pizzolato)
	- added "SHOW SHOW" and "SHOW <dev> SHOW" commands (Mark Pizzolato)
	- added support for BREAK key on Windows (Mark Pizzolato)

1.1.2 PDP-8

	- floating point processor is now enabled

2. Bugs Fixed

Please see the revision history on http://simh.trailing-edge.com or
in the source module sim_rev.h.

3. Status Report

This is the last release of SimH for which I will be sole editor. After this
release, the source is moving to a public repository:

under the general editorship of Dave Hittner and Mark Pizzolato. The status
of the individual simulators is as follows:

3.1 PDP-1

Stable and working; runs available software.

3.2 PDP-4/7/9/15

Stable and working; runs available software.

3.3 PDP-8

Stable and working; runs available software.

3.4 PDP-10 [KS-10 only]

Stable and working; runs available software.

3.5 PDP-11

Stable and working; runs available system software. The emulation of individual
models has numerous errors of detail, which prevents many diagnostics from
running correctly.

3.6 VAX-11/780

Stable and working; runs available software.

3.7 MicroVAX 3900 (VAX)

Stable and working; runs available software. Thanks to the kind generosity of
Camiel Vanderhoeven, this simulator has been verified with AXE, the VAX
architectural exerciser.

3.8 Nova

Stable and working; runs available software.

3.9 Eclipse

Stable and working, but not really supported. There is no Eclipse-specific
software available under a hobbyist license.

3.10 Interdata 16b

Stable and working, but no software for it has been found, other than
diagnostics.

3.11 Interdata 32b

Stable and working; runs 32b UNIX and diagnostics.

3.12 IBM 1401

Stable and working; runs available software.

3.13 IBM 1620

Hand debug only.  No software for it has been found or tested.

3.14 IBM 7094

Stable and working as a stock system; runs IBSYS. The CTSS extensions
have not been debugged.

3.15 IBM S/3

Stable and working, but not really supported. Runs available software.

3.16 IBM 1130

Stable and working; runs available software.  Supported and edited by
Brian Knittel.

3.17 HP 2100/1000

Stable and working; runs available software. Supported and edited by
Dave Bryan.

3.18 Honeywell 316/516

Stable and working; runs available software.

3.19 GRI-909/99

Hand debug only.  No software for it has been found or tested.

3.20 SDS-940

Hand debug only, and a few diagnostics.

3.21 LGP-30

Unfinished; hand debug only. Does not run available software, probably
due to my misunderstanding of the LGP-30 operational procedures.

3.22 Altair (original 8080 version)

Stable and working, but not really supported. Runs available software.

3.23 AltairZ80 (Z80 version)

Stable and working; runs available software. Supported and edited by
Peter Schorn.

3.24 SWTP 6800

Stable and working; runs available software. Supported and edited by
Bill Beech

3.25 Sigma 32b

Incomplete; more work is needed on the peripherals for accuracy.

3.26 Alpha

Incomplete; essentially just an EV-5 (21164) chip emulator.

4. Suggestions for Future Work

4.1 General Structure

	- Multi-threading, to allow true concurrency between SCP and the simulator
	- Graphics device support, particularly for the PDP-1 and PDP-11

4.2 Current Simulators

	- PDP-1 graphics, to run Space War
	- PDP-11 GT40 graphics, to run Lunar Lander
	- PDP-15 MUMPS-15
	- Interdata native OS debug, both 16b and 32b
	- SDS 940 timesharing operating system debug
	- IBM 7094 CTSS feature debug and operating system debug
	- IBM 1620 debug and software
	- GRI-909 software
	- Sigma 32b completion and debug
	- LGP-30 debug

4.3 Possible Future Simulators

	- Data General MV8000 (if a hobbyist license can be obtained for AOS)
	- Alpha simulator
	- HP 3000 (16b) simulator with MPE
2012-03-18 09:43:12 -07:00

210 lines
8.8 KiB
C

/*************************************************************************
* *
* $Id: s100_selchan.c 1995 2008-07-15 03:59:13Z hharte $ *
* *
* Copyright (c) 2007-2008 Howard M. Harte. *
* http://www.hartetec.com *
* *
* Permission is hereby granted, free of charge, to any person obtaining *
* a copy of this software and associated documentation files (the *
* "Software"), to deal in the Software without restriction, including *
* without limitation the rights to use, copy, modify, merge, publish, *
* distribute, sublicense, and/or sell copies of the Software, and to *
* permit persons to whom the Software is furnished to do so, subject to *
* the following conditions: *
* *
* The above copyright notice and this permission notice shall be *
* included in all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, *
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF *
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND *
* NONINFRINGEMENT. IN NO EVENT SHALL HOWARD M. HARTE BE LIABLE FOR ANY *
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, *
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE *
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. *
* *
* Except as contained in this notice, the name of Howard M. Harte shall *
* not be used in advertising or otherwise to promote the sale, use or *
* other dealings in this Software without prior written authorization *
* Howard M. Harte. *
* *
* SIMH Interface based on altairz80_hdsk.c, by Peter Schorn. *
* *
* Module Description: *
* CompuPro Selector Channel module for SIMH. *
* *
* Environment: *
* User mode only *
* *
*************************************************************************/
/*#define DBG_MSG */
#include "altairz80_defs.h"
#if defined (_WIN32)
#include <windows.h>
#endif
#ifdef DBG_MSG
#define DBG_PRINT(args) printf args
#else
#define DBG_PRINT(args)
#endif
/* Debug flags */
#define ERROR_MSG (1 << 0)
#define VERBOSE_MSG (1 << 1)
#define DMA_MSG (1 << 2)
#define SELCHAN_MAX_DRIVES 1
#define UNIT_V_SELCHAN_VERBOSE (UNIT_V_UF + 1) /* verbose mode, i.e. show error messages */
#define UNIT_SELCHAN_VERBOSE (1 << UNIT_V_SELCHAN_VERBOSE)
typedef struct {
PNP_INFO pnp; /* Plug and Play */
uint32 selchan; /* Selector Channel Register */
uint32 dma_addr; /* DMA Transfer Address */
uint32 dma_mode; /* DMA Mode register */
uint8 reg_cnt; /* Counter for selchan register */
} SELCHAN_INFO;
static SELCHAN_INFO selchan_info_data = { { 0x0, 0, 0xF0, 1 } };
static SELCHAN_INFO *selchan_info = &selchan_info_data;
int32 selchan_dma(uint8 *buf, uint32 len);
extern t_stat set_iobase(UNIT *uptr, int32 val, char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
extern uint32 PCX;
/* These are needed for DMA. */
extern void PutByteDMA(const uint32 Addr, const uint32 Value);
extern uint8 GetByteDMA(const uint32 Addr);
static t_stat selchan_reset(DEVICE *selchan_dev);
static int32 selchandev(const int32 port, const int32 io, const int32 data);
static UNIT selchan_unit[] = {
{ UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_ROABLE, 0) }
};
static REG selchan_reg[] = {
{ HRDATA (DMA_MODE, selchan_info_data.dma_mode, 8), },
{ HRDATA (DMA_ADDR, selchan_info_data.dma_addr, 24), },
{ NULL }
};
static MTAB selchan_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE", &set_iobase, &show_iobase, NULL },
/* quiet, no warning messages */
{ UNIT_SELCHAN_VERBOSE, 0, "QUIET", "QUIET", NULL },
/* verbose, show warning messages */
{ UNIT_SELCHAN_VERBOSE, UNIT_SELCHAN_VERBOSE, "VERBOSE", "VERBOSE", NULL },
{ 0 }
};
/* Debug Flags */
static DEBTAB selchan_dt[] = {
{ "ERROR", ERROR_MSG },
{ "VERBOSE",VERBOSE_MSG },
{ "DMA", DMA_MSG },
{ NULL, 0 }
};
DEVICE selchan_dev = {
"SELCHAN", selchan_unit, selchan_reg, selchan_mod,
SELCHAN_MAX_DRIVES, 10, 31, 1, SELCHAN_MAX_DRIVES, SELCHAN_MAX_DRIVES,
NULL, NULL, &selchan_reset,
NULL, NULL, NULL,
&selchan_info_data, (DEV_DISABLE | DEV_DIS | DEV_DEBUG), ERROR_MSG,
selchan_dt, NULL, "Compupro Selector Channel SELCHAN"
};
/* Reset routine */
static t_stat selchan_reset(DEVICE *dptr)
{
PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &selchandev, TRUE);
} else {
/* Connect SELCHAN at base address */
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &selchandev, FALSE) != 0) {
printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}
}
return SCPE_OK;
}
#define SELCHAN_MODE_WRITE 0x80 /* Selector Channel Memory or I/O Write */
#define SELCHAN_MODE_IO 0x40 /* Set if I/O Access, otherwise memory */
#define SELCHAN_MODE_CNT_UP 0x20 /* Set = DMA Address Count Up, otherwise down. (Mem only */
#define SELCHAN_MODE_WAIT 0x10 /* Insert one wait state. */
#define SELCHAN_MODE_DMA_MASK 0x0F /* Mask for DMA Priority field */
static int32 selchandev(const int32 port, const int32 io, const int32 data)
{
DBG_PRINT(("SELCHAN: IO %s, Port %02x" NLP, io ? "WR" : "RD", port));
if(io) {
selchan_info->selchan <<= 8;
selchan_info->selchan &= 0xFFFFFF00;
selchan_info->selchan |= data;
selchan_info->dma_addr = (selchan_info->selchan & 0xFFFFF00) >> 8;
selchan_info->dma_mode = (selchan_info->selchan & 0xFF);
selchan_info->reg_cnt ++;
if(selchan_info->reg_cnt == 4) {
sim_debug(VERBOSE_MSG, &selchan_dev, "SELCHAN: " ADDRESS_FORMAT " DMA=0x%06x, Mode=0x%02x (%s, %s, %s)\n", PCX, selchan_info->dma_addr, selchan_info->dma_mode, selchan_info->dma_mode & SELCHAN_MODE_WRITE ? "WR" : "RD", selchan_info->dma_mode & SELCHAN_MODE_IO ? "I/O" : "MEM", selchan_info->dma_mode & SELCHAN_MODE_IO ? "FIX" : selchan_info->dma_mode & SELCHAN_MODE_CNT_UP ? "INC" : "DEC");
}
return 0;
} else {
sim_debug(VERBOSE_MSG, &selchan_dev, "SELCHAN: " ADDRESS_FORMAT " Reset\n", PCX);
selchan_info->reg_cnt = 0;
return(0xFF);
}
}
int32 selchan_dma(uint8 *buf, uint32 len)
{
uint32 i;
if(selchan_info->reg_cnt != 4) {
printf("SELCHAN: " ADDRESS_FORMAT " Programming error: selector channel disabled." NLP,
PCX);
return (-1);
}
if(selchan_info->dma_mode & SELCHAN_MODE_IO)
{
printf("SELCHAN: " ADDRESS_FORMAT " I/O Not supported" NLP, PCX);
return (-1);
} else {
sim_debug(DMA_MSG, &selchan_dev, "SELCHAN: " ADDRESS_FORMAT " DMA %s Transfer, len=%d\n", PCX, (selchan_info->dma_mode & SELCHAN_MODE_WRITE) ? "WR" : "RD", len);
for(i=0;i<len;i++) {
if(selchan_info->dma_mode & SELCHAN_MODE_WRITE) {
PutByteDMA(selchan_info->dma_addr + i, buf[i]);
} else {
buf[i] = GetByteDMA(selchan_info->dma_addr + i);
}
}
if(selchan_info->dma_mode & SELCHAN_MODE_CNT_UP) {
selchan_info->dma_addr += i;
} else {
selchan_info->dma_addr -= i;
}
}
return(0);
}