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3071894c78
The makefile now works for Linux and most Unix's. However, for Solaris and MacOS, you must first export the OSTYPE environment variable: > export OSTYPE > make Otherwise, you will get build errors. 1. New Features 1.1 3.9-0 1.1.1 SCP and libraries - added *nix READLINE support (Mark Pizzolato) - added "SHOW SHOW" and "SHOW <dev> SHOW" commands (Mark Pizzolato) - added support for BREAK key on Windows (Mark Pizzolato) 1.1.2 PDP-8 - floating point processor is now enabled 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h. 3. Status Report This is the last release of SimH for which I will be sole editor. After this release, the source is moving to a public repository: under the general editorship of Dave Hittner and Mark Pizzolato. The status of the individual simulators is as follows: 3.1 PDP-1 Stable and working; runs available software. 3.2 PDP-4/7/9/15 Stable and working; runs available software. 3.3 PDP-8 Stable and working; runs available software. 3.4 PDP-10 [KS-10 only] Stable and working; runs available software. 3.5 PDP-11 Stable and working; runs available system software. The emulation of individual models has numerous errors of detail, which prevents many diagnostics from running correctly. 3.6 VAX-11/780 Stable and working; runs available software. 3.7 MicroVAX 3900 (VAX) Stable and working; runs available software. Thanks to the kind generosity of Camiel Vanderhoeven, this simulator has been verified with AXE, the VAX architectural exerciser. 3.8 Nova Stable and working; runs available software. 3.9 Eclipse Stable and working, but not really supported. There is no Eclipse-specific software available under a hobbyist license. 3.10 Interdata 16b Stable and working, but no software for it has been found, other than diagnostics. 3.11 Interdata 32b Stable and working; runs 32b UNIX and diagnostics. 3.12 IBM 1401 Stable and working; runs available software. 3.13 IBM 1620 Hand debug only. No software for it has been found or tested. 3.14 IBM 7094 Stable and working as a stock system; runs IBSYS. The CTSS extensions have not been debugged. 3.15 IBM S/3 Stable and working, but not really supported. Runs available software. 3.16 IBM 1130 Stable and working; runs available software. Supported and edited by Brian Knittel. 3.17 HP 2100/1000 Stable and working; runs available software. Supported and edited by Dave Bryan. 3.18 Honeywell 316/516 Stable and working; runs available software. 3.19 GRI-909/99 Hand debug only. No software for it has been found or tested. 3.20 SDS-940 Hand debug only, and a few diagnostics. 3.21 LGP-30 Unfinished; hand debug only. Does not run available software, probably due to my misunderstanding of the LGP-30 operational procedures. 3.22 Altair (original 8080 version) Stable and working, but not really supported. Runs available software. 3.23 AltairZ80 (Z80 version) Stable and working; runs available software. Supported and edited by Peter Schorn. 3.24 SWTP 6800 Stable and working; runs available software. Supported and edited by Bill Beech 3.25 Sigma 32b Incomplete; more work is needed on the peripherals for accuracy. 3.26 Alpha Incomplete; essentially just an EV-5 (21164) chip emulator. 4. Suggestions for Future Work 4.1 General Structure - Multi-threading, to allow true concurrency between SCP and the simulator - Graphics device support, particularly for the PDP-1 and PDP-11 4.2 Current Simulators - PDP-1 graphics, to run Space War - PDP-11 GT40 graphics, to run Lunar Lander - PDP-15 MUMPS-15 - Interdata native OS debug, both 16b and 32b - SDS 940 timesharing operating system debug - IBM 7094 CTSS feature debug and operating system debug - IBM 1620 debug and software - GRI-909 software - Sigma 32b completion and debug - LGP-30 debug 4.3 Possible Future Simulators - Data General MV8000 (if a hobbyist license can be obtained for AOS) - Alpha simulator - HP 3000 (16b) simulator with MPE
422 lines
19 KiB
C
422 lines
19 KiB
C
/* sigma_fp.c: XDS Sigma floating point simulator
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Copyright (c) 2007-2008, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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*/
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#include "sigma_defs.h"
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#define UFP_V_GUARD 4
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#define UFP_NORM (FP_NORM << UFP_V_GUARD)
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#define UFP_CARRY (UFP_NORM << 4)
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#define UFP_FRHI (UFP_CARRY|UFP_NORM|FP_M_FRHI)
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#define UFP_FRLO 0xFFFFFFFF
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/* Double precision fraction add/subtract/compare */
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/* Note: UFP_ADD (s, r, r) will not work!!! */
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#define UFP_ADD(s1,s2,d) do { \
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d.l = (s1.l + s2.l) & UFP_FRLO; \
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d.h = (s1.h + s2.h + (d.l < s2.l)) & UFP_FRHI; \
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} while (0)
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#define UFP_SUB(s1,s2,d) do { \
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d.h = (s1.h - s2.h - (s1.l < s2.l)) & UFP_FRHI; \
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d.l = (s1.l - s2.l) & UFP_FRLO; \
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} while (0)
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#define UFP_GE(s1,s2) ((s1.h > s2.h) || \
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((s1.h == s2.h) && (s1.l >= s2.l)))
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/* Variable and constant shifts; for constants, 0 < k < 32 */
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#define UFP_RSH_V(v,s) do { \
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if ((s) < 32) { \
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v.l = ((v.l >> (s)) | \
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( v.h << (32 - (s)))) & UFP_FRLO; \
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v.h = v.h >> (s); \
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} \
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else if ((s) < 64) { \
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v.l = v.h >> ((s) - 32); \
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v.h = 0; \
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} \
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else v.l = v.h = 0; \
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} while (0)
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#define UFP_RSH_K(v,s) do { \
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v.l = ((v.l >> (s)) | \
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(v.h << (32 - (s)))) & UFP_FRLO; \
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v.h = v.h >> (s); \
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} while (0)
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#define UFP_LSH_K(v,s) do { \
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v.h = ((v.h << (s)) | \
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(v.l >> (32 - (s)))) & UFP_FRHI; \
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v.l = (v.l << (s)) & UFP_FRLO; \
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} while (0)
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#define UFP_RSH_KP(v,s) do { \
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v->l = ((v->l >> (s)) | \
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(v->h << (32 - (s)))) & UFP_FRLO; \
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v->h = v->h >> (s); \
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} while (0)
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#define UFP_LSH_KP(v,s) do { \
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v->h = ((v->h << (s)) | \
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(v->l >> (32 - (s)))) & UFP_FRHI; \
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v->l = (v->l << (s)) & UFP_FRLO; \
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} while (0)
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typedef struct {
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uint32 sign;
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int32 exp;
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uint32 h;
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uint32 l;
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} ufp_t;
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extern uint32 *R;
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extern uint32 PSW1;
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extern uint32 CC;
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void fp_unpack (uint32 hi, uint32 lo, ufp_t *dst);
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t_bool fp_clnzro (ufp_t *src, t_bool abnorm);
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uint32 fp_pack (ufp_t *src, uint32 rn, t_bool dbl, t_bool rndtrap);
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uint32 fp_norm (ufp_t *src);
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uint32 fp (uint32 op, uint32 rn, uint32 bva)
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{
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uint32 rh, rl, mh, ml, i, ediff, nsh;
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t_bool s1nz, s2nz;
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t_bool dbl = ((op & 0x20) == 0);
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ufp_t fop1, fop2, t;
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ufp_t res = { 0, 0, 0, 0 };
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uint32 tr;
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if (dbl) { /* double prec? */
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rh = R[rn]; /* get reg operands */
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rl = R[rn|1];
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if ((tr = ReadD (bva, &mh, &ml, VR)) != 0) /* get mem word */
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return tr;
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}
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else { /* single precision */
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rh = R[rn]; /* pad to double */
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rl = 0;
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if ((tr = ReadW (bva, &mh, VR)) != 0)
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return tr;
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ml = 0;
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}
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fp_unpack (rh, rl, &fop1); /* unpack, test */
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fp_unpack (mh, ml, &fop2);
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CC = 0;
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switch (op) { /* case on opcode */
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case OP_FSS: /* subtract */
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case OP_FSL:
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fop2.sign = fop2.sign ^ 1; /* invert mem sign */
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/* fall through */
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case OP_FAS: /* add */
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case OP_FAL:
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s1nz = fp_clnzro (&fop1, TRUE); /* test, clean op1 */
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s2nz = fp_clnzro (&fop2, TRUE);
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if (!s1nz) /* op1 = 0? res = op2 */
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res = fop2;
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else if (!s2nz) /* op2 = 0? res = op1 */
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res = fop1;
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else { /* both non-zero */
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if (fop1.exp < fop2.exp) { /* exp1 < exp2? */
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t = fop2; /* swap operands */
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fop2 = fop1;
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fop1 = t;
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}
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ediff = fop1.exp - fop2.exp; /* exp difference */
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res.sign = fop1.sign; /* result sign, exp */
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res.exp = fop1.exp;
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if (ediff) { /* any difference? */
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UFP_RSH_V (fop2, ediff * 4); /* shift frac */
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if (dbl) { /* double? */
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if ((PSW1 & PSW1_FR) == 0) /* rounding off? */
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fop2.l &= ~0xF; /* no guard */
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}
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else fop2.l = 0; /* single? clr lo */
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}
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if (fop1.sign ^ fop2.sign) { /* eff subtract */
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if (UFP_GE (fop1, fop2)) { /* fop1 >= fop2? */
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UFP_SUB (fop1, fop2, res); /* sub fractions */
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}
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else { /* fop2 > fop1 */
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UFP_SUB (fop2, fop1, res); /* rev subtract */
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res.sign = fop2.sign; /* change signs */
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}
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} /* end subtract */
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else { /* eff add */
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UFP_ADD (fop1, fop2, res); /* add fractions */
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if (res.h & UFP_CARRY) { /* carry out? */
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UFP_RSH_K (res, 4); /* renormalize */
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res.exp = res.exp + 1; /* incr exp */
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}
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} /* end add */
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} /* end nz operands */
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if (!dbl) /* single? clr lo */
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res.l = 0;
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if ((PSW1 & PSW1_FN) == 0) { /* postnormalize? */
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if ((res.h | res.l) == 0) { /* result zero? */
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CC = CC1; /* set signif flag */
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if (PSW1 & PSW1_FS) /* trap enabled? */
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return TR_FLT;
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return fp_pack (&res, rn, dbl, FALSE); /* pack up */
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}
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nsh = fp_norm (&res); /* normalize */
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if ((res.exp < 0) && /* underflow? */
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!(PSW1 & PSW1_FZ) && /* !FN */
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(PSW1 & PSW1_FS) && /* FS */
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(nsh > 2)) { /* shifts > 2? */
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CC = CC1 | (res.sign? CC4: CC3); /* signif CC's */
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return TR_FLT; /* trap */
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} /* end if underflow */
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else if (nsh > 2) { /* shifts > 2? */
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CC |= CC1 | (res.sign? CC4: CC3); /* set CC1 */
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if (PSW1 & PSW1_FS) /* trap enabled? */
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return TR_FLT;
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}
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} /* end if postnorm */
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return fp_pack (&res, rn, dbl, TRUE); /* pack result */
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case OP_FMS:
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case OP_FML: /* floating multiply */
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s1nz = fp_clnzro (&fop1, FALSE); /* test, clean op1 */
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s2nz = fp_clnzro (&fop2, FALSE);
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if (s1nz && s2nz) { /* both non-zero? */
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fp_norm (&fop1); /* prenormalize */
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fp_norm (&fop2);
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UFP_RSH_K (fop2, 4); /* undo guard */
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res.sign = fop1.sign ^ fop2.sign; /* result sign */
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res.exp = fop1.exp + fop2.exp - FP_BIAS; /* result exp */
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if (!dbl) { /* 24b x 24b? */
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for (i = 0; i < 24; i++) { /* 24 iterations */
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if (fop2.h & 1)
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res.h = res.h + fop1.h; /* add hi only */
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UFP_RSH_K (res, 1); /* shift dp res */
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fop2.h = fop2.h >> 1;
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}
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res.l = 0; /* single prec */
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}
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else { /* some low 0's */
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for (i = 0; i < 56; i++) { /* 56 iterations */
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if (fop2.l & 1) {
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UFP_ADD (res, fop1, res);
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}
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UFP_RSH_K (res, 1);
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UFP_RSH_K (fop2, 1);
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}
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}
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fp_norm (&res); /* normalize result */
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}
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return fp_pack (&res, rn, dbl, TRUE); /* pack result */
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case OP_FDS:
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case OP_FDL: /* floating divide */
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s1nz = fp_clnzro (&fop1, FALSE); /* test, clean op1 */
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s2nz = fp_clnzro (&fop2, FALSE);
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if (!s2nz) { /* divide by zero? */
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CC = CC2; /* set CC2 */
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return TR_FLT; /* trap */
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}
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if (s1nz) { /* divd non-zero? */
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fp_norm (&fop1); /* prenormalize */
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fp_norm (&fop2);
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res.sign = fop1.sign ^ fop2.sign; /* result sign */
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res.exp = fop1.exp - fop2.exp + FP_BIAS; /* result exp */
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if (!UFP_GE (fop1, fop2)) {
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UFP_LSH_K (fop1, 4); /* ensure success */
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}
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else res.exp = res.exp + 1; /* incr exponent */
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for (i = 0; i < (uint32)(dbl? 15: 7); i++) {/* 7/15 hex digits */
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UFP_LSH_K (res, 4); /* shift quotient */
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while (UFP_GE (fop1, fop2)) { /* while sub works */
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UFP_SUB (fop1, fop2, fop1); /* decrement */
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res.l = res.l + 1; /* add quo bit */
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}
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UFP_LSH_K (fop1, 4); /* shift divd */
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} /* end hex loop */
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if (!dbl) { /* single? */
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res.h = res.l; /* move quotient */
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res.l = 0;
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}
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fp_norm (&res); /* normalize result */
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}
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return fp_pack (&res, rn, dbl, TRUE); /* pack result */
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} /* end case */
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return SCPE_IERR;
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}
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void ShiftF (uint32 rn, uint32 stype, uint32 sc)
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{
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uint32 opnd, opnd1;
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ufp_t src;
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opnd = R[rn]; /* get operands */
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opnd1 = stype? R[rn|1]: 0; /* zextend single */
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fp_unpack (opnd, opnd1, &src); /* unpack */
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CC = 0;
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if (sc & SCSIGN) { /* right? */
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sc = SHF_M_SC + 1 - sc;
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while (sc > 0) { /* while count */
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UFP_RSH_K (src, 4); /* shift right hex */
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if (stype) /* zero guard */
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src.l &= ~0xF;
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else src.h &= ~0xF;
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src.exp++; /* incr exp */
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sc--;
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if (src.exp > FP_M_EXP) { /* overflow? */
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CC |= CC2; /* set CC2, stop */
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break;
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}
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} /* end while */
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if ((src.h | src.l) == 0) { /* result 0? */
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if (stype) /* result is true 0 */
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R[rn|1] = 0;
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R[rn] = 0;
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CC = 0;
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return;
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}
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}
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else { /* left */
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if ((src.h | src.l) == 0) { /* fraction 0? */
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if (stype) /* result is true 0 */
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R[rn|1] = 0;
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R[rn] = 0;
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CC = CC1;
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return;
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}
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while ((sc > 0) && ((src.h & UFP_NORM) == 0)) { /* while count & !norm */
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UFP_LSH_K (src, 4); /* hex shift left */
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src.exp--; /* decr exp */
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sc--;
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if (src.exp < 0) { /* underflow? */
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CC |= CC2; /* set CC2, stop */
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break;
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}
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} /* end while */
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if (src.h & UFP_NORM) /* normalized? */
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CC |= CC1; /* set CC1 */
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}
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fp_pack (&src, rn, stype, FALSE); /* pack result */
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return;
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}
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void fp_unpack (uint32 hi, uint32 lo, ufp_t *dst)
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{
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dst->sign = FP_GETSIGN (hi); /* get sign */
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if (dst->sign) /* negative? */
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NEG_D (hi, lo); /* 2's compl */
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dst->h = FP_GETFRHI (hi); /* get fraction */
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dst->l = FP_GETFRLO (lo);
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dst->exp = FP_GETEXP (hi); /* get exp */
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UFP_LSH_KP (dst, 4); /* guard result */
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return;
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}
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/* Test for and clean a floating point zero
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abnorm defines whether to allow "abnormal" zeros */
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t_bool fp_clnzro (ufp_t *src, t_bool abnorm)
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{
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if (((src->h | src->l) == 0) && /* frac zero and */
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(!abnorm || (src->exp == 0))) { /* exp zero or !ab */
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src->sign = 0; /* true zero */
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src->exp = 0;
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return FALSE;
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}
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return TRUE; /* non-zero */
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}
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uint32 fp_pack (ufp_t *src, uint32 rn, t_bool dbl, t_bool rndtrap)
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{
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static ufp_t fp_zero = { 0, 0, 0, 0};
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uint32 opnd, opnd1;
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if (src->h || (dbl && src->l)) { /* result != 0? */
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CC |= (src->sign? CC4: CC3); /* set CC's */
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if (rndtrap) { /* round, trap? */
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if (PSW1 & PSW1_FR) { /* round? */
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if (dbl) { /* double prec? */
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src->l = (src->l + 0x8) & UFP_FRLO;
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src->h = src->h + (src->l < 0x8);
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}
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else src->h = src->h + 0x8; /* no, single */
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if (src->h & UFP_CARRY) { /* carry out? */
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UFP_RSH_KP (src, 4); /* renormalize */
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src->exp = src->exp + 1;
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}
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} /* end if round */
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if (src->exp > FP_M_EXP) { /* overflow? */
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CC |= CC2; /* flag */
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return TR_FLT;
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}
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else if (src->exp < 0) { /* underflow? */
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if (PSW1 & PSW1_FZ) { /* trap enabled? */
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CC |= CC1 | CC2; /* flag */
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return TR_FLT;
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}
|
|
*src = fp_zero; /* result 0 */
|
|
CC = CC1|CC2; /* special CC's */
|
|
}
|
|
} /* end rnd trap */
|
|
UFP_RSH_KP (src, 4); /* remove guard */
|
|
if (!dbl) /* single? lose lower */
|
|
src->l = 0;
|
|
if ((src->h | src->l) == 0) /* result now 0? */
|
|
src->exp = src->sign = 0;
|
|
}
|
|
else *src = fp_zero;
|
|
opnd = ((src->exp & FP_M_EXP) << FP_V_EXP) | /* repack */
|
|
((src->h & FP_M_FRHI) << FP_V_FRHI);
|
|
opnd1 = src->l & FP_M_FRLO;
|
|
if (src->sign) /* negative? */
|
|
NEG_D (opnd, opnd1);
|
|
R[rn] = opnd; /* store result */
|
|
if (dbl && ((rn & 1) == 0))
|
|
R[rn|1] = opnd1;
|
|
return 0;
|
|
}
|
|
|
|
uint32 fp_norm (ufp_t *src)
|
|
{
|
|
uint32 nsh;
|
|
|
|
nsh = 0;
|
|
src->h &= UFP_FRHI;
|
|
if (src->h || src->l) { /* if non-zero */
|
|
while ((src->h & UFP_NORM) == 0) { /* until normalized */
|
|
UFP_LSH_KP (src, 4); /* hex shift left */
|
|
src->exp--; /* decr exponent */
|
|
nsh++; /* count shifts */
|
|
}
|
|
}
|
|
return nsh;
|
|
}
|
|
|