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simh.simh/Altair8800/s100_bus.h
Patrick Linstruth aad5351080 Altair8800: New Simulator 
This is the initial release of the Altair8800 simulator.

Why another Altair simulator? AltairZ80 has been described as a
“software simulator”, where the intent is to run software designed
specifically for executing under a simulator. Altair8800 is intended
to accurately simulate the Altair hardware and execute software
that will run unchanged on real hardware. Software and disk images
can be moved between the Altair8800 simulator and real Altair and
other S-100 hardware without any changes. The Altair8800 simulator
is a tool that can assist with the restoration of vintage Altair
and other S-100 hardware and software along with the development
of new hardware and software. The accomplish this, the following
are major differences between AltairZ80 and Altair8800.

* The monolithic design where devices access other devices directly
through external variables and functions is no longer supported.
All devices exchange data through a new BUS device. Memory and I/O
address decoding and transfers are now handled by the BUS device.
All interrupt requests are handled by the BUS device.

* System RAM was moved from the CPU device to a new RAM device and
managed by the BUS device.

* Banked RAM was moved from the CPU device to a new BRAM device.

* Banked RAM can only be accessed through the BUS device. Memory in
banks that are not currently selected cannot be accessed. The AZ80
“banked” RAM was removed.

* ROMs were moved from the CPU and DSK devices to the new ROM device.
Mike Douglas’ Altmon Monitor is also available through the ROM
device. The custom AltairZ80 ALTAIRROM, which is not compatible
with original Altair disk images, is also available.

* The custom ALTAIRROM boot loader was replaced with the original
MITS Disk Boot Loader as the default ROM.

* The monolithic Multiple-CPU/RAM/ROM/IO/BankedRAM CPU device has
been replaced with a generic CPU device that provides an abstraction
layer between SIMH and the supported CPU architectures (currently
8080 and Z80). All IO is handled through the BUS device. RAM, Banked
RAM, and ROM are each handled by their own independent devices.

* The AltairZ80 SIO device was replaced with the M2SIO0 and M2SIO1
devices. The M2SIO devices fully support TMXR.

* A new SIO device was added to provide generic, programmable, Serial
IO. TMXR is not supported on this device.

* The Altair 8800 did not have PTR or PTP hardware devices. They have
been removed and replaced with the M2SIO1 device. PTR and PTP devices
are defined by software executing on the simulator.

* Contention between multiple enabled serial devices checking the
single host keyboard for input is now handled by the BUS device.
Port 0xFF sense switches was moved to a new SSW device and IMSAI
programmed output was moved to a new PO device.

* The SIMH pseudo device no longer uses the removed PTR and PTP
devices. The SIMH device has its own IO system. To avoid conflicts
with other devices and remain compatible with the R and W utilities
written for AltairZ80, SIMH “borrows” I/O ports 12H and 13H during
file transfers. Only SIMH commands needed to support R and W file
transfers are supported. All other SIMH commands were removed.

* AltairZ80-specific versions of CP/M are not supported by Altair8800.

* PC queue was removed from CPU device and replaced with CPU HISTORY.

* The Altair8800 simulator only supports 16-bit address and 8-bit
data buses. 8086 and 68K CPU architectures were removed.

* All CPU timing (clockFrequency) and “sleeps” (SIO SLEEP) have been
removed. SIMH THROTTLE is fully supported and is the recommended
way to manage simulator speed and host CPU utilization. Executing
“SET THROTTLE 100K/1”, for example, should provide ample speed
without tasking the host CPU.

* HEXLOAD and HEXSAVE commands were added. The LOAD “-h” option has
been removed. Intel Hex and sRecord (coming soon) formats are
supported.

* The WD179X device was converted to an API.

* A new DSK API was added to provide a consistent way to manage soft
sector raw disk images.

* Support for the proprietary IMD disk image format was removed. Only
RAW disk images are supported.

The following devices are supported by this initial release:

BUS - Altair (S-100) Bus
CPU - Intel 8080 / Zilog Z80
RAM - 64K RAM
ROM - ROMs
BRAM - Banked RAM
DSK - MITS 88-DCDD Floppy Disk Controller
M2SIO0 - MITS 88-2SIO Port 0
M2SIO1 - MITS 88-2SIO Port 1
SSW - Sense Switches
PO - Programmed Output
SIO - Generic Serial I/O
SBC200 - SD Systems SBC-200
TARBELL - Tarbell SD and DD Floppy Disk Controller
VFII - SD Systems VersaFloppy II
SIMH - SIMH Pseudo Device
2025-11-21 17:01:40 -05:00

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/* s100_bus.h
Copyright (c) 2025 Patrick A. Linstruth
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
PETER SCHORN BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Patrick Linstruth shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Patrick Linstruth.
History:
11/07/25 Initial version
*/
#ifndef _SIM_BUS_H
#define _SIM_BUS_H
#include "sim_defs.h"
#include "sim_tmxr.h"
#define UNIT_BUS_V_VERBOSE (UNIT_V_UF+0) /* warn if ROM is written to */
#define UNIT_BUS_VERBOSE (1 << UNIT_BUS_V_VERBOSE)
/* S100 Bus Architecture */
#define ADDRWIDTH 16
#define DATAWIDTH 8
#define ADDRRADIX 16
#define DATARADIX 16
#define MAXADDR (1 << ADDRWIDTH)
#define MAXDATA (1 << DATAWIDTH)
#define ADDRMASK (MAXADDR - 1)
#define DATAMASK (MAXDATA - 1)
#define LOG2PAGESIZE 8
#define PAGESIZE (1 << LOG2PAGESIZE)
#define MAXMEMORY MAXADDR
#define MAXBANKSIZE MAXADDR
#define MAXPAGE (MAXADDR >> LOG2PAGESIZE)
#define PAGEMASK (MAXPAGE - 1)
#define MAXBANK 16
#define MAXBANKS2LOG 5
#define ADDRESS_FORMAT "[0x%08x]"
/* This is the I/O configuration table. There are 255 possible
device addresses, if a device is plugged to a port it's routine
address is here, 'nulldev' means no device is available
*/
#define S100_IO_READ 0
#define S100_IO_WRITE 1
/* Interrupt Vectors */
#define MAX_INT_VECTORS 32 /* maximum number of interrupt vectors */
extern uint32 nmiInterrupt; /* NMI */
extern uint32 vectorInterrupt; /* Vector Interrupt bits */
extern uint8 dataBus[MAX_INT_VECTORS]; /* Data bus value */
/*
* Generic device resource information. Pointed to by DEVICE *up7
*/
typedef struct {
uint32 io_base; /* I/O Base Address */
uint32 io_size; /* I/O Address Space requirement */
uint32 mem_base; /* Memory Base Address */
uint32 mem_size; /* Memory Address space requirement */
TMXR *tmxr; /* TMXR pointer */
} RES;
/* data structure for IN/OUT instructions */
typedef struct idev {
int32 (*routine)(CONST int32 addr, CONST int32 rw, CONST int32 data);
CONST char *name;
} IDEV;
typedef struct { /* Structure to describe memory device address space */
int32 (*routine)(CONST int32 addr, CONST int32 rw, CONST int32 data);
CONST char *name; /* name of handler routine */
} MDEV;
extern t_stat s100_bus_addio(int32 port, int32 size, int32 (*routine)(CONST int32, CONST int32, CONST int32), CONST char* name);
extern t_stat s100_bus_addio_in(int32 port, int32 size, int32 (*routine)(CONST int32, CONST int32, CONST int32), CONST char* name);
extern t_stat s100_bus_addio_out(int32 port, int32 size, int32 (*routine)(CONST int32, CONST int32, CONST int32), CONST char* name);
extern t_stat s100_bus_remio(int32 port, int32 size, int32 (*routine)(CONST int32, CONST int32, CONST int32));
extern t_stat s100_bus_remio_in(int32 port, int32 size, int32 (*routine)(CONST int32, CONST int32, CONST int32));
extern t_stat s100_bus_remio_out(int32 port, int32 size, int32 (*routine)(CONST int32, CONST int32, CONST int32));
extern t_stat s100_bus_addmem(int32 baseaddr, uint32 size,
int32 (*routine)(CONST int32 addr, CONST int32 rw, CONST int32 data), CONST char *name);
extern t_stat s100_bus_remmem(int32 baseaddr, uint32 size,
int32 (*routine)(CONST int32 addr, CONST int32 rw, CONST int32 data));
extern t_stat s100_bus_setmem_dflt(int32 (*routine)(CONST int32 addr, CONST int32 rw, CONST int32 data), CONST char *name);
extern t_stat s100_bus_remmem_dflt(int32 (*routine)(CONST int32 addr, CONST int32 rw, CONST int32 data));
extern void s100_bus_get_idev(int32 port, IDEV *idev_in, IDEV *idev_out);
extern void s100_bus_get_mdev(int32 addr, MDEV *mdev);
extern int32 nulldev(CONST int32 addr, CONST int32 io, CONST int32 data);
extern uint32 s100_bus_set_addr(uint32 pc);
extern uint32 s100_bus_get_addr(void);
extern t_stat s100_bus_console(UNIT *uptr);
extern UNIT *s100_bus_get_console(void);
extern t_stat s100_bus_noconsole(UNIT *uptr);
extern t_stat s100_bus_poll_kbd(UNIT *uptr);
extern int32 s100_bus_in(int32 port);
extern void s100_bus_out(int32 port, int32 data);
extern int32 s100_bus_memr(t_addr addr);
extern void s100_bus_memw(t_addr addr, int32 data);
extern uint32 s100_bus_int(int32 vector, int32 data);
extern uint32 s100_bus_get_int(void);
extern uint32 s100_bus_get_int_data(int32 vector);
extern uint32 s100_bus_clr_int(int32 vector);
extern void s100_bus_nmi(void);
extern int32 s100_bus_get_nmi(void);
extern void s100_bus_clr_nmi(void);
#define S100_BUS_MEMR 0x01
#define S100_BUS_MEMW 0x02
#define S100_BUS_IN 0x04
#define S100_BUS_OUT 0x08
#define RESOURCE_TYPE_MEMORY (S100_BUS_MEMR | S100_BUS_MEMW)
#define RESOURCE_TYPE_IO (S100_BUS_IN | S100_BUS_OUT)
#define sim_map_resource(a,b,c,d,e,f) s100_map_resource(a,b,c,d,e,f)
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern t_stat set_membase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_membase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern void cpu_raise_interrupt(uint32 irq);
#endif
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