# configure tb_arty_dram with sys_tst_mig_arty target;
# use vhdl configure file (tb_tst_mig_arty.vhd) to allow
# that all configurations will co-exist in work library
# configure
arty_dram_aif = ../sys_tst_mig_arty.vbom
sys_conf = sys_conf_sim.vhd
# design
../../../../bplib/arty/tb/tb_arty_dram.vbom
tb_tst_mig_arty.vhd
