## $Id: sys_w11a_n2.ucf_cpp 540 2013-10-13 18:42:50Z mueller $
##
## Revision History: 
## Date         Rev Version  Comment
## 2013-10-13   540   1.1    add pad->clk constraints
## 2013-04-20   509   1.1    add fx2 support
## 2010-11-06   336   1.0.1  rename input pin CLK -> I_CLK50
## 2010-05-26   295   1.0    Initial version
##

NET "I_CLK50" TNM_NET = "I_CLK50";
TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %;
OFFSET =  IN 10 ns BEFORE "I_CLK50";
OFFSET = OUT 20 ns  AFTER "I_CLK50";

## constrain pad->net clock delay
NET CLK TNM = TNM_CLK;
TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK50) TO TNM_CLK 10 ns;
NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK;
TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns;

## std board
##
#include "bplib/nexys2/nexys2_pins.ucf"
##
## Pmod B0 - RS232 
##
#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf"
##
## Cypress FX2
##
#include "bplib/nexys2/nexys2_pins_fx2.ucf"
#include "bplib/nexys2/nexys2_time_fx2_ic.ucf"
