# libs
../../../vlib/slvtypes.vhd
../../../vlib/cdclib/cdclib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/rbus/rblib.vhd
../../../vlib/rbus/rbdlib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/sysmon/sysmonrbuslib.vbom
../../../bplib/s3board/s3boardlib.vbom
../../../bplib/mig/miglib.vbom
../../../bplib/nexys4d/miglib_nexys4d.vbom
${sys_conf := sys_conf.vhd}
# components
../../../bplib/bpgen/s7_cmt_1ce1ce2c.vbom
../../../vlib/cdclib/cdc_signal_s1_as.vbom
../../../bplib/bpgen/bp_rs232_4line_iob.vbom
../../../bplib/bpgen/sn_humanio.vbom
../../../vlib/rlink/rlink_sp2c.vbom
../tst_sram.vbom
../../../bplib/nexys4d/sramif_mig_nexys4d.vbom
../../../bplib/sysmon/sysmonx_rbus_base.vbom
../../../vlib/rbus/rbd_usracc.vbom
../../../vlib/rbus/rb_sres_or_3.vbom
# design
sys_tst_sram_n4d.vhd
@xdc:../../../bplib/nexys4d/nexys4d_pclk.xdc
@xdc:../../../bplib/nexys4d/nexys4d_pins.xdc
