## $Id: sys_tst_serloop2_n2.ucf_cpp 441 2011-12-20 17:01:16Z mueller $
##
## Revision History: 
## Date         Rev Version  Comment
## 2011-12-16   439   1.0.1  set maxdelay clk-clks to 12 ns
## 2011-09-17   410   1.0    Initial version
##

NET "I_CLK50" TNM_NET = "I_CLK50";
TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %;
OFFSET =  IN 10 ns BEFORE "I_CLK50";
OFFSET = OUT 20 ns  AFTER "I_CLK50";

## rules to prevent default 'cross clock' constraints for the dcm generated
## clocks CLK(100 MHz) and CLKS(60 MHz). All essential domain crossing done 
## via fifo's or dedicated capture/synch flops.

NET "CLK"   TNM_NET = "CLK";
NET "CLKS"  TNM_NET = "CLKS";
TIMESPEC "TS_CDC_CLK_CLKS" = FROM "CLK"  TO "CLKS" 12 ns;
TIMESPEC "TS_CDC_CLKS_CLK" = FROM "CLKS" TO "CLK"  12 ns;

## rule to allow that two DCMs are driven by one clock pin.
NET "I_CLK50" CLOCK_DEDICATED_ROUTE = FALSE;

## std board
##
#include "bplib/nexys2/nexys2_pins.ucf"
##
## Pmod B0 - RS232 
##
#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf"
