# $Id: sys_tst_sram_c7.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
#   Date          rev   viv   
#   2019-02-02   1108   2017.2
#   2019-02-02   1108   2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210]                                         # generic
{:}

# false_path -hold ignored by synth ----------------------------
I [Designutils 20-1567]                                         # generic

# port driven by constant --------------------------------------
i [Synth 8-3917] O_RGBLED0_N[\d]                                # OK 2017-06-11

# tying undriven pin to constant -------------------------------
# upper 8 LEDs unused                                           # OK 2017-06-11
i [Synth 8-3295] HIO:LED[\d*]
# only few LAMs used                                            # OK 2017-06-11
i [Synth 8-3295] RLINK:RB_LAM[\d*]

# unconnected ports --------------------------------------------
I [Synth 8-3331] RB_MREQ                                        # generic
# --> I_BTN not used                                            # OK 2017-06-11
i [Synth 8-3331] I_BTN[\d]
# --> MEM_ACK_W not used by current tst_sram                    # OK 2017-06-11
i [Synth 8-3331] tst_sram.*MEM_ACK_W
# --> rlink_sp2c doesn't use CE_USEC and CE_MSEC                # OK 2017-06-11
i [Synth 8-3331] rlink_sp2c.*CE_(USEC|MSEC)

# sequential element removed (2017.1 nonsense) -----------------
I [Synth 8-6014] _reg                                           # generic

# unused sequential element ------------------------------------
{2017.2:2018.2}
I [Synth 8-3332] R_LREGS_reg[attn][\d*]                         # generic
# --> many HIO pins not used                                    # OK 2017-06-11
i [Synth 8-3332] HIO/R_REGS_reg[led][\d*]
i [Synth 8-3332] HIO/R_REGS_reg[dsp_dp][\d*]
i [Synth 8-3332] HIO/R_REGS_reg[dsp_dat][\d*]
# --> monitor outputs moneop,monattn currently not used         # OK 2017-06-11
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn]
# --> only RB_STAT 0,1 used by tst_sram                         # OK 2017-06-11
i [Synth 8-3332] RLINK/CORE/RL/R_BREGS_reg[stat][(2|3)]
# --> CE_USEC isn't used (also not in rlink_sp2c)               # OK 2018-12-29
i [Synth 8-3332] GEN_CLKALL/DIV_CLK0/R_REGS_reg[usec]
# --> CES_USEC isn't used                                       # OK 2018-12-29
i [Synth 8-3332] GEN_CLKALL/DIV_CLK1/R_REGS_reg[usec]

{:}

# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]
I [Vivado 12-2489]                                # multiple of 1 ps
I [Physopt 32-742]                                # BRAM Flop Optimization
