# $Id: sys_tst_serloop_s3.imfset 1108 2019-02-02 23:04:38Z mueller $
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[xst]
Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'SIZE' of component 'fifo_1c_dram'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'

Input <BTN<3:2>> is never used
Input <BTN<0>> is never used
Input <SWI<3>> is never used
Input <SWI<0>> is never used
Input <SER_MONI\..*> is never used.
Input <HIO_CNTL.enaftdi> is never used

Signal <RXFIFO_SIZE<2:0>> is assigned but never used
Signal <CE_USEC> is assigned but never used

Node <HIOMAP/R_REGS.enaftdi> of sequential type is unconnected
Node <CLKDIV/R_REGS.usec> of sequential type is unconnected in
Node <HIO/HIO/IOB_BTN/R_DI_\d> of sequential type is unconnected
Node <HIO/HIO/IOB_SWI/R_DI_\d> of sequential type is unconnected
Node <HIO/HIO/DEB.DEB_SWI/R_REGS.dout_\d> of sequential type is unconnected
Node <HIO/HIO/DEB.DEB_BTN/R_REGS.dout_\d> of sequential type is unconnected
Node <HIO/HIO/DEB.DEB_SWI/R_REGS.dchange_\d> of sequential type is unconnected
Node <HIO/HIO/DEB.DEB_BTN/R_REGS.dchange_\d> of sequential type is unconnected
Node <HIO/HIO/DEB.DEB_SWI/R_REGS.dref_\d> of sequential type is unconnected
Node <HIO/HIO/DEB.DEB_BTN/R_REGS.dref_\d> of sequential type is unconnected
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[tra]

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[map]
INFO:.*
WARNING:LIT:162 .* Proper phase relationship

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[par]
The signal I_SWI<3>_IBUF has no load
The signal I_BTN<2>_IBUF has no load
The signal I_BTN<3>_IBUF has no load
There are \d+ loadless signals in this design

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[bgn]
INFO:PhysDesignRules:772 .* To achieve optimal frequency synthesis performance
