# $Id: sys_w11a_n2.imfset 1150 2019-05-19 17:52:54Z mueller $
#
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[xst]
INFO:.*Mux is complete : default of case is discarded
INFO:.*You can improve the performance of the multiplier
INFO:Xst:2679 .* The register is replaced by logic.
INFO:Xst:2117 .* was re-encoded using one-hot encoding
INFO:Xst:1767 .* can share the same physical resources
INFO:Xst:3029 .* LUT implementation is currently selected
INFO:Xst:2261 .* FF/Latch .* is equivalent to the following

Node <HIO/R_REGS.btneff_\d*> of sequential type is unconnected
Node <HIO/R_REGS.btn_\d*> of sequential type is unconnected
Node <RLINK/FX2CNTL/RXFIFO/R_REGR.sizer_\d> of sequential type is unconnected
Node <RLINK/FX2CNTL/RXFIFO/R_REGW.sizew_\d> of sequential type is unconnected
Node <RLINK/FX2CNTL/TXFIFO/R_REGR.sizer_\d> of sequential type is unconnected
Node <RLINK/FX2CNTL/TXFIFO/R_REGW.sizew_\d> of sequential type is unconnected
Node <RLINK/FX2CNTL/R_MONI_S.*> of sequential type is unconnected
Node <RLINK/FX2CNTL/R_MONI_C.*> of sequential type is unconnected
Node <RLINK/CORE/RL/R_LREGS.monattn> of sequential type is unconnected
Node <RLINK/CORE/RL/R_LREGS.moneop> of sequential type is unconnected
Node <RLINK/SERPORT/XONRX/R_REGS.rxovr> of sequential type is unconnected

Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'RL_MONI' of component 'rlink_sp1c_fx2'
Unconnected output port 'ACK_W' of component 'nx_cram_memctl_as'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Unconnected output port 'DOA' of component 'ram_2swsr_rfirst_gen'
Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen'
Unconnected output port 'BUSY' of component 'fifo_1c_dram'
Unconnected output port 'SIZE' of component 'fifo_1c_dram'
Unconnected output port 'ESUSP_O' of component 'pdp11_core'
Unconnected output port 'DONE' of component 'ib_rlim_slv'

Input <RESET> is never used
Input <CE_MSEC> is never used
Input <DM_STAT_.*> is never used
Input <CP_STAT\..*> is never used
Input <RB_MREQ\..*> is never used
Input <RB_SRES\..*> is never used
Input <IB_MREQ\..*> is never used
Input <SER_MONI\..*> is never used
Input <RLB_MONI\..*> is never used

Input <CCIN<2:1>> is never used
Input <EI_ACK> is never used
Input <IREG<\d*:\d*>> is never used
Input <MONI.idone> is never used
Input <MONI.trace_prev> is never used
Input <DIN<\d*:\d*>> is never used
Input <I_MEM_WAIT> is never used
Input <CNTL.trap_done> is never used
Input <VADDR<\d*:\d*>> is never used
Input <CE_USEC> is never used

Signal <TXSIZE_FX2> is assigned but never used
Signal <EI_ACK<\d*:\d*>> is assigned but never used

Signal <R_VMSTAT\.trap_ysv> is assigned but never used
Signal <R_VMSTAT\.trap_mmu> is assigned but never used
Signal <R_VMSTAT\.ack> is assigned but never used
Signal <R_IDSTAT\.is_res> is assigned but never used
Signal <R_IDSTAT\.fork_srcr> is assigned but never used
Signal <R_IDSTAT\.fork_op> is assigned but never used
Signal <R_IDSTAT\.force_srcsp> is assigned but never used
Signal <R_IDSTAT\.do_pref_dec> is assigned but never used
Signal <R_IDSTAT\.do_fork_srcr> is assigned but never used
Signal <R_IDSTAT\.do_fork_opg> is assigned but never used
Signal <R_IDSTAT\.do_fork_op> is assigned but never used
Signal <R_IDSTAT\.do_fork_dsta> is assigned but never used
Signal <RXFIFO_BUSY> is assigned but never used
Signal <FX2_FLAG_N<3>> is assigned but never used
Signal <RXFIFO_SIZE<2:0>> is assigned but never used
Signal <FX2_TXAFULL> is assigned but never used
Signal <FX2_RXAEMPTY> is assigned but never used

Signal <VM_CNTL_L\..*> is assigned but never used
Signal <FX2_MONI\..*> is assigned but never used
Signal <BTN> is assigned but never used
Signal <R_REGS.crdone> is assigned but never used

# IIST signals
Signal <IB_SRES_IIST\..*> is used but never assigned
Signal <EI_REQ_IIST> is used but never assigned
Signal <EI_ACK_IIST> is assigned but never used

FF/Latch <R_REGS.escseen> has a constant value of 0
FF/Latch <R_REGS.escpend> has a constant value of 0
FF/Latch <R_STATUS.suspext> has a constant value of 0
FF/Latch <R_REGS.dtyp_3> has a constant value of 0

FF/Latch <RLINK/FX2CNTL/RXFIFO/R_REGR.rstr> has a constant value of 0
FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGW.rstw> has a constant value of 0
FF/Latch <RLINK/FX2CNTL/RXFIFO/R_REGR.rstr_sc> has a constant value of 0
FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGW.rstr_c> has a constant value of 0
FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGW.rstw_sc> has a constant value of 0

FF/Latch <SYS70/W11A/SEQ/R_IDSTAT.res_sel_2> has a constant value of 0
FF/Latch <SYS70/W11A/SEQ/R_STATUS.intvect_8> has a constant value of 0
FF/Latch <CRAMCTL/IOB_MEM_ADDRH/R_DO_21> has a constant value of 0
FF/Latch <CRAMCTL/IOB_MEM_ADDRH/R_DO_20> has a constant value of 0
FF/Latch <CRAMCTL/R_REGS.cntdly_2> has a constant value of 0
FF/Latch <R_SSR0.inst_compl> has a constant value of 0
FF/Latch <RLINK/CORE/RL/R_LREGS\.attn_.*> has a constant value of 0 
FF/Latch <SYS70/DMPCNT.I0/R_REGS\.psig_\d*> has a constant value of 0
FF/Latch <SYS70/DMPCNT.I0/PRE\[\d*\]\.ENA.CNT/R_CNT_\d*> has a constant value

WARNING:Xst:38 - Value "one_hot" of property "fsm_encoding" not applicable
WARNING:Xst:38 - Value "none" of property "fsm_encoding" not applicable.
WARNING:Xst:1896 - Due to other FF/Latch trimming

WARNING:Xst:790 .*ibus/ib_intmap24.vhd.*does not match array range

#
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[tra]
INFO:.*TNM.*used in period specification.*was traced into DCM_SP

#
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[map]
The signal <I_MEM_WAIT_IBUF> is incomplete
Logical network I_MEM_WAIT_IBUF has no load
Signal I_FX2_FLAG<3> connected to .* I_FX2_FLAG<3> has been removed
There is a dangling output parity pin
WARNING:Pack:266
WARNING:PhysDesignRules:1060
INFO:.*
#
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[par]
The signal I_MEM_WAIT_IBUF has no load
There are 1 loadless signals in this design
WARNING:Place:1019
#
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[bgn]
Spartan-3 1200E and 1600E devices do not support bitstream
The signal <I_MEM_WAIT_IBUF> is incomplete
There is a dangling output parity pin
INFO:.*To achieve optimal frequency synthesis performance
WARNING:PhysDesignRules:1060