# Not meant for direct top level usage. Used with 
# tb_nexys4_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/xlib/xlib.vhd
../nexys4lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
../../../vlib/xlib/sfs_gsim_core.vbom
tb_nexys4_core.vbom
../../../vlib/simlib/simbididly.vbom
../../micron/mt45w8mw16b.vbom
../../../vlib/serport/tb/serport_master_tb.vbom
${nexys4_cram_aif := nexys4_cram_dummy.vbom}  -UUT
# design
tb_nexys4_cram.vhd
@top:tb_nexys4_cram
