## $Id: sys_w11a_n3.ucf_cpp 540 2013-10-13 18:42:50Z mueller $
##
## Revision History: 
## Date         Rev Version  Comment
## 2013-10-13   540   1.1    add pad->clk and fx2 cdc constraints
## 2013-04-21   509   1.1    add fx2 support
## 2011-11-20   430   1.0    Initial version
##

NET "I_CLK100" TNM_NET = "I_CLK100";
TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
OFFSET =  IN 10 ns BEFORE "I_CLK100";
OFFSET = OUT 20 ns  AFTER "I_CLK100";

## constrain pad->net clock delay
NET CLK TNM = TNM_CLK;
TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK100) TO TNM_CLK 10 ns;
NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK;
TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns;

## FX2 controller specific constraints
##   constrain cdc path in fifos and reset 
TIMESPEC TS_CDC_FIFO = 
   FROM FFS(*FIFO/GC?/GRAY_*.CNT/R_DATA*)
   TO   FFS(*FIFO/R_REG?_?addr_c*)
   5 ns DATAPATHONLY;

## std board
##
#include "bplib/nexys3/nexys3_pins.ucf"
##
## Pmod B0 - RS232
##
#include "bplib/nexys3/nexys3_pins_pmb0_rs232.ucf"
##
## Cypress FX2
##
#include "bplib/nexys3/nexys3_pins_fx2.ucf"
#include "bplib/nexys3/nexys3_time_fx2_ic.ucf"
