# $Id: sys_w11a_n4d.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
#   Date          rev   viv   
#   2019-02-02   1108   2017.2
#   2019-02-02   1108   2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210]                                         # generic
{:}

# binding instance .. which has no pins ------------------------
I [Synth 8-115]                                                 # generic

# false_path -hold ignored by synth ----------------------------
I [Designutils 20-1567]

# port driven by constant --------------------------------------
# --> RGBLED0 currently unused                                  # OK 2019-01-02
i [Synth 8-3917] O_RGBLED0[\d]

# unconnected ports --------------------------------------------
I [Synth 8-3331] IB_MREQ                                        # generic
I [Synth 8-3331] RB_MREQ                                        # generic
I [Synth 8-3331] DM_STAT_CO                                     # generic
I [Synth 8-3331] DM_STAT_DP                                     # generic
I [Synth 8-3331] DM_STAT_EXP                                    # generic
I [Synth 8-3331] DM_STAT_SE                                     # generic
I [Synth 8-3331] DM_STAT_VM                                     # generic
I [Synth 8-3331] CP_STAT                                        # generic
I [Synth 8-3331] SER_MONI                                       # generic
# --> ireg indeed not fully used                                # OK 2019-01-02
i [Synth 8-3331] pdp11_sequencer .* IREG[1(1|2|3|4)]
# --> ccin indedd not fully used                                # OK 2019-01-02
i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)]
# --> some psr bits are used                                    # OK 2019-01-02
i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used                                  # OK 2019-01-02
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr           # OK 2019-01-02
i [Synth 8-3331] pdp11_mmu .* CNTL[trap_done]
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse                    # OK 2019-01-02
i [Synth 8-3331] rlink_sp2c .* (CE_USEC|CE_MSEC)
# --> msec indeed not used                                      # OK 2019-01-02
i [Synth 8-3331] ibdr_rl11 .* CE_MSEC
# --> ei_ack not used, interrupt request cleared via register   # OK 2019-01-02
i [Synth 8-3331] ibdr_deuna .* EI_ACK
i [Synth 8-3331] ibd_iist .* EI_ACK
# --> data end marker not used                                  # OK 2019-01-02
i [Synth 8-3331] sramif2migui_core .*APP_RD_DATA_END

# sequential element removed (2017.1 nonsense) -----------------
I [Synth 8-6014] _reg                                           # generic

# unused sequential element ------------------------------------
{2017.2:2018.2}
I [Synth 8-3332] R_LREGS_reg[attn][\d*]                         # generic
I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*]               # generic
# --> not yet used                                              # OK 2019-01-02
i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_sequencer
# --> indeed no types with [3] set                              # OK 2019-01-02
i [Synth 8-3332] R_REGS_reg[dtyp][3].* ibdr_rhrp
# --> not yet used                                              # OK 2019-01-02
i [Synth 8-3332] R_REGS_reg[req_lock].* ibd_iist
i [Synth 8-3332] R_REGS_reg[req_boot].* ibd_iist
# --> [8] is for DZ11TX, not yet available                      # OK 2019-01-02
# --> [9] is for DZ11RX, unclear why this one isn't removed too !!
i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_sequencer
# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2019-01-02
i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer
# --> inst_compl logic disabled in pdp11_mmu                    # OK 2019-01-02
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox

{:}

# INFO: encoded FSM with state register as --------------------
# test for sys_w11a_n4 that all FSMs are one_hot
r [Synth 8-3354] R_BREGS_reg[state.*'one-hot'.*'rlink_core'
r [Synth 8-3354] R_LREGS_reg[state].*'one-hot'.*'rlink_core'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_autobaud'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_rx'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_core_rbus'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_vmbox'
r [Synth 8-3354] R_STATE_reg.*'one-hot'.*'pdp11_sequencer'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_cache'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rhrp'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rl11'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'sysmon_rbus_core'

# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]
I [Vivado 12-2489]                                # multiple of 1 ps
I [Physopt 32-742]                                # BRAM Flop Optimization
{:2017.2}
# --> spurious Invalid VCCINTIO messages                        # OK 2018-12-28
i [Designutils 20-266] Invalid Voltage Source VCCINTIO

# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[bit]
# see https://www.xilinx.com/support/answers/64180.html         # OK 2018-12-28
i [DRC REQP-1709] PLLE2_ADV
# --> DSP multiplier is not pipelined, ok                       # OK 2019-01-02
i [DRC DPOP-1] PREG Output pipelining
i [DRC DPOP-2] MREG Output pipelining
