From 0269006dc86be0ddf0f88e0a1c0930d40837a112 Mon Sep 17 00:00:00 2001 From: wfjm Date: Sun, 11 Aug 2019 09:50:44 +0200 Subject: [PATCH] docu updates [skip ci] --- doc/CHANGELOG.md | 5 ++-- doc/INSTALL_quickstart.md | 39 +++++++++++++++++------------ doc/README_known_issues.md | 31 +++++++++++++++-------- doc/w11a_os_guide.md | 8 +++--- rtl/bplib/README.md | 8 +++--- rtl/sys_gen/tst_mig/README.md | 2 +- rtl/sys_gen/tst_rlink/README.md | 4 +-- rtl/sys_gen/tst_serloop/README.md | 2 +- rtl/sys_gen/tst_snhumanio/README.md | 2 +- rtl/sys_gen/tst_sram/README.md | 4 +-- rtl/sys_gen/w11a/README.md | 6 ++--- 11 files changed, 64 insertions(+), 47 deletions(-) diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index 597f8abe..c4254910 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -27,7 +27,8 @@ The full set of tests is only run for tagged releases. ### Summary - automate oskit download and container file setup - automate testing of oskits -- get Nexys A7 board working and fully integrated +- get Nexys A7 board working and fully integrated, + close [issue #16](https://github.com/wfjm/w11/issues/16) ### New features - new tools @@ -244,7 +245,7 @@ The full set of tests is only run for tagged releases. ### Summary - add support for DDR memory via Vivado MIG cores for - Digilent Arty - - Digilent Nexys4 DDR + - Digilent Nexys4 DDR (or Nexys A7-100) - Digilent Arty S7 - add a low level MIG interface test design `sys_tst_mig_*` - update tool support diff --git a/doc/INSTALL_quickstart.md b/doc/INSTALL_quickstart.md index 9f1d16da..ef321f14 100644 --- a/doc/INSTALL_quickstart.md +++ b/doc/INSTALL_quickstart.md @@ -3,8 +3,10 @@ This _quick start guide_ describes the fastest possible path to a running operating system on a w11 on current Series-7 based boards. It leaves out legacy Spartan-3 and Spartan-6 designs, verification, test benches, test -designs, and many other aspects, for all this consult the full -[INSTALL](INSTALL.md) and the READMEs in [doc](.). This write-up +designs, and many other aspects. For all this consult the full +[INSTALL](INSTALL.md), the +[guide to boot operating systems](w11a_os_guide.md), +and the READMEs in [doc](.). This write-up focuses on the steps _[prepare](#user-content-prepare)_, _[build](#user-content-build)_ and _[boot](#user-content-boot)_, and gives one [concrete example](#user-content-tested). @@ -69,6 +71,7 @@ with the currently supported combinations basys3 b3 176 kB Digilent Basys3 board cmoda7 c7 672 kB Digilent Cmod A7 board nexys4 n4 3840 kB Digilent Nexys4 board (cellular RAM) + nexys4d n4d 3840 kB Digilent Nexys A7-100 board (DDR2) The FPGA is configured via the vivado hardware server with @@ -110,37 +113,41 @@ Key steps are The recipe was tested - system environment - Kubuntu 16.04 LTS - - Vivado 2017.1 - - on 2018-08-04 + - Vivado 2019.1 + - on 2019-08-11 -- after commit [6ee3ed6](https://github.com/wfjm/w11/commit/6ee3ed6) +- after commit [563e230](https://github.com/wfjm/w11/commit/563e230) cd $RETROBASE/tools/src time make -j 4 - # real 2m58.501s user 5m4.244s sys 0m35.600s + # real 1m40.556s user 2m53.704s sys 0m14.668s -- for design `nexys4` +- for design `nexys4d` for + [Nexys4 DDR](https://wfjm.github.io/home/w11/inst/boards.html#digi_nexys4d) or + [Nexys A7-100](https://wfjm.github.io/home/w11/inst/boards.html#digi_nexysa7) + boards. - cd $RETROBASE/rtl/sys_gen/w11a/nexys4 - time make sys_w11a_n4.bit - # real 10m48.274s user 0m55.660s sys 0m3.160s - time make sys_w11a_n4.vconfig - # real 0m32.747s user 0m15.996s sys 0m0.736s + cd $RETROBASE/rtl/sys_gen/w11a/nexys4d + time make sys_w11a_n4d.bit + # real 18m21.066s user 8m41.300s sys 0m53.416s + time make sys_w11a_n4d.vconfig + # real 0m34.484s user 0m15.540s sys 0m1.660s - for oskit `211bsd_rp` - in Linux terminal cd $RETROBASE/tools/oskit/211bsd_rp - wget http://www.retro11.de/data/oc_w11/oskits/211bsd_rpset.tgz - tar -xzf 211bsd_rpset.tgz - + 211bsd_rp_setup + console_starter -d DL0 & console_starter -d DL1 & # set board switches to SWI = 00000000 00101000 ti_w11 -tuD,12M,break,cts @211bsd_rp_boot.tcl - - in window `DL1vt100` hit `` to connect to backend, than see output and do required inputs as written in [README](../tools/oskit/211bsd_rp/README.md): + - in window `DL1vt100` hit `` to connect to backend, than see output + and do required inputs as written in the + [README](../tools/oskit/211bsd_rp/README.md): 70Boot from xp(0,0,0) at 0176700 : {} diff --git a/doc/README_known_issues.md b/doc/README_known_issues.md index e26ed50f..875c59dd 100644 --- a/doc/README_known_issues.md +++ b/doc/README_known_issues.md @@ -165,17 +165,6 @@ documentation of your board to avoid potential damage. Looking forward to receive test reports. -### V0.76-1 {[issue #16](https://github.com/wfjm/w11/issues/16)} -- Help wanted: Testing with Nexys4 DDR appreciated -The w11a design for Nexys4 DDR, see rtl/sys_gen/w11a/nexys4d, was provided -to support also an up-to-date Nexys4 board. It is so far only simulation tested. - -Testing done with a real Nexyx4 DDR, or a newer Nexys A7-100T, would be highly -appreciated. Please double check the pin assignments -(see _mig_a.prj and nexys4d*.xdc_) with the documentation of your board -to avoid potential damage. - -Looking forward to receive test reports. - ### V0.73-2 {[issue #10](https://github.com/wfjm/w11/issues/10)} -- Many post-synthesis simulations fail Many post-synthesis functional and especially post-routing timing simulations currently fail due to startup and initialization problems. @@ -226,6 +215,26 @@ free}_ ## Resolved Issues +### V0.76-1 {[issue #16](https://github.com/wfjm/w11/issues/16)} -- Help wanted: Testing with Nexys4 DDR appreciated +#### Original Issue +The w11a design for Nexys4 DDR, see +[rtl/sys_gen/w11a/nexys4d](https://github.com/wfjm/w11/tree/master/rtl/sys_gen/w11a/nexys4d), +was provided to support also an up-to-date Nexys4 board. It is so far only +simulation tested. + +Testing done with a real Nexyx4 DDR, or a newer Nexys A7-100T, would be highly +appreciated. Please double check the pin assignments +(see _mig_a.prj and nexys4d*.xdc_) with the documentation of your board +to avoid potential damage. + +Looking forward to receive test reports. + +#### Fix +Purchased Nexys A7-100 board after the +[Nexys4 board broke](https://wfjm.github.io/blogs/w11/2019-07-27-nexys4-obituary.html), +tested, and fixed one silly mistake. Closed with commit +[563e230](https://github.com/wfjm/w11/commit/563e230). + ### V0.66-1 {[issue #8](https://github.com/wfjm/w11/issues/8)} -- TM11 controller doesn't support odd transfer size #### Original Issue The TM11 controller transfers data byte wise (all disk do it 16bit diff --git a/doc/w11a_os_guide.md b/doc/w11a_os_guide.md index d3e010ae..57736663 100644 --- a/doc/w11a_os_guide.md +++ b/doc/w11a_os_guide.md @@ -18,7 +18,7 @@ communication between FPGA board and backend server can be via - Serial port - via an integrated USB-UART bridge - - on Arty, Basys3, CmodA7 and Nexys4 and Nexys4 DDR with a `FT2232HQ`, + - on Arty A7, Basys3, Cmod A7 and Nexys4 and Nexys A7 with a `FT2232HQ`, allows up to 12M Baud - on Nexys3 with a `FT232R`, allows up to 2M Baud - for all FTDI USB-UART it is essential to set them to `low latency` mode. @@ -52,10 +52,10 @@ Recommended setup for best performance (boards ordered by vintage): | Board | Channel/Interface | nom. speed | peak transfer rate | | :--------- | :--------------------- | :----------- | -----------------: | -| Arty | USB-UART bridge | 12M Baud | 1090 kB/sec | +| Arty A7 | USB-UART bridge | 12M Baud | 1090 kB/sec | | Basys3 | USB-UART bridge | 12M Baud | 1090 kB/sec | | Cmod A7 | USB-UART bridge | 12M Baud | 1090 kB/sec | -| Nexys4 DDR | USB-UART bridge | 12M Baud | 1090 kb/sec | +| Nexys A7 | USB-UART bridge | 12M Baud | 1090 kb/sec | | Nexys4 | USB-UART bridge | 12M Baud | 1090 kb/sec | | Nexys3 | Cypress FX2 USB | USB2.0 speed | 30000 kB/sec | | Nexys2 | Cypress FX2 USB | USB2.0 speed | 30000 kB/sec | @@ -77,7 +77,7 @@ Recommended setups - connect USB cable to micro-USB connector - to configure via vivado hardware server `make .vconfig` -- Nexys4 and Nexys4 DDR +- Nexys4 and Nexys A7 (or Nexys4 DDR) - connect USB cable to micro-USB connector labeled 'PROG' - to configure via vivado hardware server `make .vconfig` diff --git a/rtl/bplib/README.md b/rtl/bplib/README.md index 20e7e88e..7b1e3efe 100644 --- a/rtl/bplib/README.md +++ b/rtl/bplib/README.md @@ -3,12 +3,12 @@ and is organized in | Directory | Content | | --------- | ------- | -| [arty](arty) | support for Digilent Arty board | -| [artys7](artys7) | support for Digilent Arty S7 board | +| [arty](arty) | support for Digilent Arty A7-35 board | +| [artys7](artys7) | support for Digilent Arty S7-50 board | | [atlys](atlys) | support for Digilent Atlys board | | [basys3](basys3) | support for Digilent Basys3 board | | [bpgen](bpgen) | interfaces for IO devices common on Digilent boards | -| [cmoda7](cmoda7) | support for Digilent Cmod A7 board | +| [cmoda7](cmoda7) | support for Digilent Cmod A7-35 board | | [fx2lib](fx2lib) | interface for Cypress FX2 USB | | [fx2rlink](fx2rlink) | modules for rlink over Cypress FX2 | | [issi](issi) | simulation models for ISSI components | @@ -17,7 +17,7 @@ and is organized in | [nexys2](nexys2) | support for Digilent Nexys2 board | | [nexys3](nexys3) | support for Digilent Nexys3 board | | [nexys4](nexys4) | support for Digilent Nexys4 board (cram version) | -| [nexys4d](nexys4d) | support for Digilent Nexys4 DDR board | +| [nexys4d](nexys4d) | support for Digilent Nexys A7-100 board | | [nxcramlib](nxcramlib) | interface for ISSI CRAM | | [s3board](s3board) | support for Digilent S3BOARD board | | [sysmon](sysmon) | interface for Xilinx Series-7 sysmon | diff --git a/rtl/sys_gen/tst_mig/README.md b/rtl/sys_gen/tst_mig/README.md index f4f4d5fa..c3b7093d 100644 --- a/rtl/sys_gen/tst_mig/README.md +++ b/rtl/sys_gen/tst_mig/README.md @@ -4,4 +4,4 @@ and is organized in | Directory | Content | | --------- | ------- | | [arty](arty) | design for Digilent Arty A7-35 | -| [nexys4d](nexys4d) | design for Digilent Nexys4 DDR _!! only sim-tested !!_ | +| [nexys4d](nexys4d) | design for Digilent Nexys A7-100 | diff --git a/rtl/sys_gen/tst_rlink/README.md b/rtl/sys_gen/tst_rlink/README.md index 7eca259b..62fd657f 100644 --- a/rtl/sys_gen/tst_rlink/README.md +++ b/rtl/sys_gen/tst_rlink/README.md @@ -5,9 +5,9 @@ and is organized in | --------- | ------- | | [arty](arty) | design for Digilent Arty A7-35 | | [basys3](basys3) | design for Digilent Basys3 | -| [cmoda7](cmoda7) | design for Digilent Cmod A7 (35 die size) | +| [cmoda7](cmoda7) | design for Digilent Cmod A7-35 | | [nexys2](nexys2) | design for Digilent Nexys2 | | [nexys3](nexys3) | design for Digilent Nexys3 | | [nexys4](nexys4) | design for Digilent Nexys4 (old CRAM version) | -| [nexys4d](nexys4d) | design for Digilent Nexys4 DDR _!! only sim-tested !!_ | +| [nexys4d](nexys4d) | design for Digilent Nexys A7-100 | | [s3board](s3board) | design for Digilent S3BOARD | diff --git a/rtl/sys_gen/tst_serloop/README.md b/rtl/sys_gen/tst_serloop/README.md index 1fa2d8f7..95e3341c 100644 --- a/rtl/sys_gen/tst_serloop/README.md +++ b/rtl/sys_gen/tst_serloop/README.md @@ -6,5 +6,5 @@ and is organized in | [nexys2](nexys2) | design for Digilent Nexys2 | | [nexys3](nexys3) | design for Digilent Nexys3 | | [nexys4](nexys4) | design for Digilent Nexys4 (old CRAM version) | -| [nexys4d](nexys4d) | design for Digilent Nexys4 DDR _!! only sim-tested !!_ | +| [nexys4d](nexys4d) | design for Digilent Nexys A7-100 | | [s3board](s3board) | design for Digilent S3BOARD | diff --git a/rtl/sys_gen/tst_snhumanio/README.md b/rtl/sys_gen/tst_snhumanio/README.md index 9a26c41e..8e839d27 100644 --- a/rtl/sys_gen/tst_snhumanio/README.md +++ b/rtl/sys_gen/tst_snhumanio/README.md @@ -8,5 +8,5 @@ and is organized in | [nexys2](nexys2) | design for Digilent Nexys2 | | [nexys3](nexys3) | design for Digilent Nexys3 | | [nexys4](nexys4) | design for Digilent Nexys4 (old CRAM version) | -| [nexys4d](nexys4d) | design for Digilent Nexys4 DDR _!! only sim-tested !!_ | +| [nexys4d](nexys4d) | design for Digilent Nexys A7-100 | | [s3board](s3board) | design for Digilent S3BOARD | diff --git a/rtl/sys_gen/tst_sram/README.md b/rtl/sys_gen/tst_sram/README.md index 7a0b4d64..e22dc24b 100644 --- a/rtl/sys_gen/tst_sram/README.md +++ b/rtl/sys_gen/tst_sram/README.md @@ -4,9 +4,9 @@ and is organized in | Directory | Content | | --------- | ------- | | [arty](arty) | design for Digilent Arty A7-35 | -| [cmoda7](cmoda7) | design for Digilent Cmod A7 (35 die size) | +| [cmoda7](cmoda7) | design for Digilent Cmod A7-35 | | [nexys2](nexys2) | design for Digilent Nexys2 | | [nexys3](nexys3) | design for Digilent Nexys3 | | [nexys4](nexys4) | design for Digilent Nexys4 (old CRAM version) | -| [nexys4d](nexys4d) | design for Digilent Nexys4 DDR _!! only sim-tested !!_ | +| [nexys4d](nexys4d) | design for Digilent Nexys A7-100 | | [s3board](s3board) | design for Digilent S3BOARD | diff --git a/rtl/sys_gen/w11a/README.md b/rtl/sys_gen/w11a/README.md index 140192dc..36382b6e 100644 --- a/rtl/sys_gen/w11a/README.md +++ b/rtl/sys_gen/w11a/README.md @@ -8,10 +8,10 @@ and is organized in | [artys7](artys7) | design for Digilent Arty S7-50 (use DDR via MIG) _!! only sim-tested !!_ | | [artys7_bram](artys7_bram) | design for Digilent Arty S7-50 (use BRAM only) _!! only sim-tested !!_| | [basys3](basys3) | design for Digilent Basys3 | -| [cmoda7](cmoda7) | design for Digilent Cmod A7 (35 die size) | +| [cmoda7](cmoda7) | design for Digilent Cmod A7-35 | | [nexys2](nexys2) | design for Digilent Nexys2 | | [nexys3](nexys3) | design for Digilent Nexys3 | | [nexys4](nexys4) | design for Digilent Nexys4 (old CRAM version) | -| [nexys4d](nexys4d) | design for Digilent Nexys4 DDR (use DDR via MIG) _!! only sim-tested !!_ | -| [nexys4d_bram](nexys4d_bram) | design for Digilent Nexys4 DDR (use BRAM only) _!! only sim-tested !!_ | +| [nexys4d](nexys4d) | design for Digilent Nexys A7-100 (use DDR via MIG) | +| [nexys4d_bram](nexys4d_bram) | design for Digilent Nexys A7-100 (use BRAM only | | [s3board](s3board) | design for Digilent S3BOARD |