diff --git a/Makefile b/Makefile index df104209..094520fe 100644 --- a/Makefile +++ b/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 893 2017-05-05 17:43:53Z mueller $ +# $Id: Makefile 918 2017-06-28 20:04:17Z mueller $ # # 'Meta Makefile' for whole retro project # allows to make all synthesis targets @@ -6,6 +6,7 @@ # # Revision History: # Date Rev Version Comment +# 2017-06-28 918 1.2.8 add cmoda7 port for tst_rlink,tst_sram,w11a # 2017-05-01 891 1.2.7 add all_tcl to all; use njobihtm # 2016-10-01 810 1.2.6 move component tests to SIM_viv when vivado used # 2016-07-10 785 1.2.5 re-enable rtl/sys_gen/tst_sram/nexys4 (ok in 2016.2) @@ -75,6 +76,11 @@ SYN_viv += rtl/sys_gen/w11a/nexys4 SYN_viv += rtl/sys_gen/tst_rlink/arty SYN_viv += rtl/sys_gen/w11a/arty_bram +# CmodA7 ------------------------------------- +SYN_viv += rtl/sys_gen/tst_rlink/cmoda7 +SYN_viv += rtl/sys_gen/tst_sram/cmoda7 +SYN_viv += rtl/sys_gen/w11a/cmoda7 + # Simulation targets ------------------------------------------------- # ISE flow ----------------------------------------------- @@ -126,7 +132,12 @@ SIM_viv += rtl/sys_gen/w11a/nexys4/tb SIM_viv += rtl/sys_gen/tst_rlink/arty/tb SIM_viv += rtl/sys_gen/w11a/arty_bram/tb -# +# CmodA7 ------------------------------------- +SIM_viv += rtl/sys_gen/tst_rlink/cmoda7/tb +SIM_viv += rtl/sys_gen/tst_sram/cmoda7/tb +SIM_viv += rtl/sys_gen/w11a/cmoda7/tb + +# -------------------------------------------------------------------- .PHONY : default .PHONY : all all_ise all_viv .PHONY : all_sim_ise all_syn_ise all_syn_viv diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index f32e26c2..e9f25c70 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -18,6 +18,20 @@ The full set of tests is only run for tagged releases. ### Summary +- Add Digilent Cmod A7 (35 die size) support + - general board support + - c7_sram_memctl: SRAM memory controller (incl tb) + - is61wv5128bll: simple memory model (incl tb) + - sn_humanio_emu_rbus: human IO emulator + - 92-retro-usb-persistent.rules: add more board rules + - associated changes + - sn_humanio_rbus: add stat_rbf_emu (=0); single cycle btn pulses + - rgbdrv_analog(_rbus): add ACTLOW generic to invert output polarity + - ti_rri: adopt Digilent autodetect for CmodA7 + - add systems + - tst_rlink: rlink tested + - tst_sram: SRAM tester + - w11a: w11a system with 672 kB memory (512 SRAM + 160 BRAM) - new modules/packages - rtl/vlib/rutil.vhd: added package, with imin helper function - cleanups diff --git a/doc/w11a_os_guide.md b/doc/w11a_os_guide.md index 6d03dfcf..e74de615 100644 --- a/doc/w11a_os_guide.md +++ b/doc/w11a_os_guide.md @@ -18,7 +18,7 @@ communication between FPGA board and backend server can be via - Serial port - via an integrated USB-UART bridge - - on Arty, Basys3, and Nexys4 and Nexys4 DDR with a `FT2232HQ`, + - on Arty, Basys3, CmodA7 and Nexys4 and Nexys4 DDR with a `FT2232HQ`, allows up to 12M Baud - on nexys3 with a `FT232R`, allows up to 2M Baud - for all FTDI USB-UART it is essential to set them to `low latency` mode. @@ -54,6 +54,7 @@ Recommended setup for best performance (boards ordered by vintage): | :--------- | :--------------------- | :----------- | -----------------: | | Arty | USB-UART bridge | 12M Baud | 1090 kB/sec | | Basys3 | USB-UART bridge | 12M Baud | 1090 kB/sec | +| Cmod A7 | USB-UART bridge | 12M Baud | 1090 kB/sec | | Nexys4 DDR | USB-UART bridge | 12M Baud | 1090 kb/sec | | Nexys4 | USB-UART bridge | 12M Baud | 1090 kb/sec | | Nexys3 | Cypress FX2 USB | USB2.0 speed | 30000 kB/sec | @@ -72,6 +73,10 @@ Recommended setups - connect USB cable to micro-USB connector labeled 'PROG' - to configure via vivado hardware server `make .vconfig` +- Cmod A7 + - connect USB cable to micro-USB connector + - to configure via vivado hardware server `make .vconfig` + - Nexys4 and Nexys4 DDR - connect USB cable to micro-USB connector labeled 'PROG' - to configure via vivado hardware server `make .vconfig` @@ -124,6 +129,15 @@ All examples below use the same basic setup unix-v5 works fine. XXDP, RT11 and RSX-11M should work. 211bsd will not boot, neither most RSX-11M+ systems. + - for c7 over serial + + ti_w11 -tuD,12M,break,xon @_boot.tcl + + **Note**: the c7 w11a has currently only 672 kB memory (512 SRAM + 160 BRAM) + unix-5,XXDP,RT11,RSX-11M and most most RSX-11M+ systems should work. + 211bsd works only in the 'non-networking' configuration + [211bsd_rpmin](../tools/oskit/211bsd_rpmin) + - for n4 or n4d over serial SWI = 00000000 00101000 (gives console light display on LEDS) @@ -143,12 +157,13 @@ All examples below use the same basic setup - the letter after `-tu` is either the serial device number, denoted as ``, or the letter `D` for auto-detection of Digilent boards with a FT2232HQ based interface. - - for Arty, Basys3 and Nexys4 board simply use `D` + - for Arty, Basys3, CmodA7 and Nexys4 board simply use `D` - otherwise check with `ls /dev/ttyUSB*` to see what is available - `` is typically '1' if a single `FT2232HQ` based board is connected, - like an Arty, Basys3, or Nexys4. Initially two ttyUSB devices show up, - the lower is for FPGA configuration and will disappear when the Vivado - hardware server is used once. The upper provides the data connection. + like an Arty, Basys3, CmodA7, or Nexys4. Initially two ttyUSB devices + show up, the lower is for FPGA configuration and will disappear when + the Vivado hardware server is used once. The upper provides the data + connection. - `` is typically '0' if only a single USB-RS232 cable is connected - on LED display diff --git a/rtl/bplib/README.md b/rtl/bplib/README.md index 466beecf..b508a1f8 100644 --- a/rtl/bplib/README.md +++ b/rtl/bplib/README.md @@ -7,6 +7,7 @@ and is organized in | [atlys](atlys) | support for Digilent Atlys board | | [basys3](basys3) | support for Digilent Basys3 board | | [bpgen](bpgen) | interfaces for IO devices common on Digilent boards | +| [cmoda7](cmoda7) | support for Digilent Cmod A7 board | | [fx2lib](fx2lib) | interface for Cypress FX2 USB | | [fx2rlink](fx2rlink) | modules for rlink over Cypress FX2 | | [issi](issi) | simulation models for ISSI components | diff --git a/rtl/bplib/bpgen/bpgenlib.vhd b/rtl/bplib/bpgen/bpgenlib.vhd index 02d464b2..49ccc7e2 100644 --- a/rtl/bplib/bpgen/bpgenlib.vhd +++ b/rtl/bplib/bpgen/bpgenlib.vhd @@ -1,6 +1,6 @@ --- $Id: bpgenlib.vhd 737 2016-02-28 09:07:18Z mueller $ +-- $Id: bpgenlib.vhd 907 2017-06-05 08:19:12Z mueller $ -- --- Copyright 2011-2016 by Walter F.J. Mueller +-- Copyright 2011-2017 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Generic Board/Part components -- -- Dependencies: - --- Tool versions: ise 12.1-14.7; viv 2014.4-2015.4; ghdl 0.26-0.31 +-- Tool versions: ise 12.1-14.7; viv 2014.4-2016.4; ghdl 0.26-0.34 -- Revision History: -- Date Rev Version Comment +-- 2017-06-05 907 1.2.1 rgbdrv_analog: add ACTLOW generic -- 2016-02-27 737 1.2 add rgbdrv entity -- 2015-01-24 637 1.1.2 add generics to sn_humanio and sn_7segctl -- 2013-09-21 534 1.1.1 add bp_rs232_4l4l_iob @@ -195,7 +196,8 @@ end component; component rgbdrv_analog is -- rgbled driver: analog channel generic ( - DWIDTH : positive := 8); -- dimmer width + DWIDTH : positive := 8; -- dimmer width + ACTLOW : slbit := '0'); -- invert output polarity port ( CLK : in slbit; -- clock RESET : in slbit := '0'; -- reset diff --git a/rtl/bplib/bpgen/bpgenrbuslib.vhd b/rtl/bplib/bpgen/bpgenrbuslib.vhd index 4fa989fa..789982c3 100644 --- a/rtl/bplib/bpgen/bpgenrbuslib.vhd +++ b/rtl/bplib/bpgen/bpgenrbuslib.vhd @@ -1,6 +1,6 @@ --- $Id: bpgenrbuslib.vhd 734 2016-02-20 22:43:20Z mueller $ +-- $Id: bpgenrbuslib.vhd 912 2017-06-11 18:30:03Z mueller $ -- --- Copyright 2013-2016 by Walter F.J. Mueller +-- Copyright 2013-2017 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,11 @@ -- Description: Generic Board/Part components using rbus -- -- Dependencies: - --- Tool versions: ise 12.1-14.7; viv 2014.4-2015.4; ghdl 0.26-0.31 +-- Tool versions: ise 12.1-14.7; viv 2014.4-2017.1; ghdl 0.26-0.34 -- Revision History: -- Date Rev Version Comment +-- 2017-06-11 912 1.3.2 add sn_humanio_emu_rbus +-- 2017-06-05 907 1.3.1 rgbdrv_analog_rbus: add ACTLOW generic -- 2016-02-20 734 1.3 add rgbdrv_analog_rbus -- 2015-01-25 637 1.2 add generics to sn_humanio_rbus -- 2014-08-15 583 1.1 rb_mreq addr now 16 bit @@ -104,9 +106,30 @@ component sn_humanio_demu_rbus is -- human i/o swi,btn,led only /w rbus ); end component; +component sn_humanio_emu_rbus is -- sn_humanio rbus emulator + generic ( + SWIDTH : positive := 8; -- SWI port width + BWIDTH : positive := 4; -- BTN port width + LWIDTH : positive := 8; -- LED port width + DCWIDTH : positive := 2; -- digit counter width (2 or 3) + RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16))); + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced + BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced + LED : in slv(LWIDTH-1 downto 0); -- led data + DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data + DSP_DP : in slv((2**DCWIDTH)-1 downto 0) -- display decimal points + ); +end component; + component rgbdrv_analog_rbus is -- rgb analog from rbus generic ( DWIDTH : positive := 8; -- dimmer width + ACTLOW : slbit := '0'; -- invert output polarity RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16))); port ( CLK : in slbit; -- clock diff --git a/rtl/bplib/bpgen/rgbdrv_analog.vhd b/rtl/bplib/bpgen/rgbdrv_analog.vhd index 961df751..22901761 100644 --- a/rtl/bplib/bpgen/rgbdrv_analog.vhd +++ b/rtl/bplib/bpgen/rgbdrv_analog.vhd @@ -1,6 +1,6 @@ --- $Id: rgbdrv_analog.vhd 734 2016-02-20 22:43:20Z mueller $ +-- $Id: rgbdrv_analog.vhd 907 2017-06-05 08:19:12Z mueller $ -- --- Copyright 2016- by Walter F.J. Mueller +-- Copyright 2016-2017 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,11 +18,12 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: viv 2015.4; ghdl 0.31 +-- Tool versions: viv 2015.4-2016.4; ghdl 0.31-0.34 -- -- Revision History: -- Date Rev Version Comment --- 2016-02-20 734 1.0 Initial version +-- 2017-06-05 907 1.1 add ACTLOW generic to invert output polarity +-- 2016-02-20 734 1.0 Initial version ------------------------------------------------------------------------------ library ieee; @@ -34,7 +35,8 @@ use work.xlib.all; entity rgbdrv_analog is -- rgbled driver: analog channel generic ( - DWIDTH : positive := 8); -- dimmer width + DWIDTH : positive := 8; -- dimmer width + ACTLOW : slbit := '0'); -- invert output polarity port ( CLK : in slbit; -- clock RESET : in slbit := '0'; -- reset @@ -90,7 +92,9 @@ begin irgb(2) := RGBCNTL(2); end if; - N_RGB <= irgb; + N_RGB(0) <= ACTLOW xor irgb(0); + N_RGB(1) <= ACTLOW xor irgb(1); + N_RGB(2) <= ACTLOW xor irgb(2); end process proc_next; diff --git a/rtl/bplib/bpgen/rgbdrv_analog_rbus.vhd b/rtl/bplib/bpgen/rgbdrv_analog_rbus.vhd index 871da233..8bb8aede 100644 --- a/rtl/bplib/bpgen/rgbdrv_analog_rbus.vhd +++ b/rtl/bplib/bpgen/rgbdrv_analog_rbus.vhd @@ -1,6 +1,6 @@ --- $Id: rgbdrv_analog_rbus.vhd 734 2016-02-20 22:43:20Z mueller $ +-- $Id: rgbdrv_analog_rbus.vhd 907 2017-06-05 08:19:12Z mueller $ -- --- Copyright 2016- by Walter F.J. Mueller +-- Copyright 2016-2017 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,10 +20,11 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: ise 14.7; viv 2015.4; ghdl 0.31 +-- Tool versions: ise 14.7; viv 2015.4-2016.4; ghdl 0.31-0.34 -- -- Revision History: -- Date Rev Version Comment +-- 2017-06-05 907 1.1 add ACTLOW generic to invert output polarity -- 2016-02-20 724 1.0 Initial version ------------------------------------------------------------------------------ -- @@ -48,6 +49,7 @@ use work.bpgenlib.all; entity rgbdrv_analog_rbus is -- rgb analog from rbus generic ( DWIDTH : positive := 8; -- dimmer width + ACTLOW : slbit := '0'; -- invert output polarity RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16))); port ( CLK : in slbit; -- clock @@ -95,7 +97,8 @@ begin RGB : rgbdrv_analog generic map ( - DWIDTH => DWIDTH) + DWIDTH => DWIDTH, + ACTLOW => ACTLOW) port map ( CLK => CLK, RESET => RESET, diff --git a/rtl/bplib/bpgen/sn_humanio_emu_rbus.vbom b/rtl/bplib/bpgen/sn_humanio_emu_rbus.vbom new file mode 100644 index 00000000..5e2894e7 --- /dev/null +++ b/rtl/bplib/bpgen/sn_humanio_emu_rbus.vbom @@ -0,0 +1,6 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/rbus/rblib.vhd +# components +# design +sn_humanio_emu_rbus.vhd diff --git a/rtl/bplib/bpgen/sn_humanio_emu_rbus.vhd b/rtl/bplib/bpgen/sn_humanio_emu_rbus.vhd new file mode 100644 index 00000000..27b87d16 --- /dev/null +++ b/rtl/bplib/bpgen/sn_humanio_emu_rbus.vhd @@ -0,0 +1,267 @@ +-- $Id: sn_humanio_emu_rbus.vhd 912 2017-06-11 18:30:03Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sn_humanio_emu_rbus - syn +-- Description: sn_humanio rbus emulator +-- +-- Dependencies: - +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: viv 2017.1; ghdl 0.34 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-11 912 1.0 Initial version (derived from sn_humanio_rbus +------------------------------------------------------------------------------ +-- +-- rbus registers: +-- +-- Addr Bits Name r/w/f Function +-- 000 stat r/-/- Status register +-- 15 emu r/-/- emulation (always 1) +-- 14:12 hdig r/-/- display size as (2**DCWIDTH)-1 +-- 11:08 hled r/-/- led size as LWIDTH-1 +-- 7:04 hbtn r/-/- button size as BWIDTH-1 +-- 3:00 hswi r/-/- switch size as SWIDTH-1 +-- +-- 001 cntl r/w/- Control register +-- 4 dsp1_en r/-/- always 0 +-- 3 dsp0_en r/-/- always 0 +-- 2 dp_en r/-/- always 0 +-- 1 led_en r/-/- always 0 +-- 0 swi_en r/-/- always 1: SWI will be driven by rbus +-- +-- 010 x:00 btn -/-/f w: will pulse BTN +-- 011 x:00 swi r/w/- SWI status +-- 100 x:00 led r/-/- LED status +-- 101 x:00 dp r/-/- DSP_DP status +-- 110 15:00 dsp0 r/-/- DSP_DAT lsb status +-- 111 15:00 dsp1 r/-/- DSP_DAT msb status +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.rblib.all; + +-- ---------------------------------------------------------------------------- + +entity sn_humanio_emu_rbus is -- sn_humanio rbus emulator + generic ( + SWIDTH : positive := 8; -- SWI port width + BWIDTH : positive := 4; -- BTN port width + LWIDTH : positive := 8; -- LED port width + DCWIDTH : positive := 2; -- digit counter width (2 or 3) + RB_ADDR : slv16 := slv(to_unsigned(16#fef0#,16))); + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + SWI : out slv(SWIDTH-1 downto 0); -- switch settings + BTN : out slv(BWIDTH-1 downto 0); -- button settings + LED : in slv(LWIDTH-1 downto 0); -- led data + DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data + DSP_DP : in slv((2**DCWIDTH)-1 downto 0) -- display decimal points + ); +end sn_humanio_emu_rbus; + +architecture syn of sn_humanio_emu_rbus is + + type regs_type is record + rbsel : slbit; -- rbus select + swi : slv(SWIDTH-1 downto 0); -- rbus swi + btn : slv(BWIDTH-1 downto 0); -- rbus btn + led : slv(LWIDTH-1 downto 0); -- hio led + dsp_dat : slv(4*(2**DCWIDTH)-1 downto 0); -- hio dsp_dat + dsp_dp : slv((2**DCWIDTH)-1 downto 0); -- hio dsp_dp + end record regs_type; + + constant swizero : slv(SWIDTH-1 downto 0) := (others=>'0'); + constant btnzero : slv(BWIDTH-1 downto 0) := (others=>'0'); + constant ledzero : slv(LWIDTH-1 downto 0) := (others=>'0'); + constant dpzero : slv((2**DCWIDTH)-1 downto 0) := (others=>'0'); + constant datzero : slv(4*(2**DCWIDTH)-1 downto 0) := (others=>'0'); + + constant regs_init : regs_type := ( + '0', -- rbsel + swizero, -- swi + btnzero, -- btn + ledzero, -- led + datzero, -- dsp_dat + dpzero -- dsp_dp + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + constant stat_rbf_emu: integer := 15; + subtype stat_rbf_hdig is integer range 14 downto 12; + subtype stat_rbf_hled is integer range 11 downto 8; + subtype stat_rbf_hbtn is integer range 7 downto 4; + subtype stat_rbf_hswi is integer range 3 downto 0; + + constant cntl_rbf_dsp1_en: integer := 4; + constant cntl_rbf_dsp0_en: integer := 3; + constant cntl_rbf_dp_en: integer := 2; + constant cntl_rbf_led_en: integer := 1; + constant cntl_rbf_swi_en: integer := 0; + + constant rbaddr_stat: slv3 := "000"; -- 0 r/-/- + constant rbaddr_cntl: slv3 := "001"; -- 0 r/w/- + constant rbaddr_btn: slv3 := "010"; -- 1 -/-/f + constant rbaddr_swi: slv3 := "011"; -- 1 r/w/- + constant rbaddr_led: slv3 := "100"; -- 2 r/-/- + constant rbaddr_dp: slv3 := "101"; -- 3 r/-/- + constant rbaddr_dsp0: slv3 := "110"; -- 4 r/-/- + constant rbaddr_dsp1: slv3 := "111"; -- 5 r/-/- + + subtype dspdat_msb is integer range 4*(2**DCWIDTH)-1 downto 4*(2**DCWIDTH)-16; + subtype dspdat_lsb is integer range 15 downto 0; + +begin + + assert SWIDTH<=16 + report "assert (SWIDTH<=16)" + severity failure; + assert BWIDTH<=8 + report "assert (BWIDTH<=8)" + severity failure; + assert LWIDTH<=16 + report "assert (LWIDTH<=16)" + severity failure; + + assert DCWIDTH=2 or DCWIDTH=3 + report "assert(DCWIDTH=2 or DCWIDTH=3): unsupported DCWIDTH" + severity FAILURE; + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, RB_MREQ, LED, DSP_DAT, DSP_DP) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable irb_ack : slbit := '0'; + variable irb_busy : slbit := '0'; + variable irb_err : slbit := '0'; + variable irb_dout : slv16 := (others=>'0'); + variable irbena : slbit := '0'; + + begin + + r := R_REGS; + n := R_REGS; + + irb_ack := '0'; + irb_busy := '0'; + irb_err := '0'; + irb_dout := (others=>'0'); + + irbena := RB_MREQ.re or RB_MREQ.we; + + -- input registers + n.led := LED; + n.dsp_dat := DSP_DAT; + n.dsp_dp := DSP_DP; + -- clear btn register --> cause single cycle pulses + n.btn := (others=>'0'); + + -- rbus address decoder + n.rbsel := '0'; + if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 3)=RB_ADDR(15 downto 3) then + n.rbsel := '1'; + end if; + + -- rbus transactions + if r.rbsel = '1' then + irb_ack := irbena; -- ack all accesses + + case RB_MREQ.addr(2 downto 0) is + + when rbaddr_stat => + irb_dout(stat_rbf_emu) := '1'; + irb_dout(stat_rbf_hdig) := slv(to_unsigned((2**DCWIDTH)-1,3)); + irb_dout(stat_rbf_hled) := slv(to_unsigned(LWIDTH-1,4)); + irb_dout(stat_rbf_hbtn) := slv(to_unsigned(BWIDTH-1,4)); + irb_dout(stat_rbf_hswi) := slv(to_unsigned(SWIDTH-1,4)); + if RB_MREQ.we = '1' then + irb_ack := '0'; + end if; + + when rbaddr_cntl => + irb_dout(cntl_rbf_dsp1_en) := '0'; + irb_dout(cntl_rbf_dsp0_en) := '0'; + irb_dout(cntl_rbf_dp_en) := '0'; + irb_dout(cntl_rbf_led_en) := '0'; + irb_dout(cntl_rbf_swi_en) := '1'; + + when rbaddr_btn => + irb_dout(r.btn'range) := r.btn; + if RB_MREQ.we = '1' then + n.btn := RB_MREQ.din(n.btn'range); + end if; + + when rbaddr_swi => + irb_dout(r.swi'range) := r.swi; + if RB_MREQ.we = '1' then + n.swi := RB_MREQ.din(n.swi'range); + end if; + + when rbaddr_led => + irb_dout(r.led'range) := r.led; + + when rbaddr_dp => + irb_dout(r.dsp_dp'range) := r.dsp_dp; + + when rbaddr_dsp0 => + irb_dout := r.dsp_dat(dspdat_lsb); + + when rbaddr_dsp1 => + irb_dout := r.dsp_dat(dspdat_msb); + + when others => null; + end case; + + end if; + + N_REGS <= n; + + BTN <= R_REGS.btn; + SWI <= R_REGS.swi; + + RB_SRES <= rb_sres_init; + RB_SRES.ack <= irb_ack; + RB_SRES.busy <= irb_busy; + RB_SRES.err <= irb_err; + RB_SRES.dout <= irb_dout; + + end process proc_next; + +end syn; diff --git a/rtl/bplib/bpgen/sn_humanio_rbus.vhd b/rtl/bplib/bpgen/sn_humanio_rbus.vhd index f92a31a0..e7d269d9 100644 --- a/rtl/bplib/bpgen/sn_humanio_rbus.vhd +++ b/rtl/bplib/bpgen/sn_humanio_rbus.vhd @@ -1,6 +1,6 @@ --- $Id: sn_humanio_rbus.vhd 640 2015-02-01 09:56:53Z mueller $ +-- $Id: sn_humanio_rbus.vhd 912 2017-06-11 18:30:03Z mueller $ -- --- Copyright 2010-2015 by Walter F.J. Mueller +-- Copyright 2010-2017 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,7 +20,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31 +-- Tool versions: ise 11.4-14.7; viv 2014.4-2017.1; ghdl 0.26-0.34 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -34,6 +34,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2017-06-11 912 2.0.1 add stat_rbf_emu (=0); single cycle btn pulses -- 2015-01-31 640 2.0 add SWIDTH,LWIDTH,DCWIDTH, change register layout -- 2014-08-15 583 1.3 rb_mreq addr now 16 bit -- 2011-11-19 427 1.2.1 now numeric_std clean @@ -49,6 +50,7 @@ -- -- Addr Bits Name r/w/f Function -- 000 stat r/-/- Status register +-- 15 emu r/-/- emulation (always 0) -- 14:12 hdig r/-/- display size as (2**DCWIDTH)-1 -- 11:08 hled r/-/- led size as LWIDTH-1 -- 7:04 hbtn r/-/- button size as BWIDTH-1 @@ -163,6 +165,7 @@ architecture syn of sn_humanio_rbus is signal R_REGS : regs_type := regs_init; -- state registers signal N_REGS : regs_type := regs_init; -- next value state regs + constant stat_rbf_emu: integer := 15; subtype stat_rbf_hdig is integer range 14 downto 12; subtype stat_rbf_hled is integer range 11 downto 8; subtype stat_rbf_hbtn is integer range 7 downto 4; @@ -270,7 +273,9 @@ begin -- input register for LED signal n.ledin := LED; - + -- clear btn register --> cause single cycle pulses + n.btn := (others=>'0'); + -- rbus address decoder n.rbsel := '0'; if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 3)=RB_ADDR(15 downto 3) then @@ -284,6 +289,7 @@ begin case RB_MREQ.addr(2 downto 0) is when rbaddr_stat => + irb_dout(stat_rbf_emu) := '0'; irb_dout(stat_rbf_hdig) := slv(to_unsigned((2**DCWIDTH)-1,3)); irb_dout(stat_rbf_hled) := slv(to_unsigned(LWIDTH-1,4)); irb_dout(stat_rbf_hbtn) := slv(to_unsigned(BWIDTH-1,4)); diff --git a/rtl/bplib/cmoda7/c7_sram_memctl.vbom b/rtl/bplib/cmoda7/c7_sram_memctl.vbom new file mode 100644 index 00000000..8c713e07 --- /dev/null +++ b/rtl/bplib/cmoda7/c7_sram_memctl.vbom @@ -0,0 +1,9 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/xlib/xlib.vhd +# components +../../vlib/xlib/iob_reg_o.vbom +../../vlib/xlib/iob_reg_o_gen.vbom +../../vlib/xlib/iob_reg_io_gen.vbom +# design +c7_sram_memctl.vhd diff --git a/rtl/bplib/cmoda7/c7_sram_memctl.vhd b/rtl/bplib/cmoda7/c7_sram_memctl.vhd new file mode 100644 index 00000000..c3b52fd4 --- /dev/null +++ b/rtl/bplib/cmoda7/c7_sram_memctl.vhd @@ -0,0 +1,382 @@ +-- $Id: c7_sram_memctl.vhd 914 2017-06-25 06:17:18Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: c7_sram_memctl - syn +-- Description: Cmod A7 SRAM controller +-- +-- Dependencies: vlib/xlib/iob_reg_o +-- vlib/xlib/iob_reg_o_gen +-- vlib/xlib/iob_reg_io_gen +-- +-- Test bench: tb/tb_c7_sram_memctl +-- fw_gen/tst_sram/cmoda7/tb/tb_tst_sram_c7 +-- +-- Target Devices: generic +-- Tool versions: viv 2017.1; ghdl 0.34 +-- +-- Synthesized (viv): +-- Date Rev viv Target flop lutl lutm bram slic +-- 2017-06-11 xxx 2017.1 xc7a35t-1 x x x 0 x +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-19 914 1.0 Initial version +-- 2017-06-11 912 0.5 First draft +-- +-- Timing of some signals: +-- +-- single read request: +-- +-- state |_idle |_read |_idle | +-- +-- CLK __|^^^|___|^^^|___|^^^|___|^ +-- +-- REQ _______|^^^^^|______________ +-- WE ____________________________ +-- +-- IOB_CE __________|^^^^^^^|_________ +-- IOB_OE __________|^^^^^^^|_________ +-- +-- DO oooooooooooooooooo|ddddddd|d +-- BUSY ____________________________ +-- ACK_R __________________|^^^^^^^|_ +-- +-- single write request: +-- +-- state |_idle |_write1|_write2|_idle | +-- +-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^ +-- +-- REQ _______|^^^^^|______________ +-- WE _______|^^^^^|______________ +-- +-- IOB_CE __________|^^^^^^^^^^^^^^^|_________ +-- IOB_BE __________|^^^^^^^^^^^^^^^|_________ +-- IOB_OE ____________________________________ +-- IOB_WE ______________|^^^^^^^|_____________ +-- +-- BUSY __________|^^^^^^^|_________________ +-- ACK_W __________________|^^^^^^^|_________ +-- +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; + +entity c7_sram_memctl is -- SRAM controller for Cmod A7 + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + REQ : in slbit; -- request + WE : in slbit; -- write enable + BUSY : out slbit; -- controller busy + ACK_R : out slbit; -- acknowledge read + ACK_W : out slbit; -- acknowledge write + ACT_R : out slbit; -- signal active read + ACT_W : out slbit; -- signal active write + ADDR : in slv17; -- address + BE : in slv4; -- byte enable + DI : in slv32; -- data in (memory view) + DO : out slv32; -- data out (memory view) + O_MEM_CE_N : out slbit; -- sram: chip enable (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv19; -- sram: address lines + IO_MEM_DATA : inout slv8 -- sram: data lines + ); +end c7_sram_memctl; + + +architecture syn of c7_sram_memctl is + + type state_type is ( + s_idle, -- s_idle: wait for req + s_read0, -- s_read0: read cycle, 1st half + s_read1, -- s_read1: read cycle, 2nd half + s_write0, -- s_write0: write cycle, 1st half + s_write1 -- s_write1: write cycle, 2nd half + ); + + type regs_type is record + state : state_type; -- state + addrb : slv2; -- byte address + be : slv4; -- be pending + memdi : slv32; -- MEM_DI buffer + memdo : slv24; -- MEM_DO buffer for byte 0,1,2 + ackr : slbit; -- signal ack_r + end record regs_type; + + constant regs_init : regs_type := ( + s_idle, -- state + "00", -- addrb + "0000", -- be + (others=>'0'), -- memdi + (others=>'0'), -- memdo + '0' -- ackr + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + signal CLK_180 : slbit := '0'; + signal MEM_CE_N : slbit := '0'; + signal MEM_WE_N : slbit := '0'; + signal MEM_OE_N : slbit := '0'; + signal MEM_DI : slv8 := "00000000"; + signal MEM_DO : slv8 := "00000000"; + signal ADDRB : slv2 := "00"; + signal ADDRW_CE : slbit := '0'; + signal ADDRB_CE : slbit := '0'; + signal DATA_CEI : slbit := '0'; + signal DATA_CEO : slbit := '0'; + signal DATA_OE : slbit := '0'; + +begin + + CLK_180 <= not CLK; + + IOB_MEM_CE : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => CLK, + CE => '1', + DO => MEM_CE_N, + PAD => O_MEM_CE_N + ); + + IOB_MEM_WE : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => CLK_180, + CE => '1', + DO => MEM_WE_N, + PAD => O_MEM_WE_N + ); + + IOB_MEM_OE : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => CLK, + CE => '1', + DO => MEM_OE_N, + PAD => O_MEM_OE_N + ); + + IOB_MEM_ADDRW : iob_reg_o_gen + generic map ( + DWIDTH => 17) + port map ( + CLK => CLK, + CE => ADDRW_CE, + DO => ADDR, + PAD => O_MEM_ADDR(18 downto 2) + ); + + IOB_MEM_ADDRB : iob_reg_o_gen + generic map ( + DWIDTH => 2) + port map ( + CLK => CLK, + CE => ADDRB_CE, + DO => ADDRB, + PAD => O_MEM_ADDR(1 downto 0) + ); + + IOB_MEM_DATA : iob_reg_io_gen + generic map ( + DWIDTH => 8, + PULL => "NONE") + port map ( + CLK => CLK, + CEI => DATA_CEI, + CEO => DATA_CEO, + OE => DATA_OE, + DI => MEM_DO, + DO => MEM_DI, + PAD => IO_MEM_DATA + ); + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, REQ, WE, BE, MEM_DO, DI) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + variable ibusy : slbit := '0'; + variable iackw : slbit := '0'; + variable iactr : slbit := '0'; + variable iactw : slbit := '0'; + variable imem_ce : slbit := '0'; + variable imem_we : slbit := '0'; + variable imem_oe : slbit := '0'; + variable iaddrw_ce : slbit := '0'; + variable iaddrb : slv2 := "00"; + variable iaddrb_be : slv2 := "00"; + variable iaddrb_ce : slbit := '0'; + variable idata_cei : slbit := '0'; + variable idata_ceo : slbit := '0'; + variable idata_oe : slbit := '0'; + variable imem_di : slv8 := "00000000"; + + begin + + r := R_REGS; + n := R_REGS; + n.ackr := '0'; + + ibusy := '0'; + iackw := '0'; + iactr := '0'; + iactw := '0'; + + imem_ce := '0'; + imem_we := '0'; + imem_oe := '0'; + iaddrw_ce := '0'; + iaddrb := "00"; + iaddrb_be := "00"; + iaddrb_ce := '0'; + idata_cei := '0'; + idata_ceo := '0'; + idata_oe := '0'; + + imem_di := "00000000"; + if r.be(0) = '1' then + iaddrb_be := "00"; + imem_di := r.memdi( 7 downto 0); + elsif r.be(1) = '1' then + iaddrb_be := "01"; + imem_di := r.memdi(15 downto 8); + elsif r.be(2) = '1' then + iaddrb_be := "10"; + imem_di := r.memdi(23 downto 16); + elsif r.be(3) = '1' then + iaddrb_be := "11"; + imem_di := r.memdi(31 downto 24); + end if; + + case r.state is + when s_idle => -- s_idle: wait for req + if REQ = '1' then -- if IO requested + if WE = '0' then -- if READ requested + iaddrw_ce := '1'; -- latch word address + iaddrb_ce := '1'; -- latch byte address (use 0) + imem_ce := '1'; -- ce SRAM next cycle + imem_oe := '1'; -- oe SRAM next cycle + n.state := s_read0; -- next: read0 + else -- if WRITE requested + iaddrw_ce := '1'; -- latch word address + n.be := BE; -- latch pending BEs + n.memdi := DI; -- latch data + n.state := s_write1; -- next: write 2nd part + end if; + end if; + + when s_read0 => -- s_read0: read cycle, 1st half + ibusy := '1'; -- signal busy, unable to handle req + iactr := '1'; -- signal mem read + imem_ce := '1'; -- ce SRAM next cycle + imem_oe := '1'; -- oe SRAM next cycle + case r.addrb is -- capture last byte; inc byte count + when "00" => n.addrb := "01"; + when "01" => n.addrb := "10"; n.memdo( 7 downto 0) := MEM_DO; + when "10" => n.addrb := "11"; n.memdo(15 downto 8) := MEM_DO; + when "11" => n.addrb := "00"; n.memdo(23 downto 16) := MEM_DO; + when others => null; + end case; + n.state := s_read1; -- next: read1 + + when s_read1 => -- s_read1: read cycle, 2nd half + ibusy := '1'; -- signal busy, unable to handle req + iactr := '1'; -- signal mem read + imem_ce := '1'; -- ce SRAM next cycle + imem_oe := '1'; -- oe SRAM next cycle + idata_cei := '1'; -- latch input data + if r.addrb = "00" then -- last byte seen (counter wrapped) ? + n.ackr := '1'; -- ACK_R next cycle + n.state := s_idle; + else -- more bytes to do ? + iaddrb := r.addrb; -- use addrb counter + iaddrb_ce := '1'; -- latch byte address (use r.addrb) + n.state := s_read0; + end if; + + when s_write0 => -- s_write0: write cycle, 1st half + ibusy := '1'; -- signal busy, unable to handle req + iactw := '1'; -- signal mem write + idata_oe := '1'; -- oe FPGA next cycle + imem_ce := '1'; -- ce SRAM next cycle + imem_we := '1'; -- we SRAM next shifted cycle + n.state := s_write1; -- next: write cycle, 2nd half + + when s_write1 => -- s_write1: write cycle, 2nd half + ibusy := '1'; -- signal busy, unable to handle req + iactw := '1'; -- signal mem write + idata_oe := '1'; -- oe FPGA next cycle + imem_ce := '1'; -- ce SRAM next cycle + if r.be = "0000" then -- all done ? + iackw := '1'; -- signal write acknowledge + n.state := s_idle; -- next: idle + else -- more to do ? + idata_ceo := '1'; -- latch output data (to SRAM) + iaddrb := iaddrb_be; -- use addrb from be encode + iaddrb_ce := '1'; -- latch byte address (use iaddr_be) + n.be(to_integer(unsigned(iaddrb_be))) := '0'; -- mark byte done + n.state := s_write0; -- next: write 1st half + end if; + + when others => null; + end case; + + N_REGS <= n; + + MEM_CE_N <= not imem_ce; + MEM_WE_N <= not imem_we; + MEM_OE_N <= not imem_oe; + MEM_DI <= imem_di; + ADDRW_CE <= iaddrw_ce; + ADDRB <= iaddrb; + ADDRB_CE <= iaddrb_ce; + DATA_CEI <= idata_cei; + DATA_CEO <= idata_ceo; + DATA_OE <= idata_oe; + + BUSY <= ibusy; + ACK_R <= r.ackr; + ACK_W <= iackw; + ACT_R <= iactr; + ACT_W <= iactw; + DO <= MEM_DO & r.memdo; + + end process proc_next; + +end syn; diff --git a/rtl/bplib/cmoda7/cmoda7_pclk.xdc b/rtl/bplib/cmoda7/cmoda7_pclk.xdc new file mode 100644 index 00000000..90a97a9d --- /dev/null +++ b/rtl/bplib/cmoda7/cmoda7_pclk.xdc @@ -0,0 +1,14 @@ +# -*- tcl -*- +# $Id: cmoda7_pclk.xdc 906 2017-06-04 21:59:13Z mueller $ +# +# Copyright 2017- by Walter F.J. Mueller +# License disclaimer see License.txt in $RETROBASE directory +# +# Primary clocks for Digilent CmodA7 +# +# Revision History: +# Date Rev Version Comment +# 2017-06-04 906 1.0 Initial version +# + +create_clock -name I_CLK12 -period 83.33 -waveform {0 41.66} [get_ports I_CLK12] diff --git a/rtl/bplib/cmoda7/cmoda7_pins.xdc b/rtl/bplib/cmoda7/cmoda7_pins.xdc new file mode 100644 index 00000000..0caa691c --- /dev/null +++ b/rtl/bplib/cmoda7/cmoda7_pins.xdc @@ -0,0 +1,62 @@ +# -*- tcl -*- +# $Id: cmoda7_pins.xdc 906 2017-06-04 21:59:13Z mueller $ +# +# Copyright 2017- by Walter F.J. Mueller +# License disclaimer see License.txt in $RETROBASE directory +# +# Digilent CmodA7 core functionality +# - Configuration setup +# - config voltage +# - enable bitstream timestamp +# - Pin Locks for +# - USB UART +# - human I/O (sbuttons, leds) +# +# Revision History: +# Date Rev Version Comment +# 2017-06-04 906 1.0 Initial version +# + +# config setup -------------------------------------------------------------- +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] + +# clocks -- in bank 14 ------------------------------------------------------ +set_property PACKAGE_PIN l17 [get_ports {I_CLK12}] +set_property IOSTANDARD LVCMOS33 [get_ports {I_CLK12}] + +# +# USB UART Interface -- in bank 14 ------------------------------------------ +set_property PACKAGE_PIN j17 [get_ports {I_RXD}] +set_property PACKAGE_PIN j18 [get_ports {O_TXD}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_RXD O_TXD}] +set_property DRIVE 12 [get_ports {O_TXD}] +set_property SLEW SLOW [get_ports {O_TXD}] + +# +# buttons -- in bank 16 ----------------------------------------------------- +set_property PACKAGE_PIN a18 [get_ports {I_BTN[0]}] +set_property PACKAGE_PIN b18 [get_ports {I_BTN[1]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_BTN[*]}] + +# +# LEDs -- in bank 16 -------------------------------------------------------- +set_property PACKAGE_PIN a17 [get_ports {O_LED[0]}] +set_property PACKAGE_PIN c16 [get_ports {O_LED[1]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_LED[*]}] +set_property DRIVE 12 [get_ports {O_LED[*]}] +set_property SLEW SLOW [get_ports {O_LED[*]}] + +# +# RGB-LED -- in bank 16 ----------------------------------------------------- +set_property PACKAGE_PIN c17 [get_ports {O_RGBLED0_N[0]}] +set_property PACKAGE_PIN b16 [get_ports {O_RGBLED0_N[1]}] +set_property PACKAGE_PIN b17 [get_ports {O_RGBLED0_N[2]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_RGBLED0_N[*]}] +set_property DRIVE 12 [get_ports {O_RGBLED0_N[*]}] +set_property SLEW SLOW [get_ports {O_RGBLED0_N[*]}] diff --git a/rtl/bplib/cmoda7/cmoda7_pins_sram.xdc b/rtl/bplib/cmoda7/cmoda7_pins_sram.xdc new file mode 100644 index 00000000..6aa614e4 --- /dev/null +++ b/rtl/bplib/cmoda7/cmoda7_pins_sram.xdc @@ -0,0 +1,62 @@ +# -*- tcl -*- +# $Id: cmoda7_pins_sram.xdc 906 2017-06-04 21:59:13Z mueller $ +# +# Copyright 2017- by Walter F.J. Mueller +# License disclaimer see License.txt in $RETROBASE directory +# +# Pin locks for CmodA7 sram +# +# Revision History: +# Date Rev Version Comment +# 2017-06-04 906 1.0 Initial version +# + +# SRAM -- in bank 14 -------------------------------------------------------- +set_property PACKAGE_PIN n19 [get_ports {O_MEM_CE_N}] +set_property PACKAGE_PIN r19 [get_ports {O_MEM_WE_N}] +set_property PACKAGE_PIN p19 [get_ports {O_MEM_OE_N}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_MEM_CE_N O_MEM_WE_N O_MEM_OE_N}] +set_property DRIVE 12 [get_ports {O_MEM_CE_N O_MEM_WE_N O_MEM_OE_N}] +set_property SLEW FAST [get_ports {O_MEM_CE_N O_MEM_WE_N O_MEM_OE_N}] + +# +set_property PACKAGE_PIN m18 [get_ports {O_MEM_ADDR[0]}] +set_property PACKAGE_PIN m19 [get_ports {O_MEM_ADDR[1]}] +set_property PACKAGE_PIN k17 [get_ports {O_MEM_ADDR[2]}] +set_property PACKAGE_PIN n17 [get_ports {O_MEM_ADDR[3]}] +set_property PACKAGE_PIN p17 [get_ports {O_MEM_ADDR[4]}] +set_property PACKAGE_PIN p18 [get_ports {O_MEM_ADDR[5]}] +set_property PACKAGE_PIN r18 [get_ports {O_MEM_ADDR[6]}] +set_property PACKAGE_PIN w19 [get_ports {O_MEM_ADDR[7]}] +set_property PACKAGE_PIN u19 [get_ports {O_MEM_ADDR[8]}] +set_property PACKAGE_PIN v19 [get_ports {O_MEM_ADDR[9]}] +set_property PACKAGE_PIN w18 [get_ports {O_MEM_ADDR[10]}] +set_property PACKAGE_PIN t17 [get_ports {O_MEM_ADDR[11]}] +set_property PACKAGE_PIN t18 [get_ports {O_MEM_ADDR[12]}] +set_property PACKAGE_PIN u17 [get_ports {O_MEM_ADDR[13]}] +set_property PACKAGE_PIN u18 [get_ports {O_MEM_ADDR[14]}] +set_property PACKAGE_PIN v16 [get_ports {O_MEM_ADDR[15]}] +set_property PACKAGE_PIN w16 [get_ports {O_MEM_ADDR[16]}] +set_property PACKAGE_PIN w17 [get_ports {O_MEM_ADDR[17]}] +set_property PACKAGE_PIN v15 [get_ports {O_MEM_ADDR[18]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_MEM_ADDR[*]}] +set_property DRIVE 8 [get_ports {O_MEM_ADDR[*]}] +set_property SLEW FAST [get_ports {O_MEM_ADDR[*]}] + +# +set_property PACKAGE_PIN w15 [get_ports {IO_MEM_DATA[0]}] +set_property PACKAGE_PIN w13 [get_ports {IO_MEM_DATA[1]}] +set_property PACKAGE_PIN w14 [get_ports {IO_MEM_DATA[2]}] +set_property PACKAGE_PIN u15 [get_ports {IO_MEM_DATA[3]}] +set_property PACKAGE_PIN u16 [get_ports {IO_MEM_DATA[4]}] +set_property PACKAGE_PIN v13 [get_ports {IO_MEM_DATA[5]}] +set_property PACKAGE_PIN v14 [get_ports {IO_MEM_DATA[6]}] +set_property PACKAGE_PIN u14 [get_ports {IO_MEM_DATA[7]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {IO_MEM_DATA[*]}] +set_property DRIVE 8 [get_ports {IO_MEM_DATA[*]}] +set_property SLEW SLOW [get_ports {IO_MEM_DATA[*]}] +set_property KEEPER true [get_ports {IO_MEM_DATA[*]}] +# diff --git a/rtl/bplib/cmoda7/cmoda7_setup.tcl b/rtl/bplib/cmoda7/cmoda7_setup.tcl new file mode 100644 index 00000000..82203c52 --- /dev/null +++ b/rtl/bplib/cmoda7/cmoda7_setup.tcl @@ -0,0 +1,4 @@ +# $Id: cmoda7_setup.tcl 906 2017-06-04 21:59:13Z mueller $ +# +set rvtb_part "xc7a35tcpg236-1" +set rvtb_board "cmoda7" diff --git a/rtl/bplib/cmoda7/cmoda7lib.vhd b/rtl/bplib/cmoda7/cmoda7lib.vhd new file mode 100644 index 00000000..1d3078e0 --- /dev/null +++ b/rtl/bplib/cmoda7/cmoda7lib.vhd @@ -0,0 +1,84 @@ +-- $Id: cmoda7lib.vhd 912 2017-06-11 18:30:03Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: cmoda7lib +-- Description: CmodA7 components +-- +-- Dependencies: - +-- Tool versions: viv 2016.4-2017.1; ghdl 0.34 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-11 912 1.1 add c7_sram_memctl +-- 2017-06-04 906 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package cmoda7lib is + +component cmoda7_aif is -- CmodA7, abstract iface, base + port ( + I_CLK12 : in slbit; -- 12 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_BTN : in slv2; -- c7 buttons + O_LED : out slv2; -- c7 leds + O_RGBLED0_N: out slv3 -- c7 rgb-led 0 (act.low) + ); +end component; + +component cmoda7_sram_aif is -- CmodA7, abstract iface, base+sram + port ( + I_CLK12 : in slbit; -- 12 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_BTN : in slv2; -- c7 buttons + O_LED : out slv2; -- c7 leds + O_RGBLED0_N: out slv3; -- c7 rgb-led 0 (act.low) + O_MEM_CE_N : out slbit; -- sram: chip enable (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv19; -- sram: address lines + IO_MEM_DATA : inout slv8 -- sram: data lines + ); +end component; + +component c7_sram_memctl is -- SRAM controller + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + REQ : in slbit; -- request + WE : in slbit; -- write enable + BUSY : out slbit; -- controller busy + ACK_R : out slbit; -- acknowledge read + ACK_W : out slbit; -- acknowledge write + ACT_R : out slbit; -- signal active read + ACT_W : out slbit; -- signal active write + ADDR : in slv17; -- address + BE : in slv4; -- byte enable + DI : in slv32; -- data in (memory view) + DO : out slv32; -- data out (memory view) + O_MEM_CE_N : out slbit; -- sram: chip enable (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv19; -- sram: address lines + IO_MEM_DATA : inout slv8 -- sram: data lines + ); +end component; + +end package cmoda7lib; diff --git a/rtl/bplib/cmoda7/tb/.gitignore b/rtl/bplib/cmoda7/tb/.gitignore new file mode 100644 index 00000000..e16cba56 --- /dev/null +++ b/rtl/bplib/cmoda7/tb/.gitignore @@ -0,0 +1,4 @@ +tb_cmoda7_dummy +tb_cmoda7_sram_dummy +tb_c7_sram_memctl +tb_c7_sram_memctl_stim diff --git a/rtl/bplib/cmoda7/tb/Makefile b/rtl/bplib/cmoda7/tb/Makefile new file mode 100644 index 00000000..d7cb17ac --- /dev/null +++ b/rtl/bplib/cmoda7/tb/Makefile @@ -0,0 +1,42 @@ +# $Id: Makefile 912 2017-06-11 18:30:03Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-06-11 912 1.1 add tb_c7_sram_memctl +# 2017-06-04 906 1.0 Initial version +# +EXE_all = tb_cmoda7_dummy +EXE_all += tb_cmoda7_sram_dummy +EXE_all += tb_c7_sram_memctl +# +include ${RETROBASE}/rtl/make_viv/viv_default_cmoda7.mk +# +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/bplib/cmoda7/tb/cmoda7_dummy.vbom b/rtl/bplib/cmoda7/tb/cmoda7_dummy.vbom new file mode 100644 index 00000000..189d31d9 --- /dev/null +++ b/rtl/bplib/cmoda7/tb/cmoda7_dummy.vbom @@ -0,0 +1,4 @@ +# libs +../../../vlib/slvtypes.vhd +# design +cmoda7_dummy.vhd diff --git a/rtl/bplib/cmoda7/tb/cmoda7_dummy.vhd b/rtl/bplib/cmoda7/tb/cmoda7_dummy.vhd new file mode 100644 index 00000000..b6707524 --- /dev/null +++ b/rtl/bplib/cmoda7/tb/cmoda7_dummy.vhd @@ -0,0 +1,57 @@ +-- $Id: cmoda7_dummy.vhd 906 2017-06-04 21:59:13Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: cmoda7_dummy - syn +-- Description: cmoda7 minimal target (base; serport loopback) +-- +-- Dependencies: - +-- To test: tb_cmoda7 +-- Target Devices: generic +-- Tool versions: viv 2016.4; ghdl 0.34 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-04 906 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +entity cmoda7_dummy is -- CmodA7 dummy (base; loopback) + -- implements cmoda7_aif + port ( + I_CLK12 : in slbit; -- 12 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_BTN : in slv2; -- c7 buttons + O_LED : out slv2; -- c7 leds + O_RGBLED0_N : out slv3 -- c7 rgb-led 0 (act.low) + ); +end cmoda7_dummy; + +architecture syn of cmoda7_dummy is + +begin + + O_TXD <= I_RXD; -- loop back serport + + O_LED <= I_BTN; -- mirror BTN on LED + + O_RGBLED0_N(0) <= not I_BTN(0); -- mirror BTN on RGBLED 0 -> red + O_RGBLED0_N(1) <= not I_BTN(1); -- 1 -> green + O_RGBLED0_N(2) <= not (I_BTN(0) and I_BTN(1)); -- 0+1 -> white + +end syn; diff --git a/rtl/bplib/cmoda7/tb/cmoda7_sram_dummy.vbom b/rtl/bplib/cmoda7/tb/cmoda7_sram_dummy.vbom new file mode 100644 index 00000000..85fc7437 --- /dev/null +++ b/rtl/bplib/cmoda7/tb/cmoda7_sram_dummy.vbom @@ -0,0 +1,5 @@ +# libs +../../../vlib/slvtypes.vhd +# components +# design +cmoda7_sram_dummy.vhd diff --git a/rtl/bplib/cmoda7/tb/cmoda7_sram_dummy.vhd b/rtl/bplib/cmoda7/tb/cmoda7_sram_dummy.vhd new file mode 100644 index 00000000..bc5506b3 --- /dev/null +++ b/rtl/bplib/cmoda7/tb/cmoda7_sram_dummy.vhd @@ -0,0 +1,68 @@ +-- $Id: cmoda7_sram_dummy.vhd 906 2017-06-04 21:59:13Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: cmoda7_sram_dummy - syn +-- Description: cmoda7 target (base; serport loopback, sram protect) +-- +-- Dependencies: - +-- To test: tb_cmoda7_sram +-- Target Devices: generic +-- Tool versions: viv 2016.4; ghdl 0.34 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-04 906 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +entity cmoda7_sram_dummy is -- CmodA7 dummy (base+sram) + -- implements cmoda7_sram_aif + port ( + I_CLK12 : in slbit; -- 12 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_BTN : in slv2; -- c7 buttons + O_LED : out slv2; -- c7 leds + O_RGBLED0_N : out slv3; -- c7 rgb-led 0 (act.low) + O_MEM_CE_N : out slbit; -- sram: chip enable (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv19; -- sram: address lines + IO_MEM_DATA : inout slv8 -- sram: data lines + ); +end cmoda7_sram_dummy; + +architecture syn of cmoda7_sram_dummy is + +begin + + O_TXD <= I_RXD; -- loop back serport + + O_LED <= I_BTN; -- mirror BTN on LED + + O_RGBLED0_N(0) <= not I_BTN(0); -- mirror BTN on RGBLED 0 -> red + O_RGBLED0_N(1) <= not I_BTN(1); -- 1 -> green + O_RGBLED0_N(2) <= not (I_BTN(0) and I_BTN(1)); -- 0+1 -> white + + O_MEM_CE_N <= '1'; + O_MEM_WE_N <= '1'; + O_MEM_OE_N <= '1'; + O_MEM_ADDR <= (others=>'0'); + IO_MEM_DATA <= (others=>'Z'); + +end syn; diff --git a/rtl/bplib/cmoda7/tb/sys_conf_sim.vhd b/rtl/bplib/cmoda7/tb/sys_conf_sim.vhd new file mode 100644 index 00000000..c646f86d --- /dev/null +++ b/rtl/bplib/cmoda7/tb/sys_conf_sim.vhd @@ -0,0 +1,54 @@ +-- $Id: sys_conf_sim.vhd 906 2017-06-04 21:59:13Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for tb_cmoda7_dummy (for simulation) +-- +-- Dependencies: - +-- Tool versions: viv 2016.4; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-04 906 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 60; -- vco 720 MHz + constant sys_conf_clksys_outdivide : positive := 9; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 60; -- vco 720 MHz + constant sys_conf_clkser_outdivide : positive := 6; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "MMCM"; + + -- derived constants + + constant sys_conf_clksys : integer := + ((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; + diff --git a/rtl/bplib/cmoda7/tb/tb_cmoda7.vbom b/rtl/bplib/cmoda7/tb/tb_cmoda7.vbom new file mode 100644 index 00000000..66e1aa1b --- /dev/null +++ b/rtl/bplib/cmoda7/tb/tb_cmoda7.vbom @@ -0,0 +1,24 @@ +# Not meant for direct top level usage. Used with +# tb_cmoda7_(....)[_ssim].vbom and config +# lines to generate the different cases. +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/rlink/rlinklib.vbom +../../../vlib/xlib/xlib.vhd +../cmoda7lib.vhd +../../../vlib/simlib/simlib.vhd +../../../vlib/simlib/simbus.vhd +${sys_conf := sys_conf_sim.vhd} +# components +${gsr_pulse := ../../../vlib/xlib/gsr_pulse_dummy.vbom} +../../../vlib/simlib/simclk.vbom +../../../vlib/simlib/simclkcnt.vbom +../../../vlib/rlink/tbcore/tbcore_rlink.vbom +../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom +tb_cmoda7_core.vbom +../../../vlib/serport/tb/serport_master_tb.vbom +${cmoda7_aif := cmoda7_dummy.vbom} -UUT +# design +tb_cmoda7.vhd +@top:tb_cmoda7 diff --git a/rtl/bplib/cmoda7/tb/tb_cmoda7.vhd b/rtl/bplib/cmoda7/tb/tb_cmoda7.vhd new file mode 100644 index 00000000..35caf96e --- /dev/null +++ b/rtl/bplib/cmoda7/tb/tb_cmoda7.vhd @@ -0,0 +1,190 @@ +-- $Id: tb_cmoda7.vhd 906 2017-06-04 21:59:13Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_cmoda7 - sim +-- Description: Test bench for cmoda7 (base) +-- +-- Dependencies: simlib/simclk +-- simlib/simclkcnt +-- rlink/tbcore/tbcore_rlink +-- xlib/tb/s7_cmt_sfs_tb +-- tb_basys3_core +-- serport/tb/serport_master_tb +-- cmoda7_aif [UUT] +-- +-- To test: generic, any cmoda7_aif target +-- +-- Target Devices: generic +-- Tool versions: viv 2016.4; ghdl 0.34 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-04 906 1.0 Initial version (derived from tb_arty) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.rlinklib.all; +use work.xlib.all; +use work.cmoda7lib.all; +use work.simlib.all; +use work.simbus.all; +use work.sys_conf.all; + +entity tb_cmoda7 is +end tb_cmoda7; + +architecture sim of tb_cmoda7 is + + signal CLKOSC : slbit := '0'; -- board clock (12 Mhz) + signal CLKCOM : slbit := '0'; -- communication clock + + signal CLKCOM_CYCLE : integer := 0; + + signal RESET : slbit := '0'; + signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !! + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXERR : slbit := '0'; + signal RXACT : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_BTN : slv2 := (others=>'0'); + signal O_LED : slv2 := (others=>'0'); + signal O_RGBLED0_N : slv3 := (others=>'0'); + + signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff + + constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); + + constant clock_period : Delay_length := 83.333 ns; + constant clock_offset : Delay_length := 2000 ns; + +begin + + GINIT : entity work.gsr_pulse; + + CLKGEN : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLKOSC + ); + + CLKGEN_COM : entity work.s7_cmt_sfs_tb + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide, + CLKIN_PERIOD => 83.3, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clkser_gentype) + port map ( + CLKIN => CLKOSC, + CLKFX => CLKCOM, + LOCKED => open + ); + + CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); + + TBCORE : entity work.tbcore_rlink + port map ( + CLK => CLKCOM, + RX_DATA => TXDATA, + RX_VAL => TXENA, + RX_HOLD => TXBUSY, + TX_DATA => RXDATA, + TX_ENA => RXVAL + ); + + C7CORE : entity work.tb_cmoda7_core + port map ( + I_BTN => I_BTN + ); + + UUT : cmoda7_aif + port map ( + I_CLK12 => CLKOSC, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_BTN => I_BTN, + O_LED => O_LED, + O_RGBLED0_N => O_RGBLED0_N + ); + + SERMSTR : entity work.serport_master_tb + generic map ( + CDWIDTH => CLKDIV'length) + port map ( + CLK => CLKCOM, + RESET => RESET, + CLKDIV => CLKDIV, + ENAXON => R_PORTSEL_XON, + ENAESC => '0', + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXOK => '1', + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + RXSD => O_TXD, + TXSD => I_RXD, + RXRTS_N => open, + TXCTS_N => '0' + ); + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLKCOM); + + if RXERR = '1' then + writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1"); + writeline(output, oline); + end if; + + end loop; + + end process proc_moni; + + -- + -- Notes on portsel and XON control: + -- - most cmoda7 designs will use hardwired XON=1 + -- - but some (especially basis tests) might not use flow control + -- - that's why XON flow control must be optional and configurable ! + -- + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_portsel then + R_PORTSEL_XON <= to_x01(SB_DATA(1)); + end if; + end if; + end process proc_simbus; + +end sim; diff --git a/rtl/bplib/cmoda7/tb/tb_cmoda7_core.vbom b/rtl/bplib/cmoda7/tb/tb_cmoda7_core.vbom new file mode 100644 index 00000000..808ee4df --- /dev/null +++ b/rtl/bplib/cmoda7/tb/tb_cmoda7_core.vbom @@ -0,0 +1,6 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/simlib/simbus.vhd +# components +# design +tb_cmoda7_core.vhd diff --git a/rtl/bplib/cmoda7/tb/tb_cmoda7_core.vhd b/rtl/bplib/cmoda7/tb/tb_cmoda7_core.vhd new file mode 100644 index 00000000..b0375a71 --- /dev/null +++ b/rtl/bplib/cmoda7/tb/tb_cmoda7_core.vhd @@ -0,0 +1,63 @@ +-- $Id: tb_cmoda7_core.vhd 906 2017-06-04 21:59:13Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_cmoda7_core - sim +-- Description: Test bench for cmoda7 - core device handling +-- +-- Dependencies: - +-- +-- To test: generic, any cmoda7 target +-- +-- Target Devices: generic +-- Tool versions: viv 2016.4; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-04 906 1.0 Initial version (derived from tb_arty_core) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.simbus.all; + +entity tb_cmoda7_core is + port ( + I_BTN : out slv2 -- c7 buttons + ); +end tb_cmoda7_core; + +architecture sim of tb_cmoda7_core is + + signal R_BTN : slv2 := (others=>'0'); + + constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8)); + +begin + + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_btn then + R_BTN <= to_x01(SB_DATA(R_BTN'range)); + end if; + end if; + end process proc_simbus; + + I_BTN <= R_BTN; + +end sim; diff --git a/rtl/bplib/cmoda7/tb/tb_cmoda7_sram.vbom b/rtl/bplib/cmoda7/tb/tb_cmoda7_sram.vbom new file mode 100644 index 00000000..c8a9f626 --- /dev/null +++ b/rtl/bplib/cmoda7/tb/tb_cmoda7_sram.vbom @@ -0,0 +1,25 @@ +# Not meant for direct top level usage. Used with +# tb_cmoda7_(....)[_ssim].vbom and config +# lines to generate the different cases. +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/rlink/rlinklib.vbom +../../../vlib/xlib/xlib.vhd +../cmoda7lib.vhd +../../../vlib/simlib/simlib.vhd +../../../vlib/simlib/simbus.vhd +${sys_conf := sys_conf_sim.vhd} +# components +../../../vlib/simlib/simclk.vbom +../../../vlib/simlib/simclkcnt.vbom +../../../vlib/rlink/tbcore/tbcore_rlink.vbom +../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom +tb_cmoda7_core.vbom +../../../vlib/simlib/simbididly.vbom +../../issi/is61wv5128bll.vbom +../../../vlib/serport/tb/serport_master_tb.vbom +${cmoda7_sram_aif := cmoda7_sram_dummy.vbom} -UUT +# design +tb_cmoda7_sram.vhd +@top:tb_cmoda7_sram diff --git a/rtl/bplib/cmoda7/tb/tb_cmoda7_sram.vhd b/rtl/bplib/cmoda7/tb/tb_cmoda7_sram.vhd new file mode 100644 index 00000000..c506edf9 --- /dev/null +++ b/rtl/bplib/cmoda7/tb/tb_cmoda7_sram.vhd @@ -0,0 +1,230 @@ +-- $Id: tb_cmoda7_sram.vhd 906 2017-06-04 21:59:13Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_cmoda7_sram - sim +-- Description: Test bench for cmoda7 (base+sram) +-- +-- Dependencies: simlib/simclk +-- simlib/simclkcnt +-- rlink/tbcore/tbcore_rlink +-- xlib/tb/s7_cmt_sfs_tb +-- tb_cmoda7_core +-- serport/tb/serport_master_tb +-- cmoda7_sram_aif [UUT] +-- simlib/simbididly +-- bplib/issi/is61wv5128bll +-- +-- To test: generic, any cmoda7_sram_aif target +-- +-- Target Devices: generic +-- Tool versions: viv 2016.4; ghdl 0.34 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-04 906 1.0 Initial version (derived from tb_nexys4_cram) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.rlinklib.all; +use work.xlib.all; +use work.cmoda7lib.all; +use work.simlib.all; +use work.simbus.all; +use work.sys_conf.all; + +entity tb_cmoda7_sram is +end tb_cmoda7_sram; + +architecture sim of tb_cmoda7_sram is + + signal CLKOSC : slbit := '0'; -- board clock (12 Mhz) + signal CLKCOM : slbit := '0'; -- communication clock + + signal CLKCOM_CYCLE : integer := 0; + + signal RESET : slbit := '0'; + signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !! + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXERR : slbit := '0'; + signal RXACT : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_BTN : slv2 := (others=>'0'); + signal O_LED : slv2 := (others=>'0'); + signal O_RGBLED0_N : slv3 := (others=>'0'); + + signal TB_MEM_CE_N : slbit := '1'; + signal TB_MEM_WE_N : slbit := '1'; + signal TB_MEM_OE_N : slbit := '1'; + signal TB_MEM_ADDR : slv19 := (others=>'Z'); + signal TB_MEM_DATA : slv8 := (others=>'0'); + + signal MM_MEM_CE_N : slbit := '1'; + signal MM_MEM_WE_N : slbit := '1'; + signal MM_MEM_OE_N : slbit := '1'; + signal MM_MEM_ADDR : slv19 := (others=>'Z'); + signal MM_MEM_DATA : slv8 := (others=>'0'); + + signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff + + constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); + + constant clock_period : Delay_length := 83.333 ns; + constant clock_offset : Delay_length := 2000 ns; + constant pcb_delay : Delay_length := 1 ns; + +begin + + CLKGEN : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLKOSC + ); + + CLKGEN_COM : entity work.s7_cmt_sfs_tb + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide, + CLKIN_PERIOD => 83.3, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clkser_gentype) + port map ( + CLKIN => CLKOSC, + CLKFX => CLKCOM, + LOCKED => open + ); + + CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); + + TBCORE : entity work.tbcore_rlink + port map ( + CLK => CLKCOM, + RX_DATA => TXDATA, + RX_VAL => TXENA, + RX_HOLD => TXBUSY, + TX_DATA => RXDATA, + TX_ENA => RXVAL + ); + + C7CORE : entity work.tb_cmoda7_core + port map ( + I_BTN => I_BTN + ); + + UUT : cmoda7_sram_aif + port map ( + I_CLK12 => CLKOSC, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_BTN => I_BTN, + O_LED => O_LED, + O_RGBLED0_N => O_RGBLED0_N, + O_MEM_CE_N => TB_MEM_CE_N, + O_MEM_WE_N => TB_MEM_WE_N, + O_MEM_OE_N => TB_MEM_OE_N, + O_MEM_ADDR => TB_MEM_ADDR, + IO_MEM_DATA => TB_MEM_DATA + ); + + MM_MEM_CE_N <= TB_MEM_CE_N after pcb_delay; + MM_MEM_WE_N <= TB_MEM_WE_N after pcb_delay; + MM_MEM_OE_N <= TB_MEM_OE_N after pcb_delay; + MM_MEM_ADDR <= TB_MEM_ADDR after pcb_delay; + + BUSDLY: simbididly + generic map ( + DELAY => pcb_delay, + DWIDTH => 8) + port map ( + A => TB_MEM_DATA, + B => MM_MEM_DATA); + + MEM : entity work.is61wv5128bll + port map ( + CE_N => MM_MEM_CE_N, + OE_N => MM_MEM_OE_N, + WE_N => MM_MEM_WE_N, + ADDR => MM_MEM_ADDR, + DATA => MM_MEM_DATA + ); + + SERMSTR : entity work.serport_master_tb + generic map ( + CDWIDTH => CLKDIV'length) + port map ( + CLK => CLKCOM, + RESET => RESET, + CLKDIV => CLKDIV, + ENAXON => R_PORTSEL_XON, + ENAESC => '0', + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXOK => '1', + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + RXSD => O_TXD, + TXSD => I_RXD, + RXRTS_N => open, + TXCTS_N => '0' + ); + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLKCOM); + + if RXERR = '1' then + writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1"); + writeline(output, oline); + end if; + + end loop; + + end process proc_moni; + + -- + -- Notes on portsel and XON control: + -- - most cmoda7 designs will use hardwired XON=1 + -- - but some (especially basis tests) might not use flow control + -- - that's why XON flow control must be optional and configurable ! + -- + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_portsel then + R_PORTSEL_XON <= to_x01(SB_DATA(1)); + end if; + end if; + end process proc_simbus; + +end sim; diff --git a/rtl/bplib/issi/is61wv5128bll.vbom b/rtl/bplib/issi/is61wv5128bll.vbom new file mode 100644 index 00000000..25eca5ce --- /dev/null +++ b/rtl/bplib/issi/is61wv5128bll.vbom @@ -0,0 +1,5 @@ +# libs +../../vlib/slvtypes.vhd +# components +# design +is61wv5128bll.vhd diff --git a/rtl/bplib/issi/is61wv5128bll.vhd b/rtl/bplib/issi/is61wv5128bll.vhd new file mode 100644 index 00000000..2ad0e9d5 --- /dev/null +++ b/rtl/bplib/issi/is61wv5128bll.vhd @@ -0,0 +1,103 @@ +-- $Id: is61wv5128bll.vhd 906 2017-06-04 21:59:13Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: is61wv5128bll - sim +-- Description: ISSI IS61WV5128BLL SRAM model +-- Currently a truely minimalistic functional model, without +-- any timing checks. It assumes, that addr/data is stable at +-- the trailing edge of we. +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: viv 2016.4; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-04 906 1.0 Initial version (derived from is61lv25616al) +------------------------------------------------------------------------------ +-- Truth table accoring to data sheet: +-- +-- Mode WE_N CE_N OE_N D +-- Not selected X H X high-Z +-- Output disabled H L H high-Z +-- X L X high-Z +-- Read H L L D_out +-- Write L L X D_in + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; + +entity is61wv5128bll is -- ISSI 61WV5128bll SRAM model + port ( + CE_N : in slbit; -- chip enable (act.low) + OE_N : in slbit; -- output enable (act.low) + WE_N : in slbit; -- write enable (act.low) + ADDR : in slv19; -- address lines + DATA : inout slv8 -- data lines + ); +end is61wv5128bll; + + +architecture sim of is61wv5128bll is + + constant T_rc : Delay_length := 10 ns; -- read cycle time (min) + constant T_aa : Delay_length := 10 ns; -- address access time (max) + constant T_oha : Delay_length := 2 ns; -- output hold time (min) + constant T_ace : Delay_length := 10 ns; -- ce access time (max) + constant T_doe : Delay_length :=4.5 ns; -- oe access time (max) + constant T_hzoe : Delay_length := 4 ns; -- oe to high-Z output (max) + constant T_lzoe : Delay_length := 0 ns; -- oe to low-Z output (min) + constant T_hzce : Delay_length := 4 ns; -- ce to high-Z output (min=0,max=4) + constant T_lzce : Delay_length := 3 ns; -- ce to low-Z output (min) + + constant memsize : positive := 2**(ADDR'length); + constant datzero : slv(DATA'range) := (others=>'0'); + type ram_type is array (0 to memsize-1) of slv(DATA'range); + + signal CE : slbit := '0'; + signal OE : slbit := '0'; + signal WE : slbit := '0'; + signal WE_EFF : slbit := '0'; + +begin + + CE <= not CE_N; + OE <= not OE_N; + WE <= not WE_N; + + WE_EFF <= CE and WE; + + proc_sram: process (CE, OE, WE, WE_EFF, ADDR, DATA) + variable ram : ram_type := (others=>datzero); + begin + + if falling_edge(WE_EFF) then -- end of write cycle + -- note: to_x01 used below to prevent + -- that 'z' a written into mem. + ram(to_integer(unsigned(ADDR))) := to_x01(DATA); + end if; + + if CE='1' and OE='1' and WE='0' then -- output driver + DATA <= ram(to_integer(unsigned(ADDR))); + else + DATA <= (others=>'Z'); + end if; + + end process proc_sram; + +end sim; + diff --git a/rtl/bplib/issi/tb/.gitignore b/rtl/bplib/issi/tb/.gitignore index 16267050..55073a3d 100644 --- a/rtl/bplib/issi/tb/.gitignore +++ b/rtl/bplib/issi/tb/.gitignore @@ -1,2 +1,4 @@ tb_is61lv25616al tb_is61lv25616al_stim +tb_is61wv5128bll +tb_is61wv5128bll_stim diff --git a/rtl/bplib/issi/tb/Makefile b/rtl/bplib/issi/tb/Makefile index a9ffd0a2..e1eda216 100644 --- a/rtl/bplib/issi/tb/Makefile +++ b/rtl/bplib/issi/tb/Makefile @@ -1,13 +1,14 @@ -# $Id: Makefile 804 2016-08-28 17:33:50Z mueller $ +# $Id: Makefile 906 2017-06-04 21:59:13Z mueller $ # # Revision History: # Date Rev Version Comment +# 2017-06-04 906 1.3.1 add tb_is61wv5128bll # 2016-08-28 804 1.3 remove ISim, add XSim support # 2011-08-13 405 1.2 use includes from rtl/make # 2009-11-21 252 1.1 add ISim support # 2007-12-14 101 1.0 Initial version # -EXE_all = tb_is61lv25616al +EXE_all = tb_is61lv25616al tb_is61wv5128bll # # reference board for test synthesis is Artix-7 based Nexys4 diff --git a/rtl/bplib/issi/tb/tb_is61wv5128bll.vbom b/rtl/bplib/issi/tb/tb_is61wv5128bll.vbom new file mode 100644 index 00000000..c3b87934 --- /dev/null +++ b/rtl/bplib/issi/tb/tb_is61wv5128bll.vbom @@ -0,0 +1,7 @@ +# +# libs +../../../vlib/simlib/simlib.vhd +# components +../is61wv5128bll.vbom +# design +tb_is61wv5128bll.vhd diff --git a/rtl/bplib/issi/tb/tb_is61wv5128bll.vhd b/rtl/bplib/issi/tb/tb_is61wv5128bll.vhd new file mode 100644 index 00000000..6ac85014 --- /dev/null +++ b/rtl/bplib/issi/tb/tb_is61wv5128bll.vhd @@ -0,0 +1,178 @@ +-- $Id: tb_is61wv5128bll.vhd 906 2017-06-04 21:59:13Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_is61wv5128bll - sim +-- Description: Test bench for is61wv5128bll memory model +-- +-- Dependencies: is61wv5128bll [UUT] +-- +-- To test: is61wv5128bll +-- +-- Verified (with tb_is61wv5128bll_stim.dat): +-- Date Rev Code ghdl ise Target Comment +-- 2017-06-04 906 - 0.34 - - c:ok +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-04 906 1.0 Initial version (derived from tb_is61lv25616al) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.simlib.all; + +entity tb_is61wv5128bll is +end tb_is61wv5128bll; + +architecture sim of tb_is61wv5128bll is + + signal CE_N : slbit := '1'; + signal OE_N : slbit := '1'; + signal WE_N : slbit := '1'; + signal ADDR : slv19 := (others=>'0'); + signal DATA : slv8 := (others=>'0'); + +begin + + UUT : entity work.is61wv5128bll + port map ( + CE_N => CE_N, + OE_N => OE_N, + WE_N => WE_N, + ADDR => ADDR, + DATA => DATA + ); + + proc_stim: process + file fstim : text open read_mode is "tb_is61wv5128bll_stim"; + variable iline : line; + variable oline : line; + variable ok : boolean; + variable dname : string(1 to 6) := (others=>' '); + variable idtime : Delay_length := 0 ns; + variable imatch : boolean := false; + variable ival : slbit := '0'; + variable ival8 : slv8 := (others=>'0'); + variable ival19 : slv19 := (others=>'0'); + variable ice : slbit := '0'; + variable ioe : slbit := '0'; + variable iwe : slbit := '0'; + variable iaddr : slv19 := (others=>'0'); + variable idata : slv8 := (others=>'0'); + variable ide : slbit := '0'; + variable idchk : slv8 := (others=>'0'); + + begin + + file_loop: while not endfile(fstim) loop + + readline (fstim, iline); + + readcomment(iline, ok); + next file_loop when ok; + + readword(iline, dname, ok); + if ok then + case dname is + when "wdo " => -- wdo + read_ea(iline, idtime); + wait for idtime; + + readtagval_ea(iline, "ce", imatch, ival); + if imatch then ice := ival; end if; + readtagval_ea(iline, "oe", imatch, ival); + if imatch then ioe := ival; end if; + readtagval_ea(iline, "we", imatch, ival); + if imatch then iwe := ival; end if; + readtagval_ea(iline, "a", imatch, ival19, 16); + if imatch then iaddr := ival19; end if; + readtagval_ea(iline, "de", imatch, ival); + if imatch then ide := ival; end if; + readtagval_ea(iline, "d", imatch, ival8, 16); + if imatch then idata := ival8; end if; + + CE_N <= not ice; + OE_N <= not ioe; + WE_N <= not iwe; + ADDR <= iaddr; + if ide = '1' then + DATA <= idata; + else + DATA <= (others=>'Z'); + end if; + + write(oline, now, right, 12); + write(oline, string'(": wdo ")); + write(oline, string'(" ce=")); + write(oline, ice); + write(oline, string'(" oe=")); + write(oline, ioe); + write(oline, string'(" we=")); + write(oline, iwe); + write(oline, string'(" a=")); + writegen(oline, iaddr, right, 5, 16); + write(oline, string'(" de=")); + write(oline, ide); + if ide = '1' then + write(oline, string'(" d=")); + writegen(oline, idata, right, 4, 16); + end if; + + readtagval_ea(iline, "D", imatch, idchk, 16); + if imatch then + write(oline, string'(" D=")); + writegen(oline, DATA, right, 4, 16); + write(oline, string'(" CHECK")); + if DATA = idchk then + write(oline, string'(" OK")); + else + write(oline, string'(" FAIL exp=")); + writegen(oline, idchk, right, 4, 16); + end if; + end if; + + writeline(output, oline); + + when others => -- unknown command + write(oline, string'("?? unknown command: ")); + write(oline, dname); + writeline(output, oline); + report "aborting" severity failure; + end case; + + else + report "failed to find command" severity failure; + + end if; + + testempty_ea(iline); + + end loop; + + write(oline, now, right, 12); + write(oline, string'(": DONE")); + writeline(output, oline); + + wait; -- suspend proc_stim forever + -- no clock, sim will end + + end process proc_stim; + + +end sim; diff --git a/rtl/bplib/issi/tb/tb_is61wv5128bll_stim.dat b/rtl/bplib/issi/tb/tb_is61wv5128bll_stim.dat new file mode 100644 index 00000000..7c8a2d43 --- /dev/null +++ b/rtl/bplib/issi/tb/tb_is61wv5128bll_stim.dat @@ -0,0 +1,105 @@ +# $Id: tb_is61wv5128bll_stim.dat 906 2017-06-04 21:59:13Z mueller $ +# +C Write first 8 cells +# +wdo 0 ns ce=1 a=00000 de=1 d=70 +wdo 10 ns we=1 +wdo 20 ns we=0 +wdo 10 ns ce=1 a=00001 de=1 d=61 +wdo 10 ns we=1 +wdo 20 ns we=0 +wdo 10 ns ce=1 a=00002 de=1 d=52 +wdo 10 ns we=1 +wdo 20 ns we=0 +wdo 10 ns ce=1 a=00003 de=1 d=43 +wdo 10 ns we=1 +wdo 20 ns we=0 +wdo 10 ns ce=1 a=00004 de=1 d=34 +wdo 10 ns we=1 +wdo 20 ns we=0 +wdo 10 ns ce=1 a=00005 de=1 d=25 +wdo 10 ns we=1 +wdo 20 ns we=0 +wdo 10 ns ce=1 a=00006 de=1 d=16 +wdo 10 ns we=1 +wdo 20 ns we=0 +wdo 10 ns ce=1 a=00007 de=1 d=07 +wdo 10 ns we=1 +wdo 20 ns we=0 +# +wdo 10 ns de=0 +wdo 20 ns +# +C Read first 8 cells +# +wdo 20 ns oe=1 a=00000 +wdo 20 ns D=70 +wdo 0 ns oe=1 a=00001 +wdo 20 ns D=61 +wdo 0 ns oe=1 a=00002 +wdo 20 ns D=52 +wdo 0 ns oe=1 a=00003 +wdo 20 ns D=43 +wdo 0 ns oe=1 a=00004 +wdo 20 ns D=34 +wdo 0 ns oe=1 a=00005 +wdo 20 ns D=25 +wdo 0 ns oe=1 a=00006 +wdo 20 ns D=16 +wdo 0 ns oe=1 a=00007 +wdo 20 ns D=07 +# +wdo 0 ns oe=0 +wdo 20 ns +# +C Write last 8 cells +# +wdo 0 ns ce=1 a=3fff8 de=1 d=f8 +wdo 10 ns we=1 +wdo 20 ns we=0 +wdo 10 ns ce=1 a=3fff9 de=1 d=e9 +wdo 10 ns we=1 +wdo 20 ns we=0 +wdo 10 ns ce=1 a=3fffa de=1 d=da +wdo 10 ns we=1 +wdo 20 ns we=0 +wdo 10 ns ce=1 a=3fffb de=1 d=cb +wdo 10 ns we=1 +wdo 20 ns we=0 +wdo 10 ns ce=1 a=3fffc de=1 d=bc +wdo 10 ns we=1 +wdo 20 ns we=0 +wdo 10 ns ce=1 a=3fffd de=1 d=ad +wdo 10 ns we=1 +wdo 20 ns we=0 +wdo 10 ns ce=1 a=3fffe de=1 d=9e +wdo 10 ns we=1 +wdo 20 ns we=0 +wdo 10 ns ce=1 a=3ffff de=1 d=8f +wdo 10 ns we=1 +wdo 20 ns we=0 +# +wdo 10 ns de=0 +wdo 20 ns + +C Read some cells in staggered pattern +# +wdo 20 ns oe=1 a=00000 +wdo 20 ns D=70 +wdo 0 ns oe=1 a=3ffff +wdo 20 ns D=8f +wdo 0 ns oe=1 a=00002 +wdo 20 ns D=52 +wdo 0 ns oe=1 a=3fffd +wdo 20 ns D=ad +wdo 0 ns oe=1 a=00004 +wdo 20 ns D=34 +wdo 0 ns oe=1 a=3fffb +wdo 20 ns D=cb +wdo 0 ns oe=1 a=00006 +wdo 20 ns D=16 +wdo 0 ns oe=1 a=3fff9 +wdo 20 ns D=e9 +# +wdo 0 ns oe=0 +wdo 20 ns diff --git a/rtl/bplib/issi/tb/tbrun.yml b/rtl/bplib/issi/tb/tbrun.yml index a9ab3dd9..f398e2b7 100644 --- a/rtl/bplib/issi/tb/tbrun.yml +++ b/rtl/bplib/issi/tb/tbrun.yml @@ -1,13 +1,17 @@ -# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $ +# $Id: tbrun.yml 906 2017-06-04 21:59:13Z mueller $ # # Revision History: # Date Rev Version Comment +# 2017-06-04 906 1.2 add tb_is61wv5128bll # 2016-00-10 806 1.1 use nossim because no _ssim support available # 2016-08-12 797 1.0 Initial version # - default: mode: ${viv_modes_nossim} # -- tag: [default, viv, bplib, issi] +- tag: [default, ise, bplib, issi] test: | tbrun_tbw tb_is61lv25616al${ms} +- tag: [default, viv, bplib, issi] + test: | + tbrun_tbw tb_is61wv5128bll${ms} diff --git a/rtl/make_viv/viv_default_cmoda7.mk b/rtl/make_viv/viv_default_cmoda7.mk new file mode 100644 index 00000000..58120a01 --- /dev/null +++ b/rtl/make_viv/viv_default_cmoda7.mk @@ -0,0 +1,16 @@ +# $Id: viv_default_cmoda7.mk 906 2017-06-04 21:59:13Z mueller $ +# +# Copyright 2017- by Walter F.J. Mueller +# License disclaimer see License.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2017-06-04 906 1.0 Initial version +#--- +# +# Setup for Digilent CmodA7 +# +# setup default board and part +# +VIV_BOARD_SETUP = ${RETROBASE}/rtl/bplib/cmoda7/cmoda7_setup.tcl +# diff --git a/rtl/sys_gen/tst_rlink/cmoda7/Makefile b/rtl/sys_gen/tst_rlink/cmoda7/Makefile new file mode 100644 index 00000000..d7363737 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/cmoda7/Makefile @@ -0,0 +1,25 @@ +# $Id: Makefile 906 2017-06-04 21:59:13Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-06-04 906 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include ${RETROBASE}/rtl/make_viv/viv_default_cmoda7.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/tst_rlink/cmoda7/sys_conf.vhd b/rtl/sys_gen/tst_rlink/cmoda7/sys_conf.vhd new file mode 100644 index 00000000..401b4878 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/cmoda7/sys_conf.vhd @@ -0,0 +1,56 @@ +-- $Id: sys_conf.vhd 906 2017-06-04 21:59:13Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_c7 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2016.4; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-04 906 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 60; -- vco 720 MHz + constant sys_conf_clksys_outdivide : positive := 6; -- sys 120 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- configure further units ------------------------------------------------- + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) + + -- derived constants ======================================================= + + constant sys_conf_clksys : integer := + ((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; + diff --git a/rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vbom b/rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vbom new file mode 100644 index 00000000..a16edf5e --- /dev/null +++ b/rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vbom @@ -0,0 +1,29 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rbus/rbdlib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/sysmon/sysmonrbuslib.vbom +${sys_conf := sys_conf.vhd} +# components +[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2line_iob.vbom +../../../vlib/rlink/rlink_sp1c.vbom +../rbd_tst_rlink.vbom +../../../bplib/bpgen/rgbdrv_master.vbom +../../../bplib/bpgen/rgbdrv_analog_rbus.vbom +../../../bplib/sysmon/sysmonx_rbus_base.vbom +../../../vlib/rbus/rbd_usracc.vbom +../../../vlib/rbus/rb_sres_or_4.vbom +../../../vlib/xlib/iob_reg_o_gen.vbom +# design +sys_tst_rlink_c7.vhd +@xdc:../../../bplib/cmoda7/cmoda7_pclk.xdc +@xdc:../../../bplib/cmoda7/cmoda7_pins.xdc diff --git a/rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vhd b/rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vhd new file mode 100644 index 00000000..b7940279 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vhd @@ -0,0 +1,270 @@ +-- $Id: sys_tst_rlink_c7.vhd 907 2017-06-05 08:19:12Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_rlink_c7 - syn +-- Description: rlink tester design for CmodA7 board +-- +-- Dependencies: vlib/xlib/s7_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2line_iob +-- vlib/rlink/rlink_sp1c +-- rbd_tst_rlink +-- bplib/bpgen/rgbdrv_master +-- bplib/bpgen/rgbdrv_analog_rbus +-- bplib/sysmon/sysmonx_rbus_base +-- vlib/rbus/rbd_usracc +-- vlib/rbus/rb_sres_or_4 +-- vlib/xlib/iob_reg_o_gen +-- +-- Test bench: tb/tb_tst_rlink_c7 +-- +-- Target Devices: generic +-- Tool versions: viv 2016.4; ghdl 0.34 +-- +-- Synthesized (viv): +-- Date Rev viv Target flop lutl lutm bram slic +-- 2017-06-05 907 2016.4 xc7a35t-1 913 1556 36 3.0 513 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-04 906 1.0 Initial version (derived from sys_tst_rlink_arty) +------------------------------------------------------------------------------ +-- Usage of CmodA7 Buttons, LEDs, RGBLEDs: +-- +-- LED(1): SER_MONI.txact (shows tx activity) +-- LED(0): SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rbdlib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.sysmonrbuslib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_rlink_c7 is -- top level + -- implements cmoda7_aif + port ( + I_CLK12 : in slbit; -- 12 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_BTN : in slv2; -- c7 buttons + O_LED : out slv2; -- c7 leds + O_RGBLED0_N : out slv3 -- c7 rgb-led 0 + ); +end sys_tst_rlink_c7; + +architecture syn of sys_tst_rlink_c7 is + + signal CLK : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + + signal LED : slv2 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + signal RB_SRES_RGB0 : rb_sres_type := rb_sres_init; + signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; + signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + signal STAT : slv8 := (others=>'0'); + + signal RGBCNTL : slv3 := (others=>'0'); + signal DIMCNTL : slv12 := (others=>'0'); + + constant rbaddr_rgb0 : slv16 := x"fc00"; -- fe00/0004: 1111 1100 0000 00xx + constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx + + constant sysid_proj : slv16 := x"0101"; -- tst_rlink + constant sysid_board : slv8 := x"09"; -- cmoda7 + constant sysid_vers : slv8 := x"00"; + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + RESET <= '0'; -- so far not used + + GEN_CLKSYS : s7_cmt_sfs + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 83.3, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK12, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2line_iob + port map ( + CLK => CLK, + RXD => RXD, + TXD => TXD, + I_RXD => I_RXD, + O_TXD => O_TXD + ); + + RLINK : rlink_sp1c + generic map ( + BTOWIDTH => 6, + RTAWIDTH => 12, + SYSID => sysid_proj & sysid_board & sysid_vers, + IFAWIDTH => 5, + OFAWIDTH => 5, + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 12, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink + RBMON_RBADDR => (others=>'0')) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => '1', + ESCFILL => '0', + RXSD => RXD, + TXSD => TXD, + CTS_N => '0', + RTS_N => open, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + RBDTST : entity work.rbd_tst_rlink + port map ( + CLK => CLK, + RESET => RESET, + CE_USEC => CE_USEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TST, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RB_SRES_TOP => RB_SRES, + RXSD => RXD, + RXACT => SER_MONI.rxact, + STAT => STAT + ); + + RGBMSTR : rgbdrv_master + generic map ( + DWIDTH => DIMCNTL'length) + port map ( + CLK => CLK, + RESET => RESET, + CE_USEC => CE_USEC, + RGBCNTL => RGBCNTL, + DIMCNTL => DIMCNTL + ); + + RGB0 : rgbdrv_analog_rbus + generic map ( + DWIDTH => DIMCNTL'length, + ACTLOW => '1', -- CmodA7 has active low RGBLED + RB_ADDR => rbaddr_rgb0) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_RGB0, + RGBCNTL => RGBCNTL, + DIMCNTL => DIMCNTL, + O_RGBLED => O_RGBLED0_N + ); + + SMRB : if sys_conf_rbd_sysmon generate + I0: sysmonx_rbus_base + generic map ( -- use default INIT_ (LP: Vccint=0.95) + CLK_MHZ => sys_conf_clksys_mhz, + RB_ADDR => rbaddr_sysmon) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_SYSMON, + ALM => open, + OT => open, + TEMP => open + ); + end generate SMRB; + + UARB : rbd_usracc + port map ( + CLK => CLK, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_USRACC + ); + + RB_SRES_OR1 : rb_sres_or_4 + port map ( + RB_SRES_1 => RB_SRES_TST, + RB_SRES_2 => RB_SRES_RGB0, + RB_SRES_3 => RB_SRES_SYSMON, + RB_SRES_4 => RB_SRES_USRACC, + RB_SRES_OR => RB_SRES + ); + + IOB_LED : iob_reg_o_gen + generic map (DWIDTH => O_LED'length) + port map (CLK => CLK, CE => '1', DO => LED, PAD => O_LED); + + LED(1) <= SER_MONI.txact; + LED(0) <= SER_MONI.rxact; + +end syn; diff --git a/rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vmfset b/rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vmfset new file mode 100644 index 00000000..7906c8e3 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vmfset @@ -0,0 +1,28 @@ +# $Id: sys_tst_rlink_c7.vmfset 908 2017-06-05 21:03:06Z mueller $ +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# unconnected ports -------------------------------------------- +I [Synth 8-3331] RB_MREQ # generic +# --> rlink_sp1c doesn't use CE_USEC # OK 2017-06-05 +i [Synth 8-3331] rlink_sp1c.*CE_USEC +# --> I_BTN unused # OK 2017-06-05 +i [Synth 8-3331] I_BTN[\d+] + +# sequential element removed (2017.1 nonsense) ----------------- +I [Synth 8-6014] _reg # generic + +# unused sequential element ------------------------------------ +# --> monitor outputs moneop,monattn currently not used # OK 2017-06-05 +i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop] +i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn] +# ENAESC=0, therefore esc logic inactive # OK 2017-06-05 +i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[escseen] +i [Synth 8-3332] SERPORT/XONTX/R_REGS_reg[escpend] +# --> SER_MONI.rxovr indeed unused # OK 2017-06-05 +i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[rxovr] + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization diff --git a/rtl/sys_gen/tst_rlink/cmoda7/tb/.gitignore b/rtl/sys_gen/tst_rlink/cmoda7/tb/.gitignore new file mode 100644 index 00000000..c80a27f6 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/cmoda7/tb/.gitignore @@ -0,0 +1,2 @@ +tb_tst_rlink_c7 +sysmon_stim diff --git a/rtl/sys_gen/tst_rlink/cmoda7/tb/Makefile b/rtl/sys_gen/tst_rlink/cmoda7/tb/Makefile new file mode 100644 index 00000000..f7435ce9 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/cmoda7/tb/Makefile @@ -0,0 +1,39 @@ +# $Id: Makefile 906 2017-06-04 21:59:13Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-06-04 906 1.0 Initial version +# +EXE_all = tb_tst_rlink_c7 +# +include ${RETROBASE}/rtl/make_viv/viv_default_cmoda7.mk +# +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/tst_rlink/cmoda7/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_rlink/cmoda7/tb/sys_conf_sim.vhd new file mode 100644 index 00000000..e80c2f4a --- /dev/null +++ b/rtl/sys_gen/tst_rlink/cmoda7/tb/sys_conf_sim.vhd @@ -0,0 +1,62 @@ +-- $Id: sys_conf_sim.vhd 906 2017-06-04 21:59:13Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_c7 (for simulation) +-- +-- Dependencies: - +-- Tool versions: viv 2016.4; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-04 906 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- single clock design, clkser = clksys + constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; + constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; + constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; + constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- configure further units ------------------------------------------------- + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) + + -- derived constants ======================================================= + + constant sys_conf_clksys : integer := + ((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_rlink/cmoda7/tb/tb_tst_rlink_c7.vbom b/rtl/sys_gen/tst_rlink/cmoda7/tb/tb_tst_rlink_c7.vbom new file mode 100644 index 00000000..8e34966e --- /dev/null +++ b/rtl/sys_gen/tst_rlink/cmoda7/tb/tb_tst_rlink_c7.vbom @@ -0,0 +1,9 @@ +# configure tb_cmoda7 with sys_tst_rlink_c7 target; +# use vhdl configure file (tb_tst_rlink_c7.vhd) to allow +# that all configurations will co-exist in work library +# configure +cmoda7_aif = ../sys_tst_rlink_c7.vbom +sys_conf = sys_conf_sim.vhd +# design +../../../../bplib/cmoda7/tb/tb_cmoda7.vbom +tb_tst_rlink_c7.vhd diff --git a/rtl/sys_gen/tst_rlink/cmoda7/tb/tb_tst_rlink_c7.vhd b/rtl/sys_gen/tst_rlink/cmoda7/tb/tb_tst_rlink_c7.vhd new file mode 100644 index 00000000..0b22ce41 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/cmoda7/tb/tb_tst_rlink_c7.vhd @@ -0,0 +1,35 @@ +-- $Id: tb_tst_rlink_c7.vhd 906 2017-06-04 21:59:13Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_rlink_c7 +-- Description: Configuration for tb_tst_rlink_c7 for tb_cmoda7 +-- +-- Dependencies: sys_tst_rlink_c7 +-- +-- To test: sys_tst_rlink_c7 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-04 906 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_tst_rlink_c7 of tb_cmoda7 is + + for sim + for all : cmoda7_aif + use entity work.sys_tst_rlink_c7; + end for; + end for; + +end tb_tst_rlink_c7; diff --git a/rtl/sys_gen/tst_rlink/cmoda7/tb/tbrun.yml b/rtl/sys_gen/tst_rlink/cmoda7/tb/tbrun.yml new file mode 100644 index 00000000..be8e9720 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/cmoda7/tb/tbrun.yml @@ -0,0 +1,18 @@ +# $Id: tbrun.yml 906 2017-06-04 21:59:13Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-06-04 906 1.0 Initial version +# +- default: + mode: ${viv_modes} +# +- tag: [default, viv, sys_tst_rlink, c7, base] + test: | + tbrun_tbwrri --hxon --lsuf base --pack tst_rlink tb_tst_rlink_c7${ms} \ + "tst_rlink::setup" "tst_rlink::test_all" +# +- tag: [default, viv, sys_tst_rlink, c7, emon] + test: | + tbrun_tbwrri --hxon --lsuf emon --pack tst_rlink tb_tst_rlink_c7${ms} \ + "tst_rlink::setup" "tst_rlink::test_all_emon" diff --git a/rtl/sys_gen/tst_rlink/cmoda7/tb/tbw.dat b/rtl/sys_gen/tst_rlink/cmoda7/tb/tbw.dat new file mode 100644 index 00000000..dc1fb737 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/cmoda7/tb/tbw.dat @@ -0,0 +1,7 @@ +# $Id: tbw.dat 906 2017-06-04 21:59:13Z mueller $ +# +[tb_tst_rlink_c7] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = +sysmon_stim = ../../../../bplib/sysmon/tb/sysmon_stim_n4.dat diff --git a/rtl/sys_gen/tst_rlink/tbrun.yml b/rtl/sys_gen/tst_rlink/tbrun.yml index ac21a95d..ef837bfb 100644 --- a/rtl/sys_gen/tst_rlink/tbrun.yml +++ b/rtl/sys_gen/tst_rlink/tbrun.yml @@ -1,7 +1,8 @@ -# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $ +# $Id: tbrun.yml 906 2017-06-04 21:59:13Z mueller $ # # Revision History: # Date Rev Version Comment +# 2017-06-04 906 1.0.1 add cmoda7 # 2016-08-13 798 1.0 Initial version # - include: s3board/tb/tbrun.yml @@ -10,3 +11,4 @@ - include: nexys4/tb/tbrun.yml - include: basys3/tb/tbrun.yml - include: arty/tb/tbrun.yml +- include: cmoda7/tb/tbrun.yml diff --git a/rtl/sys_gen/tst_sram/cmoda7/Makefile b/rtl/sys_gen/tst_sram/cmoda7/Makefile new file mode 100644 index 00000000..ec8577ba --- /dev/null +++ b/rtl/sys_gen/tst_sram/cmoda7/Makefile @@ -0,0 +1,25 @@ +# $Id: Makefile 912 2017-06-11 18:30:03Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-06-11 912 1.0 Initial version +# +VBOM_all = sys_tst_sram_c7.vbom +BIT_all = $(VBOM_all:.vbom=.bit) +# +include ${RETROBASE}/rtl/make_viv/viv_default_cmoda7.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/tst_sram/cmoda7/sys_conf.vhd b/rtl/sys_gen/tst_sram/cmoda7/sys_conf.vhd new file mode 100644 index 00000000..ff9f8447 --- /dev/null +++ b/rtl/sys_gen/tst_sram/cmoda7/sys_conf.vhd @@ -0,0 +1,59 @@ +-- $Id: sys_conf.vhd 912 2017-06-11 18:30:03Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_sram_c7 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2017.1; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-11 912 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 60; -- vco 720 MHz + constant sys_conf_clksys_outdivide : positive := 9; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 60; -- vco 720 MHz + constant sys_conf_clkser_outdivide : positive := 6; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "MMCM"; + + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + + -- derived constants + + constant sys_conf_clksys : integer := + ((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clkser/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vbom b/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vbom new file mode 100644 index 00000000..f13cec94 --- /dev/null +++ b/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vbom @@ -0,0 +1,30 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rbus/rbdlib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/sysmon/sysmonrbuslib.vbom +../../../bplib/cmoda7/cmoda7lib.vhd +${sys_conf := sys_conf.vhd} +# components +[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2line_iob.vbom +../../../vlib/rlink/rlink_sp2c.vbom +../tst_sram.vbom +../../../bplib/cmoda7/c7_sram_memctl.vbom +../../../bplib/bpgen/sn_humanio_emu_rbus.vbom +../../../bplib/sysmon/sysmonx_rbus_base.vbom +../../../vlib/rbus/rbd_usracc.vbom +../../../vlib/rbus/rb_sres_or_4.vbom +# design +sys_tst_sram_c7.vhd +@xdc:../../../bplib/cmoda7/cmoda7_pclk.xdc +@xdc:../../../bplib/cmoda7/cmoda7_pins.xdc +@xdc:../../../bplib/cmoda7/cmoda7_pins_sram.xdc diff --git a/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd b/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd new file mode 100644 index 00000000..b4af1c6f --- /dev/null +++ b/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd @@ -0,0 +1,351 @@ +-- $Id: sys_tst_sram_c7.vhd 914 2017-06-25 06:17:18Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_sram_c7 - syn +-- Description: test of cmoda7 sram and its controller +-- +-- Dependencies: vlib/xlib/s7_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2line_iob +-- vlib/rlink/rlink_sp2c +-- tst_sram +-- bplib/cmoda7/c7_cram_memctl +-- bplib/bpgen/sn_humanio_eum_rbus +-- bplib/sysmon/sysmonx_rbus_base +-- vlib/rbus/rbd_usracc +-- vlib/rbus/rb_sres_or_4 +-- +-- Test bench: tb/tb_tst_sram_c7 +-- +-- Target Devices: generic +-- Tool versions: viv 2017.1; ghdl 0.34 +-- +-- Synthesized (viv): +-- Date Rev viv Target flop lutl lutm bram slic +-- 2017-06-11 912 2017.1 xc7a35t-1 x x x x x +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-11 914 1.0 Initial version +-- 2017-06-11 912 0.5 First draft (derived from sys_tst_sram_n4) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rbdlib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.sysmonrbuslib.all; +use work.cmoda7lib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_sram_c7 is -- top level + -- implements cmoda7_sram_aif + port ( + I_CLK12 : in slbit; -- 12 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_BTN : in slv2; -- c7 buttons + O_LED : out slv2; -- c7 leds + O_RGBLED0_N : out slv3; -- c7 rgb-led 0 + O_MEM_CE_N : out slbit; -- sram: chip enable (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv19; -- sram: address lines + IO_MEM_DATA : inout slv8 -- sram: data lines + ); +end sys_tst_sram_c7; + +architecture syn of sys_tst_sram_c7 is + + signal CLK : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal CLKS : slbit := '0'; + signal CES_MSEC : slbit := '0'; + + signal GBL_RESET : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv32 := (others=>'0'); + signal DSP_DP : slv8 := (others=>'0'); + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; + signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; + + signal RB_LAM_TST : slbit := '0'; + + signal MEM_RESET : slbit := '0'; + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACK_W : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv17 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx + + constant sysid_proj : slv16 := x"0104"; -- tst_sram + constant sysid_board : slv8 := x"09"; -- cmoda7 + constant sysid_vers : slv8 := x"00"; + +begin + + GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 83.3, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK12, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV_CLK : clkdivce -- usec/msec clock divider system ---- + generic map ( + CDUWIDTH => 7, -- good for up to 127 MHz ! + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------ + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide, + CLKIN_PERIOD => 83.3, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clkser_gentype) + port map ( + CLKIN => I_CLK12, + CLKFX => CLKS, + LOCKED => open + ); + + CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport --- + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clkser_mhz, + MSECDIV => 1000) + port map ( + CLK => CLKS, + CE_USEC => open, + CE_MSEC => CES_MSEC + ); + + IOB_RS232 : bp_rs232_2line_iob + port map ( + CLK => CLKS, + RXD => RXD, + TXD => TXD, + I_RXD => I_RXD, + O_TXD => O_TXD + ); + + RLINK : rlink_sp2c + generic map ( + BTOWIDTH => 6, -- 64 cycles access timeout + RTAWIDTH => 12, + SYSID => sysid_proj & sysid_board & sysid_vers, + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 12, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => 0, + RBMON_RBADDR => x"ffe8") + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => GBL_RESET, + CLKS => CLKS, + CES_MSEC => CES_MSEC, + ENAXON => '1', + ESCFILL => '0', + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + TST : entity work.tst_sram + generic map ( + RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)), + AWIDTH => 17) + port map ( + CLK => CLK, + RESET => GBL_RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TST, + RB_STAT => RB_STAT, + RB_LAM => RB_LAM_TST, + SWI => SWI(7 downto 0), + BTN => BTN(3 downto 0), + LED => LED(7 downto 0), + DSP_DAT => DSP_DAT(15 downto 0), + MEM_RESET => MEM_RESET, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ACK_W => MEM_ACK_W, + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO + ); + + SRAMCTL : c7_sram_memctl + port map ( + CLK => CLK, + RESET => MEM_RESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => MEM_ACK_W, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + HIO : sn_humanio_emu_rbus + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DCWIDTH => 3) + port map ( + CLK => CLK, + RESET => '0', + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + SMRB : sysmonx_rbus_base + generic map ( -- use default INIT_ (Vccint=1.00) + CLK_MHZ => sys_conf_clksys_mhz, + RB_ADDR => rbaddr_sysmon) + port map ( + CLK => CLK, + RESET => GBL_RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_SYSMON, + ALM => open, + OT => open, + TEMP => open + ); + + UARB : rbd_usracc + port map ( + CLK => CLK, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_USRACC + ); + + RB_SRES_OR : rb_sres_or_4 -- rbus or --------------------------- + port map ( + RB_SRES_1 => RB_SRES_TST, + RB_SRES_2 => RB_SRES_HIO, + RB_SRES_3 => RB_SRES_SYSMON, + RB_SRES_4 => RB_SRES_USRACC, + RB_SRES_OR => RB_SRES + ); + + RB_LAM(0) <= RB_LAM_TST; + + O_LED(1) <= SER_MONI.txact; + O_LED(0) <= SER_MONI.rxact; + + DSP_DP(3) <= not SER_MONI.txok; + DSP_DP(2) <= SER_MONI.txact; + DSP_DP(1) <= not SER_MONI.rxok; + DSP_DP(0) <= SER_MONI.rxact; + + DSP_DP(7 downto 4) <= "0010"; + DSP_DAT(31 downto 16) <= SER_MONI.abclkdiv(11 downto 0) & + '0' & SER_MONI.abclkdiv_f; + + -- setup unused outputs in cmoda7 + O_RGBLED0_N <= (others=>'1'); + +end syn; + diff --git a/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vmfset b/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vmfset new file mode 100644 index 00000000..eac92034 --- /dev/null +++ b/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vmfset @@ -0,0 +1,48 @@ +# $Id: sys_tst_sram_c7.vmfset 912 2017-06-11 18:30:03Z mueller $ +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# false_path -hold ignored by synth ---------------------------- +I [Designutils 20-1567] # generic + +# port driven by constant -------------------------------------- +i [Synth 8-3917] O_RGBLED0_N[\d] # OK 2017-06-11 + +# tying undriven pin to constant ------------------------------- +# upper 8 LEDs unused # OK 2017-06-11 +i [Synth 8-3295] HIO:LED[\d*] +# only few LAMs used # OK 2017-06-11 +i [Synth 8-3295] RLINK:RB_LAM[\d*] + +# unconnected ports -------------------------------------------- +I [Synth 8-3331] RB_MREQ # generic +# --> I_BTN not used # OK 2017-06-11 +i [Synth 8-3331] I_BTN[\d] +# --> MEM_ACK_W not used by current tst_sram # OK 2017-06-11 +i [Synth 8-3331] tst_sram.*MEM_ACK_W +# --> rlink_sp2c doesn't use CE_USEC and CE_MSEC # OK 2017-06-11 +i [Synth 8-3331] rlink_sp2c.*CE_(USEC|MSEC) + +# sequential element removed (2017.1 nonsense) ----------------- +I [Synth 8-6014] _reg # generic + +# unused sequential element ------------------------------------ +I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic +# --> many HIO pins not used # OK 2017-06-11 +i [Synth 8-3332] HIO/R_REGS_reg[led][\d*] +i [Synth 8-3332] HIO/R_REGS_reg[dsp_dp][\d*] +i [Synth 8-3332] HIO/R_REGS_reg[dsp_dat][\d*] +# --> monitor outputs moneop,monattn currently not used # OK 2017-06-11 +i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop] +i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn] +# --> only RB_STAT 0,1 used by tst_sram # OK 2017-06-11 +i [Synth 8-3332] RLINK/CORE/RL/R_BREGS_reg[stat][(2|3)] +# --> CE_USEC isn't used (also not in rlink_sp2c) # OK 2017-06-11 +i [Synth 8-3332] CLKDIV_CLK/R_REGS_reg[usec] +# --> CES_USEC isn't used # OK 2017-06-11 +i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec] + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization diff --git a/rtl/sys_gen/tst_sram/cmoda7/tb/.gitignore b/rtl/sys_gen/tst_sram/cmoda7/tb/.gitignore new file mode 100644 index 00000000..2a1e1c10 --- /dev/null +++ b/rtl/sys_gen/tst_sram/cmoda7/tb/.gitignore @@ -0,0 +1 @@ +tb_tst_sram_c7 diff --git a/rtl/sys_gen/tst_sram/cmoda7/tb/Makefile b/rtl/sys_gen/tst_sram/cmoda7/tb/Makefile new file mode 100644 index 00000000..863e742d --- /dev/null +++ b/rtl/sys_gen/tst_sram/cmoda7/tb/Makefile @@ -0,0 +1,39 @@ +# $Id: Makefile 912 2017-06-11 18:30:03Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-06-11 912 1.0 Initial version +# +EXE_all = tb_tst_sram_c7 +# +include ${RETROBASE}/rtl/make_viv/viv_default_cmoda7.mk +# +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/tst_sram/cmoda7/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_sram/cmoda7/tb/sys_conf_sim.vhd new file mode 100644 index 00000000..db899ba8 --- /dev/null +++ b/rtl/sys_gen/tst_sram/cmoda7/tb/sys_conf_sim.vhd @@ -0,0 +1,56 @@ +-- $Id: sys_conf_sim.vhd 912 2017-06-11 18:30:03Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_sram_c7 (for simulation) +-- +-- Dependencies: - +-- Tool versions: viv 2017.1; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2013-09-21 534 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 60; -- vco 720 MHz + constant sys_conf_clksys_outdivide : positive := 9; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 60; -- vco 720 MHz + constant sys_conf_clkser_outdivide : positive := 6; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "MMCM"; + + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + -- derived constants + + constant sys_conf_clksys : integer := + ((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_sram/cmoda7/tb/tb_tst_sram_c7.vbom b/rtl/sys_gen/tst_sram/cmoda7/tb/tb_tst_sram_c7.vbom new file mode 100644 index 00000000..c20c6bb9 --- /dev/null +++ b/rtl/sys_gen/tst_sram/cmoda7/tb/tb_tst_sram_c7.vbom @@ -0,0 +1,9 @@ +# configure tb_cmoda7_sram with sys_tst_sram_c7 target; +# use vhdl configure file (tb_tst_sram_c7.vhd) to allow +# that all configurations will co-exist in work library +# configure +cmoda7_sram_aif = ../sys_tst_sram_c7.vbom +sys_conf = sys_conf_sim.vhd +# design +../../../../bplib/cmoda7/tb/tb_cmoda7_sram.vbom +tb_tst_sram_c7.vhd diff --git a/rtl/sys_gen/tst_sram/cmoda7/tb/tb_tst_sram_c7.vhd b/rtl/sys_gen/tst_sram/cmoda7/tb/tb_tst_sram_c7.vhd new file mode 100644 index 00000000..51956e70 --- /dev/null +++ b/rtl/sys_gen/tst_sram/cmoda7/tb/tb_tst_sram_c7.vhd @@ -0,0 +1,39 @@ +-- $Id: tb_tst_sram_c7.vhd 912 2017-06-11 18:30:03Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_sram_c7 +-- Description: Configuration for tb_tst_sram_c7 for tb_cmoda7_sram +-- +-- Dependencies: sys_tst_sram_c7 +-- +-- To test: sys_tst_sram_c7 +-- +-- Verified: +-- Date Rev Code ghdl ise Target Comment +-- 2013-??-?? 534 - 0.29 13.1 O40d xc6slx16 ??? +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-11 912 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_tst_sram_c7 of tb_cmoda7_sram is + + for sim + for all : cmoda7_sram_aif + use entity work.sys_tst_sram_c7; + end for; + end for; + +end tb_tst_sram_c7; diff --git a/rtl/sys_gen/tst_sram/cmoda7/tb/tbrun.yml b/rtl/sys_gen/tst_sram/cmoda7/tb/tbrun.yml new file mode 100644 index 00000000..35eeb431 --- /dev/null +++ b/rtl/sys_gen/tst_sram/cmoda7/tb/tbrun.yml @@ -0,0 +1,18 @@ +# $Id: tbrun.yml 914 2017-06-25 06:17:18Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-06-11 912 1.0 Initial version +# +- default: + mode: ${viv_modes} +# +- tag: [default, viv, sys_tst_sram, c7, base] + test: | + tbrun_tbwrri --hxon --lsuf base --pack tst_sram tb_tst_sram_c7${ms} \ + tst_sram::setup tst_sram::test_all + +- tag: [default, viv, sys_tst_sram, c7, stress] + test: | + tbrun_tbwrri --hxon --lsuf stress --pack tst_sram tb_tst_sram_c7${ms} \ + tst_sram::setup tst_sram::test_sim diff --git a/rtl/sys_gen/tst_sram/cmoda7/tb/tbw.dat b/rtl/sys_gen/tst_sram/cmoda7/tb/tbw.dat new file mode 100644 index 00000000..f6b0da58 --- /dev/null +++ b/rtl/sys_gen/tst_sram/cmoda7/tb/tbw.dat @@ -0,0 +1,7 @@ +# $Id: tbw.dat 912 2017-06-11 18:30:03Z mueller $ +# +[tb_tst_sram_c7] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = +sysmon_stim = ../../../../bplib/sysmon/tb/sysmon_stim_n4.dat diff --git a/rtl/sys_gen/tst_sram/tbrun.yml b/rtl/sys_gen/tst_sram/tbrun.yml index e5bf2be3..dde1b180 100644 --- a/rtl/sys_gen/tst_sram/tbrun.yml +++ b/rtl/sys_gen/tst_sram/tbrun.yml @@ -1,10 +1,12 @@ -# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $ +# $Id: tbrun.yml 917 2017-06-25 18:05:28Z mueller $ # # Revision History: # Date Rev Version Comment +# 2017-06-25 917 1.1 add cmoda7 # 2016-08-13 798 1.0 Initial version # - include: s3board/tb/tbrun.yml - include: nexys2/tb/tbrun.yml - include: nexys3/tb/tbrun.yml - include: nexys4/tb/tbrun.yml +- include: cmoda7/tb/tbrun.yml diff --git a/rtl/sys_gen/w11a/README.md b/rtl/sys_gen/w11a/README.md index 7a00eb61..bc3fea70 100644 --- a/rtl/sys_gen/w11a/README.md +++ b/rtl/sys_gen/w11a/README.md @@ -5,6 +5,7 @@ and is organized in | --------- | ------- | | [arty_bram](arty_bram) | design for Digilent Arty, using BRAM only | | [basys3](basys3) | design for Digilent Basys3 | +| [cmoda7](cmoda7) | design for Digilent Cmod A7 (35 die size) | | [nexys2](nexys2) | design for Digilent Nexys2 | | [nexys3](nexys3) | design for Digilent Nexys3 | | [nexys4](nexys4) | design for Digilent Nexys4 (old CRAM version !!) | diff --git a/rtl/sys_gen/w11a/cmoda7/Makefile b/rtl/sys_gen/w11a/cmoda7/Makefile new file mode 100644 index 00000000..2eb88f3b --- /dev/null +++ b/rtl/sys_gen/w11a/cmoda7/Makefile @@ -0,0 +1,25 @@ +# $Id: Makefile 914 2017-06-25 06:17:18Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-06-24 914 1.0 Initial version +# +VBOM_all = sys_w11a_c7.vbom +BIT_all = $(VBOM_all:.vbom=.bit) +# +include ${RETROBASE}/rtl/make_viv/viv_default_cmoda7.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/w11a/cmoda7/sys_conf.vhd b/rtl/sys_gen/w11a/cmoda7/sys_conf.vhd new file mode 100644 index 00000000..cc047b9a --- /dev/null +++ b/rtl/sys_gen/w11a/cmoda7/sys_conf.vhd @@ -0,0 +1,99 @@ +-- $Id: sys_conf.vhd 918 2017-06-28 20:04:17Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_c7 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2017.1; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-24 914 1.0 Initial version (derived from _n4 version) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 60; -- vco 720 MHz + constant sys_conf_clksys_outdivide : positive := 9; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 60; -- vco 720 MHz + constant sys_conf_clkser_outdivide : positive := 6; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "MMCM"; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- configure memory controller --------------------------------------------- + constant sys_conf_memctl_mawidth : positive := 4; + constant sys_conf_memctl_nblock : positive := 10; + + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable + constant sys_conf_dmscnt : boolean := false; + constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable + constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) + + -- configure w11 cpu core -------------------------------------------------- + -- sys_conf_mem_losize is highest 64 byte MMU block number + -- the bram_memcnt uses 512kB memory blocks => 512*16 = 8192 MMU blocks + -- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks + constant sys_conf_mem_losize : natural := + (512*16) + (256*sys_conf_memctl_nblock) - 1; + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + constant sys_conf_cache_twidth : integer := 8; -- 16kB cache + + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + constant sys_conf_ibd_deuna : boolean := true; -- DEUNA + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clkser/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; diff --git a/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vbom b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vbom new file mode 100644 index 00000000..d33bf784 --- /dev/null +++ b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vbom @@ -0,0 +1,38 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rbus/rbdlib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/sysmon/sysmonrbuslib.vbom +../../../bplib/cmoda7/cmoda7lib.vhd +../../../ibus/iblib.vhd +../../../ibus/ibdlib.vhd +../../../w11a/pdp11.vhd +${sys_conf := sys_conf.vhd} +# components +[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2line_iob.vbom +../../../vlib/rlink/rlink_sp2c.vbom +../../../w11a/pdp11_sys70.vbom +../../../ibus/ibdr_maxisys.vbom +../../../bplib/cmoda7/c7_sram_memctl.vbom +../../../w11a/pdp11_bram_memctl.vbom +../../../vlib/rlink/ioleds_sp1c.vbom +../../../w11a/pdp11_hio70.vbom +../../../bplib/bpgen/sn_humanio_emu_rbus.vbom +../../../bplib/sysmon/sysmonx_rbus_base.vbom +../../../vlib/rbus/rbd_usracc.vbom +../../../vlib/rbus/rb_sres_or_4.vbom +../../../vlib/xlib/iob_reg_o_gen.vbom +# design +sys_w11a_c7.vhd +@xdc:../../../bplib/cmoda7/cmoda7_pclk.xdc +@xdc:../../../bplib/cmoda7/cmoda7_pins.xdc +@xdc:../../../bplib/cmoda7/cmoda7_pins_sram.xdc diff --git a/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd new file mode 100644 index 00000000..0c7c3d54 --- /dev/null +++ b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd @@ -0,0 +1,504 @@ +-- $Id: sys_w11a_c7.vhd 918 2017-06-28 20:04:17Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_w11a_c7 - syn +-- Description: w11a test design for Cmod A7 +-- +-- Dependencies: vlib/xlib/s7_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2line_iob +-- vlib/rlink/rlink_sp2c +-- w11a/pdp11_sys70 +-- ibus/ibdr_maxisys +-- bplib/cmoda7/c7_cram_memctl +-- w11a/pdp11_bram_memctl +-- bplib/fx2rlink/ioleds_sp1c +-- w11a/pdp11_hio70 +-- bplib/bpgen/sn_humanio_eum_rbus +-- bplib/sysmon/sysmonx_rbus_base +-- vlib/rbus/rbd_usracc +-- vlib/rbus/rb_sres_or_4 +-- vlib/xlib/iob_reg_o_gen +-- +-- Test bench: tb/tb_sys_w11a_c7 +-- +-- Target Devices: generic +-- Tool versions: viv 2017.1; ghdl 0.34 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic +-- 2017-06-27 918 2017.1 xc7a35t-1 2823 5827 150 50.0 1814 16kB cache +-- 2017-06-25 916 2017.1 xc7a35t-1 2823 5796 150 47.5 1744 +BRAM +-- 2017-06-24 914 2017.1 xc7a35t-1 2708 5668 150 26.0 1787 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-27 918 1.1.1 use 16 kB cache (all BRAM's used up) +-- 2017-06-25 916 1.1 add bram_memctl for 672 kB total memory +-- 2017-06-24 914 1.0 Initial version (derived from sys_w11a_n4) +------------------------------------------------------------------------------ +-- +-- w11a test design for Cmod A7 (using SRAM+BRAM as memory) +-- w11a + rlink + serport +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rbdlib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.sysmonrbuslib.all; +use work.cmoda7lib.all; +use work.iblib.all; +use work.ibdlib.all; +use work.pdp11.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_w11a_c7 is -- top level + -- implements cmoda7_sram_aif + port ( + I_CLK12 : in slbit; -- 12 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_BTN : in slv2; -- c7 buttons + O_LED : out slv2; -- c7 leds + O_RGBLED0_N : out slv3; -- c7 rgb-led 0 + O_MEM_CE_N : out slbit; -- sram: chip enable (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv19; -- sram: address lines + IO_MEM_DATA : inout slv8 -- sram: data lines + ); +end sys_w11a_c7; + +architecture syn of sys_w11a_c7 is + + signal CLK : slbit := '0'; + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal CLKS : slbit := '0'; + signal CES_MSEC : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; + signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + + signal GRESET : slbit := '0'; -- general reset (from rbus) + signal CRESET : slbit := '0'; -- cpu reset (from cp) + signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) + signal ITIMER : slbit := '0'; + + signal EI_PRI : slv3 := (others=>'0'); + signal EI_VECT : slv9_2 := (others=>'0'); + signal EI_ACKM : slbit := '0'; + signal CP_STAT : cp_stat_type := cp_stat_init; + signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; + + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv20 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + signal MEM_REQ_SRAM : slbit := '0'; + signal MEM_BUSY_SRAM : slbit := '0'; + signal MEM_ACK_R_SRAM : slbit := '0'; + signal MEM_ACT_R_SRAM : slbit := '0'; + signal MEM_ACT_W_SRAM : slbit := '0'; + signal MEM_DO_SRAM : slv32 := (others=>'0'); + + signal MEM_REQ_BRAM : slbit := '0'; + signal MEM_BUSY_BRAM : slbit := '0'; + signal MEM_ACK_R_BRAM : slbit := '0'; + signal MEM_ACT_R_BRAM : slbit := '0'; + signal MEM_ACT_W_BRAM : slbit := '0'; + signal MEM_ADDR_BRAM : slv20 := (others=>'0'); + signal MEM_DO_BRAM : slv32 := (others=>'0'); + + signal R_MEM_A17 : slbit := '0'; + + signal IB_MREQ : ib_mreq_type := ib_mreq_init; + signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; + + signal DISPREG : slv16 := (others=>'0'); + signal ABCLKDIV : slv16 := (others=>'0'); + + signal ESWI : slv16 := (others=>'0'); + signal EBTN : slv5 := (others=>'0'); + signal ELED : slv16 := (others=>'0'); + signal EDSP_DAT : slv32 := (others=>'0'); + signal EDSP_DP : slv8 := (others=>'0'); + + signal LED : slv2 := (others=>'0'); + + constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx + constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx + + constant sysid_proj : slv16 := x"0201"; -- w11a + constant sysid_board : slv8 := x"09"; -- cmoda7 + constant sysid_vers : slv8 := x"00"; + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 83.3, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK12, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV_CLK : clkdivce -- usec/msec clock divider system ---- + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------ + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide, + CLKIN_PERIOD => 83.3, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clkser_gentype) + port map ( + CLKIN => I_CLK12, + CLKFX => CLKS, + LOCKED => open + ); + + CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport --- + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clkser_mhz, + MSECDIV => 1000) + port map ( + CLK => CLKS, + CE_USEC => open, + CE_MSEC => CES_MSEC + ); + + IOB_RS232 : bp_rs232_2line_iob -- serport iob ---------------------- + port map ( + CLK => CLKS, + RXD => RXD, + TXD => TXD, + I_RXD => I_RXD, + O_TXD => O_TXD + ); + + RLINK : rlink_sp2c -- rlink for serport ----------------- + generic map ( + BTOWIDTH => 7, -- 128 cycles access timeout + RTAWIDTH => 12, + SYSID => sysid_proj & sysid_board & sysid_vers, + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 12, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => sys_conf_rbmon_awidth, + RBMON_RBADDR => rbaddr_rbmon) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + CLKS => CLKS, + CES_MSEC => CES_MSEC, + ENAXON => '1', -- XON statically enabled ! + ESCFILL => '0', + RXSD => RXD, + TXSD => TXD, + CTS_N => '0', + RTS_N => open, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM_CPU => RB_LAM(0), + GRESET => GRESET, + CRESET => CRESET, + BRESET => BRESET, + CP_STAT => CP_STAT, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + ITIMER => ITIMER, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO, + DM_STAT_DP => DM_STAT_DP + ); + + + IBDR_SYS : ibdr_maxisys -- IO system ------------------------- + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => GRESET, + BRESET => BRESET, + ITIMER => ITIMER, + CPUSUSP => CP_STAT.cpususp, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG + ); + + -- logic to distribute/collect request/response to SRAM/BRAM + proc_a17reg: process (CLK) + begin + + if rising_edge(CLK) then + if GRESET = '1' then + R_MEM_A17 <= '0'; + else + if MEM_REQ = '1' then + R_MEM_A17 <= MEM_ADDR(17); + end if; + end if; + end if; + + end process proc_a17reg; + + proc_a17mux: process (R_MEM_A17, MEM_REQ, MEM_ADDR, + MEM_BUSY_SRAM, MEM_BUSY_BRAM, + MEM_ACK_R_SRAM, MEM_ACK_R_BRAM, + MEM_ACT_R_SRAM, MEM_ACT_R_BRAM, + MEM_ACT_W_SRAM, MEM_ACT_W_BRAM, + MEM_DO_SRAM, MEM_DO_BRAM) + begin + + MEM_REQ_SRAM <= MEM_REQ and not MEM_ADDR(17); + MEM_REQ_BRAM <= MEM_REQ and MEM_ADDR(17); + MEM_ADDR_BRAM <= "000" & MEM_ADDR(16 downto 0); + + if R_MEM_A17 = '0' then + MEM_BUSY <= MEM_BUSY_SRAM; + MEM_ACK_R <= MEM_ACK_R_SRAM; + MEM_ACT_R <= MEM_ACT_R_SRAM; + MEM_ACT_W <= MEM_ACT_W_SRAM; + MEM_DO <= MEM_DO_SRAM; + else + MEM_BUSY <= MEM_BUSY_BRAM; + MEM_ACK_R <= MEM_ACK_R_BRAM; + MEM_ACT_R <= MEM_ACT_R_BRAM; + MEM_ACT_W <= MEM_ACT_W_BRAM; + MEM_DO <= MEM_DO_BRAM; + end if; + + end process proc_a17mux; + + SRAM_CTL : c7_sram_memctl -- SRAM memory controller ------------ + port map ( + CLK => CLK, + RESET => GRESET, + REQ => MEM_REQ_SRAM, + WE => MEM_WE, + BUSY => MEM_BUSY_SRAM, + ACK_R => MEM_ACK_R_SRAM, + ACK_W => open, + ACT_R => MEM_ACT_R_SRAM, + ACT_W => MEM_ACT_W_SRAM, + ADDR => MEM_ADDR(16 downto 0), + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO_SRAM, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + BRAM_CTL: pdp11_bram_memctl -- BRAM memory controller ------------ + generic map ( + MAWIDTH => sys_conf_memctl_mawidth, + NBLOCK => sys_conf_memctl_nblock) + port map ( + CLK => CLK, + RESET => GRESET, + REQ => MEM_REQ_BRAM, + WE => MEM_WE, + BUSY => MEM_BUSY_BRAM, + ACK_R => MEM_ACK_R_BRAM, + ACK_W => open, + ACT_R => MEM_ACT_R_BRAM, + ACT_W => MEM_ACT_W_BRAM, + ADDR => MEM_ADDR_BRAM, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO_BRAM + ); + + LED_IO : ioleds_sp1c -- hio leds from serport ------------- + port map ( + SER_MONI => SER_MONI, + IOLEDS => EDSP_DP(3 downto 0) + ); + + ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; + + HIO70 : pdp11_hio70 -- hio from sys70 -------------------- + generic map ( + LWIDTH => ELED'length, + DCWIDTH => 3) + port map ( + SEL_LED => ESWI(3), + SEL_DSP => ESWI(5 downto 4), + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + CP_STAT => CP_STAT, + DM_STAT_DP => DM_STAT_DP, + ABCLKDIV => ABCLKDIV, + DISPREG => DISPREG, + LED => ELED, + DSP_DAT => EDSP_DAT + ); + + EHIO : sn_humanio_emu_rbus -- emulated hio ---------------------- + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DCWIDTH => 3) + port map ( + CLK => CLK, + RESET => '0', + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => ESWI, + BTN => EBTN, + LED => ELED, + DSP_DAT => EDSP_DAT, + DSP_DP => EDSP_DP + ); + + SMRB : if sys_conf_rbd_sysmon generate + I0: sysmonx_rbus_base + generic map ( -- use default INIT_ (LP: Vccint=1.00) + CLK_MHZ => sys_conf_clksys_mhz, + RB_ADDR => rbaddr_sysmon) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_SYSMON, + ALM => open, + OT => open, + TEMP => open + ); + end generate SMRB; + + UARB : rbd_usracc + port map ( + CLK => CLK, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_USRACC + ); + + RB_SRES_OR : rb_sres_or_4 -- rbus or --------------------------- + port map ( + RB_SRES_1 => RB_SRES_CPU, + RB_SRES_2 => RB_SRES_HIO, + RB_SRES_3 => RB_SRES_SYSMON, + RB_SRES_4 => RB_SRES_USRACC, + RB_SRES_OR => RB_SRES + ); + + IOB_LED : iob_reg_o_gen + generic map (DWIDTH => O_LED'length) + port map (CLK => CLK, CE => '1', DO => LED, PAD => O_LED); + + LED(1) <= SER_MONI.txact; + LED(0) <= SER_MONI.rxact; + + -- setup unused outputs in cmoda7 + O_RGBLED0_N <= (others=>'1'); + +end syn; diff --git a/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vmfset b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vmfset new file mode 100644 index 00000000..89c3468a --- /dev/null +++ b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vmfset @@ -0,0 +1,102 @@ +# $Id: sys_w11a_c7.vmfset 916 2017-06-25 13:30:07Z mueller $ +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# false_path -hold ignored by synth ---------------------------- +I [Designutils 20-1567] + +# port driven by constant -------------------------------------- +# --> RGBLED0 currently unused # OK 2017-06-24 +i [Synth 8-3917] O_RGBLED0_N[\d] + +# tying undriven pin to constant ------------------------------- +# --> upper 4 DSP_DP unused # OK 2017-06-24 +i [Synth 8-3295] EHIO:DSP_DP[(4|5|6|7)] + +# unconnected ports -------------------------------------------- +I [Synth 8-3331] RB_MREQ # generic +I [Synth 8-3331] DM_STAT_DP # generic + +# sequential element removed (2017.1 nonsense) ----------------- +I [Synth 8-6014] _reg # generic + +# unused sequential element ------------------------------------ +{:2016.4} +I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic +I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*] # generic +# --> usec not used for serport clock domain # OK 2017-06-24 +i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec] +# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-24 +i [Synth 8-3332] VMBOX/MMU/R_SSR0_reg[inst_compl] +# --> not yet used # OK 2017-06-24 +i [Synth 8-3332] SEQ/R_STATUS_reg[suspext] +# --> mawidth=4, nblock=10, so some cellen unused # OK 2017-06-25 +i [Synth 8-3332] BRAM_CTL/R_REGS_reg[cellen][1\d] +# --> indeed no types with [3] set # OK 2017-06-24 +i [Synth 8-3332] R_REGS_reg[dtyp][3].*ibdr_rhrp +# --> not yet used # OK 2017-06-24 +i [Synth 8-3332] R_REGS_reg[req_lock].*ibd_iist +i [Synth 8-3332] R_REGS_reg[req_boot].*ibd_iist +# --> [8] is for DZ11TX, not yet available # OK 2017-06-24 +# --> [9] is for DZ11RX, unclear why this one isn't removed too !! +i [Synth 8-3332] SEQ/R_STATUS_reg[intvect][8] +# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2017-06-24 +i [Synth 8-3332] SEQ/R_IDSTAT_reg[res_sel][2] +# --> monitor outputs moneop,monattn currently not used # OK 2017-06-24 +i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop] +i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn] +# --> scnt disabled, thus 3 SNUM bits '0' # OK 2017-06-24 +i [Synth 8-3332] R_REGS_reg[se_snum][(4|5|6)] +# --> upper 4 DSP_DP unused # OK 2017-06-24 +i [Synth 8-3332] R_REGS_reg[dsp_dp][(4|5|6|7)] + +{2017.1:} +I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic +I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic +# --> usec not used for serport clock domain # OK 2017-06-24 +i [Synth 8-3332] R_REGS_reg[usec].* clkdivce +# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-24 +i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox +# --> not yet used # OK 2017-06-24 +i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_sequencer +# --> mawidth=4, nblock=11, so some cellen unused # OK 2017-06-25 +i [Synth 8-3332] R_REGS_reg[cellen][1\d].* pdp11_bram_memctl +# --> indeed no types with [3] set # OK 2017-06-24 +i [Synth 8-3332] R_REGS_reg[dtyp][3].* ibdr_rhrp +# --> not yet used # OK 2017-06-24 +i [Synth 8-3332] R_REGS_reg[req_lock].* ibd_iist +i [Synth 8-3332] R_REGS_reg[req_boot].* ibd_iist +# --> [8] is for DZ11TX, not yet available # OK 2017-06-24 +# --> [9] is for DZ11RX, unclear why this one isn't removed too !! +i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_sequencer +# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2017-06-24 +i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer +# --> monitor outputs moneop,monattn currently not used # OK 2017-06-24 +i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop].* rlink_sp2c +i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn].* rlink_sp2c +# --> scnt disabled, thus 3 SNUM bits '0' # OK 2017-06-24 +i [Synth 8-3332] R_REGS_reg[se_snum][(4|5|6)] +# --> upper 4 DSP_DP unused # OK 2017-06-24 +i [Synth 8-3332] R_REGS_reg[dsp_dp][(4|5|6|7)] + +{:} + +# INFO: encoded FSM with state register as -------------------- +# test for sys_w11a_n4 that all FSMs are one_hot +r [Synth 8-3354] R_BREGS_reg[state.*'one-hot'.*'rlink_core' +r [Synth 8-3354] R_LREGS_reg[state].*'one-hot'.*'rlink_core' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_autobaud' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_rx' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_core_rbus' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_vmbox' +r [Synth 8-3354] R_STATE_reg.*'one-hot'.*'pdp11_sequencer' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_cache' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rhrp' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rl11' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'c7_sram_memctl' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'sysmon_rbus_core' + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization diff --git a/rtl/sys_gen/w11a/cmoda7/tb/.gitignore b/rtl/sys_gen/w11a/cmoda7/tb/.gitignore new file mode 100644 index 00000000..47ae0365 --- /dev/null +++ b/rtl/sys_gen/w11a/cmoda7/tb/.gitignore @@ -0,0 +1,2 @@ +tb_w11a_c7 +sysmon_stim diff --git a/rtl/sys_gen/w11a/cmoda7/tb/Makefile b/rtl/sys_gen/w11a/cmoda7/tb/Makefile new file mode 100644 index 00000000..0c3010a3 --- /dev/null +++ b/rtl/sys_gen/w11a/cmoda7/tb/Makefile @@ -0,0 +1,39 @@ +# $Id: Makefile 914 2017-06-25 06:17:18Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-06-24 914 1.0 Initial version +# +EXE_all = tb_w11a_c7 +# +include ${RETROBASE}/rtl/make_viv/viv_default_cmoda7.mk +# +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/w11a/cmoda7/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/cmoda7/tb/sys_conf_sim.vhd new file mode 100644 index 00000000..6b6896a0 --- /dev/null +++ b/rtl/sys_gen/w11a/cmoda7/tb/sys_conf_sim.vhd @@ -0,0 +1,96 @@ +-- $Id: sys_conf_sim.vhd 918 2017-06-28 20:04:17Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_c7 (for simulation) +-- +-- Dependencies: - +-- Tool versions: viv 2017.1; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-24 914 1.0 Initial version (cloned from _n4) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 60; -- vco 720 MHz + constant sys_conf_clksys_outdivide : positive := 9; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 60; -- vco 720 MHz + constant sys_conf_clkser_outdivide : positive := 6; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "MMCM"; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- configure memory controller --------------------------------------------- + constant sys_conf_memctl_mawidth : positive := 4; + constant sys_conf_memctl_nblock : positive := 10; + + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable + constant sys_conf_dmscnt : boolean := false; + constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable + constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) + + -- configure w11 cpu core -------------------------------------------------- + -- sys_conf_mem_losize is highest 64 byte MMU block number + -- the bram_memcnt uses 512kB memory blocks => 512*16 = 8192 MMU blocks + -- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks + constant sys_conf_mem_losize : natural := + (512*16) + (256*sys_conf_memctl_nblock) - 1; + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + constant sys_conf_cache_twidth : integer := 8; -- 16kB cache + + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + constant sys_conf_ibd_deuna : boolean := true; -- DEUNA + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; diff --git a/rtl/sys_gen/w11a/cmoda7/tb/tb_w11a_c7.vbom b/rtl/sys_gen/w11a/cmoda7/tb/tb_w11a_c7.vbom new file mode 100644 index 00000000..9ec8a7a0 --- /dev/null +++ b/rtl/sys_gen/w11a/cmoda7/tb/tb_w11a_c7.vbom @@ -0,0 +1,9 @@ +# configure tb_cmoda7_sram with sys_w11a_c7 target; +# use vhdl configure file (tb_w11a_c7.vhd) to allow +# that all configurations will co-exist in work library +# configure +cmoda7_sram_aif = ../sys_w11a_c7.vbom +sys_conf = sys_conf_sim.vhd +# design +../../../../bplib/cmoda7/tb/tb_cmoda7_sram.vbom +tb_w11a_c7.vhd diff --git a/rtl/sys_gen/w11a/cmoda7/tb/tb_w11a_c7.vhd b/rtl/sys_gen/w11a/cmoda7/tb/tb_w11a_c7.vhd new file mode 100644 index 00000000..aeecfb11 --- /dev/null +++ b/rtl/sys_gen/w11a/cmoda7/tb/tb_w11a_c7.vhd @@ -0,0 +1,40 @@ +-- $Id: tb_w11a_c7.vhd 914 2017-06-25 06:17:18Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_w11a_c7 +-- Description: Configuration for tb_w11a_c7 for tb_crama7_sram +-- +-- Dependencies: sys_w11a_c7 +-- +-- To test: sys_w11a_c7 +-- +-- Verified (with (#1) ../../tb/tb_rritba_pdp11core_stim.dat +-- (#2) ../../tb/tb_pdp11_core_stim.dat): +-- Date Rev Code ghdl ise Target Comment +-- 2017-06-24 914 - -.-- - - -:-- +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-06-24 914 1.0 Initial version (cloned from _n4) +------------------------------------------------------------------------------ + +configuration tb_w11a_c7 of tb_cmoda7_sram is + + for sim + for all : cmoda7_sram_aif + use entity work.sys_w11a_c7; + end for; + end for; + +end tb_w11a_c7; diff --git a/rtl/sys_gen/w11a/cmoda7/tb/tb_w11a_c7_ssim.vbom b/rtl/sys_gen/w11a/cmoda7/tb/tb_w11a_c7_ssim.vbom new file mode 100644 index 00000000..0c03c433 --- /dev/null +++ b/rtl/sys_gen/w11a/cmoda7/tb/tb_w11a_c7_ssim.vbom @@ -0,0 +1,8 @@ +# configure for _*sim case +# Note: this tb uses sys_w11a_c7.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +# configure +nexys4_cram_aif = sys_w11a_c7_ssim.vhd +# design +tb_w11a_c7.vbom +@top:tb_w11a_c7 diff --git a/rtl/sys_gen/w11a/cmoda7/tb/tbrun.yml b/rtl/sys_gen/w11a/cmoda7/tb/tbrun.yml new file mode 100644 index 00000000..2d50c392 --- /dev/null +++ b/rtl/sys_gen/w11a/cmoda7/tb/tbrun.yml @@ -0,0 +1,29 @@ +# $Id: tbrun.yml 916 2017-06-25 13:30:07Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-06-24 914 1.0 Initial version +# +- default: + mode: ${viv_modes} +# +- tag: [default, viv, sys_w11a, c7, stim1] + test: | + tbrun_tbwrri --hxon --lsuf stim1 tb_w11a_c7${ms} \ + "rlink::run_rri ../../../../w11a/tb/tb_rlink_tba_pdp11core_stim.dat" + +- tag: [default, viv, sys_w11a, c7, stim2] + test: | + tbrun_tbwrri --hxon --lsuf stim2 --pack rw11 tb_w11a_c7${ms} \ + "rw11::setup_cpu" \ + "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat 60." + +- tag: [default, viv, sys_w11a, c7, tbcpu] + test: | + tbrun_tbwrri --hxon --lsuf tbcpu --pack rw11 tb_w11a_c7${ms} \ + "rw11::setup_cpu" "rw11::tbench @cpu_all.dat" + +- tag: [default, viv, sys_w11a, c7, tbdev] + test: | + tbrun_tbwrri --hxon --lsuf tbdev --pack rw11 tb_w11a_c7${ms} \ + "rw11::setup_cpu" "rw11::tbench @dev_all.dat" diff --git a/rtl/sys_gen/w11a/cmoda7/tb/tbw.dat b/rtl/sys_gen/w11a/cmoda7/tb/tbw.dat new file mode 100644 index 00000000..7eb24960 --- /dev/null +++ b/rtl/sys_gen/w11a/cmoda7/tb/tbw.dat @@ -0,0 +1,7 @@ +# $Id: tbw.dat 914 2017-06-25 06:17:18Z mueller $ +# +[tb_w11a_c7] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = +sysmon_stim = ../../../../bplib/sysmon/tb/sysmon_stim_n4.dat diff --git a/rtl/sys_gen/w11a/tbrun.yml b/rtl/sys_gen/w11a/tbrun.yml index b29da990..f1be1f26 100644 --- a/rtl/sys_gen/w11a/tbrun.yml +++ b/rtl/sys_gen/w11a/tbrun.yml @@ -1,7 +1,8 @@ -# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $ +# $Id: tbrun.yml 916 2017-06-25 13:30:07Z mueller $ # # Revision History: # Date Rev Version Comment +# 2017-06-25 914 1.1 add cmoda7 # 2016-08-22 800 1.0 Initial version # - include: s3board/tb/tbrun.yml @@ -10,3 +11,4 @@ - include: nexys4/tb/tbrun.yml - include: basys3/tb/tbrun.yml - include: arty_bram/tb/tbrun.yml +- include: cmoda7/tb/tbrun.yml diff --git a/tbrun.yml b/tbrun.yml index dbac662c..de33b71c 100644 --- a/tbrun.yml +++ b/tbrun.yml @@ -1,4 +1,4 @@ -# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $ +# $Id: tbrun.yml 913 2017-06-13 20:18:49Z mueller $ # # Revision History: # Date Rev Version Comment @@ -11,6 +11,7 @@ - include: rtl/bplib/micron/tb/tbrun.yml - include: rtl/bplib/nxcramlib/tb/tbrun.yml - include: rtl/bplib/s3board/tb/tbrun.yml +- include: rtl/bplib/cmoda7/tb/tbrun.yml - include: rtl/w11a/tb/tbrun.yml - include: rtl/sys_gen/tst_serloop/tbrun.yml - include: rtl/sys_gen/tst_rlink/tbrun.yml diff --git a/tools/bin/ti_rri b/tools/bin/ti_rri index 36841d65..2c4fbeae 100755 --- a/tools/bin/ti_rri +++ b/tools/bin/ti_rri @@ -1,6 +1,6 @@ #! /usr/bin/env tclshcpp # -*- tcl -*- -# $Id: ti_rri 883 2017-04-22 11:57:38Z mueller $ +# $Id: ti_rri 918 2017-06-28 20:04:17Z mueller $ # # Copyright 2011-2017 by Walter F.J. Mueller # @@ -15,6 +15,7 @@ # # Revision History: # Date Rev Version Comment +# 2017-06-28 918 1.4.5 adopt Digilent autodetect for CmodA7 # 2017-04-22 883 1.4.4 setup rbus monitor if detected # 2017-01-08 843 1.4.3 allow --term=USBD for Digilent autodetect # 2015-01-09 776 1.2.2 add --tout option to setup rlc timeout before connect @@ -275,10 +276,12 @@ if { $opts(term) } { set id_in {} foreach line [split $text "\n"] { set line [string trim $line] - regexp -- {^E: ID_SERIAL=(.*)_(\d*)$} $line matched id_id id_sn - regexp -- {^E: ID_USB_INTERFACE_NUM=(.*)$} $line matched id_in + regexp -- {^E: ID_SERIAL=(.*)_([0-9a-fA-F]+)$} $line matched id_id id_sn + regexp -- {^E: ID_USB_INTERFACE_NUM=(.*)$} $line matched id_in } - if {$id_id eq "Digilent_Digilent_USB_Device" && $id_in eq "01"} { + if {($id_id eq "Digilent_Digilent_USB_Device" || \ + $id_id eq "Digilent_Digilent_Adept_USB_Device" ) \ + && $id_in eq "01"} { set dev_usbd $udev break } diff --git a/tools/bin/ti_w11 b/tools/bin/ti_w11 index 9e06867b..b24968aa 100755 --- a/tools/bin/ti_w11 +++ b/tools/bin/ti_w11 @@ -1,11 +1,12 @@ #!/usr/bin/perl -w -# $Id: ti_w11 843 2017-01-08 18:15:27Z mueller $ +# $Id: ti_w11 916 2017-06-25 13:30:07Z mueller $ # # Copyright 2013-2017 by Walter F.J. Mueller # License disclaimer see License.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2017-06-25 916 1.4.2 add -c7 (cmoda7 support) # 2017-01-08 843 1.4.1 allow -tuD,.... for Digilent autodetect; add -bn4d # 2016-12-31 834 1.4 use rw11::shell by default; add -ns to suppress it # 2016-06-18 776 1.3.5 use ti_rri --tout now @@ -53,6 +54,7 @@ my $val_tb_n4 = "tbw $sysbase/nexys4/tb/tb_w11a_n4 -fifo"; my $val_tb_bn4 = "tbw $sysbase/nexys4_bram/tb/tb_w11a_br_n4 -fifo"; my $val_tb_bn4d = "tbw $sysbase/nexys4d_bram/tb/tb_w11a_br_n4d -fifo"; my $val_tb_bar = "tbw $sysbase/arty_bram/tb/tb_w11a_br_arty -fifo"; +my $val_tb_c7 = "tbw $sysbase/cmoda7/tb/tb_w11a_c7 -fifo"; my $val_tb; my $val_e; @@ -132,6 +134,12 @@ while (scalar(@ARGV)) { $val_tb = $val_tb_bar; shift @ARGV; + } elsif ($curarg =~ m{^-c7$} ) { # -c7 (use -fx by default) + $opt_io = 'f'; + $opt_f = 'x'; + $val_tb = $val_tb_c7; + shift @ARGV; + } elsif ($curarg =~ m{^-f(c|x|1|1x|2|2x)$} ) { # -f.. $opt_f = $1; shift @ARGV; @@ -343,6 +351,7 @@ exit 1; sub print_usage { print "usage: ti_w11 ...\n"; print " setup options for ghdl simulation runs:\n"; + print " -c7 start tb_w11a_c7 simulation (default: -fx)\n"; print " -b3 start tb_w11a_b3 simulation (default: -fx)\n"; print " -n4 start tb_w11a_n4 simulation\n"; print " -bn4 start tb_w11a_br_n4 simulation\n"; diff --git a/tools/man/man1/ti_w11.1 b/tools/man/man1/ti_w11.1 index 8a04a8e0..b50ea033 100644 --- a/tools/man/man1/ti_w11.1 +++ b/tools/man/man1/ti_w11.1 @@ -1,11 +1,11 @@ .\" -*- nroff -*- -.\" $Id: ti_w11.1 845 2017-01-15 14:58:27Z mueller $ +.\" $Id: ti_w11.1 916 2017-06-25 13:30:07Z mueller $ .\" .\" Copyright 2013-2017 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ . -.TH TI_W11 1 2017-01-14 "Retro Project" "Retro Project Manual" +.TH TI_W11 1 2017-06-25 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME ti_w11 \- Quick starter for \fBti_rri\fP with \fBw11\fP CPU designs @@ -55,6 +55,8 @@ use /dev/ttyUSB* (* is device number \fIN\fP or 'D') . .SS "setup options for ghdl simulation runs" .PD 0 +.IP \fB-c7\fP +start \fItb_w11a_c7\fP simulation (Cmod A7, default \fB-fx\fP) .IP \fB-b3\fP start \fItb_w11a_b3\fP simulation (Basys3, default \fB-fx\fP) .IP \fB-n4\fP @@ -81,7 +83,7 @@ for mode \fIm\fP are .IP \fBc\fP 4 use Cypress FX2 data path (cuff, only for -n2 and -n3) .IP \fBx\fP 4 -use 1st serport with hardwired xon (for -b3 and -arty) +use 1st serport with hardwired xon (for -b3,-bar,-c7) .IP \fB1\fP 4 use 1st serport .IP \fB1x\fP 4 diff --git a/tools/sys/92-retro-usb-persistent.rules b/tools/sys/92-retro-usb-persistent.rules index 0fcfbd49..c1d3b22c 100644 --- a/tools/sys/92-retro-usb-persistent.rules +++ b/tools/sys/92-retro-usb-persistent.rules @@ -1,4 +1,4 @@ -# $Id: 92-retro-usb-persistent.rules 902 2017-06-03 14:02:17Z mueller $ +# $Id: 92-retro-usb-persistent.rules 918 2017-06-28 20:04:17Z mueller $ # # udev rules to create persistent names for Digilent FT2232C style FPGA boards # @@ -11,7 +11,17 @@ # interface number are properties of different device layers and multiple # ATTRS{} must match in one layer # -# NOTE: this is an example, adopt ID_SERIAL_SHORT to your needs +# NOTE: this is an example, adopt ID_SERIAL_SHORT to your needs, use +# udevadm info -q all -n /dev/ttyUSB2 # change USB2 to need # # - Digilent nexys4 board ------------------------------------------------ SUBSYSTEM=="tty", ENV{ID_USB_INTERFACE_NUM}=="01", ENV{ID_MODEL}=="Digilent_USB_Device", ENV{ID_SERIAL_SHORT}=="210274628291", SYMLINK="fpga_n4" +# +# - Digilent basys3 board ------------------------------------------------ +SUBSYSTEM=="tty", ENV{ID_USB_INTERFACE_NUM}=="01", ENV{ID_MODEL}=="Digilent_USB_Device", ENV{ID_SERIAL_SHORT}=="210183638100", SYMLINK="fpga_b3" +# +# - Digilent arty board -------------------------------------------------- +SUBSYSTEM=="tty", ENV{ID_USB_INTERFACE_NUM}=="01", ENV{ID_MODEL}=="Digilent_USB_Device", ENV{ID_SERIAL_SHORT}=="210319788597", SYMLINK="fpga_arty" +# +# - Digilent arty board -------------------------------------------------- +SUBSYSTEM=="tty", ENV{ID_USB_INTERFACE_NUM}=="01", ENV{ID_MODEL}=="Digilent_Adept_USB_Device", ENV{ID_SERIAL_SHORT}=="210328A414AD", SYMLINK="fpga_c7" diff --git a/tools/tcl/rbs3hio/util.tcl b/tools/tcl/rbs3hio/util.tcl index 152eec5f..ec157f07 100644 --- a/tools/tcl/rbs3hio/util.tcl +++ b/tools/tcl/rbs3hio/util.tcl @@ -1,4 +1,4 @@ -# $Id: util.tcl 895 2017-05-07 07:38:47Z mueller $ +# $Id: util.tcl 912 2017-06-11 18:30:03Z mueller $ # # Copyright 2011-2017 by Walter F.J. Mueller # @@ -30,7 +30,7 @@ namespace eval rbs3hio { # # setup register descriptions for s3_humanio_rbus # - regdsc STAT {hdig 14 3} {hled 11 4} {hbtn 7 4} {hswi 3 4} + regdsc STAT {emu 15} {hdig 14 3} {hled 11 4} {hbtn 7 4} {hswi 3 4} regdsc CNTL {dsp1en 4} {dsp0en 3} {dpen 2} {leden 1} {swien 0} #