diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md
index 4414b32a..94b9eac2 100644
--- a/doc/CHANGELOG.md
+++ b/doc/CHANGELOG.md
@@ -2,6 +2,7 @@
### Table of contents
- Current [HEAD](#user-content-head)
+- Release [w11a_V0.752](#user-content-w11a_V0.752)
- Release [w11a_V0.751](#user-content-w11a_V0.751)
- Release [w11a_V0.75](#user-content-w11a_V0.75)
- Release [w11a_V0.742](#user-content-w11a_V0.742)
@@ -19,10 +20,33 @@ software or firmware builds or that the documentation is consistent.
The full set of tests is only run for tagged releases.
### Summary
+
+
+---
+## 2018-08-26: [w11a_V0.752](https://github.com/wfjm/w11/releases/tag/w11a_V0.752) - rev 1041(wfjm)
+### Summary
+- the Arty board is now also offered with a Spartan-7 FPGA. To evaluate the
+ Spartan vs Artix performance a w11a port to the Arty S7 board was added.
+ The design runs with 80 MHz, same clock rate as achieved with Artix-7 FPGAs.
+ _Note_: the design is only simulation tested, was _not FPGA tested_ !!
+- use vivado 2017.2 as default (needed for Spartan-7 support). All vivado
+ versions from 2017.3 to 2018.2 were tested. All designs build properly under
+ vivado 2018.2, but the CPU time for a build increased very substantially,
+ so they are currently not used as default build tool.
+
+### New features
+- Add Digilent Arty A7 (50 die size) support
+ - general board support (for rev E board)
+ - rgbdrv_3x2mux.vhd : driver for array with 2 RGB LEDs
+ - add systems
+ - w11a: w11a system with 256 kB memory (from BRAM) (_only sim tested_)
+### Changes
- xviv_msg_filter: allow {yyyy.x} tags (in addition to ranges)
- xviv_msg_summary: check also for .bit and .dcp files
-- get vivado 2017.2 ready; all designs build under 2017.2 and 2018.2
-- *.vmfset: update rules to cover 2017.4-2018.2
+- get vivado 2017.2 ready (needed for Spartan-7 support)
+- test vivado 2017.3 - 2018.2 ready
+ - *.vmfset: update rules to cover 2017.4-2018.2
+ - all designs build under 2017.2 and 2018.2
---
@@ -50,7 +74,7 @@ The full set of tests is only run for tagged releases.
- rgbdrv_analog(_rbus): add ACTLOW generic to invert output polarity
- ti_rri: adopt Digilent autodetect for CmodA7
- add systems
- - tst_rlink: rlink tested
+ - tst_rlink: rlink tester
- tst_sram: SRAM tester
- w11a: w11a system with 672 kB memory (512 SRAM + 160 BRAM)
- rtl/vlib/rutil.vhd: added package, with imin helper function
diff --git a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd
index 06299c6d..7921d90b 100644
--- a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd
+++ b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd
@@ -1,6 +1,6 @@
--- $Id: sys_w11a_br_arty.vhd 984 2018-01-02 20:56:27Z mueller $
+-- $Id: sys_w11a_br_arty.vhd 1039 2018-08-12 10:04:09Z mueller $
--
--- Copyright 2016-2017 by Walter F.J. Mueller
+-- Copyright 2016-2018 by Walter F.J. Mueller
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -33,10 +33,15 @@
-- Test bench: tb/tb_sys_w11a_br_arty
--
-- Target Devices: generic
--- Tool versions: viv 2015.4-2016.4; ghdl 0.33
+-- Tool versions: viv 2015.4-2018.2; ghdl 0.33-0.34
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
+-- 2018-08-11 1038 2018.2 xc7a35t-1 2283 5190 138 47.5 1602
+-- 2018-08-11 1038 2018.1 xc7a35t-1 2283 5193 138 47.5 1616
+-- 2018-08-11 1038 2017.4 xc7a35t-1 2278 5130 138 47.5 1541
+-- 2018-08-11 1038 2017.2 xc7a35t-1 2275 5104 138 47.5 1581
+-- 2018-08-11 1038 2017.1 xc7a35t-1 2275 5104 138 47.5 1581
-- 2017-04-16 881 2016.4 xc7a35t-1 2275 5104 138 47.5 1611 +DEUNA
-- 2017-01-29 846 2016.4 xc7a35t-1 2225 5100 138 47.5 1555 +int24
-- 2016-05-26 768 2016.1 xc7a35t-1 2226 5080 138 47.5 1569 fsm+dsm=0
diff --git a/tools/dox/w11_cpp.Doxyfile b/tools/dox/w11_cpp.Doxyfile
index e8d7e444..ea14d3cb 100644
--- a/tools/dox/w11_cpp.Doxyfile
+++ b/tools/dox/w11_cpp.Doxyfile
@@ -5,7 +5,7 @@
#---------------------------------------------------------------------------
DOXYFILE_ENCODING = UTF-8
PROJECT_NAME = "w11 - cpp"
-PROJECT_NUMBER = 0.751
+PROJECT_NUMBER = 0.752
PROJECT_BRIEF = "Backend server for Rlink and w11"
PROJECT_LOGO =
OUTPUT_DIRECTORY = $(RETRODOXY)/w11/cpp
diff --git a/tools/dox/w11_tcl.Doxyfile b/tools/dox/w11_tcl.Doxyfile
index e62891da..4fdce5f4 100644
--- a/tools/dox/w11_tcl.Doxyfile
+++ b/tools/dox/w11_tcl.Doxyfile
@@ -5,7 +5,7 @@
#---------------------------------------------------------------------------
DOXYFILE_ENCODING = UTF-8
PROJECT_NAME = "w11 - tcl"
-PROJECT_NUMBER = 0.751
+PROJECT_NUMBER = 0.752
PROJECT_BRIEF = "Backend server for Rlink and w11"
PROJECT_LOGO =
OUTPUT_DIRECTORY = $(RETRODOXY)/w11/tcl
diff --git a/tools/dox/w11_vhd_all.Doxyfile b/tools/dox/w11_vhd_all.Doxyfile
index 6ab395e3..e63dec22 100644
--- a/tools/dox/w11_vhd_all.Doxyfile
+++ b/tools/dox/w11_vhd_all.Doxyfile
@@ -5,7 +5,7 @@
#---------------------------------------------------------------------------
DOXYFILE_ENCODING = UTF-8
PROJECT_NAME = "w11 - vhd"
-PROJECT_NUMBER = 0.751
+PROJECT_NUMBER = 0.752
PROJECT_BRIEF = "W11 CPU core and support modules"
PROJECT_LOGO =
OUTPUT_DIRECTORY = $(RETRODOXY)/w11/vhd