From 0e87dd8670dfb8d0e8821120fcd96dc743a9d6a8 Mon Sep 17 00:00:00 2001 From: wfjm Date: Wed, 2 Jan 2019 10:06:25 +0100 Subject: [PATCH] add sramif2migui: w11a SRAM to MIG UI interface core --- .travis.yml | 19 +- doc/CHANGELOG.md | 10 +- rtl/bplib/mig/migui2bram.vbom | 12 + rtl/bplib/mig/migui2bram.vhd | 180 ++++++ rtl/bplib/mig/sramif2migui_core.vbom | 10 + rtl/bplib/mig/sramif2migui_core.vhd | 423 ++++++++++++++ rtl/bplib/mig/tb/.gitignore | 5 + rtl/bplib/mig/tb/Makefile | 45 ++ rtl/bplib/mig/tb/sys_conf_ba3_bram.vhd | 42 ++ rtl/bplib/mig/tb/sys_conf_ba3_msim.vhd | 42 ++ rtl/bplib/mig/tb/sys_conf_ba4_bram.vhd | 42 ++ rtl/bplib/mig/tb/sys_conf_ba4_msim.vhd | 42 ++ rtl/bplib/mig/tb/tb_sramif2migui_core.vbom | 13 + rtl/bplib/mig/tb/tb_sramif2migui_core.vhd | 532 ++++++++++++++++++ .../mig/tb/tb_sramif2migui_core_ba3_bram.vbom | 6 + .../mig/tb/tb_sramif2migui_core_ba3_msim.vbom | 6 + .../mig/tb/tb_sramif2migui_core_ba4_bram.vbom | 6 + .../mig/tb/tb_sramif2migui_core_ba4_msim.vbom | 6 + .../mig/tb/tb_sramif2migui_core_stim.dat | 268 +++++++++ rtl/bplib/mig/tb/tbrun.yml | 26 + rtl/bplib/mig/tb/tbw.dat | 10 + tbrun.yml | 5 +- 22 files changed, 1737 insertions(+), 13 deletions(-) create mode 100644 rtl/bplib/mig/migui2bram.vbom create mode 100644 rtl/bplib/mig/migui2bram.vhd create mode 100644 rtl/bplib/mig/sramif2migui_core.vbom create mode 100644 rtl/bplib/mig/sramif2migui_core.vhd create mode 100644 rtl/bplib/mig/tb/.gitignore create mode 100644 rtl/bplib/mig/tb/Makefile create mode 100644 rtl/bplib/mig/tb/sys_conf_ba3_bram.vhd create mode 100644 rtl/bplib/mig/tb/sys_conf_ba3_msim.vhd create mode 100644 rtl/bplib/mig/tb/sys_conf_ba4_bram.vhd create mode 100644 rtl/bplib/mig/tb/sys_conf_ba4_msim.vhd create mode 100644 rtl/bplib/mig/tb/tb_sramif2migui_core.vbom create mode 100644 rtl/bplib/mig/tb/tb_sramif2migui_core.vhd create mode 100644 rtl/bplib/mig/tb/tb_sramif2migui_core_ba3_bram.vbom create mode 100644 rtl/bplib/mig/tb/tb_sramif2migui_core_ba3_msim.vbom create mode 100644 rtl/bplib/mig/tb/tb_sramif2migui_core_ba4_bram.vbom create mode 100644 rtl/bplib/mig/tb/tb_sramif2migui_core_ba4_msim.vbom create mode 100644 rtl/bplib/mig/tb/tb_sramif2migui_core_stim.dat create mode 100644 rtl/bplib/mig/tb/tbrun.yml create mode 100644 rtl/bplib/mig/tb/tbw.dat diff --git a/.travis.yml b/.travis.yml index 9d933f62..279e5343 100644 --- a/.travis.yml +++ b/.travis.yml @@ -5,25 +5,27 @@ sudo: required # matrix: include: - - name: "gcc 4.8" + - name: "Ub 14.04 -- gcc 4.8" env: MATRIX_EVAL="CC=gcc && CXX=g++" - - name: "gcc 7" + - name: "Ub 14.04 -- gcc 7" addons: apt: sources: ubuntu-toolchain-r-test packages: g++-7 env: MATRIX_EVAL="CC=gcc-7 && CXX=g++-7" - - name: "clang" + - name: "Ub 14.04 -- clang" env: MATRIX_EVAL="CC=clang && CXX=clang++" + - name: "Ub 16.04 -- gcc" + dist: xenial + env: MATRIX_EVAL="CC=gcc && CXX=g++" + # before_install: - | sudo apt-get install -y \ - libboost-dev libboost-date-time-dev \ - libboost-thread-dev libboost-regex-dev \ libusb-1.0-0-dev \ tcl8.6 tcl8.6-dev tcllib tclreadline \ libyaml-libyaml-perl @@ -34,7 +36,8 @@ before_install: # before_script: - - less /proc/cpuinfo | grep "^model name" | head -n 1 + - cat /proc/cpuinfo + - lsb_release -d - bash -c '${CC} --version' - bash -c '${CXX} --version' - export RETROBASE=$PWD @@ -48,13 +51,13 @@ before_script: # script: - - make -j 2 -C tools/src + - time make -j 2 -C tools/src - make -j 2 -C tools/src/testtclsh - make all_tcl - make -C tools/asm-11/tests allexp - make -C tools/asm-11/tests-err allexp - | - tbrun -j 2 -nomake \ + time tbrun -j 2 -nomake \ -tag default,memlib \ -tag default,genlib \ -tag default,comlib \ diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index 101f9c70..9033a6e3 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -32,11 +32,15 @@ The full set of tests is only run for tagged releases. - s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk - cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input - migui_core_gsim: highly simplified MIG UI simulation model + - sramif2migui_core: w11a SRAM to MIG UI interface core ### Changes -- viv_tools_build - - export log and rpt generated in OOC synthesis runs - - downgrade SSN critical warnings to warnings +- general + - travis: use -j 2 +- tools changes + - viv_tools_build + - export log and rpt generated in OOC synthesis runs + - downgrade SSN critical warnings to warnings ### Bug Fixes - nexys4d_pins.xdc: BUFFIX: Fix faulty IO voltage for I_SWI[8,9] diff --git a/rtl/bplib/mig/migui2bram.vbom b/rtl/bplib/mig/migui2bram.vbom new file mode 100644 index 00000000..82553b79 --- /dev/null +++ b/rtl/bplib/mig/migui2bram.vbom @@ -0,0 +1,12 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/memlib/memlib.vhd +../../vlib/cdclib/cdclib.vhd +../../vlib/xlib/xlib.vhd +# components +[vsyn]../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl,vsim]../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../vlib/memlib/ram_1swsr_wfirst_gen.vbom +../../vlib/cdclib/cdc_signal_s1_as.vbom +# design +migui2bram.vhd diff --git a/rtl/bplib/mig/migui2bram.vhd b/rtl/bplib/mig/migui2bram.vhd new file mode 100644 index 00000000..da6ae72c --- /dev/null +++ b/rtl/bplib/mig/migui2bram.vhd @@ -0,0 +1,180 @@ +-- $Id: migui2bram.vhd 1096 2018-12-29 07:54:17Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: migui2bram - sim +-- Description: MIG to BRAM adapter +-- +-- Dependencies: xlib/s7_cmt_sfs +-- memlib/ram_1swsr_wfirst_gen +-- cdclib/cdc_signal_s1_as +-- Test bench: - +-- Target Devices: 7-Series +-- Tool versions: viv 2017.2; ghdl 0.34 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2018-12-28 1096 1.0 Initial version +-- 2018-11-10 1067 0.1 First draft +-- +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.memlib.all; +use work.cdclib.all; +use work.xlib.all; + +entity migui2bram is -- MIG to BRAM adapter + generic ( + BAWIDTH : positive := 4; -- byte address width + MAWIDTH : positive := 28; -- memory address width + RAWIDTH : positive := 19; -- BRAM memory address width + RDELAY : positive := 5; -- read response delay + CLKMUI_MUL : positive := 6; -- multiplier for MIGUI clock + CLKMUI_DIV : positive := 12; -- divider for MIGUI clock + CLKMSYS_PERIOD : real := 6.000); -- MIG SYS_CLK period + port ( + SYS_CLK : in slbit; -- system clock + SYS_RST : in slbit; -- system reset + UI_CLK : out slbit; -- MIGUI clock + UI_CLK_SYNC_RST : out slbit; -- MIGUI reset + INIT_CALIB_COMPLETE : out slbit; -- MIGUI calibration done + APP_RDY : out slbit; -- MIGUI ready for cmd + APP_EN : in slbit; -- MIGUI command enable + APP_CMD : in slv3; -- MIGUI command + APP_ADDR : in slv(MAWIDTH-1 downto 0); -- MIGUI address + APP_WDF_RDY : out slbit; -- MIGUI ready for data write + APP_WDF_WREN : in slbit; -- MIGUI data write enable + APP_WDF_DATA : in slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI write data + APP_WDF_MASK : in slv((2**BAWIDTH)-1 downto 0); -- MIGUI write mask + APP_WDF_END : in slbit; -- MIGUI write end + APP_RD_DATA_VALID : out slbit; -- MIGUI read valid + APP_RD_DATA : out slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI read data + APP_RD_DATA_END : out slbit -- MIGUI read end + ); +end migui2bram; + + +architecture syn of migui2bram is + + constant mwidth : positive := 2**BAWIDTH; -- mask width (8 or 16) + + signal CLKFX : slbit := '0'; + signal CLK : slbit := '0'; -- local copy of UI_CLK + signal R_RDVAL : slv(RDELAY downto 0) := (others=>'0'); + + signal LOCKED : slbit := '0'; -- raw from mmcm + signal LOCKED_UICLK : slbit := '0'; -- sync'ed to UI_CLK + + +begin + + assert BAWIDTH = 3 or BAWIDTH = 4 + report "assert( BAWIDTH = 3 or 4 )" + severity failure; + + GEN_CLKMUI : s7_cmt_sfs -- ui clock ------------ + generic map ( + VCO_DIVIDE => 1, + VCO_MULTIPLY => CLKMUI_MUL, + OUT_DIVIDE => CLKMUI_DIV, + CLKIN_PERIOD => CLKMSYS_PERIOD, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => "MMCM") + port map ( + CLKIN => SYS_CLK, + CLKFX => CLKFX, + LOCKED => LOCKED + ); + + CLK <= CLKFX; -- !! copy both local CLK and exported + UI_CLK <= CLKFX; -- !! UI_CLK to avoid delta cycle diff + + CDC_LOCKED : cdc_signal_s1_as + port map ( + CLKO => CLK, + DI => LOCKED, + DO => LOCKED_UICLK + ); + + MARRAY: for col in mwidth-1 downto 0 generate + signal MEM_WE : slbit := '0'; + begin + MEM_WE <= APP_WDF_WREN and not APP_WDF_MASK(col); -- WE = not MASK ! + MCELL : ram_1swsr_wfirst_gen + generic map ( + AWIDTH => RAWIDTH-BAWIDTH, + DWIDTH => 8) -- byte wide + port map ( + CLK => CLK, + EN => APP_EN, + WE => MEM_WE, + ADDR => APP_ADDR(RAWIDTH-1 downto BAWIDTH), + DI => APP_WDF_DATA(8*col+7 downto 8*col), + DO => APP_RD_DATA(8*col+7 downto 8*col) + ); + end generate MARRAY; + + UI_CLK_SYNC_RST <= not LOCKED_UICLK; + INIT_CALIB_COMPLETE <= LOCKED_UICLK; + + APP_RDY <= '1'; + APP_WDF_RDY <= '1'; + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if SYS_RST = '1' then + R_RDVAL <= (others=>'0'); + else + R_RDVAL(0) <= APP_EN and not APP_WDF_WREN; + R_RDVAL(RDELAY downto 1) <= R_RDVAL(RDELAY-1 downto 0); + end if; + end if; + + end process proc_regs; + + APP_RD_DATA_VALID <= R_RDVAL(RDELAY); + APP_RD_DATA_END <= R_RDVAL(RDELAY); + +-- synthesis translate_off + + proc_moni: process (CLK) + begin + if rising_edge(CLK) then + if SYS_RST = '0' then + if APP_EN = '1' then + assert unsigned(APP_ADDR(MAWIDTH-1 downto RAWIDTH)) = 0 + report "migui2bram: FAIL: out of memory size access" + severity error; + else + assert APP_WDF_WREN = '0' + report "migui2bram: FAIL: APP_WDF_WREN=1 when APP_EN=0" + severity error; + end if; + assert APP_WDF_WREN = APP_WDF_END + report "migui2bram: FAIL: APP_WDF_WREN /= APP_WDF_END" + severity error; + end if; + end if; + end process proc_moni; + +-- synthesis translate_on + +end syn; diff --git a/rtl/bplib/mig/sramif2migui_core.vbom b/rtl/bplib/mig/sramif2migui_core.vbom new file mode 100644 index 00000000..66929145 --- /dev/null +++ b/rtl/bplib/mig/sramif2migui_core.vbom @@ -0,0 +1,10 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/memlib/memlib.vhd +../../vlib/cdclib/cdclib.vhd +miglib.vhd +# components +../../vlib/memlib/fifo_2c_dram2.vbom +../../vlib/cdclib/cdc_signal_s1.vbom +# design +sramif2migui_core.vhd diff --git a/rtl/bplib/mig/sramif2migui_core.vhd b/rtl/bplib/mig/sramif2migui_core.vhd new file mode 100644 index 00000000..8a17ea99 --- /dev/null +++ b/rtl/bplib/mig/sramif2migui_core.vhd @@ -0,0 +1,423 @@ +-- $Id: sramif2migui_core.vhd 1096 2018-12-29 07:54:17Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sramif2migui_core - syn +-- Description: SRAM to MIG interface core +-- +-- Dependencies: memlib/fifo_2c_dram2 +-- cdclib/cdc_signal_s1 +-- Test bench: tb/tb_sramif2migui_core +-- Target Devices: generic +-- Tool versions: viv 2017.2; ghdl 0.34 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2018-12-28 1096 1.0 Initial version +-- 2018-11-04 1066 0.1 First draft +-- +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.memlib.all; +use work.cdclib.all; +use work.miglib.all; + +entity sramif2migui_core is -- SRAM to MIG interface core + generic ( + BAWIDTH : positive := 4; -- byte address width + MAWIDTH : positive := 28); -- memory address width + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + REQ : in slbit; -- request + WE : in slbit; -- write enable + BUSY : out slbit; -- controller busy + ACK_R : out slbit; -- acknowledge read + ACK_W : out slbit; -- acknowledge write + ACT_R : out slbit; -- signal active read + ACT_W : out slbit; -- signal active write + ADDR : in slv20; -- address (32 bit word address) + BE : in slv4; -- byte enable + DI : in slv32; -- data in (memory view) + DO : out slv32; -- data out (memory view) + MONI : out sramif2migui_moni_type; -- monitor signals + UI_CLK : in slbit; -- MIGUI clock + UI_CLK_SYNC_RST : in slbit; -- MIGUI reset + INIT_CALIB_COMPLETE : in slbit; -- MIGUI calibration done + APP_RDY : in slbit; -- MIGUI ready for cmd + APP_EN : out slbit; -- MIGUI command enable + APP_CMD : out slv3; -- MIGUI command + APP_ADDR : out slv(MAWIDTH-1 downto 0); -- MIGUI address + APP_WDF_RDY : in slbit; -- MIGUI ready for data write + APP_WDF_WREN : out slbit; -- MIGUI data write enable + APP_WDF_DATA : out slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI write data + APP_WDF_MASK : out slv((2**BAWIDTH)-1 downto 0); -- MIGUI write mask + APP_WDF_END : out slbit; -- MIGUI write end + APP_RD_DATA_VALID : in slbit; -- MIGUI read valid + APP_RD_DATA : in slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI read data + APP_RD_DATA_END : in slbit -- MIGUI read end + ); +end sramif2migui_core; + + +architecture syn of sramif2migui_core is + + constant mwidth : positive := 2**BAWIDTH; -- mask width (8 or 16) + constant dwidth : positive := 8*mwidth; -- data width (64 or 128) + constant tawidth : positive := 20-(BAWIDTH-2); -- tag address width + constant rfwidth : positive := dwidth+mwidth+tawidth+1; -- req fifo width + + -- sram address fields + subtype sa_f_ta is integer range 20-1 downto BAWIDTH-2; -- tag addr + subtype sa_f_ga is integer range BAWIDTH-3 downto 0; -- group addr + -- mig address fields + subtype ma_f_ta is integer range 22-1 downto BAWIDTH; -- tag addr + + -- request fifo data fields + subtype rf_f_data is integer range dwidth+mwidth+tawidth + downto MWIDTH+tawidth+1; + subtype rf_f_mask is integer range mwidth+tawidth downto tawidth+1; + subtype rf_f_addr is integer range tawidth downto 1; + constant rf_f_we : integer := 0; + + constant ngrp : positive := 2**(BAWIDTH-2); -- # of 32bit groups (2 or 4) + + type regs_type is record + actr : slbit; -- active read flag + actw : slbit; -- active write flag + ackr : slbit; -- read acknowledge + req_addr : slv20; -- request address + req_be : slv4; -- request be + req_di : slv32; -- request di + res_do : slv32; -- response do + rdbuf : slv(dwidth-1 downto 0); -- read buffer + rdtag : slv(tawidth-1 downto 0); -- read tag address + rdval : slbit; -- read buffer valid + rdnew : slbit; -- read buffer new + rdpend : slbit; -- read request pending + wrbuf : slv(dwidth-1 downto 0); -- write buffer + wrtag : slv(tawidth-1 downto 0); -- write tag address + wrpend : slv(mwidth-1 downto 0); -- write buffer pending flags + end record regs_type; + + constant bufzero : slv(dwidth-1 downto 0) := (others=>'0'); + constant tagzero : slv(tawidth-1 downto 0) := (others=>'0'); + constant pendzero : slv(mwidth-1 downto 0) := (others=>'0'); + + constant regs_init : regs_type := ( + '0','0','0', -- actr,actw,ackr + (others=>'0'), -- req_addr + (others=>'0'), -- req_be + (others=>'0'), -- req_di + (others=>'0'), -- res_do + bufzero, -- rdbuf + tagzero, -- rdtag + '0','0','0', -- rdval,rdnew,rdpend + bufzero, -- wrbuf + tagzero, -- wrtag + pendzero -- wrpend + ); + + signal R_REGS : regs_type := regs_init; + signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) + + signal REQ_DI : slv(rfwidth-1 downto 0) := (others=>'0'); + signal REQ_DO : slv(rfwidth-1 downto 0) := (others=>'0'); + signal REQ_ENA : slbit := '0'; + signal REQ_VAL : slbit := '0'; + signal REQ_HOLD : slbit := '0'; + signal REQ_SIZE : slv4 := (others=>'0'); + + signal RES_DI : slv(dwidth-1 downto 0) := (others=>'0'); + signal RES_DO : slv(dwidth-1 downto 0) := (others=>'0'); + signal RES_ENA : slbit := '0'; + signal RES_VAL : slbit := '0'; + + signal APP_RDY_CLK : slbit := '0'; -- APP_RDY sync'ed to CLK + signal APP_WDF_RDY_CLK : slbit := '0'; -- APP_WDF_RDY_CLK sync'ed to CLK + signal MIGUIRST_CLK : slbit := '0'; -- UI_CLK_SYNC_RST sync'ed to CLK + signal MIGCACO_CLK : slbit := '0'; -- INIT_CALIB_COMPLETE sync'ed to CLK + +begin + + assert BAWIDTH = 3 or BAWIDTH = 4 + report "assert( BAWIDTH = 3 or 4 )" + severity failure; + + REQFIFO : fifo_2c_dram2 -- request fifo + generic map ( + AWIDTH => 4, + DWIDTH => rfwidth) + port map ( + CLKW => CLK, + CLKR => UI_CLK, + RESETW => '0', + RESETR => '0', + DI => REQ_DI, + ENA => REQ_ENA, + BUSY => open, + DO => REQ_DO, + VAL => REQ_VAL, + HOLD => REQ_HOLD, + SIZEW => REQ_SIZE, + SIZER => open + ); + + RESFIFO : fifo_2c_dram2 -- response fifo + generic map ( + AWIDTH => 4, + DWIDTH => dwidth) + port map ( + CLKW => UI_CLK, + CLKR => CLK, + RESETW => '0', + RESETR => '0', + DI => RES_DI, + ENA => RES_ENA, + BUSY => open, + DO => RES_DO, + VAL => RES_VAL, + HOLD => '0', + SIZEW => open, + SIZER => open + ); + + -- cdc for monitoring sigals from UI_CLK to CLK + CDC_CRDY : cdc_signal_s1 + port map ( + CLKO => CLK, + DI => APP_RDY, + DO => APP_RDY_CLK + ); + CDC_WRDY : cdc_signal_s1 + port map ( + CLKO => CLK, + DI => APP_WDF_RDY, + DO => APP_WDF_RDY_CLK + ); + CDC_UIRST : cdc_signal_s1 + port map ( + CLKO => CLK, + DI => UI_CLK_SYNC_RST, + DO => MIGUIRST_CLK + ); + CDC_CACO : cdc_signal_s1 + port map ( + CLKO => CLK, + DI => INIT_CALIB_COMPLETE, + DO => MIGCACO_CLK + ); + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, REQ, ADDR, BE, DI, WE, + REQ_SIZE, RES_VAL, RES_DO, + APP_RDY_CLK, APP_WDF_RDY_CLK, MIGUIRST_CLK, MIGCACO_CLK) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable iga : integer := 0; + variable ireqena : slbit := '0'; + variable iackw : slbit := '0'; + variable imoni : sramif2migui_moni_type := sramif2migui_moni_init; + + variable iwrbuf : slv(dwidth-1 downto 0) := (others=>'0'); + variable ireqdi : slv(rfwidth-1 downto 0) := (others=>'0'); + + begin + + r := R_REGS; + n := R_REGS; + + iga := 0; + ireqena := '0'; + iackw := '0'; + imoni := sramif2migui_moni_init; + + imoni.migcbusy := not APP_RDY_CLK; + imoni.migwbusy := not APP_WDF_RDY_CLK; + imoni.miguirst := MIGUIRST_CLK; + imoni.migcacow := not MIGCACO_CLK; + + -- setup request fifo data for write (the default) + ireqdi(rf_f_data) := r.wrbuf; + ireqdi(rf_f_mask) := not r.wrpend; -- -- MASK = not WE !! + ireqdi(rf_f_addr) := r.wrtag; + ireqdi(rf_f_we) := '1'; + + n.ackr := '0'; -- ensure one-shot + + -- handle idle state, capture input, and activate read or write + if r.actr='0' and r.actw='0' then + if REQ = '1' then + n.req_addr := ADDR; + n.req_be := BE; + n.req_di := DI; + if WE = '1' then -- write request + n.actw := '1'; + if r.wrtag = ADDR(sa_f_ta) then -- row hit + imoni.wrrhit := '1'; + else -- row miss + if r.wrpend /= pendzero then -- if write buffer pending + ireqena := '1'; -- queue write request + n.wrpend := pendzero; -- clear pending flags + imoni.wrflush := '1'; + end if; + end if; + + else -- read request + n.actr := '1'; + end if; -- WE='1' + + end if; -- REQ='1' + end if; + + iga := to_integer(unsigned(r.req_addr(sa_f_ga))); -- current group index + + -- handle write request + if r.actw = '1' then + -- write into wrbuf and wrpend, no pending data left when here + if r.req_be(0) = '1' then + n.wrbuf(32*iga+ 7 downto 32*iga ) := r.req_di( 7 downto 0); + end if; + if r.req_be(1) = '1' then + n.wrbuf(32*iga+15 downto 32*iga+ 8) := r.req_di(15 downto 8); + end if; + if r.req_be(2) = '1' then + n.wrbuf(32*iga+23 downto 32*iga+16) := r.req_di(23 downto 16); + end if; + if r.req_be(3) ='1' then + n.wrbuf(32*iga+31 downto 32*iga+24) := r.req_di(31 downto 24); + end if; + + n.wrtag := r.req_addr(sa_f_ta); -- set new tag address + n.wrpend(4*iga+3 downto 4*iga) := -- and update pending flags + n.wrpend(4*iga+3 downto 4*iga) or r.req_be; + + if r.rdtag = r.req_addr(sa_f_ta) then -- invalidate rdbuf if same tag + n.rdval := '0'; + end if; + + -- ensure that at most 4 pending writes in queue + -- REQ_SIZE gives # of available slots, empty FIFO has REQ_SIZE=15 + -- REQ_SIZE is 11 when 4 requests are on flight + if unsigned(REQ_SIZE) >= 11 then + n.actw := '0'; -- mark request done + iackw := '1'; -- send ack signal + end if; + end if; + + -- handle read request + if r.actr = '1' then + if r.rdtag=r.req_addr(sa_f_ta) and r.rdval='1' then -- + n.res_do := r.rdbuf(32*iga+31 downto 32*iga); + n.actr := '0'; -- mark request done + n.ackr := '1'; -- send ack signal + n.rdnew := '0'; -- mark used + imoni.rdrhit := not r.rdnew; + else + if r.wrpend /= pendzero then -- if write buffer pending + ireqena := '1'; -- queue write request + n.wrpend := pendzero; -- clear pending flags + imoni.wrflush := '1'; + elsif r.rdpend = '0' then + ireqdi(rf_f_addr) := r.req_addr(sa_f_ta); + ireqdi(rf_f_we) := '0'; + n.rdtag := r.req_addr(sa_f_ta); -- new tag + n.rdval := '0'; -- mark rdbuf invalid + n.rdpend := '1'; -- assert read pending + ireqena := '1'; -- queue read request + end if; + end if; + end if; + + -- handle read response + if RES_VAL = '1' then + n.rdbuf := RES_DO; -- capture data + n.rdval := '1'; -- mark valid + n.rdnew := '1'; -- mark new + n.rdpend := '0'; -- deassert read pending + end if; + + N_REGS <= n; + + REQ_DI <= ireqdi; + REQ_ENA <= ireqena; + MONI <= imoni; + + -- block input if busy or UI clock in RESET + BUSY <= r.actr or r.actw or MIGUIRST_CLK; + + ACK_R <= r.ackr; + ACK_W <= iackw; + ACT_R <= r.actr; + ACT_W <= r.actw; + DO <= r.res_do; + + end process proc_next; + + proc_req2app: process (APP_RDY, APP_WDF_RDY, REQ_VAL, REQ_DO, + INIT_CALIB_COMPLETE) + begin + + REQ_HOLD <= '0'; + + APP_ADDR <= (others=>'0'); + APP_ADDR(ma_f_ta) <= REQ_DO(rf_f_addr); + APP_WDF_DATA <= REQ_DO(rf_f_data); + APP_WDF_MASK <= REQ_DO(rf_f_mask); + + APP_EN <= '0'; + APP_CMD <= c_migui_cmd_read; + APP_WDF_WREN <= '0'; + APP_WDF_END <= '0'; + + if APP_RDY='1' and APP_WDF_RDY='1' and INIT_CALIB_COMPLETE='1' then + if REQ_VAL = '1' then + APP_EN <= '1'; + if REQ_DO(rf_f_we) = '1' then + APP_CMD <= c_migui_cmd_write; + APP_WDF_WREN <= '1'; + APP_WDF_END <= '1'; + end if; -- REQ_DO(rf_f_we) = '1' + end if; -- REQ_VAL = '1' + else + REQ_HOLD <= '1'; + end if; -- APP_RDY='1' and APP_WDF_RDY='1 + + end process proc_req2app; + + proc_app2res: process (APP_RD_DATA_VALID, APP_RD_DATA) + begin + RES_ENA <= APP_RD_DATA_VALID; + RES_DI <= APP_RD_DATA; + end process proc_app2res; + +end syn; diff --git a/rtl/bplib/mig/tb/.gitignore b/rtl/bplib/mig/tb/.gitignore new file mode 100644 index 00000000..f64e6871 --- /dev/null +++ b/rtl/bplib/mig/tb/.gitignore @@ -0,0 +1,5 @@ +tb_sramif2migui_core_ba3_bram +tb_sramif2migui_core_ba3_msim +tb_sramif2migui_core_ba4_bram +tb_sramif2migui_core_ba4_msim +tb_sramif2migui_core_stim diff --git a/rtl/bplib/mig/tb/Makefile b/rtl/bplib/mig/tb/Makefile new file mode 100644 index 00000000..c0612eab --- /dev/null +++ b/rtl/bplib/mig/tb/Makefile @@ -0,0 +1,45 @@ +# $Id: Makefile 1069 2018-11-16 17:11:30Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2018-11-16 1069 1.0 Initial version +# +EXE_all = tb_sramif2migui_core_ba3_bram +EXE_all += tb_sramif2migui_core_ba3_msim +EXE_all += tb_sramif2migui_core_ba4_bram +EXE_all += tb_sramif2migui_core_ba4_msim +# +# reference board for test synthesis is Artix-7 based Nexys4 +ifndef XTW_BOARD + XTW_BOARD=nexys4 +endif +include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk +# +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) +endif +# diff --git a/rtl/bplib/mig/tb/sys_conf_ba3_bram.vhd b/rtl/bplib/mig/tb/sys_conf_ba3_bram.vhd new file mode 100644 index 00000000..f742d23b --- /dev/null +++ b/rtl/bplib/mig/tb/sys_conf_ba3_bram.vhd @@ -0,0 +1,42 @@ +-- $Id: sys_conf_ba3_bram.vhd 1069 2018-11-16 17:11:30Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf_ba4_msim +-- Description: Definitions for tb_sramif2migui_core (bawidth=3;btyp=bram) +-- +-- Dependencies: - +-- Tool versions: viv 2017.2; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2018-11-16 1069 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +package sys_conf is + + -- define constants -------------------------------------------------------- + constant c_btyp_msim : string := "MSIM"; + constant c_btyp_bram : string := "BRAM"; + + -- configure --------------------------------------------------------------- + constant sys_conf_mawidth : positive := 28; + constant sys_conf_bawidth : positive := 3; -- 64 bit data path + constant sys_conf_sawidth : positive := 19; -- msim memory size + constant sys_conf_rawidth : positive := 19; -- bram memory size + constant sys_conf_rdelay : positive := 1; -- bram read delay + constant sys_conf_btyp : string := c_btyp_bram; + +end package sys_conf; diff --git a/rtl/bplib/mig/tb/sys_conf_ba3_msim.vhd b/rtl/bplib/mig/tb/sys_conf_ba3_msim.vhd new file mode 100644 index 00000000..5253c0e2 --- /dev/null +++ b/rtl/bplib/mig/tb/sys_conf_ba3_msim.vhd @@ -0,0 +1,42 @@ +-- $Id: sys_conf_ba3_msim.vhd 1069 2018-11-16 17:11:30Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf_ba4_msim +-- Description: Definitions for tb_sramif2migui_core (bawidth=3;btyp=msim) +-- +-- Dependencies: - +-- Tool versions: viv 2017.2; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2018-11-16 1069 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +package sys_conf is + + -- define constants -------------------------------------------------------- + constant c_btyp_msim : string := "MSIM"; + constant c_btyp_bram : string := "BRAM"; + + -- configure --------------------------------------------------------------- + constant sys_conf_mawidth : positive := 28; + constant sys_conf_bawidth : positive := 3; -- 64 bit data path + constant sys_conf_sawidth : positive := 19; -- msim memory size + constant sys_conf_rawidth : positive := 19; -- bram memory size + constant sys_conf_rdelay : positive := 1; -- bram read delay + constant sys_conf_btyp : string := c_btyp_msim; + +end package sys_conf; diff --git a/rtl/bplib/mig/tb/sys_conf_ba4_bram.vhd b/rtl/bplib/mig/tb/sys_conf_ba4_bram.vhd new file mode 100644 index 00000000..2a1a178d --- /dev/null +++ b/rtl/bplib/mig/tb/sys_conf_ba4_bram.vhd @@ -0,0 +1,42 @@ +-- $Id: sys_conf_ba4_bram.vhd 1069 2018-11-16 17:11:30Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf_ba4_msim +-- Description: Definitions for tb_sramif2migui_core (bawidth=4;btyp=bram) +-- +-- Dependencies: - +-- Tool versions: viv 2017.2; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2018-11-16 1069 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +package sys_conf is + + -- define constants -------------------------------------------------------- + constant c_btyp_msim : string := "MSIM"; + constant c_btyp_bram : string := "BRAM"; + + -- configure --------------------------------------------------------------- + constant sys_conf_mawidth : positive := 28; + constant sys_conf_bawidth : positive := 4; -- 128 bit data path + constant sys_conf_sawidth : positive := 19; -- msim memory size + constant sys_conf_rawidth : positive := 19; -- bram memory size + constant sys_conf_rdelay : positive := 1; -- bram read delay + constant sys_conf_btyp : string := c_btyp_bram; + +end package sys_conf; diff --git a/rtl/bplib/mig/tb/sys_conf_ba4_msim.vhd b/rtl/bplib/mig/tb/sys_conf_ba4_msim.vhd new file mode 100644 index 00000000..34352112 --- /dev/null +++ b/rtl/bplib/mig/tb/sys_conf_ba4_msim.vhd @@ -0,0 +1,42 @@ +-- $Id: sys_conf_ba4_msim.vhd 1069 2018-11-16 17:11:30Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf_ba4_msim +-- Description: Definitions for tb_sramif2migui_core (bawidth=4;btyp=msim) +-- +-- Dependencies: - +-- Tool versions: viv 2017.2; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2018-11-16 1069 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +package sys_conf is + + -- define constants -------------------------------------------------------- + constant c_btyp_msim : string := "MSIM"; + constant c_btyp_bram : string := "BRAM"; + + -- configure --------------------------------------------------------------- + constant sys_conf_mawidth : positive := 28; + constant sys_conf_bawidth : positive := 4; -- 128 bit data path + constant sys_conf_sawidth : positive := 19; -- msim memory size + constant sys_conf_rawidth : positive := 19; -- bram memory size + constant sys_conf_rdelay : positive := 1; -- bram read delay + constant sys_conf_btyp : string := c_btyp_msim; + +end package sys_conf; diff --git a/rtl/bplib/mig/tb/tb_sramif2migui_core.vbom b/rtl/bplib/mig/tb/tb_sramif2migui_core.vbom new file mode 100644 index 00000000..694a4fbe --- /dev/null +++ b/rtl/bplib/mig/tb/tb_sramif2migui_core.vbom @@ -0,0 +1,13 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/simlib/simlib.vhd +../miglib.vhd +${sys_conf := sys_conf_ba4_msim.vhd} +# components +../../../vlib/simlib/simclk.vbom +../../../vlib/simlib/simclkcnt.vbom +../sramif2migui_core.vbom +../migui_core_gsim.vbom +../migui2bram.vbom +# design +tb_sramif2migui_core.vhd diff --git a/rtl/bplib/mig/tb/tb_sramif2migui_core.vhd b/rtl/bplib/mig/tb/tb_sramif2migui_core.vhd new file mode 100644 index 00000000..7354de1b --- /dev/null +++ b/rtl/bplib/mig/tb/tb_sramif2migui_core.vhd @@ -0,0 +1,532 @@ +-- $Id: tb_sramif2migui_core.vhd 1093 2018-12-25 19:52:53Z mueller $ +-- +-- Copyright 2018- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_sramif2migui_core - sim +-- Description: Test bench for sramif2migui_core and migui_core_gsim +-- +-- Dependencies: vlib/simlib/simclk +-- vlib/simlib/simclkcnt +-- migui_core_gsim +-- sramif2migui_core +-- migui_core_gsim +-- migui2bram +-- +-- To test: sramif2migui_core +-- +-- Target Devices: generic +-- Tool versions: viv 2017.2; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2018-12-25 1093 1.0 Initial version +-- 2018-11-10 1067 0.1 First draft (derived fr tb_nx_cram_memctl.vhd) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.simlib.all; +use work.miglib.all; +use work.sys_conf.all; + +entity tb_sramif2migui_core is +end tb_sramif2migui_core; + +architecture sim of tb_sramif2migui_core is + + constant clkmui_mul : positive := 6; + constant clkmui_div : positive := 12; + + constant c_caco_wait : positive := 50; -- UI_CLK cycles till CALIB_COMP = 1 + + constant mwidth : positive := 2**sys_conf_bawidth; -- mask width (8 or 16) + constant dwidth : positive := 8*mwidth; -- data width (64 or 128) + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + signal REQ : slbit := '0'; + signal WE : slbit := '0'; + signal BUSY : slbit := '0'; + signal ACK_R : slbit := '0'; + signal ACK_W : slbit := '0'; + signal ACT_R : slbit := '0'; + signal ACT_W : slbit := '0'; + signal ADDR : slv20 := (others=>'0'); + signal BE : slv4 := (others=>'0'); + signal DI : slv32 := (others=>'0'); + signal DO : slv32 := (others=>'0'); + signal MONI : sramif2migui_moni_type := sramif2migui_moni_init; + + signal SYS_CLK : slbit := '0'; + signal SYS_RST : slbit := '0'; + + signal UI_CLK : slbit := '0'; + signal UI_CLK_SYNC_RST : slbit := '0'; + signal INIT_CALIB_COMPLETE : slbit := '0'; + signal APP_RDY : slbit := '0'; + signal APP_EN : slbit := '0'; + signal APP_CMD : slv3:= (others=>'0'); + signal APP_ADDR : slv(sys_conf_mawidth-1 downto 0):= (others=>'0'); + signal APP_WDF_RDY : slbit := '0'; + signal APP_WDF_WREN : slbit := '0'; + signal APP_WDF_DATA : slv(dwidth-1 downto 0):= (others=>'0'); + signal APP_WDF_MASK : slv(mwidth-1 downto 0):= (others=>'0'); + signal APP_WDF_END : slbit := '0'; + signal APP_RD_DATA_VALID : slbit := '0'; + signal APP_RD_DATA : slv(dwidth-1 downto 0):= (others=>'0'); + signal APP_RD_DATA_END : slbit := '0'; + + signal R_MEMON : slbit := '0'; + signal N_CHK_DATA : slbit := '0'; + signal N_REF_DATA : slv32 := (others=>'0'); + signal N_REF_ADDR : slv20 := (others=>'0'); + signal R_CHK_DATA_AL : slbit := '0'; + signal R_REF_DATA_AL : slv32 := (others=>'0'); + signal R_REF_ADDR_AL : slv20 := (others=>'0'); + signal R_CHK_DATA_DL : slbit := '0'; + signal R_REF_DATA_DL : slv32 := (others=>'0'); + signal R_REF_ADDR_DL : slv20 := (others=>'0'); + + signal R_NRDRHIT : integer := 0; + signal R_NWRRHIT : integer := 0; + signal R_NWRFLUSH : integer := 0; + signal R_NMIGCBUSY : integer := 0; + signal R_NMIGWBUSY : integer := 0; + signal R_NMIGCACOW : integer := 0; + + signal CLK_STOP : slbit := '0'; + signal CLK_CYCLE : integer := 0; + signal UI_CLK_CYCLE : integer := 0; + + constant clock_period : Delay_length := 12.5 ns; + constant clock_offset : Delay_length := 200 ns; + constant setup_time : Delay_length := 3 ns; + constant c2out_time : Delay_length := 5 ns; + + constant sysclock_period : Delay_length := 5.833 ns; + constant sysclock_offset : Delay_length := 200 ns; + +begin + + USRCLKGEN : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK, + CLK_STOP => CLK_STOP + ); + + SYSCLKGEN : simclk + generic map ( + PERIOD => sysclock_period, + OFFSET => sysclock_offset) + port map ( + CLK => SYS_CLK, + CLK_STOP => CLK_STOP + ); + + CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE); + UICLKCNT : simclkcnt port map (CLK => UI_CLK, CLK_CYCLE => UI_CLK_CYCLE); + + SR2MU : sramif2migui_core + generic map ( + BAWIDTH => sys_conf_bawidth, + MAWIDTH => sys_conf_mawidth) + port map ( + CLK => CLK, + RESET => RESET, + REQ => REQ, + WE => WE, + BUSY => BUSY, + ACK_R => ACK_R, + ACK_W => ACK_W, + ACT_R => ACT_R, + ACT_W => ACT_W, + ADDR => ADDR, + BE => BE, + DI => DI, + DO => DO, + MONI => MONI, + UI_CLK => UI_CLK, + UI_CLK_SYNC_RST => UI_CLK_SYNC_RST, + INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE, + APP_RDY => APP_RDY, + APP_EN => APP_EN, + APP_CMD => APP_CMD, + APP_ADDR => APP_ADDR, + APP_WDF_RDY => APP_WDF_RDY, + APP_WDF_WREN => APP_WDF_WREN, + APP_WDF_DATA => APP_WDF_DATA, + APP_WDF_MASK => APP_WDF_MASK, + APP_WDF_END => APP_WDF_END, + APP_RD_DATA_VALID => APP_RD_DATA_VALID, + APP_RD_DATA => APP_RD_DATA, + APP_RD_DATA_END => APP_RD_DATA_END + ); + + BTYP_MSIM : if sys_conf_btyp = c_btyp_msim generate + I0 : migui_core_gsim + generic map ( + BAWIDTH => sys_conf_bawidth, + MAWIDTH => sys_conf_mawidth, + SAWIDTH => sys_conf_sawidth, + CLKMUI_MUL => clkmui_mul, + CLKMUI_DIV => clkmui_div) + port map ( + SYS_CLK => SYS_CLK, + SYS_RST => SYS_RST, + UI_CLK => UI_CLK, + UI_CLK_SYNC_RST => UI_CLK_SYNC_RST, + INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE, + APP_RDY => APP_RDY, + APP_EN => APP_EN, + APP_CMD => APP_CMD, + APP_ADDR => APP_ADDR, + APP_WDF_RDY => APP_WDF_RDY, + APP_WDF_WREN => APP_WDF_WREN, + APP_WDF_DATA => APP_WDF_DATA, + APP_WDF_MASK => APP_WDF_MASK, + APP_WDF_END => APP_WDF_END, + APP_RD_DATA_VALID => APP_RD_DATA_VALID, + APP_RD_DATA => APP_RD_DATA, + APP_RD_DATA_END => APP_RD_DATA_END, + APP_REF_REQ => '0', + APP_ZQ_REQ => '0', + APP_REF_ACK => open, + APP_ZQ_ACK => open + ); + end generate BTYP_MSIM; + + BTYP_BRAM : if sys_conf_btyp = c_btyp_bram generate + I0 : migui2bram + generic map ( + BAWIDTH => sys_conf_bawidth, + MAWIDTH => sys_conf_mawidth, + RAWIDTH => sys_conf_rawidth, + RDELAY => sys_conf_rdelay, + CLKMUI_MUL => clkmui_mul, + CLKMUI_DIV => clkmui_div, + CLKMSYS_PERIOD => 6.000) + port map ( + SYS_CLK => SYS_CLK, + SYS_RST => SYS_RST, + UI_CLK => UI_CLK, + UI_CLK_SYNC_RST => UI_CLK_SYNC_RST, + INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE, + APP_RDY => APP_RDY, + APP_EN => APP_EN, + APP_CMD => APP_CMD, + APP_ADDR => APP_ADDR, + APP_WDF_RDY => APP_WDF_RDY, + APP_WDF_WREN => APP_WDF_WREN, + APP_WDF_DATA => APP_WDF_DATA, + APP_WDF_MASK => APP_WDF_MASK, + APP_WDF_END => APP_WDF_END, + APP_RD_DATA_VALID => APP_RD_DATA_VALID, + APP_RD_DATA => APP_RD_DATA, + APP_RD_DATA_END => APP_RD_DATA_END + ); + end generate BTYP_BRAM; + + proc_stim: process + file fstim : text open read_mode is "tb_sramif2migui_core_stim"; + variable iline : line; + variable oline : line; + variable ok : boolean; + variable dname : string(1 to 6) := (others=>' '); + variable idelta : integer := 0; + variable iaddr : slv20 := (others=>'0'); + variable idata : slv32 := (others=>'0'); + variable ibe : slv4 := (others=>'0'); + variable ival : slbit := '0'; + variable nbusy : integer := 0; + variable nwreq : natural := 0; + variable nrdrhit : integer := 0; + variable nwrrhit : integer := 0; + variable nwrflush : integer := 0; + variable nmigcbusy : integer := 0; + variable nmigwbusy : integer := 0; + variable nmigcacow : integer := 0; + + begin + + wait for clock_offset - setup_time; + + file_loop: while not endfile(fstim) loop + + readline (fstim, iline); + + readcomment(iline, ok); + next file_loop when ok; + + readword(iline, dname, ok); + if ok then + case dname is + when ".memon" => -- .memon + read_ea(iline, ival); + R_MEMON <= ival; + wait for 2*clock_period; + + when ".reset" => -- .reset + write(oline, string'(".reset")); + writeline(output, oline); + RESET <= '1'; + wait for clock_period; + RESET <= '0'; + wait for 9*clock_period; + + when ".wreq " => -- .wreq + read_ea(iline, nwreq); + + when ".wait " => -- .wait + read_ea(iline, idelta); + wait for idelta*clock_period; + + when "read " => -- read + readgen_ea(iline, iaddr, 16); + readgen_ea(iline, idata, 16); + ADDR <= iaddr; + REQ <= '1'; + WE <= '0'; + + writetimestamp(oline, CLK_CYCLE, ": stim read "); + writegen(oline, iaddr, right, 6, 16); + write(oline, string'(" ")); + writegen(oline, idata, right, 9, 16); + + nbusy := 0; + while BUSY = '1' loop + nbusy := nbusy + 1; + wait for clock_period; + end loop; + + write(oline, string'(" nb=")); + write(oline, nbusy, right, 2); + write(oline, string'(" mo=")); + write(oline, R_NRDRHIT-nrdrhit, right, 2); + write(oline, R_NWRRHIT-nwrrhit, right, 2); + write(oline, R_NWRFLUSH-nwrflush, right, 2); + write(oline, R_NMIGCBUSY-nmigcbusy, right, 2); + write(oline, R_NMIGWBUSY-nmigwbusy, right, 2); + write(oline, string'(" ")); + write(oline, R_NMIGCACOW-nmigcacow, right, 1); + writeline(output, oline); + nrdrhit := R_NRDRHIT; + nwrrhit := R_NWRRHIT; + nwrflush := R_NWRFLUSH; + nmigcbusy := R_NMIGCBUSY; + nmigwbusy := R_NMIGWBUSY; + nmigcacow := R_NMIGCACOW; + + N_CHK_DATA <= '1', '0' after clock_period; + N_REF_DATA <= idata; + N_REF_ADDR <= iaddr; + + wait for clock_period; + REQ <= '0'; + if nwreq > 0 then wait for nwreq*clock_period; end if; + + when "write " => -- write + readgen_ea(iline, iaddr, 16); + read_ea(iline, ibe); + readgen_ea(iline, idata, 16); + ADDR <= iaddr; + BE <= ibe; + DI <= idata; + REQ <= '1'; + WE <= '1'; + + writetimestamp(oline, CLK_CYCLE, ": stim write"); + writegen(oline, iaddr, right, 6, 16); + writegen(oline, ibe , right, 5, 2); + writegen(oline, idata, right, 9, 16); + + nbusy := 0; + while BUSY = '1' loop + nbusy := nbusy + 1; + wait for clock_period; + end loop; + + write(oline, string'(" nb=")); + write(oline, nbusy, right, 2); + write(oline, string'(" mo=")); + write(oline, R_NRDRHIT-nrdrhit, right, 2); + write(oline, R_NWRRHIT-nwrrhit, right, 2); + write(oline, R_NWRFLUSH-nwrflush, right, 2); + write(oline, R_NMIGCBUSY-nmigcbusy, right, 2); + write(oline, R_NMIGWBUSY-nmigwbusy, right, 2); + write(oline, string'(" ")); + write(oline, R_NMIGCACOW-nmigcacow, right, 1); + writeline(output, oline); + nrdrhit := R_NRDRHIT; + nwrrhit := R_NWRRHIT; + nwrflush := R_NWRFLUSH; + nmigcbusy := R_NMIGCBUSY; + nmigwbusy := R_NMIGWBUSY; + nmigcacow := R_NMIGCACOW; + + wait for clock_period; + REQ <= '0'; + if nwreq > 0 then wait for nwreq*clock_period; end if; + + when others => -- bad directive + write(oline, string'("?? unknown directive: ")); + write(oline, dname); + writeline(output, oline); + report "aborting" severity failure; + end case; + else + report "failed to find command" severity failure; + + end if; + + testempty_ea(iline); + + end loop; -- file fstim + + wait for 10*clock_period; + + writetimestamp(oline, CLK_CYCLE, ": stat moni-cnt= "); + write(oline, R_NRDRHIT, right, 5); + write(oline, string'(",")); + write(oline, R_NWRRHIT, right, 5); + write(oline, string'(",")); + write(oline, R_NWRFLUSH, right, 5); + write(oline, string'(",")); + write(oline, R_NMIGCBUSY, right, 5); + write(oline, string'(",")); + write(oline, R_NMIGWBUSY, right, 5); + write(oline, string'(",")); + write(oline, R_NMIGCACOW, right, 5); + writeline(output, oline); + + writetimestamp(oline, CLK_CYCLE, ": DONE "); + writeline(output, oline); + + CLK_STOP <= '1'; + + wait; -- suspend proc_stim forever + -- clock is stopped, sim will end + + end process proc_stim; + + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLK); + + -- performance counter + if MONI.rdrhit = '1' then + R_NRDRHIT <= R_NRDRHIT + 1; + end if; + if MONI.wrrhit = '1' then + R_NWRRHIT <= R_NWRRHIT + 1; + end if; + if MONI.wrflush = '1' then + R_NWRFLUSH <= R_NWRFLUSH + 1; + end if; + if MONI.migcbusy = '1' then + R_NMIGCBUSY <= R_NMIGCBUSY + 1; + end if; + if MONI.migwbusy = '1' then + R_NMIGWBUSY <= R_NMIGWBUSY + 1; + end if; + if MONI.migcacow = '1' then + R_NMIGCACOW <= R_NMIGCACOW + 1; + end if; + + if ACK_R = '1' then + writetimestamp(oline, CLK_CYCLE, ": moni "); + writegen(oline, DO, right, 9, 16); + if R_CHK_DATA_DL = '1' then + write(oline, string'(" CHECK")); + if R_REF_DATA_DL = DO then + write(oline, string'(" OK")); + else + write(oline, string'(" FAIL, exp=")); + writegen(oline, R_REF_DATA_DL, right, 9, 16); + write(oline, string'(" for a=")); + writegen(oline, R_REF_ADDR_DL, right, 5, 16); + end if; + R_CHK_DATA_DL <= '0'; + end if; + writeline(output, oline); + end if; + + if R_CHK_DATA_AL = '1' then + R_CHK_DATA_DL <= R_CHK_DATA_AL; + R_REF_DATA_DL <= R_REF_DATA_AL; + R_REF_ADDR_DL <= R_REF_ADDR_AL; + R_CHK_DATA_AL <= '0'; + end if; + if N_CHK_DATA = '1' then + R_CHK_DATA_AL <= N_CHK_DATA; + R_REF_DATA_AL <= N_REF_DATA; + R_REF_ADDR_AL <= N_REF_ADDR; + end if; + + end loop; + + end process proc_moni; + + + proc_memon: process + variable oline : line; + begin + + loop + wait until rising_edge(UI_CLK); + + if R_MEMON = '1' then + if APP_EN = '1' then + writetimestamp(oline, UI_CLK_CYCLE, ": mreq "); + write(oline, APP_CMD, right, 3); + write(oline, string'(",")); + write(oline, APP_RDY, right); + write(oline, string'(",")); + write(oline, APP_WDF_RDY, right); + writegen(oline, + APP_ADDR(sys_conf_sawidth-sys_conf_bawidth-1 downto 0), + right, 7, 16); + write(oline, APP_WDF_WREN, right, 2); + write(oline, APP_WDF_END, right, 2); + if APP_WDF_WREN = '1' then + writegen(oline, APP_WDF_MASK, right, (mwidth/4)+1, 16); + writegen(oline, APP_WDF_DATA, right, (dwidth/4)+1, 16); + end if; + writeline(output, oline); + end if; + + if APP_RD_DATA_VALID = '1' then + writetimestamp(oline, UI_CLK_CYCLE, ": mres "); + write(oline, APP_RD_DATA_END, right); + writegen(oline, APP_RD_DATA, right, (dwidth/4)+1, 16); + writeline(output, oline); + end if; + + end if; + + end loop; + + end process proc_memon; + + +end sim; diff --git a/rtl/bplib/mig/tb/tb_sramif2migui_core_ba3_bram.vbom b/rtl/bplib/mig/tb/tb_sramif2migui_core_ba3_bram.vbom new file mode 100644 index 00000000..a39d76ab --- /dev/null +++ b/rtl/bplib/mig/tb/tb_sramif2migui_core_ba3_bram.vbom @@ -0,0 +1,6 @@ +# configure tb_sramif2migui_core for bawidth=3 and bram backend +# configure +sys_conf = sys_conf_ba3_bram.vhd +# design +tb_sramif2migui_core.vbom +@top:tb_sramif2migui_core diff --git a/rtl/bplib/mig/tb/tb_sramif2migui_core_ba3_msim.vbom b/rtl/bplib/mig/tb/tb_sramif2migui_core_ba3_msim.vbom new file mode 100644 index 00000000..b9d19edd --- /dev/null +++ b/rtl/bplib/mig/tb/tb_sramif2migui_core_ba3_msim.vbom @@ -0,0 +1,6 @@ +# configure tb_sramif2migui_core for bawidth=3 and msim backend +# configure +sys_conf = sys_conf_ba3_msim.vhd +# design +tb_sramif2migui_core.vbom +@top:tb_sramif2migui_core diff --git a/rtl/bplib/mig/tb/tb_sramif2migui_core_ba4_bram.vbom b/rtl/bplib/mig/tb/tb_sramif2migui_core_ba4_bram.vbom new file mode 100644 index 00000000..c22a9312 --- /dev/null +++ b/rtl/bplib/mig/tb/tb_sramif2migui_core_ba4_bram.vbom @@ -0,0 +1,6 @@ +# configure tb_sramif2migui_core for bawidth=4 and bram backend +# configure +sys_conf = sys_conf_ba4_bram.vhd +# design +tb_sramif2migui_core.vbom +@top:tb_sramif2migui_core diff --git a/rtl/bplib/mig/tb/tb_sramif2migui_core_ba4_msim.vbom b/rtl/bplib/mig/tb/tb_sramif2migui_core_ba4_msim.vbom new file mode 100644 index 00000000..23d159dc --- /dev/null +++ b/rtl/bplib/mig/tb/tb_sramif2migui_core_ba4_msim.vbom @@ -0,0 +1,6 @@ +# configure tb_sramif2migui_core for bawidth=4 and msim backend +# configure +sys_conf = sys_conf_ba4_msim.vhd +# design +tb_sramif2migui_core.vbom +@top:tb_sramif2migui_core diff --git a/rtl/bplib/mig/tb/tb_sramif2migui_core_stim.dat b/rtl/bplib/mig/tb/tb_sramif2migui_core_stim.dat new file mode 100644 index 00000000..1da4f2b5 --- /dev/null +++ b/rtl/bplib/mig/tb/tb_sramif2migui_core_stim.dat @@ -0,0 +1,268 @@ +# $Id: tb_sramif2migui_core_stim.dat 1069 2018-11-16 17:11:30Z mueller $ +# +# annotation assumes a 128 bit wide mig iface +# -> 8 16bit words per row buffer +# -> 4 32bit words per row buffer +# +.memon 1 +.wreq 0 +# +C write four consecutive rows back-to-back +# +write 000000 1111 30201000 +write 000001 1111 31211101 +write 000002 1111 32221202 +write 000003 1111 33231303 + +write 000004 1111 34241404 +write 000005 1111 35251505 +write 000006 1111 36261606 +write 000007 1111 37271707 + +write 000008 1111 38281808 +write 000009 1111 39291909 +write 00000a 1111 3a2a1a0a +write 00000b 1111 3b2b1b0b + +write 00000c 1111 3c2c1c0c +write 00000d 1111 3d2d1d0d +write 00000e 1111 3e2e1e0e +write 00000f 1111 3f2f1f0f +# +C read four consecutive rows back-to-back +# +read 000000 30201000 +read 000001 31211101 +read 000002 32221202 +read 000003 33231303 + +read 000004 34241404 +read 000005 35251505 +read 000006 36261606 +read 000007 37271707 + +read 000008 38281808 +read 000009 39291909 +read 00000a 3a2a1a0a +read 00000b 3b2b1b0b + +read 00000c 3c2c1c0c +read 00000d 3d2d1d0d +read 00000e 3e2e1e0e +read 00000f 3f2f1f0f +# +C read four consecutive rows in non-sequential order +# +read 000007 37271707 +read 000000 30201000 +read 00000e 3e2e1e0e +read 000001 31211101 +read 000008 38281808 +read 000002 32221202 +read 00000d 3d2d1d0d +read 000003 33231303 +read 00000c 3c2c1c0c +read 000006 36261606 +read 000009 39291909 +read 000004 34241404 +read 00000a 3a2a1a0a +read 000005 35251505 +read 00000b 3b2b1b0b +read 00000f 3f2f1f0f +# +C write four non-consecutive groups of two rows with 3 cycle wait +.wreq 3 +write 000100 1111 50004000 +write 000101 1111 50014001 +write 000102 1111 50024002 +write 000103 1111 50034003 +# +write 000104 1111 50044004 +write 000105 1111 50054005 +write 000106 1111 50064006 +write 000107 1111 50074007 +# +write 001100 1111 51004100 +write 001101 1111 51014101 +write 001102 1111 51024102 +write 001103 1111 51034103 +# +write 001104 1111 51044104 +write 001105 1111 51054105 +write 001106 1111 51064106 +write 001107 1111 51074107 +# +write 002100 1111 52004200 +write 002101 1111 52014201 +write 002102 1111 52024202 +write 002103 1111 52034203 +# +write 002104 1111 52044204 +write 002105 1111 52054205 +write 002106 1111 52064206 +write 002107 1111 52074207 +# +write 003100 1111 53004300 +write 003101 1111 53014301 +write 003102 1111 53024302 +write 003103 1111 53034303 +# +write 003104 1111 53044304 +write 003105 1111 53054305 +write 003106 1111 53064306 +write 003107 1111 53074307 +# +C read four non-consecutive groups of two rows with 3 cycle wait +.wreq 3 +read 000100 50004000 +read 000101 50014001 +read 000102 50024002 +read 000103 50034003 +# +read 000104 50044004 +read 000105 50054005 +read 000106 50064006 +read 000107 50074007 +# +read 001100 51004100 +read 001101 51014101 +read 001102 51024102 +read 001103 51034103 +# +read 001104 51044104 +read 001105 51054105 +read 001106 51064106 +read 001107 51074107 +# +read 002100 52004200 +read 002101 52014201 +read 002102 52024202 +read 002103 52034203 +# +read 002104 52044204 +read 002105 52054205 +read 002106 52064206 +read 002107 52074207 +# +write 001100 1111 51004100 +write 001101 1111 51014101 +write 001102 1111 51024102 +write 001103 1111 51034103 +# +write 001104 1111 51044104 +write 001105 1111 51054105 +write 001106 1111 51064106 +write 001107 1111 51074107 +# +write 002100 1111 52004200 +write 002101 1111 52014201 +write 002102 1111 52024202 +write 002103 1111 52034203 +# +write 002104 1111 52044204 +write 002105 1111 52054205 +write 002106 1111 52064206 +write 002107 1111 52074207 +# +write 003100 1111 53004300 +write 003101 1111 53014301 +write 003102 1111 53024302 +write 003103 1111 53034303 +# +write 003104 1111 53044304 +write 003105 1111 53054305 +write 003106 1111 53064306 +write 003107 1111 53074307 +# +C read four non-consecutive groups of two rows with 3 cycle wait +.wreq 3 +read 000100 50004000 +read 000101 50014001 +read 000102 50024002 +read 000103 50034003 +# +read 000104 50044004 +read 000105 50054005 +read 000106 50064006 +read 000107 50074007 +# +read 001100 51004100 +read 001101 51014101 +read 001102 51024102 +read 001103 51034103 +# +read 001104 51044104 +read 001105 51054105 +read 001106 51064106 +read 001107 51074107 +# +read 002100 52004200 +read 002101 52014201 +read 002102 52024202 +read 002103 52034203 +# +read 002104 52044204 +read 002105 52054205 +read 002106 52064206 +read 002107 52074207 +# +read 003100 53004300 +read 003101 53014301 +read 003102 53024302 +read 003103 53034303 +# +read 003104 53044304 +read 003105 53054305 +read 003106 53064306 +read 003107 53074307 +# +C byte writes with immediate read-back +# +write 000100 0001 fffffff8 +read 000100 500040f8 +write 000101 0010 fffff9ff +read 000101 5001f901 +write 000102 0100 fffaffff +read 000102 50fa4002 +write 000103 1000 fbffffff +read 000103 fb034003 +# +C scattered byte writes with scattered read-back +# +.wreq 0 +write 001100 1000 b0eeeeee +write 001101 0100 eeb1eeee +write 002100 0011 eeee3210 +write 002101 0110 ee7654ee +# +write 002102 1100 3210eeee +write 002103 1001 76eeee54 +write 001102 0010 eeeeb2ee +write 001103 0001 eeeeeeb3 +# +write 001104 1000 b4eeeeee +write 002104 1110 012345ee +write 001105 0100 eeb5eeee +write 002105 1101 6712ee23 +write 001106 0010 eeeeb6ee +write 002106 1011 45ee6701 +write 001107 0001 eeeeeeb7 +write 002107 0111 ee234567 +# +read 001100 b0004100 +read 002100 52003210 +read 001101 51b14101 +read 002101 52765401 +read 001102 5102b202 +read 002102 32104202 +read 001103 510341b3 +read 002103 76034254 +# +read 001104 b4044104 +read 002104 01234504 +read 001105 51b54105 +read 002105 67124223 +read 001106 5106b606 +read 002106 45066701 +read 001107 510741b7 +read 002107 52234567 diff --git a/rtl/bplib/mig/tb/tbrun.yml b/rtl/bplib/mig/tb/tbrun.yml new file mode 100644 index 00000000..8f2789d8 --- /dev/null +++ b/rtl/bplib/mig/tb/tbrun.yml @@ -0,0 +1,26 @@ +# $Id: tbrun.yml 1069 2018-11-16 17:11:30Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2018-11-16 1069 1.0 Initial version +# +- default: + mode: ${viv_modes} +# +- tag: [default, viv, mig, sramif2migui_core, ba3, bram] + test: | + tbrun_tbw tb_sramif2migui_core_ba3_bram${ms} +# +- tag: [default, viv, mig, sramif2migui_core, ba3, msim] + test: | + tbrun_tbw tb_sramif2migui_core_ba3_msim${ms} +# +- tag: [default, viv, mig, sramif2migui_core, ba4, bram] + test: | + tbrun_tbw tb_sramif2migui_core_ba4_bram${ms} +# +- tag: [default, viv, mig, sramif2migui_core, ba4, msim] + test: | + tbrun_tbw tb_sramif2migui_core_ba4_msim${ms} + + diff --git a/rtl/bplib/mig/tb/tbw.dat b/rtl/bplib/mig/tb/tbw.dat new file mode 100644 index 00000000..3fa7d9e9 --- /dev/null +++ b/rtl/bplib/mig/tb/tbw.dat @@ -0,0 +1,10 @@ +# $Id: tbw.dat 1069 2018-11-16 17:11:30Z mueller $ +# +[tb_sramif2migui_core_ba3_bram] +tb_sramif2migui_core_stim = tb_sramif2migui_core_stim.dat +[tb_sramif2migui_core_ba3_msim] +tb_sramif2migui_core_stim = tb_sramif2migui_core_stim.dat +[tb_sramif2migui_core_ba4_bram] +tb_sramif2migui_core_stim = tb_sramif2migui_core_stim.dat +[tb_sramif2migui_core_ba4_msim] +tb_sramif2migui_core_stim = tb_sramif2migui_core_stim.dat diff --git a/tbrun.yml b/tbrun.yml index ffb9dff0..a64b5854 100644 --- a/tbrun.yml +++ b/tbrun.yml @@ -1,8 +1,8 @@ -# $Id: tbrun.yml 1098 2018-12-30 11:40:42Z mueller $ +# $Id: tbrun.yml 1099 2018-12-31 09:07:36Z mueller $ # # Revision History: # Date Rev Version Comment -# 2018-12-30 1097 1.0.1 add tst_mig +# 2018-12-30 1099 1.0.1 add tst_mig, bplib/mig # 2016-08-27 802 1.0 Initial version # - include: rtl/vlib/comlib/tb/tbrun.yml @@ -13,6 +13,7 @@ - include: rtl/bplib/nxcramlib/tb/tbrun.yml - include: rtl/bplib/s3board/tb/tbrun.yml - include: rtl/bplib/cmoda7/tb/tbrun.yml +- include: rtl/bplib/mig/tb/tbrun.yml - include: rtl/w11a/tb/tbrun.yml - include: rtl/sys_gen/tst_serloop/tbrun.yml - include: rtl/sys_gen/tst_rlink/tbrun.yml