diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index 33043d95..276a071c 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -10,9 +10,17 @@ --- ## HEAD +### Proviso +_The HEAD version is shows the current development. No guarantees that +software or firmware builds or that the documentation is consistent. +The full set of tests is only run for releases._ + ### Summary +- [w11 shell](../tools/tcl/rw11/shell.tcl) re-organized abd expanded, + now default in [ti_w11](../tools/bin/ti_w11) - `CPUERR` cleared with cpu reset (see [ECO-029](ECO-029-cpuerr_creset.md)) - `PS` initialized now with `000000` (see [ECO-028](ECO-028-ps_init.md)) +- added **preliminary** and **FPGA untested** support for nexys4 DDR --- diff --git a/rtl/bplib/nexys4d/nexys4d_pclk.xdc b/rtl/bplib/nexys4d/nexys4d_pclk.xdc new file mode 100644 index 00000000..1c90e801 --- /dev/null +++ b/rtl/bplib/nexys4d/nexys4d_pclk.xdc @@ -0,0 +1,13 @@ +# $Id: nexys4d_pclk.xdc 838 2017-01-04 20:57:57Z mueller $ +# +# Copyright 2017- by Walter F.J. Mueller +# License disclaimer see License.txt in $RETROBASE directory +# +# Primary clocks for Nexys4 DDR +# +# Revision History: +# Date Rev Version Comment +# 2017-01-04 838 1.0 Initial version +# + +create_clock -name I_CLK100 -period 10 -waveform {0 5} [get_ports I_CLK100] diff --git a/rtl/bplib/nexys4d/nexys4d_pins.xdc b/rtl/bplib/nexys4d/nexys4d_pins.xdc new file mode 100644 index 00000000..26047186 --- /dev/null +++ b/rtl/bplib/nexys4d/nexys4d_pins.xdc @@ -0,0 +1,138 @@ +# -*- tcl -*- +# $Id: nexys4d_pins.xdc 838 2017-01-04 20:57:57Z mueller $ +# +# Copyright 2017- by Walter F.J. Mueller +# License disclaimer see License.txt in $RETROBASE directory +# +# Nexys 4DDR core functionality +# - Configuration setup +# - config voltage +# - enable bitstream timestamp +# - Pin Locks for +# - USB UART +# - human I/O (switches, buttons, leds, display) +# +# Revision History: +# Date Rev Version Comment +# 2017-01-04 838 1.0 Initial version +# + +# config setup -------------------------------------------------------------- +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] + +# clocks -- in bank 35 ------------------------------------------------------ +set_property PACKAGE_PIN e3 [get_ports {I_CLK100}] +set_property IOSTANDARD LVCMOS33 [get_ports {I_CLK100}] + +# +# USB UART Interface -- in bank 35 ------------------------------------------ +set_property PACKAGE_PIN c4 [get_ports {I_RXD}] +set_property PACKAGE_PIN d4 [get_ports {O_TXD}] +set_property PACKAGE_PIN d3 [get_ports {O_RTS_N}] +set_property PACKAGE_PIN e5 [get_ports {I_CTS_N}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_RXD O_TXD O_RTS_N I_CTS_N}] +set_property DRIVE 12 [get_ports {O_TXD O_RTS_N}] +set_property SLEW SLOW [get_ports {O_TXD O_RTS_N}] + +# +# switches -- in bank 14+15 ------------------------------------------------- +set_property PACKAGE_PIN j15 [get_ports {I_SWI[0]}] +set_property PACKAGE_PIN l16 [get_ports {I_SWI[1]}] +set_property PACKAGE_PIN m13 [get_ports {I_SWI[2]}] +set_property PACKAGE_PIN r15 [get_ports {I_SWI[3]}] +set_property PACKAGE_PIN r17 [get_ports {I_SWI[4]}] +set_property PACKAGE_PIN t18 [get_ports {I_SWI[5]}] +set_property PACKAGE_PIN u18 [get_ports {I_SWI[6]}] +set_property PACKAGE_PIN r13 [get_ports {I_SWI[7]}] +set_property PACKAGE_PIN t8 [get_ports {I_SWI[8]}] +set_property PACKAGE_PIN u8 [get_ports {I_SWI[9]}] +set_property PACKAGE_PIN r16 [get_ports {I_SWI[10]}] +set_property PACKAGE_PIN t13 [get_ports {I_SWI[11]}] +set_property PACKAGE_PIN h6 [get_ports {I_SWI[12]}] +set_property PACKAGE_PIN u12 [get_ports {I_SWI[13]}] +set_property PACKAGE_PIN u11 [get_ports {I_SWI[14]}] +set_property PACKAGE_PIN v10 [get_ports {I_SWI[15]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_SWI[*]}] + +# +# buttons -- in bank 14+15 -------------------------------------------------- +# sequence: clockwise(U-R-D-L) - middle - reset +set_property PACKAGE_PIN m18 [get_ports {I_BTN[0]}] +set_property PACKAGE_PIN m17 [get_ports {I_BTN[1]}] +set_property PACKAGE_PIN p18 [get_ports {I_BTN[2]}] +set_property PACKAGE_PIN p17 [get_ports {I_BTN[3]}] +set_property PACKAGE_PIN n17 [get_ports {I_BTN[4]}] +set_property PACKAGE_PIN c12 [get_ports {I_BTNRST_N}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_BTN[*]}] +set_property IOSTANDARD LVCMOS33 [get_ports {I_BTNRST_N}] + +# +# LEDs -- in bank 14+15------------------------------------------------------ +set_property PACKAGE_PIN h17 [get_ports {O_LED[0]}] +set_property PACKAGE_PIN k15 [get_ports {O_LED[1]}] +set_property PACKAGE_PIN j13 [get_ports {O_LED[2]}] +set_property PACKAGE_PIN n14 [get_ports {O_LED[3]}] +set_property PACKAGE_PIN r18 [get_ports {O_LED[4]}] +set_property PACKAGE_PIN v17 [get_ports {O_LED[5]}] +set_property PACKAGE_PIN u17 [get_ports {O_LED[6]}] +set_property PACKAGE_PIN u16 [get_ports {O_LED[7]}] +set_property PACKAGE_PIN v16 [get_ports {O_LED[8]}] +set_property PACKAGE_PIN t15 [get_ports {O_LED[9]}] +set_property PACKAGE_PIN u14 [get_ports {O_LED[10]}] +set_property PACKAGE_PIN t16 [get_ports {O_LED[11]}] +set_property PACKAGE_PIN v15 [get_ports {O_LED[12]}] +set_property PACKAGE_PIN v14 [get_ports {O_LED[13]}] +set_property PACKAGE_PIN v12 [get_ports {O_LED[14]}] +set_property PACKAGE_PIN v11 [get_ports {O_LED[15]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_LED[*]}] +set_property DRIVE 12 [get_ports {O_LED[*]}] +set_property SLEW SLOW [get_ports {O_LED[*]}] + +# +# RGB-LEDs -- in bank 14+15 ------------------------------------------------- +set_property PACKAGE_PIN n15 [get_ports {O_RGBLED0[0]}] +set_property PACKAGE_PIN m16 [get_ports {O_RGBLED0[1]}] +set_property PACKAGE_PIN r12 [get_ports {O_RGBLED0[2]}] + +set_property PACKAGE_PIN n16 [get_ports {O_RGBLED1[0]}] +set_property PACKAGE_PIN r11 [get_ports {O_RGBLED1[1]}] +set_property PACKAGE_PIN g14 [get_ports {O_RGBLED1[2]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_RGBLED0[*] O_RGBLED1[*]}] +set_property DRIVE 12 [get_ports {O_RGBLED0[*] O_RGBLED1[*]}] +set_property SLEW SLOW [get_ports {O_RGBLED0[*] O_RGBLED1[*]}] + +# +# 7 segment display -- in bank 14+15----------------------------------------- +set_property PACKAGE_PIN j17 [get_ports {O_ANO_N[0]}] +set_property PACKAGE_PIN j18 [get_ports {O_ANO_N[1]}] +set_property PACKAGE_PIN t9 [get_ports {O_ANO_N[2]}] +set_property PACKAGE_PIN j14 [get_ports {O_ANO_N[3]}] +set_property PACKAGE_PIN p14 [get_ports {O_ANO_N[4]}] +set_property PACKAGE_PIN t14 [get_ports {O_ANO_N[5]}] +set_property PACKAGE_PIN k2 [get_ports {O_ANO_N[6]}] +set_property PACKAGE_PIN u13 [get_ports {O_ANO_N[7]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_ANO_N[*]}] +set_property DRIVE 12 [get_ports {O_ANO_N[*]}] +set_property SLEW SLOW [get_ports {O_ANO_N[*]}] +# +set_property PACKAGE_PIN t10 [get_ports {O_SEG_N[0]}] +set_property PACKAGE_PIN r10 [get_ports {O_SEG_N[1]}] +set_property PACKAGE_PIN k16 [get_ports {O_SEG_N[2]}] +set_property PACKAGE_PIN k13 [get_ports {O_SEG_N[3]}] +set_property PACKAGE_PIN p15 [get_ports {O_SEG_N[4]}] +set_property PACKAGE_PIN t11 [get_ports {O_SEG_N[5]}] +set_property PACKAGE_PIN l18 [get_ports {O_SEG_N[6]}] +set_property PACKAGE_PIN h15 [get_ports {O_SEG_N[7]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_SEG_N[*]}] +set_property DRIVE 12 [get_ports {O_SEG_N[*]}] +set_property SLEW SLOW [get_ports {O_SEG_N[*]}] +# diff --git a/rtl/bplib/nexys4d/nexys4dlib.vhd b/rtl/bplib/nexys4d/nexys4dlib.vhd new file mode 100644 index 00000000..e28fb91b --- /dev/null +++ b/rtl/bplib/nexys4d/nexys4dlib.vhd @@ -0,0 +1,51 @@ +-- $Id: nexys4dlib.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: nexys4dlib +-- Description: Nexys 4DDR components +-- +-- Dependencies: - +-- Tool versions: viv 2016.2; ghdl 0.33 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package nexys4dlib is + +component nexys4d_aif is -- NEXYS 4D, abstract iface, base + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4 switches + I_BTN : in slv5; -- n4 buttons + I_BTNRST_N : in slbit; -- n4 reset button + O_LED : out slv16; -- n4 leds + O_RGBLED0 : out slv3; -- n4 rgb-led 0 + O_RGBLED1 : out slv3; -- n4 rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end component; + +end package nexys4dlib; diff --git a/rtl/bplib/nexys4d/tb/Makefile b/rtl/bplib/nexys4d/tb/Makefile new file mode 100644 index 00000000..a6c5e9dc --- /dev/null +++ b/rtl/bplib/nexys4d/tb/Makefile @@ -0,0 +1,39 @@ +# $Id: Makefile 838 2017-01-04 20:57:57Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-01-04 838 1.0 Initial version +# +EXE_all = tb_nexys4d_dummy +# +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4d.mk +# +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/bplib/nexys4d/tb/nexys4d_dummy.vbom b/rtl/bplib/nexys4d/tb/nexys4d_dummy.vbom new file mode 100644 index 00000000..ec802757 --- /dev/null +++ b/rtl/bplib/nexys4d/tb/nexys4d_dummy.vbom @@ -0,0 +1,4 @@ +# libs +../../../vlib/slvtypes.vhd +# design +nexys4d_dummy.vhd diff --git a/rtl/bplib/nexys4d/tb/nexys4d_dummy.vhd b/rtl/bplib/nexys4d/tb/nexys4d_dummy.vhd new file mode 100644 index 00000000..a8cf391d --- /dev/null +++ b/rtl/bplib/nexys4d/tb/nexys4d_dummy.vhd @@ -0,0 +1,67 @@ +-- $Id: nexys4d_dummy.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: nexys4d_dummy - syn +-- Description: nexys4d minimal target (base; serport loopback) +-- +-- Dependencies: - +-- To test: tb_nexys4d +-- Target Devices: generic +-- Tool versions: viv 2016.4; ghdl 0.33 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version (derived from nexys4_dummy) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +entity nexys4d_dummy is -- NEXYS 4DDR dummy (base; loopback) + -- implements nexys4d_aif + port ( + I_CLK100 : in slbit; -- 100 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4d switches + I_BTN : in slv5; -- n4d buttons + I_BTNRST_N : in slbit; -- n4d reset button + O_LED : out slv16; -- n4d leds + O_RGBLED0 : out slv3; -- n4d rgb-led 0 + O_RGBLED1 : out slv3; -- n4d rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end nexys4d_dummy; + +architecture syn of nexys4d_dummy is + +begin + + O_TXD <= I_RXD; -- loop back serport + O_RTS_N <= I_CTS_N; + + O_LED <= I_SWI; -- mirror SWI on LED + + O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED + O_RGBLED1 <= not I_BTNRST_N & I_BTN(4) & I_BTN(3); + + O_ANO_N <= (others=>'1'); + O_SEG_N <= (others=>'1'); + +end syn; diff --git a/rtl/bplib/nexys4d/tb/sys_conf_sim.vhd b/rtl/bplib/nexys4d/tb/sys_conf_sim.vhd new file mode 100644 index 00000000..c60b633d --- /dev/null +++ b/rtl/bplib/nexys4d/tb/sys_conf_sim.vhd @@ -0,0 +1,54 @@ +-- $Id: sys_conf_sim.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for tb_nexys4d_dummy (for simulation) +-- +-- Dependencies: - +-- Tool versions: viv 2016.2; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "MMCM"; + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; + diff --git a/rtl/bplib/nexys4d/tb/tb_nexys4d.vbom b/rtl/bplib/nexys4d/tb/tb_nexys4d.vbom new file mode 100644 index 00000000..b665ad51 --- /dev/null +++ b/rtl/bplib/nexys4d/tb/tb_nexys4d.vbom @@ -0,0 +1,23 @@ +# Not meant for direct top level usage. Used with +# tb_nexys4d_(....)[_ssim].vbom and config +# lines to generate the different cases. +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/rlink/rlinklib.vbom +../../../vlib/xlib/xlib.vhd +../nexys4dlib.vhd +../../../vlib/simlib/simlib.vhd +../../../vlib/simlib/simbus.vhd +${sys_conf := sys_conf_sim.vhd} +# components +../../../vlib/simlib/simclk.vbom +../../../vlib/simlib/simclkcnt.vbom +../../../vlib/rlink/tbcore/tbcore_rlink.vbom +../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom +tb_nexys4d_core.vbom +../../../vlib/serport/tb/serport_master_tb.vbom +${nexys4d_aif := nexys4d_dummy.vbom} -UUT +# design +tb_nexys4d.vhd +@top:tb_nexys4d diff --git a/rtl/bplib/nexys4d/tb/tb_nexys4d.vhd b/rtl/bplib/nexys4d/tb/tb_nexys4d.vhd new file mode 100644 index 00000000..55e74897 --- /dev/null +++ b/rtl/bplib/nexys4d/tb/tb_nexys4d.vhd @@ -0,0 +1,198 @@ +-- $Id: tb_nexys4d.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_nexys4d - sim +-- Description: Test bench for nexys4d (base) +-- +-- Dependencies: simlib/simclk +-- simlib/simclkcnt +-- rlink/tbcore/tbcore_rlink +-- xlib/tb/s7_cmt_sfs_tb +-- tb_nexys4d_core +-- serport/tb/serport_master_tb +-- nexys4d_aif [UUT] +-- +-- To test: generic, any nexys4d_aif target +-- +-- Target Devices: generic +-- Tool versions: viv 2016.2; ghdl 0.33 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version (derived from tb_nexys4) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.rlinklib.all; +use work.xlib.all; +use work.nexys4dlib.all; +use work.simlib.all; +use work.simbus.all; +use work.sys_conf.all; + +entity tb_nexys4d is +end tb_nexys4d; + +architecture sim of tb_nexys4d is + + signal CLKOSC : slbit := '0'; -- board clock (100 Mhz) + signal CLKCOM : slbit := '0'; -- communication clock + + signal CLKCOM_CYCLE : integer := 0; + + signal RESET : slbit := '0'; + signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !! + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXERR : slbit := '0'; + signal RXACT : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal O_RTS_N : slbit := '0'; + signal I_CTS_N : slbit := '0'; + signal I_SWI : slv16 := (others=>'0'); + signal I_BTN : slv5 := (others=>'0'); + signal I_BTNRST_N : slbit := '1'; + signal O_LED : slv16 := (others=>'0'); + signal O_RGBLED0 : slv3 := (others=>'0'); + signal O_RGBLED1 : slv3 := (others=>'0'); + signal O_ANO_N : slv8 := (others=>'0'); + signal O_SEG_N : slv8 := (others=>'0'); + + signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff + + constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); + + constant clock_period : Delay_length := 10 ns; + constant clock_offset : Delay_length := 200 ns; + +begin + + CLKGEN : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLKOSC + ); + + CLKGEN_COM : entity work.s7_cmt_sfs_tb + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clkser_gentype) + port map ( + CLKIN => CLKOSC, + CLKFX => CLKCOM, + LOCKED => open + ); + + CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); + + TBCORE : entity work.tbcore_rlink + port map ( + CLK => CLKCOM, + RX_DATA => TXDATA, + RX_VAL => TXENA, + RX_HOLD => TXBUSY, + TX_DATA => RXDATA, + TX_ENA => RXVAL + ); + + N4CORE : entity work.tb_nexys4d_core + port map ( + I_SWI => I_SWI, + I_BTN => I_BTN, + I_BTNRST_N => I_BTNRST_N + ); + + UUT : nexys4d_aif + port map ( + I_CLK100 => CLKOSC, + I_RXD => I_RXD, + O_TXD => O_TXD, + O_RTS_N => O_RTS_N, + I_CTS_N => I_CTS_N, + I_SWI => I_SWI, + I_BTN => I_BTN, + I_BTNRST_N => I_BTNRST_N, + O_LED => O_LED, + O_RGBLED0 => O_RGBLED0, + O_RGBLED1 => O_RGBLED1, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + SERMSTR : entity work.serport_master_tb + generic map ( + CDWIDTH => CLKDIV'length) + port map ( + CLK => CLKCOM, + RESET => RESET, + CLKDIV => CLKDIV, + ENAXON => R_PORTSEL_XON, + ENAESC => '0', + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXOK => '1', + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + RXSD => O_TXD, + TXSD => I_RXD, + RXRTS_N => I_CTS_N, + TXCTS_N => O_RTS_N + ); + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLKCOM); + + if RXERR = '1' then + writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1"); + writeline(output, oline); + end if; + + end loop; + + end process proc_moni; + + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_portsel then + R_PORTSEL_XON <= to_x01(SB_DATA(1)); + end if; + end if; + end process proc_simbus; + +end sim; diff --git a/rtl/bplib/nexys4d/tb/tb_nexys4d_core.vbom b/rtl/bplib/nexys4d/tb/tb_nexys4d_core.vbom new file mode 100644 index 00000000..5d1878e6 --- /dev/null +++ b/rtl/bplib/nexys4d/tb/tb_nexys4d_core.vbom @@ -0,0 +1,6 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/simlib/simbus.vhd +# components +# design +tb_nexys4d_core.vhd diff --git a/rtl/bplib/nexys4d/tb/tb_nexys4d_core.vhd b/rtl/bplib/nexys4d/tb/tb_nexys4d_core.vhd new file mode 100644 index 00000000..662ecf93 --- /dev/null +++ b/rtl/bplib/nexys4d/tb/tb_nexys4d_core.vhd @@ -0,0 +1,74 @@ +-- $Id: tb_nexys4d_core.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_nexys4d_core - sim +-- Description: Test bench for nexys4d - core device handling +-- +-- Dependencies: - +-- +-- To test: generic, any nexys4d target +-- +-- Target Devices: generic +-- Tool versions: viv 2016.2; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 834 1.0 Initial version (derived from tb_nexys4_core) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.simbus.all; + +entity tb_nexys4d_core is + port ( + I_SWI : out slv16; -- n4d switches + I_BTN : out slv5; -- n4d buttons + I_BTNRST_N : out slbit -- n4d reset button + ); +end tb_nexys4d_core; + +architecture sim of tb_nexys4d_core is + + signal R_SWI : slv16 := (others=>'0'); + signal R_BTN : slv5 := (others=>'0'); + signal R_BTNRST : slbit := '0'; + + constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8)); + constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8)); + +begin + + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_swi then + R_SWI <= to_x01(SB_DATA(R_SWI'range)); + end if; + if SB_ADDR = sbaddr_btn then + R_BTN <= to_x01(SB_DATA(R_BTN'range)); + R_BTNRST <= to_x01(SB_DATA(5)); + end if; + end if; + end process proc_simbus; + + I_SWI <= R_SWI; + I_BTN <= R_BTN; + I_BTNRST_N <= not R_BTNRST; + +end sim; diff --git a/rtl/make_viv/viv_default_nexys4d.mk b/rtl/make_viv/viv_default_nexys4d.mk new file mode 100644 index 00000000..d1d320f2 --- /dev/null +++ b/rtl/make_viv/viv_default_nexys4d.mk @@ -0,0 +1,16 @@ +# $Id: viv_default_nexys4d.mk 838 2017-01-04 20:57:57Z mueller $ +# +# Copyright 2017- by Walter F.J. Mueller +# License disclaimer see License.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2017-01-04 838 1.0 Initial version +#--- +# +# Setup for Digilent Nexys4 DDR +# +# setup default board and part +# +VIV_BOARD_SETUP = ${RETROBASE}/rtl/bplib/nexys4d/nexys4d_setup.tcl +# diff --git a/rtl/sys_gen/tst_rlink/nexys4d/Makefile b/rtl/sys_gen/tst_rlink/nexys4d/Makefile new file mode 100644 index 00000000..4e84ae38 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4d/Makefile @@ -0,0 +1,25 @@ +# $Id: Makefile 838 2017-01-04 20:57:57Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-01-04 838 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4d.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/tst_rlink/nexys4d/sys_conf.vhd b/rtl/sys_gen/tst_rlink/nexys4d/sys_conf.vhd new file mode 100644 index 00000000..0798ad32 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4d/sys_conf.vhd @@ -0,0 +1,66 @@ +-- $Id: sys_conf.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_n4d (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2016.2; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- single clock design, clkser = clksys + constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; + constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; + constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; + constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- configure further units ------------------------------------------------- + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) + + -- derived constants ======================================================= + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; + diff --git a/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vbom b/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vbom new file mode 100644 index 00000000..37a73ef2 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vbom @@ -0,0 +1,30 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rbus/rbdlib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/sysmon/sysmonrbuslib.vbom +${sys_conf := sys_conf.vhd} +# components +[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_4line_iob.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../vlib/rlink/rlink_sp1c.vbom +../rbd_tst_rlink.vbom +../../../bplib/bpgen/rgbdrv_master.vbom +../../../bplib/bpgen/rgbdrv_analog_rbus.vbom +../../../bplib/sysmon/sysmonx_rbus_base.vbom +../../../vlib/rbus/rbd_usracc.vbom +../../../vlib/rbus/rb_sres_or_2.vbom +../../../vlib/rbus/rb_sres_or_6.vbom +# design +sys_tst_rlink_n4d.vhd +@xdc:../../../bplib/nexys4d/nexys4d_pclk.xdc +@xdc:../../../bplib/nexys4d/nexys4d_pins.xdc diff --git a/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd b/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd new file mode 100644 index 00000000..16001274 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd @@ -0,0 +1,379 @@ +-- $Id: sys_tst_rlink_n4d.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_rlink_n4d - syn +-- Description: rlink tester design for nexys4d +-- +-- Dependencies: vlib/xlib/s7_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_4line_iob +-- bplib/bpgen/sn_humanio_rbus +-- vlib/rlink/rlink_sp1c +-- rbd_tst_rlink +-- bplib/bpgen/rgbdrv_master +-- bplib/bpgen/rgbdrv_analog_rbus +-- bplib/sysmon/sysmonx_rbus_base +-- vlib/rbus/rbd_usracc +-- vlib/rbus/rb_sres_or_2 +-- vlib/rbus/rb_sres_or_6 +-- +-- Test bench: tb/tb_tst_rlink_n4d +-- +-- Target Devices: generic +-- Tool versions: ise 14.5-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic +-- 2016-04-02 758 2015.4 xc7a100t-1 1113 1461 36 3.0 528 usracc +-- 2016-03-27 753 2015.4 xc7a100t-1 1124 1461 36 3.0 522 meminf +-- 2016-03-13 743 2015.4 xc7a100t-1 1124 1463 64 4.5 567 +XADC +-- 2016-02-20 734 2015.4 xc7a100t-1 1080 1424 64 4.5 502 +RGB +-- 2015-01-31 640 2014.4 xc7a100t-1 990 1360 64 4.5 495 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-06-05 772 1.5.3 use CDUWIDTH=7, 120 MHz clock is natural choice +-- 2016-04-02 758 1.5.2 add rbd_usracc_e2 (bitfile+jtag timestamp access) +-- 2016-03-19 748 1.5.1 define rlink SYSID +-- 2016-03-12 741 1.5 add sysmon_rbus +-- 2016-02-20 734 1.4.2 add rgbdrv_analog_rbus for two rgb leds +-- 2015-04-11 666 1.4.1 rearrange XON handling +-- 2015-02-06 643 1.4 factor out memory +-- 2015-02-01 641 1.3.1 separate I_BTNRST_N; autobaud on msb of display +-- 2015-01-31 640 1.3 drop fusp iface; use new sn_hio +-- 2014-11-09 603 1.2 use new rlink v4 iface and 4 bit STAT +-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit +-- 2013-09-28 535 1.0 Initial version (derived from sys_tst_rlink_n3) +------------------------------------------------------------------------------ +-- Usage of Nexys 4DDR Switches, Buttons, LEDs: +-- +-- SWI(7:2): no function (only connected to sn_humanio_rbus) +-- SWI(1): 1 enable XON +-- SWI(0): -unused- +-- +-- LED(7): SER_MONI.abact +-- LED(6:2): no function (only connected to sn_humanio_rbus) +-- LED(1): timer 1 busy +-- LED(0): timer 0 busy +-- +-- DSP: SER_MONI.clkdiv (from auto bauder) +-- DP(3): not SER_MONI.txok (shows tx back preasure) +-- DP(2): SER_MONI.txact (shows tx activity) +-- DP(1): not SER_MONI.rxok (shows rx back preasure) +-- DP(0): SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rbdlib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.sysmonrbuslib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_rlink_n4d is -- top level + -- implements nexys4d_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4d switches + I_BTN : in slv5; -- n4d buttons + I_BTNRST_N : in slbit; -- n4d reset button + O_LED : out slv16; -- n4d leds + O_RGBLED0 : out slv3; -- n4d rgb-led 0 + O_RGBLED1 : out slv3; -- n4d rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end sys_tst_rlink_n4d; + +architecture syn of sys_tst_rlink_n4d is + + signal CLK : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv32 := (others=>'0'); + signal DSP_DP : slv8 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + signal RB_SRES_RGB0 : rb_sres_type := rb_sres_init; + signal RB_SRES_RGB1 : rb_sres_type := rb_sres_init; + signal RB_SRES_RGB : rb_sres_type := rb_sres_init; + signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; + signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + signal STAT : slv8 := (others=>'0'); + + signal RGBCNTL : slv3 := (others=>'0'); + signal DIMCNTL : slv12 := (others=>'0'); + + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx + constant rbaddr_rgb0 : slv16 := x"fc00"; -- fe00/0004: 1111 1100 0000 00xx + constant rbaddr_rgb1 : slv16 := x"fc04"; -- fe04/0004: 1111 1100 0000 01xx + constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx + + constant sysid_proj : slv16 := x"0101"; -- tst_rlink + constant sysid_board : slv8 := x"06"; -- nexys4d + constant sysid_vers : slv8 := x"00"; + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + RESET <= '0'; -- so far not used + + GEN_CLKSYS : s7_cmt_sfs + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, -- good up to 127 MHz + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_4line_iob + port map ( + CLK => CLK, + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_CTS_N => I_CTS_N, + O_RTS_N => O_RTS_N + ); + + HIO : sn_humanio_rbus + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DCWIDTH => 3, + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RLINK : rlink_sp1c + generic map ( + BTOWIDTH => 6, + RTAWIDTH => 12, + SYSID => sysid_proj & sysid_board & sysid_vers, + IFAWIDTH => 5, + OFAWIDTH => 5, + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 12, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink + RBMON_RBADDR => (others=>'0')) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ESCFILL => '0', + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + RBDTST : entity work.rbd_tst_rlink + port map ( + CLK => CLK, + RESET => RESET, + CE_USEC => CE_USEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TST, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RB_SRES_TOP => RB_SRES, + RXSD => RXD, + RXACT => SER_MONI.rxact, + STAT => STAT + ); + + RGBMSTR : rgbdrv_master + generic map ( + DWIDTH => DIMCNTL'length) + port map ( + CLK => CLK, + RESET => RESET, + CE_USEC => CE_USEC, + RGBCNTL => RGBCNTL, + DIMCNTL => DIMCNTL + ); + + RGB0 : rgbdrv_analog_rbus + generic map ( + DWIDTH => DIMCNTL'length, + RB_ADDR => rbaddr_rgb0) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_RGB0, + RGBCNTL => RGBCNTL, + DIMCNTL => DIMCNTL, + O_RGBLED => O_RGBLED0 + ); + + RGB1 : rgbdrv_analog_rbus + generic map ( + DWIDTH => DIMCNTL'length, + RB_ADDR => rbaddr_rgb1) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_RGB1, + RGBCNTL => RGBCNTL, + DIMCNTL => DIMCNTL, + O_RGBLED => O_RGBLED1 + ); + + + SMRB : if sys_conf_rbd_sysmon generate + I0: sysmonx_rbus_base + generic map ( -- use default INIT_ (Vccint=1.00) + CLK_MHZ => sys_conf_clksys_mhz, + RB_ADDR => rbaddr_sysmon) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_SYSMON, + ALM => open, + OT => open, + TEMP => open + ); + end generate SMRB; + + UARB : rbd_usracc + port map ( + CLK => CLK, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_USRACC + ); + + RB_SRES_ORRGB : rb_sres_or_2 + port map ( + RB_SRES_1 => RB_SRES_RGB0, + RB_SRES_2 => RB_SRES_RGB1, + RB_SRES_OR => RB_SRES_RGB + ); + + RB_SRES_OR1 : rb_sres_or_6 + port map ( + RB_SRES_1 => RB_SRES_HIO, + RB_SRES_2 => RB_SRES_TST, + RB_SRES_3 => RB_SRES_RGB, + RB_SRES_4 => RB_SRES_SYSMON, + RB_SRES_5 => RB_SRES_USRACC, + RB_SRES_OR => RB_SRES + ); + + DSP_DAT(31 downto 20) <= SER_MONI.abclkdiv(11 downto 0); + DSP_DAT(19) <= '0'; + DSP_DAT(18 downto 16) <= SER_MONI.abclkdiv_f; + DSP_DP(7 downto 4) <= "0010"; + + DSP_DAT(15 downto 0) <= (others=>'0'); + + DSP_DP(3) <= not SER_MONI.txok; + DSP_DP(2) <= SER_MONI.txact; + DSP_DP(1) <= not SER_MONI.rxok; + DSP_DP(0) <= SER_MONI.rxact; + + LED(15 downto 8) <= SWI(15 downto 8); + LED(7) <= SER_MONI.abact; + LED(6 downto 2) <= (others=>'0'); + LED(1) <= STAT(1); + LED(0) <= STAT(0); + +end syn; diff --git a/rtl/sys_gen/tst_rlink/nexys4d/tb/.gitignore b/rtl/sys_gen/tst_rlink/nexys4d/tb/.gitignore new file mode 100644 index 00000000..6c05344d --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4d/tb/.gitignore @@ -0,0 +1,2 @@ +tb_tst_rlink_n4d +sysmon_stim diff --git a/rtl/sys_gen/tst_rlink/nexys4d/tb/Makefile b/rtl/sys_gen/tst_rlink/nexys4d/tb/Makefile new file mode 100644 index 00000000..01a37552 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4d/tb/Makefile @@ -0,0 +1,39 @@ +# $Id: Makefile 838 2017-01-04 20:57:57Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-01-04 838 1.0 Initial version +# +EXE_all = tb_tst_rlink_n4d +# +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4d.mk +# +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/tst_rlink/nexys4d/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_rlink/nexys4d/tb/sys_conf_sim.vhd new file mode 100644 index 00000000..34d58778 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4d/tb/sys_conf_sim.vhd @@ -0,0 +1,63 @@ +-- $Id: sys_conf_sim.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2013-2016 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_n4 (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2016-03-12 741 1.1 add sysmon_rbus +-- 2013-09-28 535 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- single clock design, clkser = clksys + constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; + constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; + constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; + constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- configure further units ------------------------------------------------- + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) + + -- derived constants ======================================================= + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_rlink/nexys4d/tb/tb_tst_rlink_n4d.vbom b/rtl/sys_gen/tst_rlink/nexys4d/tb/tb_tst_rlink_n4d.vbom new file mode 100644 index 00000000..ed0b0f39 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4d/tb/tb_tst_rlink_n4d.vbom @@ -0,0 +1,9 @@ +# configure tb_nexsy4d with sys_tst_rlink_n4d target; +# use vhdl configure file (tb_tst_rlink_n4d.vhd) to allow +# that all configurations will co-exist in work library +# configure +nexys4d_aif = ../sys_tst_rlink_n4d.vbom +sys_conf = sys_conf_sim.vhd +# design +../../../../bplib/nexys4d/tb/tb_nexys4d.vbom +tb_tst_rlink_n4d.vhd diff --git a/rtl/sys_gen/tst_rlink/nexys4d/tb/tb_tst_rlink_n4d.vhd b/rtl/sys_gen/tst_rlink/nexys4d/tb/tb_tst_rlink_n4d.vhd new file mode 100644 index 00000000..55701ed0 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4d/tb/tb_tst_rlink_n4d.vhd @@ -0,0 +1,35 @@ +-- $Id: tb_tst_rlink_n4d.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_rlink_n4d +-- Description: Configuration for tb_tst_rlink_n4d for tb_nexys4d +-- +-- Dependencies: sys_tst_rlink_n4d +-- +-- To test: sys_tst_rlink_n4d +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_tst_rlink_n4d of tb_nexys4d is + + for sim + for all : nexys4d_aif + use entity work.sys_tst_rlink_n4d; + end for; + end for; + +end tb_tst_rlink_n4d; diff --git a/rtl/sys_gen/tst_rlink/nexys4d/tb/tb_tst_rlink_n4d_ssim.vbom b/rtl/sys_gen/tst_rlink/nexys4d/tb/tb_tst_rlink_n4d_ssim.vbom new file mode 100644 index 00000000..4f46c1e0 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4d/tb/tb_tst_rlink_n4d_ssim.vbom @@ -0,0 +1,8 @@ +# configure for _*sim case +# Note: this tb uses sys_tst_rlink_n4d.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +# configure +nexys4d_aif = sys_tst_rlink_n4d_ssim.vhd +# design +tb_tst_rlink_n4d.vbom +@top:tb_tst_rlink_n4d diff --git a/rtl/sys_gen/tst_rlink/nexys4d/tb/tbrun.yml b/rtl/sys_gen/tst_rlink/nexys4d/tb/tbrun.yml new file mode 100644 index 00000000..89d38676 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4d/tb/tbrun.yml @@ -0,0 +1,18 @@ +# $Id: tbrun.yml 838 2017-01-04 20:57:57Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-01-04 838 1.0 Initial version +# +- default: + mode: ${viv_modes} +# +- tag: [viv, sys_tst_rlink, n4d, base] + test: | + tbrun_tbwrri --lsuf base --pack tst_rlink tb_tst_rlink_n4d${ms} \ + "tst_rlink::setup" "tst_rlink::test_all" +# +- tag: [viv, sys_tst_rlink, n4d, emon] + test: | + tbrun_tbwrri --lsuf emon --pack tst_rlink tb_tst_rlink_n4d${ms} \ + "tst_rlink::setup" "tst_rlink::test_all_emon" diff --git a/rtl/sys_gen/tst_rlink/nexys4d/tb/tbw.dat b/rtl/sys_gen/tst_rlink/nexys4d/tb/tbw.dat new file mode 100644 index 00000000..a59ae2f5 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4d/tb/tbw.dat @@ -0,0 +1,7 @@ +# $Id: tbw.dat 838 2017-01-04 20:57:57Z mueller $ +# +[tb_tst_rlink_n4d] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = +sysmon_stim = ../../../../bplib/sysmon/tb/sysmon_stim_n4.dat diff --git a/rtl/sys_gen/tst_serloop/nexys4/tb/sys_conf1_sim.vhd b/rtl/sys_gen/tst_serloop/nexys4/tb/sys_conf1_sim.vhd index 84e98699..19d2e9e7 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/tb/sys_conf1_sim.vhd +++ b/rtl/sys_gen/tst_serloop/nexys4/tb/sys_conf1_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf1_sim.vhd 753 2016-03-28 08:57:31Z mueller $ +-- $Id: sys_conf1_sim.vhd 838 2017-01-04 20:57:57Z mueller $ -- -- Copyright 2015-2016 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_serloop1_n4 (for test bench) -- -- Dependencies: - --- Tool versions: viv 2014.4-2015.4; ghdl 0.31-033 +-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 -- Revision History: -- Date Rev Version Comment -- 2016-03-27 753 1.1 clock now from cmt and configurable diff --git a/rtl/sys_gen/tst_serloop/nexys4d/Makefile b/rtl/sys_gen/tst_serloop/nexys4d/Makefile new file mode 100644 index 00000000..4e84ae38 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/Makefile @@ -0,0 +1,25 @@ +# $Id: Makefile 838 2017-01-04 20:57:57Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-01-04 838 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4d.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/tst_serloop/nexys4d/sys_conf1.vhd b/rtl/sys_gen/tst_serloop/nexys4d/sys_conf1.vhd new file mode 100644 index 00000000..70335f58 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/sys_conf1.vhd @@ -0,0 +1,56 @@ +-- $Id: sys_conf1.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop1_n4d (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2016.2; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + + constant sys_conf_clkdiv_usecdiv : integer := 100; -- default usec + constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec + + -- configure hio interfaces ----------------------------------------------- + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- configure serport ------------------------------------------------------ + constant sys_conf_uart_defbaud : integer := 115200; -- default 115k baud + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_uart_cdinit : integer := + (sys_conf_clksys/sys_conf_uart_defbaud)-1; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_serloop/nexys4d/sys_conf2.vhd b/rtl/sys_gen/tst_serloop/nexys4d/sys_conf2.vhd new file mode 100644 index 00000000..a0aad243 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/sys_conf2.vhd @@ -0,0 +1,67 @@ +-- $Id: sys_conf2.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop2_n4d (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2016.2; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 5; -- f 20 Mhz + constant sys_conf_clksys_vcomultiply : positive := 36; -- vco 720 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 72 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + + constant sys_conf_clksys_msecdiv : integer := 1000; -- default msec + + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; + + constant sys_conf_clkser_msecdiv : integer := 1000; -- default msec + + -- configure hio interfaces ----------------------------------------------- + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- configure serport ------------------------------------------------------ + constant sys_conf_uart_defbaud : integer := 115200; -- default 115k baud + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + + constant sys_conf_uart_cdinit : integer := + (sys_conf_clkser/sys_conf_uart_defbaud)-1; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop1_n4d.vbom b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop1_n4d.vbom new file mode 100644 index 00000000..c7fb11dc --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop1_n4d.vbom @@ -0,0 +1,21 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../tst_serlooplib.vbom +../../../vlib/serport/serportlib.vbom +${sys_conf := sys_conf1.vhd} +# components +[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_4line_iob.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_serloop_hiomap.vbom +../../../vlib/serport/serport_1clock.vbom +../tst_serloop.vbom +# design +sys_tst_serloop1_n4d.vhd +@xdc:../../../bplib/nexys4d/nexys4d_pclk.xdc +@xdc:../../../bplib/nexys4d/nexys4d_pins.xdc diff --git a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop1_n4d.vhd b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop1_n4d.vhd new file mode 100644 index 00000000..631cc0cf --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop1_n4d.vhd @@ -0,0 +1,236 @@ +-- $Id: sys_tst_serloop1_n4d.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_serloop1_n4d - syn +-- Description: Tester serial link for nexys4d (serport_1clock case) +-- +-- Dependencies: vlib/xlib/s7_cmt_sfs +-- vlib/genlib/clkdivce +-- bpgen/bp_rs232_4line_iob +-- bpgen/sn_humanio +-- tst_serloop_hiomap +-- vlib/serport/serport_1clock +-- tst_serloop +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: viv 2016.2; ghdl 0.33 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic +-- 2017-01-xx xxx 2016.2 xc7a100t-1 xxx xxxx xx 0 xxx +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version (derived from sys_tst_serloop1_n4) +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.tst_serlooplib.all; +use work.serportlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_serloop1_n4d is -- top level + -- implements nexys4d_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4d switches + I_BTN : in slv5; -- n4d buttons + I_BTNRST_N : in slbit; -- n4d reset button + O_LED : out slv16; -- n4d leds + O_RGBLED0 : out slv3; -- n4d rgb-led 0 + O_RGBLED1 : out slv3; -- n4d rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end sys_tst_serloop1_n4d; + +architecture syn of sys_tst_serloop1_n4d is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RXD : slbit := '0'; + signal TXD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv32 := (others=>'0'); + signal DSP_DP : slv8 := (others=>'0'); + + signal HIO_CNTL : hio_cntl_type := hio_cntl_init; + signal HIO_STAT : hio_stat_type := hio_stat_init; + + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXHOLD : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal SER_MONI : serport_moni_type := serport_moni_init; + +begin + + GEN_CLKSYS : s7_cmt_sfs -- clock generator ------------------- + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => sys_conf_clkdiv_msecdiv) + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DCWIDTH => 3, + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => '0', + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RESET <= BTN(0); -- BTN(0) will reset tester !! + + HIOMAP : tst_serloop_hiomap + port map ( + CLK => CLK, + RESET => RESET, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + SWI => SWI(7 downto 0), + BTN => BTN(3 downto 0), + LED => LED(7 downto 0), + DSP_DAT => DSP_DAT(15 downto 0), + DSP_DP => DSP_DP(3 downto 0) + ); + + IOB_RS232 : bp_rs232_4line_iob + port map ( + CLK => CLK, + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_CTS_N => I_CTS_N, + O_RTS_N => O_RTS_N + ); + + SERPORT : serport_1clock + generic map ( + CDWIDTH => 12, + CDINIT => sys_conf_uart_cdinit, + RXFAWIDTH => 5, + TXFAWIDTH => 5) + port map ( + CLK => CLK, + CE_MSEC => CE_MSEC, + RESET => RESET, + ENAXON => HIO_CNTL.enaxon, + ENAESC => HIO_CNTL.enaesc, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + MONI => SER_MONI, + RXSD => RXD, + TXSD => TXD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N + ); + + TESTER : tst_serloop + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + -- show autobauder clock divisor on msb of display + DSP_DAT(31 downto 20) <= SER_MONI.abclkdiv(11 downto 0); + DSP_DAT(19) <= '0'; + DSP_DAT(18 downto 16) <= SER_MONI.abclkdiv_f; + DSP_DP(7 downto 4) <= "0010"; + + -- setup unused outputs in nexys4d + O_RGBLED0 <= (others=>'0'); + O_RGBLED1 <= (others=>not I_BTNRST_N); + +end syn; diff --git a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vbom b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vbom new file mode 100644 index 00000000..24e4ae91 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vbom @@ -0,0 +1,21 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../tst_serlooplib.vbom +../../../vlib/serport/serportlib.vbom +${sys_conf := sys_conf2.vhd} +# components +[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_4line_iob.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_serloop_hiomap.vbom +../../../vlib/serport/serport_2clock2.vbom +../tst_serloop.vbom +# design +sys_tst_serloop2_n4d.vhd +@xdc:../../../bplib/nexys4d/nexys4d_pclk.xdc +@xdc:../../../bplib/nexys4d/nexys4d_pins.xdc diff --git a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd new file mode 100644 index 00000000..b2069174 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd @@ -0,0 +1,266 @@ +-- $Id: sys_tst_serloop2_n4d.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_serloop1_n4d - syn +-- Description: Tester serial link for nexys4d (serport_1clock case) +-- +-- Dependencies: vlib/xlib/s7_cmt_sfs +-- vlib/genlib/clkdivce +-- bpgen/bp_rs232_4line_iob +-- bpgen/sn_humanio +-- tst_serloop_hiomap +-- vlib/serport/serport_2clock2 +-- tst_serloop +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: viv 2016.2; ghdl 0.33 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic +-- 2017-xx-xx xxx 2016.2 xc7a100t-1 xxx xxxx xx 0 xxx +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version (derived from sys_tst_serloop2_n4) +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.tst_serlooplib.all; +use work.serportlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_serloop2_n4d is -- top level + -- implements nexys4d_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4d switches + I_BTN : in slv5; -- n4d buttons + I_BTNRST_N : in slbit; -- n4d reset button + O_LED : out slv16; -- n4d leds + O_RGBLED0 : out slv3; -- n4d rgb-led 0 + O_RGBLED1 : out slv3; -- n4d rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end sys_tst_serloop2_n4d; + +architecture syn of sys_tst_serloop2_n4d is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal CLKS : slbit := '0'; + signal CES_MSEC : slbit := '0'; + + signal RXD : slbit := '0'; + signal TXD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv32 := (others=>'0'); + signal DSP_DP : slv8 := (others=>'0'); + + signal HIO_CNTL : hio_cntl_type := hio_cntl_init; + signal HIO_STAT : hio_stat_type := hio_stat_init; + + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXHOLD : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal SER_MONI : serport_moni_type := serport_moni_init; + +begin + + GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV_CLK : clkdivce + generic map ( + CDUWIDTH => 8, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => sys_conf_clksys_msecdiv) + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + GEN_CLKSER : s7_cmt_sfs -- clock generator serport ----------- + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clkser_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLKS, + LOCKED => open + ); + + CLKDIV_CLKS : clkdivce + generic map ( + CDUWIDTH => 7, -- good up to 127 MHz + USECDIV => sys_conf_clkser_mhz, + MSECDIV => sys_conf_clkser_msecdiv) + port map ( + CLK => CLKS, + CE_USEC => open, + CE_MSEC => CES_MSEC + ); + + HIO : sn_humanio + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DCWIDTH => 3, + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => '0', + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RESET <= BTN(0); -- BTN(0) will reset tester !! + + HIOMAP : tst_serloop_hiomap + port map ( + CLK => CLK, + RESET => RESET, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + SWI => SWI(7 downto 0), + BTN => BTN(3 downto 0), + LED => LED(7 downto 0), + DSP_DAT => DSP_DAT(15 downto 0), + DSP_DP => DSP_DP(3 downto 0) + ); + + IOB_RS232 : bp_rs232_4line_iob + port map ( + CLK => CLKS, + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_CTS_N => I_CTS_N, + O_RTS_N => O_RTS_N + ); + + SERPORT : serport_2clock2 + generic map ( + CDWIDTH => 12, + CDINIT => sys_conf_uart_cdinit, + RXFAWIDTH => 5, + TXFAWIDTH => 5) + port map ( + CLKU => CLK, + RESET => RESET, + CLKS => CLKS, + CES_MSEC => CES_MSEC, + ENAXON => HIO_CNTL.enaxon, + ENAESC => HIO_CNTL.enaesc, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + MONI => SER_MONI, + RXSD => RXD, + TXSD => TXD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N + ); + + TESTER : tst_serloop + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + -- show autobauder clock divisor on msb of display + DSP_DAT(31 downto 20) <= SER_MONI.abclkdiv(11 downto 0); + DSP_DAT(19) <= '0'; + DSP_DAT(18 downto 16) <= SER_MONI.abclkdiv_f; + DSP_DP(7 downto 4) <= "0010"; + + -- setup unused outputs in nexys4d + O_RGBLED0 <= (others=>'0'); + O_RGBLED1 <= (others=>not I_BTNRST_N); + +end syn; diff --git a/rtl/sys_gen/tst_serloop/nexys4d/tb/.gitignore b/rtl/sys_gen/tst_serloop/nexys4d/tb/.gitignore new file mode 100644 index 00000000..78932086 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/tb/.gitignore @@ -0,0 +1,3 @@ +tb_tst_serloop1_n4 +tb_tst_serloop2_n4 +tb_tst_serloop_stim diff --git a/rtl/sys_gen/tst_serloop/nexys4d/tb/Makefile b/rtl/sys_gen/tst_serloop/nexys4d/tb/Makefile new file mode 100644 index 00000000..cfe8d510 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/tb/Makefile @@ -0,0 +1,40 @@ +# $Id: Makefile 838 2017-01-04 20:57:57Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-01-04 838 1.0 Initial version +# +EXE_all = tb_tst_serloop1_n4d +EXE_all += tb_tst_serloop2_n4d +# +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4d.mk +# +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/tst_serloop/nexys4d/tb/sys_conf1_sim.vhd b/rtl/sys_gen/tst_serloop/nexys4d/tb/sys_conf1_sim.vhd new file mode 100644 index 00000000..40273d30 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/tb/sys_conf1_sim.vhd @@ -0,0 +1,58 @@ +-- $Id: sys_conf1_sim.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop1_n4d (for test bench) +-- +-- Dependencies: - +-- Tool versions: viv 2016.2; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- in simulation a usec stays to 120 cycles (1.0 usec) and a msec to + -- 240 cycles (2 usec). This affects mainly the autobauder. A break will be + -- detected after 128 msec periods, this in simulation after 256 usec or + -- 30720 cycles. This is compatible with bitrates of 115200 baud or higher + -- (115200 <-> 8.68 usec <-> 1040 cycles) + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + + constant sys_conf_clkdiv_msecdiv : integer := 2; -- shortened !! + + -- configure hio interfaces ----------------------------------------------- + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- configure serport ------------------------------------------------------ + constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_serloop/nexys4d/tb/sys_conf2_sim.vhd b/rtl/sys_gen/tst_serloop/nexys4d/tb/sys_conf2_sim.vhd new file mode 100644 index 00000000..129d3b31 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/tb/sys_conf2_sim.vhd @@ -0,0 +1,70 @@ +-- $Id: sys_conf2_sim.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop2_n4d (for test bench) +-- +-- Dependencies: - +-- Tool versions: 2016.2; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- in simulation a usec stays to 120 cycles (1.0 usec) and a msec to + -- 240 cycles (2 usec). This affects mainly the autobauder. A break will be + -- detected after 128 msec periods, this in simulation after 256 usec or + -- 30720 cycles. This is compatible with bitrates of 115200 baud or higher + -- (115200 <-> 8.68 usec <-> 1040 cycles) + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 5; -- f 20 Mhz + constant sys_conf_clksys_vcomultiply : positive := 36; -- vco 720 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 72 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + + constant sys_conf_clksys_msecdiv : integer := 2; -- shortened !! + + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; + + constant sys_conf_clkser_msecdiv : integer := 2; -- shortened !! + + -- configure hio interfaces ----------------------------------------------- + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- configure serport ------------------------------------------------------ + constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; diff --git a/rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop1_n4d.vbom b/rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop1_n4d.vbom new file mode 100644 index 00000000..dec0c587 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop1_n4d.vbom @@ -0,0 +1,11 @@ +# libs +../../../../vlib/slvtypes.vhd +../../../../vlib/simlib/simlib.vhd +${sys_conf := sys_conf1_sim.vhd} +# components +../../../../vlib/simlib/simclk.vbom +../../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom +../sys_tst_serloop1_n4d.vbom -UUT +../../tb/tb_tst_serloop.vbom +# design +tb_tst_serloop1_n4d.vhd diff --git a/rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop1_n4d.vhd b/rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop1_n4d.vhd new file mode 100644 index 00000000..60271f5d --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop1_n4d.vhd @@ -0,0 +1,135 @@ +-- $Id: tb_tst_serloop1_n4d.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_serloop1_n4d - sim +-- Description: Test bench for sys_tst_serloop1_n4d +-- +-- Dependencies: simlib/simclk +-- vlib/xlib/tb/s7_cmt_sfs_tb +-- sys_tst_serloop1_n4d [UUT] +-- tb/tb_tst_serloop +-- +-- To test: sys_tst_serloop1_n4d +-- +-- Target Devices: generic +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version (cloned from tb_tst_serloop1_n4) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.simlib.all; +use work.sys_conf.all; + +entity tb_tst_serloop1_n4d is +end tb_tst_serloop1_n4d; + +architecture sim of tb_tst_serloop1_n4d is + + signal CLK100 : slbit := '0'; + + signal CLK : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal O_RTS_N : slbit := '0'; + signal I_CTS_N : slbit := '0'; + signal I_SWI : slv16 := (others=>'0'); + signal I_BTN : slv5 := (others=>'0'); + + signal RXD : slbit := '1'; + signal TXD : slbit := '1'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + + constant clock_period : Delay_length := 10 ns; + constant clock_offset : Delay_length := 200 ns; + constant delay_time : Delay_length := 2 ns; + +begin + + SYSCLK : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK100 + ); + + GEN_CLKSYS : entity work.s7_cmt_sfs_tb + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => CLK100, + CLKFX => CLK, + LOCKED => open + ); + + UUT : entity work.sys_tst_serloop1_n4d + port map ( + I_CLK100 => CLK100, + I_RXD => I_RXD, + O_TXD => O_TXD, + O_RTS_N => O_RTS_N, + I_CTS_N => I_CTS_N, + I_SWI => I_SWI, + I_BTN => I_BTN, + I_BTNRST_N => '1', + O_LED => open, + O_RGBLED0 => open, + O_RGBLED1 => open, + O_ANO_N => open, + O_SEG_N => open + ); + + GENTB : entity work.tb_tst_serloop + port map ( + CLKS => CLK, + CLKH => CLK, + P0_RXD => RXD, + P0_TXD => TXD, + P0_RTS_N => RTS_N, + P0_CTS_N => CTS_N, + P1_RXD => open, -- port 1 unused for n4d ! + P1_TXD => '0', + P1_RTS_N => '0', + P1_CTS_N => open, + SWI => SWI(7 downto 0), + BTN => BTN(3 downto 0) + ); + + I_RXD <= RXD after delay_time; + TXD <= O_TXD after delay_time; + RTS_N <= O_RTS_N after delay_time; + I_CTS_N <= CTS_N after delay_time; + + I_SWI <= SWI after delay_time; + I_BTN <= BTN after delay_time; + +end sim; diff --git a/rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop1_n4d_ssim.vbom b/rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop1_n4d_ssim.vbom new file mode 100644 index 00000000..5534e167 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop1_n4d_ssim.vbom @@ -0,0 +1,12 @@ +# libs +../../../../vlib/slvtypes.vhd +../../../../vlib/simlib/simlib.vhd +${sys_conf := sys_conf1_sim.vhd} +# components +../../../../vlib/simlib/simclk.vbom +../../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom +sys_tst_serloop1_n4d_ssim.vhd -UUT +../../tb/tb_tst_serloop.vbom +# design +tb_tst_serloop1_n4d.vhd +@top:tb_tst_serloop1_n4d diff --git a/rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop2_n4d.vbom b/rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop2_n4d.vbom new file mode 100644 index 00000000..0169c175 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop2_n4d.vbom @@ -0,0 +1,11 @@ +# libs +../../../../vlib/slvtypes.vhd +../../../../vlib/simlib/simlib.vhd +${sys_conf := sys_conf2_sim.vhd} +# components +../../../../vlib/simlib/simclk.vbom +../../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom +../sys_tst_serloop2_n4d.vbom -UUT +../../tb/tb_tst_serloop.vbom +# design +tb_tst_serloop2_n4d.vhd diff --git a/rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop2_n4d.vhd b/rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop2_n4d.vhd new file mode 100644 index 00000000..c6071a9a --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop2_n4d.vhd @@ -0,0 +1,151 @@ +-- $Id: tb_tst_serloop2_n4d.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_serloop2_n4d - sim +-- Description: Test bench for sys_tst_serloop2_n4d +-- +-- Dependencies: simlib/simclk +-- vlib/xlib/tb/s7_cmt_sfs_tb +-- sys_tst_serloop2_n4d [UUT] +-- tb/tb_tst_serloop +-- +-- To test: sys_tst_serloop2_n4d +-- +-- Target Devices: generic +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version (cloned from tb_tst_serloop2_n4) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.simlib.all; +use work.sys_conf.all; + +entity tb_tst_serloop2_n4d is +end tb_tst_serloop2_n4d; + +architecture sim of tb_tst_serloop2_n4d is + + signal CLK100 : slbit := '0'; + + signal CLKS : slbit := '0'; + signal CLKH : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal O_RTS_N : slbit := '0'; + signal I_CTS_N : slbit := '0'; + signal I_SWI : slv16 := (others=>'0'); + signal I_BTN : slv5 := (others=>'0'); + + signal RXD : slbit := '1'; + signal TXD : slbit := '1'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + + constant clock_period : Delay_length := 10 ns; + constant clock_offset : Delay_length := 200 ns; + constant delay_time : Delay_length := 2 ns; + +begin + + SYSCLK : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK100 + ); + + GEN_CLKSYS : entity work.s7_cmt_sfs_tb + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => CLK100, + CLKFX => CLKH, + LOCKED => open + ); + + GEN_CLKSER : entity work.s7_cmt_sfs_tb + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clkser_gentype) + port map ( + CLKIN => CLK100, + CLKFX => CLKS, + LOCKED => open + ); + + UUT : entity work.sys_tst_serloop2_n4d + port map ( + I_CLK100 => CLK100, + I_RXD => I_RXD, + O_TXD => O_TXD, + O_RTS_N => O_RTS_N, + I_CTS_N => I_CTS_N, + I_SWI => I_SWI, + I_BTN => I_BTN, + I_BTNRST_N => '1', + O_LED => open, + O_RGBLED0 => open, + O_RGBLED1 => open, + O_ANO_N => open, + O_SEG_N => open + ); + + GENTB : entity work.tb_tst_serloop + port map ( + CLKS => CLKS, + CLKH => CLKH, + P0_RXD => RXD, + P0_TXD => TXD, + P0_RTS_N => RTS_N, + P0_CTS_N => CTS_N, + P1_RXD => open, -- port 1 unused for n4d ! + P1_TXD => '0', + P1_RTS_N => '0', + P1_CTS_N => open, + SWI => SWI(7 downto 0), + BTN => BTN(3 downto 0) + ); + + I_RXD <= RXD after delay_time; + TXD <= O_TXD after delay_time; + RTS_N <= O_RTS_N after delay_time; + I_CTS_N <= CTS_N after delay_time; + + I_SWI <= SWI after delay_time; + I_BTN <= BTN after delay_time; + +end sim; diff --git a/rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop2_n4d_ssim.vbom b/rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop2_n4d_ssim.vbom new file mode 100644 index 00000000..c5965baa --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop2_n4d_ssim.vbom @@ -0,0 +1,12 @@ +# libs +../../../../vlib/slvtypes.vhd +../../../../vlib/simlib/simlib.vhd +${sys_conf := sys_conf2_sim.vhd} +# components +../../../../vlib/simlib/simclk.vbom +../../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom +sys_tst_serloop2_n4d_ssim.vhd -UUT +../../tb/tb_tst_serloop.vbom +# design +tb_tst_serloop2_n4d.vhd +@top:tb_tst_serloop2_n4d diff --git a/rtl/sys_gen/tst_serloop/nexys4d/tb/tbrun.yml b/rtl/sys_gen/tst_serloop/nexys4d/tb/tbrun.yml new file mode 100644 index 00000000..d78b56a2 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/tb/tbrun.yml @@ -0,0 +1,16 @@ +# $Id: tbrun.yml 838 2017-01-04 20:57:57Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-08-21 799 1.0 Initial version +# +- default: + mode: ${viv_modes} +# +- tag: [viv, sys_tst_serloop1, n4d] + test: | + tbrun_tbw tb_tst_serloop1_n4d${ms} + +- tag: [viv, sys_tst_serloop2, n4d] + test: | + tbrun_tbw tb_tst_serloop2_n4d${ms} diff --git a/rtl/sys_gen/tst_serloop/nexys4d/tb/tbw.dat b/rtl/sys_gen/tst_serloop/nexys4d/tb/tbw.dat new file mode 100644 index 00000000..bc7200a9 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/tb/tbw.dat @@ -0,0 +1,6 @@ +# $Id: tbw.dat 838 2017-01-04 20:57:57Z mueller $ +# +[tb_tst_serloop1_n4d] +tb_tst_serloop_stim = ../../tb/tb_tst_serloop_p0_cts_stim.dat +[tb_tst_serloop2_n4d] +tb_tst_serloop_stim = ../../tb/tb_tst_serloop_p0_cts_stim.dat diff --git a/rtl/sys_gen/tst_snhumanio/nexys4d/Makefile b/rtl/sys_gen/tst_snhumanio/nexys4d/Makefile new file mode 100644 index 00000000..9bc39139 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/nexys4d/Makefile @@ -0,0 +1,26 @@ +# $Id: Makefile 838 2017-01-04 20:57:57Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-01-04 838 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4d.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/tst_snhumanio/nexys4d/sys_conf.vhd b/rtl/sys_gen/tst_snhumanio/nexys4d/sys_conf.vhd new file mode 100644 index 00000000..703da063 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/nexys4d/sys_conf.vhd @@ -0,0 +1,35 @@ +-- $Id: sys_conf.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_snhumanio_n4d (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2016.2; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + +end package sys_conf; + diff --git a/rtl/sys_gen/tst_snhumanio/nexys4d/sys_tst_snhumanio_n4d.vbom b/rtl/sys_gen/tst_snhumanio/nexys4d/sys_tst_snhumanio_n4d.vbom new file mode 100644 index 00000000..32b17288 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/nexys4d/sys_tst_snhumanio_n4d.vbom @@ -0,0 +1,13 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +${sys_conf := sys_conf.vhd} +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_snhumanio.vbom +# design +sys_tst_snhumanio_n4d.vhd +@xdc:../../../bplib/nexys4d/nexys4d_pclk.xdc +@xdc:../../../bplib/nexys4d/nexys4d_pins.xdc diff --git a/rtl/sys_gen/tst_snhumanio/nexys4d/sys_tst_snhumanio_n4d.vhd b/rtl/sys_gen/tst_snhumanio/nexys4d/sys_tst_snhumanio_n4d.vhd new file mode 100644 index 00000000..2e875e17 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/nexys4d/sys_tst_snhumanio_n4d.vhd @@ -0,0 +1,140 @@ +-- $Id: sys_tst_snhumanio_n4d.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_snhumanio_n4d - syn +-- Description: snhumanio tester design for nexys4d +-- +-- Dependencies: vlib/genlib/clkdivce +-- bplib/bpgen/sn_humanio +-- tst_snhumanio +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: viv 2016.2; ghdl 0.31 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic +-- 2017-01-xx xxx 2016.2 xc7a100t-1 xxx xxx 0 0 xx +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version +------------------------------------------------------------------------------ +-- Usage of Nexys 4DDR Switches, Buttons, LEDs: +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_snhumanio_n4d is -- top level + -- implements nexys4d_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4d switches + I_BTN : in slv5; -- n4d buttons + I_BTNRST_N : in slbit; -- n4d reset button + O_LED : out slv16; -- n4d leds + O_RGBLED0 : out slv3; -- n4d rgb-led 0 + O_RGBLED1 : out slv3; -- n4d rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end sys_tst_snhumanio_n4d; + +architecture syn of sys_tst_snhumanio_n4d is + + signal CLK : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_MSEC : slbit := '0'; + +begin + + RESET <= '0'; -- so far not used + + CLK <= I_CLK100; + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => 100, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio + generic map ( + BWIDTH => 5, + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI(7 downto 0), + I_BTN => I_BTN, + O_LED => O_LED(7 downto 0), + O_ANO_N => O_ANO_N(3 downto 0), + O_SEG_N => O_SEG_N + ); + + HIOTEST : entity work.tst_snhumanio + generic map ( + BWIDTH => 5) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + O_TXD <= I_RXD; + O_RTS_N <= I_CTS_N; + + O_LED(15 downto 8) <= not I_SWI(15 downto 8); + O_ANO_N(7 downto 4) <= (others=>'1'); + + O_RGBLED0 <= (others=>'0'); + O_RGBLED1 <= (others=>not I_BTNRST_N); + +end syn; diff --git a/rtl/sys_gen/w11a/README.md b/rtl/sys_gen/w11a/README.md index 99ba75e0..7a00eb61 100644 --- a/rtl/sys_gen/w11a/README.md +++ b/rtl/sys_gen/w11a/README.md @@ -8,4 +8,5 @@ and is organized in | [nexys2](nexys2) | design for Digilent Nexys2 | | [nexys3](nexys3) | design for Digilent Nexys3 | | [nexys4](nexys4) | design for Digilent Nexys4 (old CRAM version !!) | +| [nexys4d_bram](nexys4d_bram) | design for Digilent Nexys4 DDR, using BRAM only **UNTESTED** | | [s3board](s3board) | design for Digilent S3BOARD | diff --git a/rtl/sys_gen/w11a/nexys4d_bram/.gitignore b/rtl/sys_gen/w11a/nexys4d_bram/.gitignore new file mode 100644 index 00000000..48a711a8 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d_bram/.gitignore @@ -0,0 +1,3 @@ +sys_w11a_br_n4.ucf +log_* +_impact* diff --git a/rtl/sys_gen/w11a/nexys4d_bram/Makefile b/rtl/sys_gen/w11a/nexys4d_bram/Makefile new file mode 100644 index 00000000..4e84ae38 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d_bram/Makefile @@ -0,0 +1,25 @@ +# $Id: Makefile 838 2017-01-04 20:57:57Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-01-04 838 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4d.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/w11a/nexys4d_bram/sys_conf.vhd b/rtl/sys_gen/w11a/nexys4d_bram/sys_conf.vhd new file mode 100644 index 00000000..5ba59e1f --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d_bram/sys_conf.vhd @@ -0,0 +1,98 @@ +-- $Id: sys_conf.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_br_n4d (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2016.2; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version (derived from _br_n4 version) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- configure memory controller --------------------------------------------- + constant sys_conf_memctl_mawidth : positive := 5; + constant sys_conf_memctl_nblock : positive := 32; + + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs + constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs + constant sys_conf_dmscnt : boolean := false; + constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable + constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) + + -- configure w11 cpu core -------------------------------------------------- + -- sys_conf_mem_losize is highest 64 byte MMU block number + -- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks + constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1; +--constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte +--constant sys_conf_mem_losize : natural := 8#003777#; -- 128 kByte (debug) + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + constant sys_conf_cache_twidth : integer := 9; -- 8kB cache + + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clkser/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; diff --git a/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vbom b/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vbom new file mode 100644 index 00000000..ae2ea822 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vbom @@ -0,0 +1,36 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rbus/rbdlib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/sysmon/sysmonrbuslib.vbom +../../../bplib/nxcramlib/nxcramlib.vhd +../../../ibus/iblib.vhd +../../../ibus/ibdlib.vhd +../../../w11a/pdp11.vhd +${sys_conf := sys_conf.vhd} +# components +[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_4line_iob.vbom +../../../vlib/rlink/rlink_sp2c.vbom +../../../w11a/pdp11_sys70.vbom +../../../ibus/ibdr_maxisys.vbom +../../../w11a/pdp11_bram_memctl.vbom +../../../vlib/rlink/ioleds_sp1c.vbom +../../../w11a/pdp11_statleds.vbom +../../../w11a/pdp11_hio70.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../bplib/sysmon/sysmonx_rbus_base.vbom +../../../vlib/rbus/rbd_usracc.vbom +../../../vlib/rbus/rb_sres_or_4.vbom +# design +sys_w11a_br_n4d.vhd +@xdc:../../../bplib/nexys4d/nexys4d_pclk.xdc +@xdc:../../../bplib/nexys4d/nexys4d_pins.xdc diff --git a/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vhd b/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vhd new file mode 100644 index 00000000..15fd3f6d --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vhd @@ -0,0 +1,463 @@ +-- $Id: sys_w11a_br_n4d.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_w11a_br_n4d - syn +-- Description: w11a test design for nexys4d (bram only) +-- +-- Dependencies: vlib/xlib/s7_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_4line_iob +-- vlib/rlink/rlink_sp2c +-- w11a/pdp11_sys70 +-- ibus/ibdr_maxisys +-- w11a/pdp11_bram_memctl +-- vlib/rlink/ioleds_sp1c +-- w11a/pdp11_hio70 +-- bplib/bpgen/sn_humanio_rbus +-- bplib/sysmon/sysmonx_rbus_base +-- vlib/rbus/rbd_usracc +-- vlib/rbus/rb_sres_or_4 +-- +-- Test bench: tb/tb_sys_w11a_br_n4d +-- +-- Target Devices: generic +-- Tool versions: viv 2016.2; ghdl 0.33 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic +-- 2017-01-xx xxx 2016.2 xc7a100t-1 xxxx xxxx xxx xxx.x xxxx +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version (derived from sys_w11a_br_n4) +------------------------------------------------------------------------------ +-- +-- w11a test design for nexys4d +-- w11a + rlink + serport +-- +-- Usage of Nexys 4DDR Switches, Buttons, LEDs +-- +-- SWI(15:5): no function (only connected to sn_humanio_rbus) +-- (5): select DSP(7:4) display +-- 0 abclkdiv & abclkdiv_f +-- 1 PC +-- (4): select DSP(3:0) display +-- 0 DISPREG +-- 1 DR emulation +-- (3): select LED display +-- 0 overall status +-- 1 DR emulation +-- (2): unused-reserved (USB port select) +-- (1): 1 enable XON +-- (0): unused-reserved (serial port select) +-- +-- LEDs if SWI(3) = 1 +-- (15:0) DR emulation; shows R0 during wait like 11/45+70 +-- +-- LEDs if SWI(3) = 0 +-- (7) MEM_ACT_W +-- (6) MEM_ACT_R +-- (5) cmdbusy (all rlink access, mostly rdma) +-- (4:0) if cpugo=1 show cpu mode activity +-- (4) kernel mode, pri>0 +-- (3) kernel mode, pri=0 +-- (2) kernel mode, wait +-- (1) supervisor mode +-- (0) user mode +-- if cpugo=0 shows cpurust +-- (4) '1' +-- (3:0) cpurust code +-- +-- DSP(7:4) shows abclkdiv & abclkdiv_f or PS, depending on SWI(5) +-- DSP(3:0) shows DISPREG or DR emulation, depending on SWI(4) +-- DP(3:0) shows IO activity +-- (3) not SER_MONI.txok (shows tx back preasure) +-- (2) SER_MONI.txact (shows tx activity) +-- (1) not SER_MONI.rxok (shows rx back preasure) +-- (0) SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rbdlib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.sysmonrbuslib.all; +use work.iblib.all; +use work.ibdlib.all; +use work.pdp11.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_w11a_br_n4d is -- top level + -- implements nexys4d_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4d switches + I_BTN : in slv5; -- n4d buttons + I_BTNRST_N : in slbit; -- n4d reset button + O_LED : out slv16; -- n4d leds + O_RGBLED0 : out slv3; -- n4d rgb-led 0 + O_RGBLED1 : out slv3; -- n4d rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end sys_w11a_br_n4d; + +architecture syn of sys_w11a_br_n4d is + + signal CLK : slbit := '0'; + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal CLKS : slbit := '0'; + signal CES_MSEC : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; + signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv32 := (others=>'0'); + signal DSP_DP : slv8 := (others=>'0'); + + signal GRESET : slbit := '0'; -- general reset (from rbus) + signal CRESET : slbit := '0'; -- cpu reset (from cp) + signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) + signal ITIMER : slbit := '0'; + + signal EI_PRI : slv3 := (others=>'0'); + signal EI_VECT : slv9_2 := (others=>'0'); + signal EI_ACKM : slbit := '0'; + + signal CP_STAT : cp_stat_type := cp_stat_init; + signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; + + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv20 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + signal IB_MREQ : ib_mreq_type := ib_mreq_init; + signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; + + signal DISPREG : slv16 := (others=>'0'); + signal STATLEDS : slv8 := (others=>'0'); + signal ABCLKDIV : slv16 := (others=>'0'); + + constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx + constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx + + constant sysid_proj : slv16 := x"0201"; -- w11a + constant sysid_board : slv8 := x"06"; -- nexys4d + constant sysid_vers : slv8 := x"00"; + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV_CLK : clkdivce -- usec/msec clock divider system ---- + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------ + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clkser_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLKS, + LOCKED => open + ); + + CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport --- + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clkser_mhz, + MSECDIV => 1000) + port map ( + CLK => CLKS, + CE_USEC => open, + CE_MSEC => CES_MSEC + ); + + IOB_RS232 : bp_rs232_4line_iob -- serport iob ---------------------- + port map ( + CLK => CLKS, + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_CTS_N => I_CTS_N, + O_RTS_N => O_RTS_N + ); + + RLINK : rlink_sp2c -- rlink for serport ----------------- + generic map ( + BTOWIDTH => 7, -- 128 cycles access timeout + RTAWIDTH => 12, + SYSID => sysid_proj & sysid_board & sysid_vers, + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 12, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => sys_conf_rbmon_awidth, + RBMON_RBADDR => rbaddr_rbmon) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + CLKS => CLKS, + CES_MSEC => CES_MSEC, + ENAXON => SWI(1), + ESCFILL => '0', + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM_CPU => RB_LAM(0), + GRESET => GRESET, + CRESET => CRESET, + BRESET => BRESET, + CP_STAT => CP_STAT, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + ITIMER => ITIMER, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO, + DM_STAT_DP => DM_STAT_DP + ); + + IBDR_SYS : ibdr_maxisys -- IO system ------------------------- + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => GRESET, + BRESET => BRESET, + ITIMER => ITIMER, + CPUSUSP => CP_STAT.cpususp, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG + ); + + BRAM_CTL: pdp11_bram_memctl -- memory controller ----------------- + generic map ( + MAWIDTH => sys_conf_memctl_mawidth, + NBLOCK => sys_conf_memctl_nblock) + port map ( + CLK => CLK, + RESET => GRESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => open, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO + ); + + LED_IO : ioleds_sp1c -- hio leds from serport ------------- + port map ( + SER_MONI => SER_MONI, + IOLEDS => DSP_DP(3 downto 0) + ); + DSP_DP(7 downto 4) <= "0010"; + ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; + + HIO70 : pdp11_hio70 -- hio from sys70 -------------------- + generic map ( + LWIDTH => LED'length, + DCWIDTH => 3) + port map ( + SEL_LED => SWI(3), + SEL_DSP => SWI(5 downto 4), + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + CP_STAT => CP_STAT, + DM_STAT_DP => DM_STAT_DP, + ABCLKDIV => ABCLKDIV, + DISPREG => DISPREG, + LED => LED, + DSP_DAT => DSP_DAT + ); + + HIO : sn_humanio_rbus -- hio manager ----------------------- + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DCWIDTH => 3, + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + SMRB : if sys_conf_rbd_sysmon generate + I0: sysmonx_rbus_base + generic map ( -- use default INIT_ (Vccint=1.00) + CLK_MHZ => sys_conf_clksys_mhz, + RB_ADDR => rbaddr_sysmon) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_SYSMON, + ALM => open, + OT => open, + TEMP => open + ); + end generate SMRB; + + UARB : rbd_usracc + port map ( + CLK => CLK, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_USRACC + ); + + RB_SRES_OR : rb_sres_or_4 -- rbus or --------------------------- + port map ( + RB_SRES_1 => RB_SRES_CPU, + RB_SRES_2 => RB_SRES_HIO, + RB_SRES_3 => RB_SRES_SYSMON, + RB_SRES_4 => RB_SRES_USRACC, + RB_SRES_OR => RB_SRES + ); + + -- setup unused outputs in nexys4d + O_RGBLED0 <= (others=>'0'); + O_RGBLED1 <= (others=>not I_BTNRST_N); + +end syn; diff --git a/rtl/sys_gen/w11a/nexys4d_bram/tb/.gitignore b/rtl/sys_gen/w11a/nexys4d_bram/tb/.gitignore new file mode 100644 index 00000000..608558b3 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d_bram/tb/.gitignore @@ -0,0 +1,3 @@ +tb_w11a_br_n4 +sys_w11a_br_n4.ucf +sysmon_stim diff --git a/rtl/sys_gen/w11a/nexys4d_bram/tb/Makefile b/rtl/sys_gen/w11a/nexys4d_bram/tb/Makefile new file mode 100644 index 00000000..b79f508c --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d_bram/tb/Makefile @@ -0,0 +1,39 @@ +# $Id: Makefile 838 2017-01-04 20:57:57Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-01-04 838 1.0 Initial version +# +EXE_all = tb_w11a_br_n4d +# +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4d.mk +# +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/w11a/nexys4d_bram/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/nexys4d_bram/tb/sys_conf_sim.vhd new file mode 100644 index 00000000..c56e1a8e --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d_bram/tb/sys_conf_sim.vhd @@ -0,0 +1,94 @@ +-- $Id: sys_conf_sim.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_br_n4d (for simulation) +-- +-- Dependencies: - +-- Tool versions: viv 2016.2; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 644 1.0 Initial version (cloned from _br_n4) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- configure memory controller --------------------------------------------- + constant sys_conf_memctl_mawidth : positive := 5; + constant sys_conf_memctl_nblock : positive := 32; + + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs + constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs + constant sys_conf_dmscnt : boolean := false; + constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable + constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs + constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) + + -- configure w11 cpu core -------------------------------------------------- + -- sys_conf_mem_losize is highest 64 byte MMU block number + -- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks + constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1; + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + constant sys_conf_cache_twidth : integer := 9; -- 8kB cache + + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; diff --git a/rtl/sys_gen/w11a/nexys4d_bram/tb/tb_w11a_br_n4d.vbom b/rtl/sys_gen/w11a/nexys4d_bram/tb/tb_w11a_br_n4d.vbom new file mode 100644 index 00000000..0aac983c --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d_bram/tb/tb_w11a_br_n4d.vbom @@ -0,0 +1,9 @@ +# configure tb_nexys4d with sys_w11a_br_n4d target; +# use vhdl configure file (tb_w11a_br_n4d.vhd) to allow +# that all configurations will co-exist in work library +# configure +nexys4d_aif = ../sys_w11a_br_n4d.vbom +sys_conf = sys_conf_sim.vhd +# design +../../../../bplib/nexys4d/tb/tb_nexys4d.vbom +tb_w11a_br_n4d.vhd diff --git a/rtl/sys_gen/w11a/nexys4d_bram/tb/tb_w11a_br_n4d.vhd b/rtl/sys_gen/w11a/nexys4d_bram/tb/tb_w11a_br_n4d.vhd new file mode 100644 index 00000000..11e30aa4 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d_bram/tb/tb_w11a_br_n4d.vhd @@ -0,0 +1,40 @@ +-- $Id: tb_w11a_br_n4d.vhd 838 2017-01-04 20:57:57Z mueller $ +-- +-- Copyright 2017- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_w11a_br_n4d +-- Description: Configuration for tb_w11a_br_n4d for tb_nexys4d +-- +-- Dependencies: sys_w11a_br_n4d +-- +-- To test: sys_w11a_br_n4d +-- +-- Verified (with (#1) ../../tb/tb_rritba_pdp11core_stim.dat +-- (#2) ../../tb/tb_pdp11_core_stim.dat): +-- Date Rev Code ghdl ise Target Comment +-- 2011-11-25 295 - -.-- - - -:-- +-- +-- Revision History: +-- Date Rev Version Comment +-- 2017-01-04 838 1.0 Initial version (cloned from _br_n4) +------------------------------------------------------------------------------ + +configuration tb_w11a_br_n4d of tb_nexys4d is + + for sim + for all : nexys4d_aif + use entity work.sys_w11a_br_n4d; + end for; + end for; + +end tb_w11a_br_n4d; diff --git a/rtl/sys_gen/w11a/nexys4d_bram/tb/tb_w11a_br_n4d_ssim.vbom b/rtl/sys_gen/w11a/nexys4d_bram/tb/tb_w11a_br_n4d_ssim.vbom new file mode 100644 index 00000000..d755d8ad --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d_bram/tb/tb_w11a_br_n4d_ssim.vbom @@ -0,0 +1,8 @@ +# configure for _*sim case +# Note: this tb uses sys_w11a_n4d.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +# configure +nexys4d_aif = sys_w11a_br_n4d_ssim.vhd +# design +tb_w11a_br_n4d.vbom +@top:tb_w11a_br_n4d diff --git a/rtl/sys_gen/w11a/nexys4d_bram/tb/tbrun.yml b/rtl/sys_gen/w11a/nexys4d_bram/tb/tbrun.yml new file mode 100644 index 00000000..e2b30d42 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d_bram/tb/tbrun.yml @@ -0,0 +1,34 @@ +# $Id: tbrun.yml 838 2017-01-04 20:57:57Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2017-01-04 800 1.0 Initial version +# +- default: + mode: ${viv_modes} +# +- tag: [viv, sys_w11a, br_n4d, stim1] + test: | + tbrun_tbwrri --lsuf stim1 tb_w11a_br_n4d${ms} \ + "rlink::run_rri ../../../../w11a/tb/tb_rlink_tba_pdp11core_stim.dat" + +- tag: [viv, sys_w11a, br_n4d, mem70] + test: | + tbrun_tbwrri --lsuf mem70 --pack rw11 tb_w11a_br_n4d${ms} \ + "rw11::setup_cpu" "rw11::run_pdpcp ../../tb/tb_w11a_mem70.dat" + +- tag: [viv, sys_w11a, br_n4d, stim2] + test: | + tbrun_tbwrri --lsuf stim2 --pack rw11 tb_w11a_br_n4d${ms} \ + "rw11::setup_cpu" \ + "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat 60." + +- tag: [viv, sys_w11a, br_n4d, tbcpu] + test: | + tbrun_tbwrri --lsuf tbcpu --pack rw11 tb_w11a_br_n4d${ms} \ + "rw11::setup_cpu" "rw11::tbench @cpu_all.dat" + +- tag: [viv, sys_w11a, br_n4d, tbdev] + test: | + tbrun_tbwrri --lsuf tbdev --pack rw11 tb_w11a_br_n4d${ms} \ + "rw11::setup_cpu" "rw11::tbench @dev_all.dat" diff --git a/rtl/sys_gen/w11a/nexys4d_bram/tb/tbw.dat b/rtl/sys_gen/w11a/nexys4d_bram/tb/tbw.dat new file mode 100644 index 00000000..1d281f6f --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d_bram/tb/tbw.dat @@ -0,0 +1,7 @@ +# $Id: tbw.dat 838 2017-01-04 20:57:57Z mueller $ +# +[tb_w11a_br_n4d] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = +sysmon_stim = ../../../../bplib/sysmon/tb/sysmon_stim_n4.dat diff --git a/tools/dox/w11_cpp.Doxyfile b/tools/dox/w11_cpp.Doxyfile index adbd8377..d322bed2 100644 --- a/tools/dox/w11_cpp.Doxyfile +++ b/tools/dox/w11_cpp.Doxyfile @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - cpp" -PROJECT_NUMBER = 0.74 +PROJECT_NUMBER = 0.741 PROJECT_BRIEF = "Backend server for Rlink and w11" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/cpp diff --git a/tools/dox/w11_tcl.Doxyfile b/tools/dox/w11_tcl.Doxyfile index b607f06d..4d6318df 100644 --- a/tools/dox/w11_tcl.Doxyfile +++ b/tools/dox/w11_tcl.Doxyfile @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - tcl" -PROJECT_NUMBER = 0.74 +PROJECT_NUMBER = 0.741 PROJECT_BRIEF = "Backend server for Rlink and w11" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/tcl diff --git a/tools/dox/w11_vhd_all.Doxyfile b/tools/dox/w11_vhd_all.Doxyfile index f30b47c6..eaf7b81a 100644 --- a/tools/dox/w11_vhd_all.Doxyfile +++ b/tools/dox/w11_vhd_all.Doxyfile @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - vhd" -PROJECT_NUMBER = 0.74 +PROJECT_NUMBER = 0.741 PROJECT_BRIEF = "W11 CPU core and support modules" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/vhd @@ -108,6 +108,8 @@ EXCLUDE_SYMLINKS = NO EXCLUDE_PATTERNS = */*_ssim.vhd \ */*_fsim.vhd \ */*_tsim.vhd \ + */*_osim.vhd \ + */*_rsim.vhd \ */.svn* \ */tests/* EXCLUDE_SYMBOLS =