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- final touch-up for V0.53 minor release

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Walter F.J. Mueller 2011-04-17 12:32:28 +00:00
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commit 0f28defb8a
17 changed files with 682 additions and 46 deletions
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113
doc/INSTALL.txt
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@ -1,15 +1,22 @@
# $Id: INSTALL.txt 317 2010-07-22 19:36:56Z mueller $
# $Id: INSTALL.txt 376 2011-04-17 12:24:07Z mueller $
Guide to install and build w11a
Guide to install and build w11a systems, test benches and support software
Table of content:
1. Download
2. Install and setup the build system
3. Compile UNISIM/SIMPRIM libraries for ghdl
4. The build system
5. Building test benches
6. Building systems
1. Download
2. Setup environment variables
3. Compile UNISIM/SIMPRIM libraries for ghdl
4. Compile and install the support software
a. Compile sharable libraries
b. Setup Tcl packages
5. The build system
6. Building test benches
a. General instructions
b. Available test benches
7. Building systems
a. General instructions
b. Available systems
1. Download ---------------------------------------------------------------
@ -27,16 +34,21 @@ Guide to install and build w11a
cd <wdir>
svn co http://opencores.org/ocsvn/w11/w11/trunk
2. Install and setup the build system -------------------------------------
2. Setup environment variables --------------------------------------------
The build system for test benches and systems requires
- the definition of the environment variable RETROBASE
- that the tools binary directory is in the path
The make flow for building test benches (ghdl and ISim based) and systems
(Xilinx xst based) as well as the support software (mainly the rlink backend
server) requires
- the definition of the environment variable RETROBASE
- that the tools binary directory is in the path
- that the tools library directory is in the library path
For bash and alike use
export RETROBASE=<wdir>
export PATH=$PATH:$RETROBASE/tools/bin
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RETROBASE/tools/lib
After that building functional model based test benches will work. If you
want to also build post-xst or post-par test benches read next section.
@ -63,8 +75,48 @@ Guide to install and build w11a
If you have several WebPack versions installed, repeat for each version.
4. Compile and install the support software -------------------------------
4. The build system -------------------------------------------------------
4a. Compile sharable libraries ---------------------------------------
To build all sharable libraries
cd $RETROBASE/tools/src
make -j 4
To cleanup, e.g. before a re-build
cd $RETROBASE/tools/src
rm_dep
make realclean
4b. Setup Tcl environment --------------------------------------------
The Tcl files are organized in several packages. To create the Tcl
package files (pkgIndex.tcl)
cd $RETROBASE/tools/tcl
setup_packages
To use these packages it is convenient to make them available via the
'auto_path' mechanism. To do that add in your .tclshrc or .wishrc
lappend auto_path [file join $env(RETROBASE) tools tcl]
lappend auto_path [file join $env(RETROBASE) tools lib]
The w11 distribution contains two ready to use .tclshrc or .wishrc
files which
- include the auto_path statements above
- activate tclreadline (and thus in tclshrc an event loop)
To use them simply copy them into your home directory (or soft link them)
cd $HOME
ln -s $RETROBASE/tools/tcl/.tclshrc .
ln -s $RETROBASE/tools/tcl/.wishrc .
5. The build system -------------------------------------------------------
Simulation and synthesis tools usually need a list of the VHDL source
files, often in proper compilation order (libraries before components).
@ -92,7 +144,9 @@ Guide to install and build w11a
even more. Using the vbom's a large number of designs can be easily
maintained.
5. Building test benches --------------------------------------------------
6. Building test benches --------------------------------------------------
6a. General instructions ---------------------------------------------
To compile a test bench named <tbench> all is needed is
@ -112,7 +166,13 @@ Guide to install and build w11a
The 'make ghdl_tmp_clean' is needed to flush the ghdl work area from
the compilation remains of earlier functional model compiles.
6. Building systems -------------------------------------------------------
6b. Available test benches -------------------------------------------
See file w11a_tb_guide.txt
7. Building systems -------------------------------------------------------
7a. General instructions ---------------------------------------------
To generate a bit file for a system named <sys> all is needed is
@ -137,3 +197,26 @@ Guide to install and build w11a
make <sys>.ngc
make <sys>.ncd
7b. Available systems ------------------------------------------------
Note: Currently ready to build versions exist for
Digilent S3BOARD (-1000 FPGA version)
Digilent Nexys2 board (-1200 FPGA version)
1. rlink tester
a. for Digilent Nexys2 board
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2
make sys_tst_rlink_n2.bit
2. w11a systems
a. for Digilent S3BOARD
cd $RETROBASE/rtl/sys_gen/w11a/s3board
make sys_w11a_s3.bit
b. for Digilent Nexys2 board
cd $RETROBASE/rtl/sys_gen/w11a/nexys2
make sys_w11a_n2.bit

70
doc/README.txt
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@ -1,4 +1,4 @@
# $Id: README.txt 353 2011-01-02 21:02:48Z mueller $
# $Id: README.txt 376 2011-04-17 12:24:07Z mueller $
Release notes for w11a
@ -31,6 +31,8 @@ Release notes for w11a
rtl/bplib/s3board - for Digilent S3BOARD
rtl/ibus - ibus devices (UNIBUS peripherals)
rtl/sys_gen - top level designs
rtl/sys_gen/tst_rlink - top level designs for an rlink tester
rtl/sys_gen/tst_rlink/nexys2 - rlink tester system for Digilent Nexsy2
rtl/sys_gen/w11a - top level designs for w11a SoC
rtl/sys_gen/w11a/nexys2 - w11a SoC for Digilent Nexsy2
rtl/sys_gen/w11a/s3board - w11a SoC for Digilent S3BOARD
@ -46,13 +48,69 @@ Release notes for w11a
rtl/w11a - w11a core
tools helper programs
tools/bin - scripts and binaries
tools/dox - Doxygen documentation configuration
tools/make - make includes
tools/src - C++ sources
tools/src/librlink - basic rlink interface
tools/src/librlinktpp - C++ to tcl binding for rlink interface
tools/src/librtools - general support classes and methods
tools/src/librtcltools - support classes to implement Tcl bindings
tools/src/librutiltpp - Tcl support commands implemented in C++
tools/tcl - Tcl scripts
3. Change Log ----------------------------------------------------------------
- trunk (2011-01-02: svn rev 9(oc) 352(wfjm); untagged w11a_V0.52) +++++++++
- trunk (2011-04-17: svn rev 11(oc) 376(wfjm); untagged w11a_V0.53) ++++++++++
- Summary
- Introduced rbus protocol V3
- Introduce C++ and Tcl based backend server. A set of C++ classes provide
the basic rlink communication promitives. Additional glue classes provide
a Tcl binding. This first phase contains the basic functionality needed
to control simple test benches.
- add an 'rlink exerciser' (tst_rlink) and a top level design for a Nexys2
board (sys_tst_rlink_n2) and a test suite implemented in Tcl.
- Note: No functional changes in w11a core and I/O system at this point!
The w11a demonstrator systems are still operated with the old
backend code (pi_rri).
- New features
- new directory trees for
- C++ sources of backend (plus make and doxygen documentation support)
- tools/dox - Doxygen documentation configuration
- tools/make - make includes
- tools/src/librlink - basic rlink interface
- tools/src/librlinktpp - C++ to tcl binding for rlink interface
- tools/src/librtools - general support classes and methods
- tools/src/librtcltools - support classes to implement Tcl bindings
- tools/src/librutiltpp - Tcl support commands implemented in C++
- VHDL sources of an 'rlink exerciser'
- rtl/sys_gen/tst_rlink - top level designs for an rlink tester
- rtl/sys_gen/tst_rlink/nexys2 - rlink tester system for Nexsy2 board
- Tcl sources of 'rlink exerciser'
- tools/tcl/rlink - defs and proc's for basic rlink functions
- tools/tcl/rutil - general support procs
- tools/tcl/rbtest - defs and proc's for rbd_tester
- tools/tcl/rbbram - defs and proc's for rbd_bram
- tools/tcl/rbmoni - defs and proc's for rbd_rbmon
- tools/tcl/rbs3hio - defs and proc's for s3_humanio_rbus
- tools/tcl/tst_rlink - defs and proc's for tst_rlink
- new modules
- rtl/vlib/rbus
- rbd_bram - rbus bram test target
- rbd_eyemon - eye monitor for serport's
- rbd_rbmon - rbus monitor
- rbd_tester - rbus tester
- rbd_timer - usec precision timer
- rtl/vlib/memlib
- additional wrappers for distributed and block memories added
- tools/bin
- ti_rri: Tcl driver for rlink tests and servers (will replace pi_rri)
- trunk (2011-01-02: svn rev 9(oc) 352(wfjm); untagged w11a_V0.52) +++++++++++
- Summary
- Introduce rbus protocol V3
- reorganize rbus and rlink modules, many renames
- Changes
@ -121,10 +179,10 @@ Release notes for w11a
- added several rbus devices useful for debugging
- rbd_tester: test target, used for example in test benches
- trunk (2010-11-28: svn rev 8(oc) 341(wfjm); untagged w11a_V0.51) ++++++++
- trunk (2010-11-28: svn rev 8(oc) 341(wfjm); untagged w11a_V0.51) +++++++++++
- Summary
- Introduced ibus protocol V2
- Introduce ibus protocol V2
- Nexys2 systems use DCM
- sys_w11a_n2 now runs with 58 MHz
@ -158,7 +216,7 @@ Release notes for w11a
- Bug fixes
- rtl/vlib/Makefile.xflow: use default .opt files under rtl/vlib again.
- w11a_V0.5 (2010-07-23) ++++++++++++++++++++++++++++++++++++++++++++++++++
- w11a_V0.5 (2010-07-23) +++++++++++++++++++++++++++++++++++++++++++++++++++++
Initial release with
- w11a CPU core

41
doc/w11a_tb_guide.txt
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@ -1,4 +1,4 @@
# $Id: w11a_tb_guide.txt 352 2011-01-02 13:01:37Z mueller $
# $Id: w11a_tb_guide.txt 376 2011-04-17 12:24:07Z mueller $
Guide to running w11a test benches
@ -124,7 +124,7 @@ Guide to running w11a test benches
3. System tests benches ---------------------------------------------------
The system tests allow to verify to verify the full 11/70 SoC design.
The system tests allow to verify to verify a full system design.
In this case vhdl test bench code contains
- (simple) models of the memories used on the FPGA boards
- drivers for the rlink connection (currently just serialport)
@ -133,13 +133,34 @@ Guide to running w11a test benches
This way the whole ghdl simulation can be controlled via a di-directional
byte stream.
The rlink backend process, currently a perl script named pi_rri, can connect
either via a named pipe to a ghdl simulation, or via a serial port to a
FPGA board. This way the same tests can be executed in simulation and
on real hardware.
The rlink backend process can connect either via a named pipe to a ghdl
simulation, or via a serial port to a FPGA board. This way the same tests
can be executed in simulation and on real hardware.
Currently two backend implementations are available:
- pi_rri: written in perl (old, slow, but full functionality)
- ti_tti: written in C++ and Tcl (new, fast, but as of V0.53 only with
limited functionality; will replace pi_rri).
4. Available system tests benches -----------------------------------------
4a. rlink tester -----------------------------------------------------
The sys_tst_rlink design is a test target for validating the rlink
and rbus functionality at all levels.
- sys_tst_rlink_n2 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb
make tb_tst_rlink_n2
time ti_rri --run="tbw tb_tst_rlink_n2" --fifo --logl=3 -- \
"package require tst_rlink" "tst_rlink::setup" "tst_rlink::test_all" |\
tee tb_tst_rlink_n2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
-> 1769140.0 ns 88446: DONE
-> real 0m15.289s
4b. w11a systems -----------------------------------------------------
The stimulus file used in the w11a core test can be executed in the
full system context (both s3board and nexys2 versions) with the
following commands. Note that the cycle number printed in the DONE
@ -147,7 +168,7 @@ Guide to running w11a test benches
backend process and thus scheduling of backend vs. ghdl process
can affect the result.
- sys_w11a_s3 system test
- sys_w11a_s3 test bench
cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb
make tb_w11a_s3
@ -156,9 +177,9 @@ Guide to running w11a test benches
@../../../../w11a/tb/tb_pdp11core_stim.dat |\
tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
-> 7757655.0 ns 387873: DONE
-> real 0m49.835s user 0m50.203s sys 0m0.696s
-> real 0m49.835s user 0m50.203s sys 0m0.696s
- sys_w11a_n2 system test
- sys_w11a_n2 test bench
cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
make tb_w11a_n2
@ -167,4 +188,4 @@ Guide to running w11a test benches
@../../../../w11a/tb/tb_pdp11core_stim.dat |\
tee tb_w11a_n2_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
-> 6673237.2 ns 387035: DONE
-> real 0m56.173s user 0m56.612s sys 0m0.604s
-> real 0m56.173s user 0m56.612s sys 0m0.604s

11
tools/bin/ti_rri
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@ -1,6 +1,6 @@
#! /usr/bin/env tclsh
# -*- tcl -*-
# $Id: ti_rri 375 2011-04-02 07:56:47Z mueller $
# $Id: ti_rri 376 2011-04-17 12:24:07Z mueller $
#
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@ -15,12 +15,12 @@
#
# Revision History:
# Date Rev Version Comment
# 2011-04-02 376 1.0 Initial version
# 2011-04-17 376 1.0 Initial version
# 2011-03-19 371 0.1 First draft
#
#
# --fifo[=name,keep]
# --term[=???] ; not yet implemented...
# --term[=name,baud,break]
# --run=command
# --log=filename ; default "-"
# --logl=n ; default 2
@ -128,8 +128,11 @@ if { $opts(term) } {
set dev [lindex $nlist 0]
set baud [lindex $nlist 1]
set brk [lindex $nlist 2]
if {$dev eq ""} {set dev "/dev/ttyS0"}
if {$dev eq ""} {set dev "USB0"}
if {$baud eq ""} {set baud "115k"}
if {! [regexp -- {^/dev} $dev]} {
set dev "/dev/tty$dev"
}
set url "term:$dev?baud=$baud"
if {$brk ne ""} {append url ";break"}
rlc open $url

9
tools/src/librlinktpp/RtclRlinkConnect.cpp
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@ -1,4 +1,4 @@
// $Id: RtclRlinkConnect.cpp 375 2011-04-02 07:56:47Z mueller $
// $Id: RtclRlinkConnect.cpp 376 2011-04-17 12:24:07Z mueller $
//
// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
@ -13,13 +13,14 @@
//
// Revision History:
// Date Rev Version Comment
// 2011-04-17 376 1.0.1 M_wtlam: now correct log levels
// 2011-03-27 374 1.0 Initial version
// 2011-02-11 360 0.1 First draft
// ---------------------------------------------------------------------------
/*!
\file
\version $Id: RtclRlinkConnect.cpp 375 2011-04-02 07:56:47Z mueller $
\version $Id: RtclRlinkConnect.cpp 376 2011-04-17 12:24:07Z mueller $
\brief Implemenation of class RtclRlinkConnect.
*/
@ -512,7 +513,7 @@ int RtclRlinkConnect::M_wtlam(RtclArgs& args)
args.AppendResult(emsg.Message());
return kERR;
} else if (twait == -1.) {
if (Obj().GetLogOpts().printlevel >= 2) {
if (Obj().GetLogOpts().printlevel >= 1) {
Obj().LogFile()() << "-- wtlam to=" << RosPrintf(tout, "f", 0,3)
<< " FAIL timeout" << endl;
fErrCnt += 1;
@ -521,7 +522,7 @@ int RtclRlinkConnect::M_wtlam(RtclArgs& args)
}
}
if (Obj().GetLogOpts().printlevel >= 1) {
if (Obj().GetLogOpts().printlevel >= 3) {
Obj().LogFile()() << "-- wtlam to=" << RosPrintf(tout, "f", 0,3)
<< " T=" << RosPrintf(twait, "f", 0,3)
<< " OK" << endl;

25
tools/src/librtools/Rtools.cpp
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@ -13,6 +13,7 @@
//
// Revision History:
// Date Rev Version Comment
// 2011-04-10 376 1.0.1 add ThrowLogic(), ThrowRuntime()
// 2011-03-12 368 1.0 Initial version
// ---------------------------------------------------------------------------
@ -25,6 +26,7 @@
#include <stdexcept>
#include "Rtools.hpp"
#include "RerrMsg.hpp"
using namespace std;
using namespace Retro;
@ -54,6 +56,29 @@ std::string Rtools::Flags2String(uint32_t flags, const RflagName* fnam,
return rval;
}
//------------------------------------------+-----------------------------------
//! FIXME_docs
void Rtools::ThrowLogic(const std::string& meth,
const std::string& text, int errnum)
{
RerrMsg emsg;
emsg.Init(meth, text);
if (errnum != 0) emsg.AppendErrno(errnum);
throw logic_error(emsg.Message());
}
//------------------------------------------+-----------------------------------
//! FIXME_docs
void Rtools::ThrowRuntime(const std::string& meth,
const std::string& text, int errnum)
{
RerrMsg emsg;
emsg.Init(meth, text);
if (errnum != 0) emsg.AppendErrno(errnum);
throw runtime_error(emsg.Message());
}
//------------------------------------------+-----------------------------------
#if (defined(Retro_NoInline) || defined(Retro_Rtools_NoInline))

5
tools/src/librtools/Rtools.hpp
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@ -13,6 +13,7 @@
//
// Revision History:
// Date Rev Version Comment
// 2011-04-10 376 1.0.1 add ThrowLogic(), ThrowRuntime()
// 2011-03-12 368 1.0 Initial version
// ---------------------------------------------------------------------------
@ -39,6 +40,10 @@ namespace Retro {
namespace Rtools {
std::string Flags2String(uint32_t flags, const RflagName* fnam,
char delim='|');
void ThrowLogic(const std::string& meth,
const std::string& text, int errnum=0);
void ThrowRuntime(const std::string& meth,
const std::string& text, int errnum=0);
};
} // end namespace Retro

16
tools/tcl/.tclshrc Normal file
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@ -0,0 +1,16 @@
# -*- tcl -*-
# $Id: .tclshrc 376 2011-04-17 12:24:07Z mueller $
#
lappend auto_path [file join $env(RETROBASE) tools tcl]
lappend auto_path [file join $env(RETROBASE) tools lib]
#
if {$tcl_interactive} {
package require tclreadline
namespace eval tclreadline {
proc prompt1 {} {
set version [info tclversion]
return "tclsh$version > "
}
}
::tclreadline::Loop
}

16
tools/tcl/.wishrc Normal file
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@ -0,0 +1,16 @@
# -*- tcl -*-
# $Id: .wishrc 376 2011-04-17 12:24:07Z mueller $
#
lappend auto_path [file join $env(RETROBASE) tools tcl]
lappend auto_path [file join $env(RETROBASE) tools lib]
#
if {$tcl_interactive} {
package require tclreadline
namespace eval tclreadline {
proc prompt1 {} {
set version [info tclversion]
return "tclsh$version > "
}
}
::tclreadline::Loop
}

145
tools/tcl/rbbram/perf.tcl Normal file
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@ -0,0 +1,145 @@
# $Id: perf.tcl 376 2011-04-17 12:24:07Z mueller $
#
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation, either version 2, or at your option any later version.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for complete details.
#
# Revision History:
# Date Rev Version Comment
# 2011-04-17 376 1.0 Initial version
#
package provide rbbram 1.0
namespace eval rbbram {
#
# perf_blk: determine wblk/rblk write performance
#
proc perf_blk {{tmax 1000}} {
if {$tmax < 1} { error "-E: perf_blk: tmax argument must be >= 1" }
set amax [regget rbbram::CNTL(addr) -1]
set rval \
"nblk 1 wblk | 2 wblk | 4 wblk | 1 rblk | 2 rblk | 4 rblk "
append rval \
"\n ms/r kB/s ms/r kB/s ms/r kB/s ms/r kB/s ms/r kB/s ms/r kB/s"
foreach nblk {1 2 4 8 16 32 64 128 256} {
set wbuf0 {}
set wbuf1 {}
set wbuf2 {}
set wbuf3 {}
for {set i 0} {$i < $nblk} {incr i} {
lappend wbuf0 $i
lappend wbuf1 [expr 0x1000 + $i]
lappend wbuf2 [expr 0x2000 + $i]
lappend wbuf3 [expr 0x3000 + $i]
}
set pval {}
# single wblk
set tbeg [clock clicks -milliseconds]
set addr 0x0000
for {set i 1} {1} {incr i} {
rlc exec \
-wreg br.cntl $addr \
-wblk br.data $wbuf0
set trun [expr [clock clicks -milliseconds] - $tbeg]
if {$trun > $tmax} { break }
set addr [expr ( $addr + $nblk ) & $amax]
}
lappend pval 1 $i $trun
# double wblk
set tbeg [clock clicks -milliseconds]
set addr 0x0000
for {set i 1} {1} {incr i} {
rlc exec \
-wreg br.cntl $addr \
-wblk br.data $wbuf0 \
-wblk br.data $wbuf1
set trun [expr [clock clicks -milliseconds] - $tbeg]
if {$trun > $tmax} { break }
set addr [expr ( $addr + 2 * $nblk ) & $amax]
}
lappend pval 2 $i $trun
# quad wblk
set tbeg [clock clicks -milliseconds]
set addr 0x0000
for {set i 1} {1} {incr i} {
rlc exec \
-wreg br.cntl $addr \
-wblk br.data $wbuf0 \
-wblk br.data $wbuf1 \
-wblk br.data $wbuf2 \
-wblk br.data $wbuf3
set trun [expr [clock clicks -milliseconds] - $tbeg]
if {$trun > $tmax} { break }
set addr [expr ( $addr + 4 * $nblk ) & $amax]
}
lappend pval 4 $i $trun
# single rblk
set tbeg [clock clicks -milliseconds]
set addr 0x0000
for {set i 1} {1} {incr i} {
rlc exec \
-wreg br.cntl $addr \
-rblk br.data $nblk rbuf0
set trun [expr [clock clicks -milliseconds] - $tbeg]
if {$trun > $tmax} { break }
set addr [expr ( $addr + $nblk ) & $amax]
}
lappend pval 1 $i $trun
# double rblk
set tbeg [clock clicks -milliseconds]
set addr 0x0000
for {set i 1} {1} {incr i} {
rlc exec \
-wreg br.cntl $addr \
-rblk br.data $nblk rbuf0 \
-rblk br.data $nblk rbuf1
set trun [expr [clock clicks -milliseconds] - $tbeg]
if {$trun > $tmax} { break }
set addr [expr ( $addr + 2 * $nblk ) & $amax]
}
lappend pval 2 $i $trun
# quad rblk
set tbeg [clock clicks -milliseconds]
set addr 0x0000
for {set i 1} {1} {incr i} {
rlc exec \
-wreg br.cntl $addr \
-rblk br.data $nblk rbuf0 \
-rblk br.data $nblk rbuf1 \
-rblk br.data $nblk rbuf2 \
-rblk br.data $nblk rbuf3
set trun [expr [clock clicks -milliseconds] - $tbeg]
if {$trun > $tmax} { break }
set addr [expr ( $addr + 4 * $nblk ) & $amax]
}
lappend pval 4 $i $trun
set oline [format "\n%4d" $nblk]
foreach {nr i trun} $pval {
set ms [expr double($trun) / double($nr*$i)]
set kb [expr double(2*$nr*$i*$nblk) / double($trun)]
append oline [format " %5.1f %5.1f" $ms $kb]
}
append rval $oline
}
return $rval
}
}

4
tools/tcl/rbbram/util.tcl
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@ -1,4 +1,4 @@
# $Id: util.tcl 375 2011-04-02 07:56:47Z mueller $
# $Id: util.tcl 376 2011-04-17 12:24:07Z mueller $
#
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@ -13,7 +13,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2011-03-19 372 0.1 Initial version
# 2011-03-19 372 1.0 Initial version
#
package provide rbbram 1.0

101
tools/tcl/rbemon/test_rbtest_sim.tcl Normal file
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@ -0,0 +1,101 @@
# $Id: test_rbtest_sim.tcl 376 2011-04-17 12:24:07Z mueller $
#
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation, either version 2, or at your option any later version.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for complete details.
#
# Revision History:
# Date Rev Version Comment
# 2011-04-17 376 1.0 Initial version
#
package provide rbemon 1.0
package require rbtest
namespace eval rbemon {
#
# some simple tests against rbd_tester registers in sim mode
#
proc test_rbtest_sim {} {
set esdval 0x00
set esdmsk [regbld rlink::STAT {stat -1}]
#
set errcnt 0
rlc errcnt -clear
#
rlc log "rbemon::test_rbtest_sim - start"
#
#-------------------------------------------------------------------------
rlc log " test 1: write to te.data, verify that transitions seen"
set bsize 25
#
rlc exec -wreg em.rdiv 0 -estat $esdval $esdmsk
rlc log " - data - 01 10 va00 va01 va02 va03 va04 va05 va06 va07 va08 va09"
#
# Note: avoid chars which will be escpaped, like 10000000, for this test
#
foreach {pat ena01 ena10 exp} \
[list [bvi b 00000000] 1 1 [list 0 0 0 0 0 0 0 0 1 0]\
[bvi b 00000001] 1 1 [list 1 1 0 0 0 0 0 0 1 0]\
[bvi b 00000010] 1 1 [list 0 1 1 0 0 0 0 0 1 0]\
[bvi b 00000100] 1 1 [list 0 0 1 1 0 0 0 0 1 0]\
[bvi b 00001000] 1 1 [list 0 0 0 1 1 0 0 0 1 0]\
[bvi b 00010000] 1 1 [list 0 0 0 0 1 1 0 0 1 0]\
[bvi b 00100000] 1 1 [list 0 0 0 0 0 1 1 0 1 0]\
[bvi b 01000000] 1 1 [list 0 0 0 0 0 0 1 1 1 0]\
[bvi b 11111111] 1 1 [list 1 0 0 0 0 0 0 0 0 0]\
[bvi b 11111110] 1 1 [list 0 1 0 0 0 0 0 0 0 0]\
[bvi b 01010101] 1 1 [list 1 1 1 1 1 1 1 1 1 0]\
[bvi b 00110011] 1 1 [list 1 0 1 0 1 0 1 0 1 0]\
[bvi b 00000001] 0 1 [list 0 1 0 0 0 0 0 0 0 0]\
[bvi b 00000001] 1 0 [list 1 0 0 0 0 0 0 0 1 0]\
[bvi b 01010101] 0 1 [list 0 1 0 1 0 1 0 1 0 0]\
[bvi b 01010101] 1 0 [list 1 0 1 0 1 0 1 0 1 0]\
] {
set bdata {}
for {set i 0} {$i < $bsize} {incr i} {
lappend bdata [expr ( $pat << 8 ) | $pat]
}
rbemon::clear
rbemon::start $ena01 $ena10
rlc exec -wblk te.data $bdata -estat $esdval $esdmsk
rbemon::stop
set edata [rbemon::read 10]
set oline " "
set pafa "OK"
append oline [pbvi b8 $pat]
append oline [format " %d %d" $ena01 $ena10]
for {set i 0} {$i < 10} {incr i} {
set ebin [lindex $edata $i]
set eexp [lindex $exp $i]
append oline [format " %3d" $ebin]
if {($eexp != 0 && $ebin < 2 * $bsize) ||
($eexp == 0 && $ebin >= 2 * $bsize)} {
append oline "#"
set pafa "FAIL"
incr errcnt
} else {
append oline "!"
}
}
append oline " "
append oline $pafa
rlc log $oline
}
#
#-------------------------------------------------------------------------
incr errcnt [rlc errcnt -clear]
return $errcnt
}
}

23
tools/tcl/rbemon/util.tcl
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@ -1,4 +1,4 @@
# $Id: util.tcl 375 2011-04-02 07:56:47Z mueller $
# $Id: util.tcl 376 2011-04-17 12:24:07Z mueller $
#
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@ -13,6 +13,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2011-04-17 376 1.0.1 add proc read
# 2011-04-02 375 1.0 Initial version
#
@ -81,5 +82,25 @@ namespace eval rbemon {
proc stop {} {
rlc exec -wreg em.cntl 0x0000
}
#
# read: read eyemon data
#
proc read {{nval 512}} {
set addr 0
set rval {}
while {$nval > 0} {
set nblk [expr $nval << 1]
if {$nblk > 256} {set nblk 256}
rlc exec \
-wreg em.addr $addr \
-rblk em.data $nblk rawdat
foreach {dl dh} $rawdat {
lappend rval [expr ( $dh << 16 ) | $dl]
}
incr addr $nblk
set nval [expr $nval - ( $nblk >> 1 ) ]
}
return $rval
}
}

55
tools/tcl/rbs3hio/util.tcl
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@ -1,4 +1,4 @@
# $Id: util.tcl 375 2011-04-02 07:56:47Z mueller $
# $Id: util.tcl 376 2011-04-17 12:24:07Z mueller $
#
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@ -13,6 +13,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2011-04-17 376 1.0.1 print: show also switch values; add proc disptest
# 2011-03-27 374 1.0 Initial version
# 2011-03-19 372 0.1 First draft
#
@ -28,6 +29,7 @@ namespace eval rbs3hio {
#
regdsc CNTL {daten 11} {dpen 10} {leden 9} {swien 8} {btn 3 4}
regdsc LED {dp 11 4} {led 7 8}
#
# setup: amap definitions for s3_humanio_rbus
#
@ -37,12 +39,14 @@ namespace eval rbs3hio {
rlc amap -insert hi.led [expr $base + 0x02]
rlc amap -insert hi.dsp [expr $base + 0x03]
}
#
# init: reset s3_humanio_rbus (clear all enables)
#
proc init {} {
rlc exec -wreg hi.cntl 0x0000
}
#
# print: show status
#
@ -56,7 +60,8 @@ namespace eval rbs3hio {
set led [regget rbs3hio::LED(led) $r_led]
set dp [regget rbs3hio::LED(dp) $r_led]
append rval " cntl: [regtxt rbs3hio::CNTL $r_cntl]"
append rval "\n leds: [pbvi b8 $led]"
append rval "\n swi: [pbvi b8 $r_swi]"
append rval "\n led: [pbvi b8 $led]"
set dspval ""
for {set i 3} {$i >= 0} {incr i -1} {
set digval [expr ( $r_dsp >> ( 4 * $i ) ) & 0x0f]
@ -67,4 +72,50 @@ namespace eval rbs3hio {
append rval "\n disp: [pbvi b16 $r_dsp] - [pbvi b4 $dp] -> \"$dspval\""
return $rval
}
#
# disptest: blink through the leds
#
proc disptest {} {
rlc exec -rreg hi.cntl r_cntl
set swien [regget rbs3hio::CNTL(swien) $r_cntl]
rlc exec -wreg hi.cntl [regbld rbs3hio::CNTL daten dpen leden \
[list swien $swien] ]
foreach ledval {0x0f 0xf0 0xff} {
set dpval [expr $ledval & 0x0f]
set hiled [regbld rbs3hio::LED [list led $ledval] [list dp $dpval]]
rlc exec \
-wreg hi.led $hiled \
-wreg hi.dsp 0xffff
after 250
}
for {set i 0} {$i <= 0xf} {incr i} {
set ledval [expr ( $i << 4 ) | $i]
set dspval [expr ( $ledval << 8 ) | $ledval]
set hiled [regbld rbs3hio::LED [list led $ledval] [list dp $i]]
rlc exec \
-wreg hi.led $hiled \
-wreg hi.dsp $dspval
after 250
}
set ledval 0x01
for {set i 0} {$i < 32} {incr i} {
set dpval [expr $ledval & 0x0f]
set hiled [regbld rbs3hio::LED [list led $ledval] [list dp $dpval]]
rlc exec \
-wreg hi.led $hiled \
-wreg hi.dsp $i
after 50
set ledval [expr $ledval << 1]
if {$ledval & 0x100} {set ledval [expr ( $ledval & 0xff ) | 0x01]}
}
rlc exec \
-wreg hi.cntl $r_cntl \
-wreg hi.led 0x0 \
-wreg hi.dsp 0x0
}
}

56
tools/tcl/tst_rlink/perf.tcl Normal file
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@ -0,0 +1,56 @@
# $Id: perf.tcl 376 2011-04-17 12:24:07Z mueller $
#
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation, either version 2, or at your option any later version.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for complete details.
#
# Revision History:
# Date Rev Version Comment
# 2011-04-17 376 1.0 Initial version
#
package provide tst_rlink 1.0
namespace eval tst_rlink {
#
# perf_wtlam: determine wtlam latency using timer.0
#
proc perf_wtlam {{tmax 1000}} {
if {$tmax < 1} { error "-E: perf_wtlam: tmax argument must be >= 1" }
set rval "delay latency"
rlc exec -init 0xff [regbld rlink::INIT anena]
for {set dly 250} {$dly <= 10000} {incr dly 250} {
rlc exec \
-wreg timer.0 0 \
-wreg timer.1 0
rlc exec -attn
set tbeg [clock clicks -milliseconds]
rlc exec -wreg timer.0 $dly
for {set i 1} {1} {incr i} {
rlc wtlam 1.
rlc exec \
-attn \
-wreg timer.0 $dly
set trun [expr [clock clicks -milliseconds] - $tbeg]
if {$trun > $tmax} { break }
}
set ms [expr double($trun) / double($i)]
append rval [format "\n%5d %6.2f" $dly $ms]
}
rlc exec -init 0xff [regbld rlink::INIT {anena 0}]
return $rval
}
}

6
tools/tcl/tst_rlink/test_all.tcl
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@ -1,4 +1,4 @@
# $Id: test_all.tcl 375 2011-04-02 07:56:47Z mueller $
# $Id: test_all.tcl 376 2011-04-17 12:24:07Z mueller $
#
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@ -13,6 +13,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2011-04-17 376 1.0.1 add rbemon::test_rbtest_sim (if in sum mode)
# 2011-04-02 375 1.0 Initial version
# 2011-03-26 373 0.1 First draft
#
@ -33,6 +34,9 @@ namespace eval tst_rlink {
incr errcnt [rbmoni::test_regs]
incr errcnt [rbmoni::test_rbtest]
incr errcnt [rbemon::test_regs]
if {[rlink::issim]} {
incr errcnt [rbemon::test_rbtest_sim]
}
puts "tst_rlink::test_all errcnt = $errcnt --> [rutil::errcnt2txt $errcnt]"

32
tools/tcl/tst_rlink/util.tcl
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@ -1,4 +1,4 @@
# $Id: util.tcl 375 2011-04-02 07:56:47Z mueller $
# $Id: util.tcl 376 2011-04-17 12:24:07Z mueller $
#
# Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@ -13,6 +13,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2011-04-17 376 1.0.1 add proc scan_baud
# 2011-04-02 375 1.0 Initial version
# 2011-03-19 372 0.1 First draft
#
@ -53,4 +54,33 @@ namespace eval tst_rlink {
rbemon::init
rlink::init; # re-reset rlink
}
#
# scan_baud: scan through baud rates, show uart clkdiv value
#
proc scan_baud {{bmax 500000}} {
if {! [rlink::isopen]} {error "-E: rlink port not open"}
set rlpath [rlc open]
regexp -- {^term:(.*)\?} $rlpath dummy rldev
if {$rldev eq ""} {error "-E: rlink not connected to a term: device"}
set rval " baud hi.dsp clkdiv sysclk"
set blist {9600 19200 38400 57600 115200 230400 460800
500000 921600 1000000 2000000 3000000}
foreach baud $blist {
if {$baud > $bmax} { break }
rlc close
rlc open "term:$rldev?baud=${baud};break"
rlc exec -rreg hi.dsp hidsp
set mhz [expr double($baud*$hidsp) / 1.e6]
append rval [format "\n%7d 0x%4.4x %6d %6.2f" \
$baud $hidsp [expr $hidsp + 1] $mhz]
}
rlc close
if {! [regexp -- {;break} $rlpath]} {append rlpath ";break"}
rlc open "${rlpath}"
return $rval
}
}