From 1627b34e3e9101415f747a05fc0f2a18df9f43ed Mon Sep 17 00:00:00 2001 From: wfjm Date: Fri, 27 Jan 2023 11:39:28 +0100 Subject: [PATCH] tcode: use .mcall and mlib --- tools/asm-11/lib/halt_checks.mac | 60 ------- tools/asm-11/lib/push_pop.mac | 24 --- tools/asm-11/lib/tcode_std_start.mac | 7 +- tools/asm-11/lib/vec_cpucatch.mac | 40 ++--- tools/asm-11/lib/vec_cpucatch_reset.mac | 40 ++--- tools/asm-11/lib/vec_devcatch.mac | 70 +++----- tools/asm-11/lib/vec_devcatch_reset.mac | 64 +++---- tools/asm-11/mlib/vecclr.mac | 8 + tools/asm-11/mlib/vecini.mac | 9 + tools/asm-11/mlib/vecset.mac | 11 ++ tools/bin/asm-11 | 4 +- tools/tcode/cpu_badinst_nofpp.mac | 24 +-- tools/tcode/cpu_basics.mac | 43 ++--- tools/tcode/cpu_details.mac | 150 +++++++--------- tools/tcode/cpu_eis.mac | 7 +- tools/tcode/cpu_mmu.mac | 219 ++++++++++-------------- tools/tcode/cpu_selftest.mac | 20 ++- 17 files changed, 298 insertions(+), 502 deletions(-) delete mode 100644 tools/asm-11/lib/halt_checks.mac delete mode 100644 tools/asm-11/lib/push_pop.mac create mode 100644 tools/asm-11/mlib/vecclr.mac create mode 100644 tools/asm-11/mlib/vecini.mac create mode 100644 tools/asm-11/mlib/vecset.mac diff --git a/tools/asm-11/lib/halt_checks.mac b/tools/asm-11/lib/halt_checks.mac deleted file mode 100644 index 56d206c7..00000000 --- a/tools/asm-11/lib/halt_checks.mac +++ /dev/null @@ -1,60 +0,0 @@ -; $Id: halt_checks.mac 1322 2022-11-28 19:31:57Z mueller $ -; SPDX-License-Identifier: GPL-3.0-or-later -; Copyright 2022- by Walter F.J. Mueller -; -; Macros for checking a location and halt on error -; -; cmp on eq - .macro hcmpeq,src,dst - cmp src,dst - beq .+4 - halt - .endm -; cmpb on eq - .macro hcmbeq,src,dst - cmpb src,dst - beq .+4 - halt - .endm -; bit on ne - .macro hbitne,src,dst - bit src,dst - bne .+4 - halt - .endm -; bit on eq - .macro hbiteq,src,dst - bit src,dst - beq .+4 - halt - .endm -; tst on eq - .macro htsteq,src - tst src - beq .+4 - halt - .endm -; tstb on eq - .macro htsbeq,src - tstb src - beq .+4 - halt - .endm -; tst on ne - .macro htstne,src - tst src - bne .+4 - halt - .endm -; tstb on ne - .macro htsbne,src - tstb src - bne .+4 - halt - .endm -; tst on ge - .macro htstge,src - tst src - bge .+4 - halt - .endm diff --git a/tools/asm-11/lib/push_pop.mac b/tools/asm-11/lib/push_pop.mac deleted file mode 100644 index 567dcb98..00000000 --- a/tools/asm-11/lib/push_pop.mac +++ /dev/null @@ -1,24 +0,0 @@ -; $Id: push_pop.mac 1325 2022-12-07 11:52:36Z mueller $ -; SPDX-License-Identifier: GPL-3.0-or-later -; Copyright 2022- by Walter F.J. Mueller -; -; Macros for stack handling: push/pop and pushb/popb -; - .macro push,src - mov src,-(sp) - .endm - .macro pushb,src - movb src,-(sp) - .endm -; - .macro push2,src1,src2 - mov src1,-(sp) - mov src2,-(sp) - .endm -; - .macro pop,dst - mov (sp)+,dst - .endm - .macro popb,dst - movb (sp)+,dst - .endm diff --git a/tools/asm-11/lib/tcode_std_start.mac b/tools/asm-11/lib/tcode_std_start.mac index c7e3b02d..12f04e58 100644 --- a/tools/asm-11/lib/tcode_std_start.mac +++ b/tools/asm-11/lib/tcode_std_start.mac @@ -1,6 +1,6 @@ -; $Id: tcode_std_start.mac 1283 2022-08-22 10:07:58Z mueller $ +; $Id: tcode_std_start.mac 1357 2023-01-26 19:24:10Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later -; Copyright 2015-2022 by Walter F.J. Mueller +; Copyright 2015-2023 by Walter F.J. Mueller ; ; Default tcode startup code ; @@ -18,9 +18,6 @@ ; .include |lib/vec_cpucatch.mac| .include |lib/vec_devcatch.mac| -; - .include |lib/halt_checks.mac| - .include |lib/push_pop.mac| ; sy.w1a = 010000/256. ; sysid prefix for w11a systems sy.sih = 110000/256. ; sysid prefix for SimH environment diff --git a/tools/asm-11/lib/vec_cpucatch.mac b/tools/asm-11/lib/vec_cpucatch.mac index 6a76abfe..0cbad18c 100644 --- a/tools/asm-11/lib/vec_cpucatch.mac +++ b/tools/asm-11/lib/vec_cpucatch.mac @@ -1,29 +1,19 @@ -; $Id: vec_cpucatch.mac 1184 2019-07-10 20:39:44Z mueller $ +; $Id: vec_cpucatch.mac 1357 2023-01-26 19:24:10Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later -; Copyright 2013- by Walter F.J. Mueller +; Copyright 2013-2023 by Walter F.J. Mueller ; ; vector catcher for basic cpu interrupts ; - . = 000004 -v..iit: .word v..iit+2 ; vec 4 - .word 0 -v..rit: .word v..rit+2 ; vec 10 - .word 0 -v..bpt: .word v..bpt+2 ; vec 14 (T bit; BPT) - .word 0 -v..iot: .word v..iot+2 ; vec 20 (IOT) - .word 0 -v..pwr: .word v..pwr+2 ; vec 24 (Power fail, not used) - .word 0 -v..emt: .word v..emt+2 ; vec 30 (EMT) - .word 0 -v..trp: .word v..trp+2 ; vec 34 (TRAP) - .word 0 - - . = 000240 -v..pir: .word v..pir+2 ; vec 240 (PIRQ) - .word 0 -v..fpp: .word v..fpp+2 ; vec 244 (FPP) - .word 0 -v..mmu: .word v..mmu+2 ; vec 250 (MMU) - .word 0 + .mcall vecini +; + vecini 004,v..iit ; vec 4 + vecini 010,v..rit ; vec 10 + vecini 014,v..bpt ; vec 14 (T bit; BPT) + vecini 020,v..iot ; vec 20 (IOT) + vecini 024,v..pwr ; vec 24 (Power fail) + vecini 030,v..emt ; vec 30 (EMT) + vecini 034,v..trp ; vec 34 (TRAP) + vecini 240,v..pir ; vec 240 (PIRQ) + vecini 244,v..fpp ; vec 244 (FPP) + vecini 250,v..mmu ; vec 250 (MMU) +; diff --git a/tools/asm-11/lib/vec_cpucatch_reset.mac b/tools/asm-11/lib/vec_cpucatch_reset.mac index 4434960f..3f6738d7 100644 --- a/tools/asm-11/lib/vec_cpucatch_reset.mac +++ b/tools/asm-11/lib/vec_cpucatch_reset.mac @@ -1,29 +1,19 @@ -; $Id: vec_cpucatch_reset.mac 1184 2019-07-10 20:39:44Z mueller $ +; $Id: vec_cpucatch_reset.mac 1357 2023-01-26 19:24:10Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later -; Copyright 2015- by Walter F.J. Mueller +; Copyright 2015-2023 by Walter F.J. Mueller ; ; re-write vector catcher for basic cpu interrupts -; - mov #v..iit+2,v..iit ; vec 4 - clr v..iit+2 - mov #v..rit+2,v..rit ; vec 10 - clr v..rit+2 -; - mov #v..bpt+2,v..bpt ; vec 14 (T bit; BPT) - clr v..bpt+2 - mov #v..iot+2,v..iot ; vec 20 (IOT) - clr v..iot+2 - mov #v..pwr+2,v..pwr ; vec 24 (Power fail, not used) - clr v..pwr+2 - mov #v..emt+2,v..emt ; vec 30 (EMT) - clr v..emt+2 - mov #v..trp+2,v..trp ; vec 34 (TRAP) - clr v..trp+2 -; - mov #v..pir+2,v..pir ; vec 240 (PIRQ) - clr v..pir+2 - mov #v..fpp+2,v..fpp ; vec 244 (FPP) - clr v..fpp+2 - mov #v..mmu+2,v..mmu ; vec 250 (MMU) - clr v..mmu+2 +; + .mcall vecclr + + vecclr v..iit ; vec 4 + vecclr v..rit ; vec 10 + vecclr v..bpt ; vec 14 (T bit; BPT) + vecclr v..iot ; vec 20 (IOT) + vecclr v..pwr ; vec 24 (Power fail) + vecclr v..emt ; vec 30 (EMT) + vecclr v..trp ; vec 34 (TRAP) + vecclr v..pir ; vec 240 (PIRQ) + vecclr v..fpp ; vec 244 (FPP) + vecclr v..mmu ; vec 250 (MMU) ; diff --git a/tools/asm-11/lib/vec_devcatch.mac b/tools/asm-11/lib/vec_devcatch.mac index ce8e3025..61c93b9d 100644 --- a/tools/asm-11/lib/vec_devcatch.mac +++ b/tools/asm-11/lib/vec_devcatch.mac @@ -1,6 +1,6 @@ -; $Id: vec_devcatch.mac 1184 2019-07-10 20:39:44Z mueller $ +; $Id: vec_devcatch.mac 1357 2023-01-26 19:24:10Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later -; Copyright 2015- by Walter F.J. Mueller +; Copyright 2015-2023 by Walter F.J. Mueller ; ; vector catcher for device interrupts (subset used by w11) ; @@ -25,58 +25,28 @@ ; 160100 310? 5 9 9 3 3/1 DZ11-RX ; 314? 5 8 8 ^ DZ11-TX ; - . = 000060 -v..tti: .word v..tti+2 ; vec 60 (DL11-RX 1st) - .word 0 -v..tto: .word v..tto+2 ; vec 64 (DL11-TX 1st) - .word 0 + .mcall vecini ; -v..ptr: .word v..ptr+2 ; vec 70 (PC11/PTR) - .word 0 -v..ptp: .word v..ptp+2 ; vec 74 (PC11/PTP) - .word 0 -; - . = 000100 -v..kwl: .word v..kwl+2 ; vec 100 (KW11-L) - .word 0 -v..kwp: .word v..kwp+2 ; vec 104 (KW11-P) - .word 0 -; - . = 000120 -v..xu: .word v..xu+2 ; vec 120 (DEUNA) - .word 0 -; - . = 000160 -v..rl: .word v..rl+2 ; vec 160 (RL11) - .word 0 + vecini 060,v..tti ; vec 60 (DL11-RX 1st) + vecini 064,v..tto ; vec 64 (DL11-TX 1st) + vecini 070,v..ptr ; vec 70 (PC11/PTR) + vecini 074,v..ptp ; vec 74 (PC11/PTP) + vecini 100,v..kwl ; vec 100 (KW11-L) + vecini 104,v..kwp ; vec 104 (KW11-P) + vecini 120,v..xu ; vec 120 (DEUNA) + vecini 160,v..rl ; vec 160 (RL11) ; ; Note on vector 200 ; MAINDECs use 200 also as default start address. This vector catcher ; might therefore be overwritten later by startup code of test programs. ; - . = 000200 -v..lp: .word v..lp+2 ; vec 200 (LP11) - .word 0 -; - . = 000220 -v..rk: .word v..rk+2 ; vec 220 (RK11) - .word 0 -v..tm: .word v..tm+2 ; vec 224 (TM11) - .word 0 -; - . = 000254 -v..rp: .word v..rp+2 ; vec 254 (RHRP) - .word 0 -v..iis: .word v..iis+2 ; vec 260 (IIST) - .word 0 -; - . = 000300 -v..d2r: .word v..d2r+2 ; vec 300 (DL11-RX 2nd) - .word 0 -v..d2t: .word v..d2t+2 ; vec 304 (DL11-TX 2nd) - .word 0 -v..dzr: .word v..dzr+2 ; vec 310 (DZ11-RX) - .word 0 -v..dzt: .word v..dzt+2 ; vec 314 (DZ11-TX) - .word 0 + vecini 200,v..lp ; vec 200 (LP11) + vecini 220,v..rk ; vec 220 (RK11) + vecini 224,v..tm ; vec 224 (TM11) + vecini 254,v..rp ; vec 254 (RHRP) + vecini 260,v..iis ; vec 260 (IIST) + vecini 300,v..d2r ; vec 300 (DL11-RX 2nd) + vecini 304,v..d2t ; vec 304 (DL11-TX 2nd) + vecini 310,v..dzr ; vec 310 (DZ11-RX) + vecini 314,v..dzt ; vec 314 (DZ11-TX) ; diff --git a/tools/asm-11/lib/vec_devcatch_reset.mac b/tools/asm-11/lib/vec_devcatch_reset.mac index 5b8aa376..34c39a26 100644 --- a/tools/asm-11/lib/vec_devcatch_reset.mac +++ b/tools/asm-11/lib/vec_devcatch_reset.mac @@ -1,50 +1,26 @@ -; $Id: vec_devcatch_reset.mac 1184 2019-07-10 20:39:44Z mueller $ +; $Id: vec_devcatch_reset.mac 1357 2023-01-26 19:24:10Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later -; Copyright 2015-2019 by Walter F.J. Mueller +; Copyright 2015-2023 by Walter F.J. Mueller ; ; re-write vector catcher for device interrupts (subset used by w11) -; - mov #v..tti+2,v..tti ; vec 60 (DL11-RX 1st) - clr v..tti+2 - mov #v..tto+2,v..tto ; vec 64 (DL11-TX 1st) - clr v..tto+2 ; - mov #v..ptr+2,v..ptr ; vec 70 (PC11/PTR) - clr v..ptr+2 - mov #v..ptp+2,v..ptp ; vec 74 (PC11/PTP) - clr v..ptp+2 + .mcall vecclr ; - mov #v..kwl+2,v..kwl ; vec 100 (KW11-L) - clr v..kwl+2 - mov #v..kwp+2,v..kwp ; vec 104 (KW11-P) - clr v..kwp+2 -; - mov #v..xu+2,v..xu ; vec 120 (DEUNA) - clr v..xu+2 -; - mov #v..rl+2,v..rl ; vec 160 (RL11) - clr v..rl+2 -; - mov #v..lp+2,v..lp ; vec 200 (LP11) - clr v..lp+2 -; - mov #v..rk+2,v..rk ; vec 220 (RK11) - clr v..rk+2 - mov #v..tm+2,v..tm ; vec 224 (TM11) - clr v..tm+2 -; - mov #v..rp+2,v..rp ; vec 254 (RHRP) - clr v..rp+2 - mov #v..iis+2,v..iis ; vec 260 (IIST) - clr v..iis+2 -; - mov #v..d2r+2,v..d2r ; vec 300 (DL11-RX 2nd) - clr v..d2r+2 - mov #v..d2t+2,v..d2t ; vec 304 (DL11-TX 2nd) - clr v..d2t+2 -; - mov #v..dzr+2,v..dzr ; vec 310 (DZ11-RX) - clr v..dzr+2 - mov #v..dzt+2,v..dzt ; vec 314 (DZ11-TX) - clr v..dzt+2 + vecclr v..tti ; vec 60 (DL11-RX 1st) + vecclr v..tto ; vec 64 (DL11-TX 1st) + vecclr v..ptr ; vec 70 (PC11/PTR) + vecclr v..ptp ; vec 74 (PC11/PTP) + vecclr v..kwl ; vec 100 (KW11-L) + vecclr v..kwp ; vec 104 (KW11-P) + vecclr v..xu ; vec 120 (DEUNA) + vecclr v..rl ; vec 160 (RL11) + vecclr v..lp ; vec 200 (LP11) + vecclr v..rk ; vec 220 (RK11) + vecclr v..tm ; vec 224 (TM11) + vecclr v..rp ; vec 254 (RHRP) + vecclr v..iis ; vec 260 (IIST) + vecclr v..d2r ; vec 300 (DL11-RX 2nd) + vecclr v..d2t ; vec 304 (DL11-TX 2nd) + vecclr v..dzr ; vec 310 (DZ11-RX) + vecclr v..dzt ; vec 314 (DZ11-TX) ; diff --git a/tools/asm-11/mlib/vecclr.mac b/tools/asm-11/mlib/vecclr.mac new file mode 100644 index 00000000..7e87a4a6 --- /dev/null +++ b/tools/asm-11/mlib/vecclr.mac @@ -0,0 +1,8 @@ +; $Id: vecclr.mac 1357 2023-01-26 19:24:10Z mueller $ +; SPDX-License-Identifier: GPL-3.0-or-later +; Copyright 2023- by Walter F.J. Mueller +; + .macro vecclr,name + mov #name+2,@#name + clr @#name+2 + .endm diff --git a/tools/asm-11/mlib/vecini.mac b/tools/asm-11/mlib/vecini.mac new file mode 100644 index 00000000..0e228a3e --- /dev/null +++ b/tools/asm-11/mlib/vecini.mac @@ -0,0 +1,9 @@ +; $Id: vecini.mac 1357 2023-01-26 19:24:10Z mueller $ +; SPDX-License-Identifier: GPL-3.0-or-later +; Copyright 2023- by Walter F.J. Mueller +; + .macro vecini,addr,name + . = addr +name: .word name+2 + .word 0 + .endm diff --git a/tools/asm-11/mlib/vecset.mac b/tools/asm-11/mlib/vecset.mac new file mode 100644 index 00000000..7432aa2b --- /dev/null +++ b/tools/asm-11/mlib/vecset.mac @@ -0,0 +1,11 @@ +; $Id: vecset.mac 1357 2023-01-26 19:24:10Z mueller $ +; SPDX-License-Identifier: GPL-3.0-or-later +; Copyright 2023- by Walter F.J. Mueller +; + .macro vecset,name,hdl,pri + mov #hdl,@#name + .if b,pri + clr @#name+2 + .iff + mov #pri,@#name+2 + .endm diff --git a/tools/bin/asm-11 b/tools/bin/asm-11 index 6186696b..1d4a205d 100755 --- a/tools/bin/asm-11 +++ b/tools/bin/asm-11 @@ -1,10 +1,11 @@ #!/usr/bin/perl -w -# $Id: asm-11 1356 2023-01-26 15:10:23Z mueller $ +# $Id: asm-11 1357 2023-01-26 19:24:10Z mueller $ # SPDX-License-Identifier: GPL-3.0-or-later # Copyright 2013-2023 by Walter F.J. Mueller # # Revision History: # Date Rev Version Comment +# 2023-01-26 1357 1.2.3 skip redundant loads in .mcall # 2023-01-25 1355 1.2.2 rewrite macro args handling; add .narg,.nchr,.ntype # 2023-01-24 1354 1.2.1 add .error,.print,.mcall,.mdelete; add -L; add ...top # 2023-01-22 1353 1.2 add .if, .if(f|t|tf), .endc, .rept, .endr, .mexit @@ -509,6 +510,7 @@ sub pass1_line { # handle .mcall ------------------------------------------ if (defined $$rl{oper} && $$rl{oper} eq '.mcall') { foreach my $mname (@{$$rl{mcall}}) { + next if exists $mst{$mname}; # quit if already loaded my $fname; foreach (@{$opts{L}}) { if (-r "$_/${mname}.mac") { diff --git a/tools/tcode/cpu_badinst_nofpp.mac b/tools/tcode/cpu_badinst_nofpp.mac index 64cdfc8f..7d645a56 100644 --- a/tools/tcode/cpu_badinst_nofpp.mac +++ b/tools/tcode/cpu_badinst_nofpp.mac @@ -1,15 +1,19 @@ -; $Id: cpu_badinst_nofpp.mac 1262 2022-07-25 09:44:55Z mueller $ +; $Id: cpu_badinst_nofpp.mac 1358 2023-01-27 10:37:36Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later -; Copyright 2022- by Walter F.J. Mueller +; Copyright 2022-2023 by Walter F.J. Mueller ; ; Revision History: ; Date Rev Version Comment +; 2023-01-27 1358 1.1 use .mcall and mlib ; 2022-07-24 1262 1.0 Initial version ; 2022-07-16 1257 0.1 First draft ; ; Test that invalid instructions trap (including fpp) ; .include |lib/tcode_std_base.mac| +; + .mcall hcmpeq + .mcall vecset,vecclr ; ; Section A: verify that invalid instructions trap =========================== jmp ta0101 @@ -25,7 +29,7 @@ trpcnt: .word 0 ; jmp to register ; Note: 44,45,70 and J11 trap to 10, all other trap to 4 ; -ta0101: mov #vh.exp,v..rit ; setup rit handler +ta0101: vecset v..rit,vh.exp ; setup rit handler clr trpcnt ; jsr pc,r0 @@ -37,7 +41,7 @@ ta0101: mov #vh.exp,v..rit ; setup rit handler jmp r5 halt ; - mov #v..rit+2,v..rit ; restore rit catcher + vecclr v..rit ; restore rit catcher hcmpeq trpcnt,#4. ; 9999$: iot ; end of test A1.1 @@ -46,7 +50,7 @@ ta0101: mov #vh.exp,v..rit ; setup rit handler ; check that the following instructions trap to 4 (iit) ; halt in supervisor and user mode ; -ta0102: mov #vh.exp,v..iit ; setup iit handler +ta0102: vecset v..iit,vh.exp ; setup iit handler clr trpcnt ; mov #cp.cms,cp.psw ; supervisor mode @@ -57,7 +61,7 @@ ta0102: mov #vh.exp,v..iit ; setup iit handler nop ; skipped by vh.exp clr cp.psw ; back to kernel mode ; - mov #v..iit+2,v..iit ; restore iit catcher + vecclr v..iit ; restore iit catcher hcmpeq trpcnt,#2. ; 9999$: iot ; end of test A1.2 @@ -65,7 +69,7 @@ ta0102: mov #vh.exp,v..iit ; setup iit handler ; Test A1.3 -- reserved (except fpp) +++++++++++++++++++++++++++++++++ ; check that reserved instruction code trap to 10 (rit) ; -ta0103: mov #vh.exp,v..rit ; setup iit handler +ta0103: vecset v..rit,vh.exp ; setup iit handler clr trpcnt ; .word 000007 ; 000007 {MFPT in 11/44, J11} @@ -127,7 +131,7 @@ ta0103: mov #vh.exp,v..rit ; setup iit handler .word 107777 halt ; - mov #v..rit+2,v..rit ; restore iit catcher + vecclr v..rit ; restore iit catcher hcmpeq trpcnt,#29. ; 9999$: iot ; end of test A1.3 @@ -135,7 +139,7 @@ ta0103: mov #vh.exp,v..rit ; setup iit handler ; Test A1.4 -- reserved (nofpp) ++++++++++++++++++++++++++++++++++++++ ; check that fpp instructions code trap to 10 (rit) ; -ta0104: mov #vh.exp,v..rit ; setup iit handler +ta0104: vecset v..rit,vh.exp ; setup iit handler clr trpcnt ; .word 170000 ; 170000-177777 @@ -143,7 +147,7 @@ ta0104: mov #vh.exp,v..rit ; setup iit handler .word 177777 halt ; - mov #v..rit+2,v..rit ; restore iit catcher + vecclr v..rit ; restore iit catcher hcmpeq trpcnt,#2. ; 9999$: iot ; end of test A1.4 diff --git a/tools/tcode/cpu_basics.mac b/tools/tcode/cpu_basics.mac index 5b9116f4..fc2611c1 100644 --- a/tools/tcode/cpu_basics.mac +++ b/tools/tcode/cpu_basics.mac @@ -1,9 +1,10 @@ -; $Id: cpu_basics.mac 1351 2023-01-13 08:38:27Z mueller $ +; $Id: cpu_basics.mac 1358 2023-01-27 10:37:36Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later ; Copyright 2015-2023 by Walter F.J. Mueller ; ; Revision History: ; Date Rev Version Comment +; 2023-01-27 1358 1.1 use .mcall and mlib ; 2023-01-07 1347 1.0 Initial version ; 2015-08-30 710 0.1 First draft ; @@ -17,6 +18,10 @@ ; .include |lib/tcode_std_base.mac| .include |lib/defs_kwl.mac| +; + .mcall push + .mcall hcmpeq,hcmbeq,htsteq,htsbeq,hbiteq,hbitne + .mcall vecset,vecclr ; ; Section A: ccops + flow control bxx, sob, jmp, jsr, rts, mark ============== ; A1 ccop + bbx @@ -3152,8 +3157,7 @@ tf0202: mov #cp.psw,r0 ; tf0203: cmpb systyp,#sy.sih ; skip on SimH (no SPL 11/70 semantics) beq 9999$ - mov #100$,v..pir ; set up PIRQ handler - mov #cp.pr7,v..pir+2 + vecset v..pir,100$,cp.pr7 ; set up PIRQ handler spl 7 movb #bit01,cp.pir+1 ; request PIRQ 1 spl 0 ; SPL enforces execution of next inst @@ -3162,8 +3166,7 @@ tf0203: cmpb systyp,#sy.sih ; skip on SimH (no SPL 11/70 semantics) ; 100$: halt ; -200$: mov #v..pir+2,v..pir - clr v..pir+2 +200$: vecclr v..pir ; reset PIRQ handler 9999$: iot ; end of test F2.3 ; @@ -3178,37 +3181,31 @@ tf0203: cmpb systyp,#sy.sih ; skip on SimH (no SPL 11/70 semantics) ; ; Test F3.1 trap instructions: bpt,iot,emt,trap ++++++++++++++++++++++ ; -tf0301: mov #v..iot+2,v..iot ; block iot handler - clr v..iot+2 +tf0301: vecclr v..iot ; IOT handler to catcher clr cp.psw ; clear psw mov #3000$,r5 ; setup expect buffer ; ; test bpt ; - mov #2000$,v..bpt ; setup bpt handler: nzvc = 0011 - mov #cp.pr7!cp00vc,v..bpt+2 + vecset v..bpt,2000$,cp.pr7!cp00vc ; setup bpt handler: nzvc = 0011 spl 1 ccc sec bpt ; bpt with pr1 + nzvc = 0001 - mov #v..bpt+2,v..bpt ; block bpt again - clr v..bpt+2 + vecclr v..bpt ; block bpt again ; ; test iot ; - mov #2000$,v..iot ; setup bpt handler: nzvc = 0100 - mov #cp.pr7!cp0z00,v..iot+2 + vecset v..iot,2000$,cp.pr7!cp0z00 ; setup bpt handler: nzvc = 0100 spl 2 ccc sev iot ; iot with pr2 + nzvc = 0010 - mov #v..iot+2,v..iot ; block iot again - clr v..iot+2 + vecclr v..iot ; block iot again ; ; test emt 123 ; - mov #2000$,v..emt ; setup emt handler: nzvc = 0101 - mov #cp.pr7!cp0z0c,v..emt+2 + vecset v..emt,2000$,cp.pr7!cp0z0c ; setup emt handler: nzvc = 0101 spl 3 ccc sez @@ -3218,13 +3215,11 @@ tf0301: mov #v..iot+2,v..iot ; block iot handler ccc sez emt 234 ; emt with pr4 + nzvc = 0100 - mov #v..emt+2,v..emt ; block emt again - clr v..emt+2 + vecclr v..emt ; block emt again ; ; test trap 321 ; - mov #2000$,v..trp ; setup trap handler: nzvc = 0110 - mov #cp.pr7!cp0zv0,v..trp+2 + vecset v..trp,2000$,cp.pr7!cp0zv0 ; setup trap handler: nzvc = 0110 spl 5 ccc sen @@ -3234,14 +3229,12 @@ tf0301: mov #v..iot+2,v..iot ; block iot handler ccc sen trap 135 ; trap with pr6 + nzvc = 1000 - mov #v..trp+2,v..trp ; block trap again - clr v..trp+2 + vecclr v..trp ; block trap again ; ; end of trap instruction tests ; cmp r5,#3001$ - mov #vh.iot,v..iot ; restore iot handler - mov #cp.pr7,v..iot+2 + vecset v..iot,vh.iot,cp.pr7 ; restore iot handler jmp 9999$ ; ; vector handler (used for all trap type instructions) diff --git a/tools/tcode/cpu_details.mac b/tools/tcode/cpu_details.mac index d713759b..d9d47a0d 100644 --- a/tools/tcode/cpu_details.mac +++ b/tools/tcode/cpu_details.mac @@ -1,9 +1,10 @@ -; $Id: cpu_details.mac 1351 2023-01-13 08:38:27Z mueller $ +; $Id: cpu_details.mac 1358 2023-01-27 10:37:36Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later ; Copyright 2022-2023 by Walter F.J. Mueller ; ; Revision History: ; Date Rev Version Comment +; 2023-01-27 1358 1.1 use .mcall and mlib ; 2023-01-11 1349 1.0 Initial version ; 2022-07-18 1259 0.1 First draft ; @@ -14,6 +15,10 @@ ; .include |lib/tcode_std_base.mac| .include |lib/defs_mmu.mac| +; + .mcall push,pop,push2 + .mcall hcmpeq,htsteq,htstne,htstge,hbiteq,hbitne + .mcall vecset,vecclr ; ; Preface: set up MMU for kernel mode (for some tests) ======================= ; @@ -131,8 +136,7 @@ pi.n06=6*042 ; lsb for pir 6 next pi.n07=7*042 ; lsb for pir 7 next ; -ta0101: mov #1000$,v..pir ; set up handler - mov #cp.pr7,v..pir+2 ; which runs at pr7 +ta0101: vecset v..pir,1000$,cp.pr7 ; set up PIRQ handler at pr7 mov #cp.pir,r3 ; ptr to PIRQ mov #cp.psw,r4 ; ptr to PSW mov #1200$,r5 ; ptr to check data @@ -148,8 +152,7 @@ ta0101: mov #1000$,v..pir ; set up handler spl 0 nop ; allow interrupts to happen htsteq (r3) ; PIRQ should clear now - mov #v..pir+2,v..pir; restore pirq vector catcher - clr v..pir+2 + vecclr v..pir ; restore pirq vector catcher jmp 9999$ ; ; PIRQ interrupt handler @@ -203,8 +206,7 @@ ta0101: mov #1000$,v..pir ; set up handler ; write of the PIRQ register ; ta0102: spl 0 ; ensure execution at PR0 - mov #1000$,v..pir ; set up handler - mov #cp.pr7,v..pir+2 ; which runs at pr7 + vecset v..pir,1000$,cp.pr7 ; set up PIRQ handler at pr7 mov #pi.r03,cp.pir ; request PIRQ 3 halt ; halt if not taken immediatly ; @@ -212,8 +214,7 @@ ta0102: spl 0 ; ensure execution at PR0 mov #1100$,(sp) ; continue rti ; -1100$: mov #v..pir+2,v..pir; restore pirq vector catcher - clr v..pir+2 +1100$: vecclr v..pir ; restore pirq vector catcher ; 9999$: iot ; end of test A1.2 ; @@ -222,8 +223,7 @@ ta0102: spl 0 ; ensure execution at PR0 ; ; setup for all A2.* tests mov #cp.err,r0 ; ptr tp CPUERR - mov #vhugen,v..iit ; set iit handler - clr v..iit+2 ; pr0 kernel + vecset v..iit,vhugen ; set iit handler at pr0 ; ; Test A2.1 -- CPUERR cp.hlt +++++++++++++++++++++++++++++++++++++++++ ; Test cp.hlt: halt in non-kernel mode @@ -444,7 +444,7 @@ ta0210: cmpb systyp,#sy.sih ; SimH uses J11 semantics ; ; ----------------------------------------------- ; end of A2.* tests, restore iit handler - mov v..iit+2,v..iit ; restore iit handler + vecclr v..iit ; restore iit catcher ; ; Test A3: STKLIM + stack traps and aborts ++++++++++++++++++++++++++++++++++ ; This sub-section verifies operation of STKLIM register, @@ -507,8 +507,7 @@ ta0302: ; 10$: mov #1200$,r0 ; ptr to value list mov #<1210$-1200$>/2,r1 ; # of values - mov #1000$,v..iit ; set up iit handler - mov #cp.pr3,v..iit+2 ; use pr3 as handler signature + vecset v..iit,1000$,cp.pr3 ; set up iit handler, pr3 as signature ; 100$: spl 6 ; use pr6 as code signature mov (r0)+,r5 ; get value @@ -554,8 +553,7 @@ ta0302: ; 1020$: clr cp.slr ; STKLIM to default mov #stack,sp ; SP to default - mov #v..iit+2,v..iit ; v..iit to catcher - clr v..iit+2 + vecclr v..iit ; v..iit to catcher spl 0 ; prio to default br 2000$ ; @@ -571,7 +569,7 @@ ta0302: ; mov #2300$,r0 ; ptr to values mov #<2310$-2300$>/2,r1 ; # of values - mov #2200$,v..iit ; set up iit handler + vecset v..iit,2200$ ; set up iit handler mov #1400,cp.slr ; set yellow limit to 1776 ; 2100$: mov (r0)+,sp ; set SP to test value @@ -583,8 +581,7 @@ ta0302: ; clr cp.slr ; STKLIM to default mov #stack,sp ; SP to default - mov #v..iit+2,v..iit ; v..iit to catcher - clr v..iit+2 + vecclr v..iit ; v..iit to catcher br 3000$ ; 2300$: .word 001400 ; probe 1376 (possible yellow mirror) @@ -601,17 +598,17 @@ ta0302: ; mov #1400,cp.slr ; set STKLIM mov #1300,sp ; SP deep in red zone - mov #3100$,v..iit ; set up iit handler + vecset v..iit,3100$ ; set up iit handler clr -(sp) ; expect red abort halt 3100$: htsteq sp ; check SP=0, on emergency stack - mov #3200$,v..iit ; set up iit handler + vecset v..iit,3200$ ; set up iit handler clr -(sp) ; expect red abort again halt 3200$: htsteq sp ; check SP=0 because of PSW protection clr cp.slr ; STKLIM to default mov #stack,sp ; SP to default - mov #v..iit+2,v..iit ; v..iit to catcher + vecclr v..iit ; v..iit to catcher ; 9999$: iot ; end of test A3.2 ; @@ -635,12 +632,9 @@ ta0303: tstb systyp ; skip if not on w11 ; ; part 1: test instructions that should trap ------------------------- ; - mov #1000$,v..iit ; set up iit handler - clr v..iit+2 - mov #1100$,v..emt ; set up emt handler - clr v..emt+2 - mov #1200$,v..trp ; set up trap handler - clr v..trp+2 + vecset v..iit,1000$ ; set up iit handler + vecset v..emt,1100$ ; set up emt handler + vecset v..trp,1200$ ; set up trap handler clr r2 ; clear trap counter ; ; dstw mode 1,2,4,6 @@ -674,9 +668,9 @@ ta0303: tstb systyp ; skip if not on w11 1300$: rts pc ; dummy routine ; 1500$: hcmpeq #15.,r2 ; all traps taken ? - mov #v..iit+2,v..iit ; v..iit to catcher - mov #v..emt+2,v..emt ; v..emt to catcher - mov #v..trp+2,v..trp ; v..trp to catcher + vecclr v..iit ; v..iit to catcher + vecclr v..emt ; v..emt to catcher + vecclr v..trp ; v..trp to catcher ; ; part 2: test instructions that should not trap --------------------- ; @@ -711,10 +705,8 @@ ta0303: tstb systyp ; skip if not on w11 ; The iit handler must therefore execute at PR7 to lockout interrupts. ; When the iit handler returns, the pir hander will execute. ; -3000$: mov #3100$,v..iit ; set up iit handler - mov #cp.pr7,v..iit+2 ; lockout interrupts ! - mov #3200$,v..pir ; set up pir handler - mov #cp.pr7,v..pir+2 ; lockout interrupts +3000$: vecset v..iit,3100$,cp.pr7 ; set up iit handler, lockout interrupts + vecset v..pir,3200$,cp.pr7 ; set up pir handler, lockout interrupts mov #stack,sp ; SP to default (STKLIM still 1400) clr r2 ; clear trap counter mov #cp.pir,r3 ; ptr to cp.pir @@ -747,10 +739,8 @@ ta0303: tstb systyp ; skip if not on w11 .word 177777,1. ; iit marker + pr1 pirq ; 3900$: hcmpeq #3.,r2 ; all traps taken ? - mov #v..iit+2,v..iit ; v..iit to catcher - clr v..iit+2 - mov #v..pir+2,v..pir ; v..pir to catcher - clr v..pir+2 + vecclr v..iit ; v..iit to catcher + vecclr v..pir ; v..pir to catcher ; ; final cleanup clr cp.slr ; STKLIM to default @@ -764,9 +754,7 @@ ta0303: tstb systyp ; skip if not on w11 ; Verifies that vector push after trap instructions and interrupts abort ; Abort on 1st and 2nd push is tested. ; -ta0304: - mov #1000$,v..iit ; set up iit handler - mov #cp.pr7,v..iit+2 ; lockout interrupts ! +ta0304: vecset v..iit,1000$,cp.pr7 ; set up iit handler, lockout interrupts mov #1400,cp.slr ; yellow <=1776 and red <= 1736 clr @#1736 ; ensure top red word zero clr cp.err ; clear CPUERR @@ -821,8 +809,7 @@ ta0304: jmp (r5) ; continue ; 9000$: clr cp.slr ; STKLIM to default - mov #v..iit+2,v..iit ; v..iit to catcher - clr v..iit+2 + vecclr v..iit ; v..iit to catcher mov #stack,sp ; SP to default spl 0 ; back to PR0 ; @@ -839,10 +826,8 @@ ta0304: ta0305: cmpb systyp,#sy.sih ; skip in SimH (different stklim logic) beq 9999$ ; - mov #200$,v..iit ; set up iit handler - mov #cp.pr5!cp0z0c,v..iit+2 ; use PR5+0Z0C as signature iit - mov #110$,v..trp ; set up TRAP handler (catcher) - mov #cp.pr6!cpn0v0,v..trp+2 ; use PR6+N0V0 as signature trp + vecset v..iit,200$,cp.pr5!cp0z0c ; set up iit handler, PR5+0Z0C as sig + vecset v..trp,110$,cp.pr6!cpn0v0 ; set up TRAP handler,PR6+N0V0 as sig mov #1400,cp.slr ; yellow <=1776 and red <= 1736 ; ; on abort 2nd push ------------------------------ @@ -885,10 +870,8 @@ ta0305: cmpb systyp,#sy.sih ; skip in SimH (different stklim logic) hcmpeq 2(sp),#cp.pr2!cp0z00 ; PS: should be code signature ; ; restore - mov #v..iit+2,v..iit ; v..iit to catcher - clr v..iit+2 - mov #v..trp+2,v..trp ; v..trp to catcher - clr v..trp+2 + vecclr v..iit ; v..iit to catcher + vecclr v..trp ; v..trp to catcher mov #stack,sp ; SP to default spl 0 ; back to PR0 ; @@ -1164,7 +1147,7 @@ ta0403: ; ; part 1: tbit after RTI --------------------------------------------- ; - mov #200$,v..bpt + vecset v..bpt,200$ rtijmp #cp.t,#100$ ; PS: tbit; PC 100$ 100$: nop ; should not execute halt @@ -1173,11 +1156,11 @@ ta0403: 200$: hcmpeq #stack-4,sp ; check single frame hcmpeq #100$,(sp) ; check saved PC before nop mov #stack,sp ; restore - mov #v..bpt+2,v..bpt + vecclr v..bpt ; ; part 2: tbit after RTT --------------------------------------------- ; -2000$: mov #2200$,v..bpt +2000$: vecset v..bpt,2200$ rttjmp #cp.t,#2100$ ; PS: tbit; PC 2100$ 2100$: nop ; should execute halt @@ -1186,20 +1169,16 @@ ta0403: 2200$: hcmpeq #stack-4,sp ; check single frame hcmpeq #2100$+2,(sp) ; check saved PC after nop mov #stack,sp ; restore - mov #v..bpt+2,v..bpt + vecclr v..bpt ; 9999$: iot ; end of test A4.3 ; ; Test A4.4 -- tbit trace tests ++++++++++++++++++++++++++++++++++++++ ; -ta0404: mov #vhtbpt,v..bpt ; BPT handler - mov #cp.pr7,v..bpt+2 ; run at PR7 (lockout PIRQ) - mov #vhtemt,v..emt ; EMT handler - clr v..emt+2 ; run at PR0 (no PIRQ competion) - mov #vhtpir,v..pir ; PIRQ handler - mov #cp.pr7,v..pir+2 ; run at PR7 (lockout PIRQ) - mov #vhttrp,v..trp ; TRAP handler - clr v..trp+2 ; run at PR0 (no PIRQ competion) +ta0404: vecset v..bpt,vhtbpt,cp.pr7 ; BPT handler, PR7 (lockout PIRQ) + vecset v..emt,vhtemt ; EMT handler, PR0 (no PIRQ competion) + vecset v..pir,vhtpir,cp.pr7 ; PIRQ handler,PR7 (lockout PIRQ) + vecset v..trp,vhttrp ; TRAP handler,PR0 (no PIRQ competion) ; ; part 0: traced TRAP that clears tbit ------------------------------ ; Checks that a traced TRAP which loads a PS with tbit=0 does not trap. @@ -1432,7 +1411,7 @@ ta0404: mov #vhtbpt,v..bpt ; BPT handler ; Checks that an aborted instruction doesnt tbit trap. ; Uses a bus timeout as abort reason (access to 160000). ; -7000$: mov #7300$,v..iit ; setup local vector 4 handler +7000$: vecset v..iit,7300$ ; setup local vector 4 handler mov #7200$,r5 rttjmp #cp.t,#7100$ ; enable tbit ; @@ -1448,7 +1427,7 @@ ta0404: mov #vhtbpt,v..bpt ; BPT handler htinit 7200$,1. ; expect 1 item htitem #014,#7110$ ; bpt after 1st clr ; - mov #v..iit+2,v..iit ; restore + vecclr v..iit ; restore ; ; part 8: traced RTI that clears tbit ------------------------------- ; Checks that a traced RTI loading a PS with tbit=0 does not trap. @@ -1478,8 +1457,7 @@ ta0404: mov #vhtbpt,v..bpt ; BPT handler 9000$: cmpb systyp,#sy.sih ; skip on SimH (RTI traps, EMT not) beq 10000$ ; - mov #9100$,v..emt - mov #cp.t,v..emt+2 + vecset v..emt,9100$,cp.t ; set emt handler with T bit mov #9200$,r5 ; emt 100 @@ -1504,8 +1482,7 @@ ta0404: mov #vhtbpt,v..bpt ; BPT handler 10000$: cmpb systyp,#sy.sih ; skip on SimH (RTI traps, PIRQ not) beq 9999$ ; - mov #10100$,v..pir - mov #cp.pr7!cp.t,v..pir+2 + vecset v..pir,10100$,cp.pr7!cp.t ; set PIRQ handler, PR7 + T bit mov #10200$,r5 ; movb #bit01,cp.pir+1 ; request PIRQ 1 @@ -1524,14 +1501,10 @@ ta0404: mov #vhtbpt,v..bpt ; BPT handler ; ; restore ------------------------------------------------------------ ; - mov #v..bpt+2,v..bpt ; restore v..bpt to catcher - clr v..bpt+2 - mov #v..emt+2,v..emt ; restore v..emt to catcher - clr v..emt+2 - mov #v..pir+2,v..pir ; restore v..pir to catcher - clr v..pir+2 - mov #v..trp+2,v..trp ; restore v..trp to catcher - clr v..trp+2 + vecclr v..bpt ; restore v..bpt to catcher + vecclr v..emt ; restore v..emt to catcher + vecclr v..pir ; restore v..pir to catcher + vecclr v..trp ; restore v..trp to catcher ; 9999$: iot ; end of test A4.4 ; @@ -1866,7 +1839,7 @@ tb0301: mov #123,r0 ; src for MOV 4000$: cmpb systyp,#sy.sih ; skip on SimH beq 9999$ clr r5 ; abort counter - mov #4100$,v..iit ; set up iit handler + vecset v..iit,4100$ ; set up iit handler mov #1,r1 ; odd dst for (r1),(r1)+,-(r1),0(r1) mov #300$,r2 ; odd dst for @(r2)+,@-(r2),@0(r2) scc @@ -1887,7 +1860,7 @@ tb0301: mov #123,r0 ; src for MOV rti ; continue (possible here!) ; 4200$: hcmpeq #7.,r5 ; check that all 7 mov got address error - mov #v..iit+2,v..iit ; restore + vecclr v..iit ; restore ; 9999$: iot ; end of test B3.1 ; @@ -1900,7 +1873,7 @@ tb0302: cmpb systyp,#sy.sih ; skip on SimH beq 9999$ ; mov #1,r1 ; use odd address - mov #1000$,v..iit ; set up iit handler + vecset v..iit,1000$ ; set up iit handler clr -(sp) ; push value scc mtpi (r1) ; will fail @@ -1908,7 +1881,7 @@ tb0302: cmpb systyp,#sy.sih ; skip on SimH ; 1000$: hcmpeq #cpnzvc,2(sp) ; check PS cc untouched mov #stack,sp ; restore - mov #v..iit+2,v..iit ; restore + vecclr v..iit ; restore ; 9999$: iot ; end of test B3.2 ; @@ -1921,7 +1894,7 @@ tb0303: cmpb systyp,#sy.sih ; skip on SimH ; inc sp ; set up odd stack mov #100$,r1 ; set up read address (a valid one) - mov #1000$,v..iit ; set up iit handler + vecset v..iit,1000$ ; set up iit handler scc mfpi (r1) ; will fail halt @@ -1931,7 +1904,7 @@ tb0303: cmpb systyp,#sy.sih ; skip on SimH 1000$: hcmpeq #cpnzvc,2(sp) ; check PS cc untouched htsteq sp ; check that fatal stack error seen mov #stack,sp ; restore - mov #v..iit+2,v..iit ; restore + vecclr v..iit ; restore ; 9999$: iot ; end of test B3.3 ; @@ -1980,7 +1953,7 @@ tb0304: clr r0 ; src for INC ; part 2: check cc for INC after abort for all memory modes ; 2000$: clr r5 - mov #2100$,v..iit ; set up iit handler + vecset v..iit,2100$ ; set up iit handler mov #1,r1 ; odd dst for (r1),(r1)+,-(r1),0(r1) mov #300$,r2 ; odd dst for @(r2)+,@-(r2),@0(r2) scc @@ -2001,7 +1974,7 @@ tb0304: clr r0 ; src for INC rti ; continue (possible here!) ; 2200$: hcmpeq #7.,r5 ; check that all 7 inc got address error - mov #v..iit+2,v..iit ; restore + vecclr v..iit ; restore ; 9999$: iot ; end of test B3.4 ; @@ -2133,8 +2106,7 @@ tc0102: mov #1000$,r4 ; Test C1.3 -- Registers accessible via 177700-1777717 +++++++++++++++ ; CPU access to 177700-177717 (regs) timesout {70,J11} or not {05,10} ; -tc0103: mov #vhugen,v..iit ; set iit handler - clr v..iit+2 ; pr0 kernel +tc0103: vecset v..iit,vhugen ; set iit handler, pr0 kernel ; mov #1000$,vhustp ; continuation address tst @#177700 ; should fail @@ -2144,7 +2116,7 @@ tc0103: mov #vhugen,v..iit ; set iit handler tst @#177716 ; should fail halt ; -1100$: mov v..iit+2,v..iit ; restore iit handler +1100$: vecclr v..iit ; restore iit handler ; 9999$: iot ; end of test C1.3 ; diff --git a/tools/tcode/cpu_eis.mac b/tools/tcode/cpu_eis.mac index 53e416b3..1a3df8d8 100644 --- a/tools/tcode/cpu_eis.mac +++ b/tools/tcode/cpu_eis.mac @@ -1,15 +1,18 @@ -; $Id: cpu_eis.mac 1329 2022-12-11 17:28:28Z mueller $ +; $Id: cpu_eis.mac 1358 2023-01-27 10:37:36Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later -; Copyright 2022- by Walter F.J. Mueller +; Copyright 2022-2023 by Walter F.J. Mueller ; ; Revision History: ; Date Rev Version Comment +; 2023-01-27 1358 1.1 use .mcall and mlib ; 2022-07-25 1263 1.0 Initial version ; 2022-07-11 1251 0.1 First draft ; ; Test CPU EIS instructions ; .include |lib/tcode_std_base.mac| +; + .mcall hcmpeq ; ; Section A: div ============================================================= ; This section verifies diff --git a/tools/tcode/cpu_mmu.mac b/tools/tcode/cpu_mmu.mac index 9336a443..33b103ed 100644 --- a/tools/tcode/cpu_mmu.mac +++ b/tools/tcode/cpu_mmu.mac @@ -1,9 +1,10 @@ -; $Id: cpu_mmu.mac 1347 2023-01-07 12:48:58Z mueller $ +; $Id: cpu_mmu.mac 1358 2023-01-27 10:37:36Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later ; Copyright 2022-2023 by Walter F.J. Mueller ; ; Revision History: ; Date Rev Version Comment +; 2023-01-27 1358 1.1 use .mcall and mlib ; 2023-01-05 1346 1.0 Initial version ; 2022-07-24 1262 0.1 First draft ; @@ -27,6 +28,11 @@ ; .include |lib/tcode_std_base.mac| .include |lib/defs_mmu.mac| +; + .mcall push,pop + .mcall hcmpeq,hcmbeq,htsteq,htstge,hbiteq,hbitne + .mcall vecset,vecclr +; ; some useful definitions uipdr0 = uipdr+ 0 uipar0 = uipar+ 0 @@ -409,9 +415,7 @@ tb0202: mov #kipar6,r0 ; ptr to kipar6 ; tb0301: ; set up emt handler - mov #vhuemt,v..emt - clr v..emt+2 ; pr0 kernel -; enable mmu + vecset v..emt,vhuemt ; set up emt handler, pr0 kernel clr mmr3 ; no d dspace, no 22bit mov #m0.ena,mmr0 ; enable mmu ;! MMU 18 ; @@ -468,8 +472,7 @@ tb0301: clr sipar0 ; reset ; mmu off ;! MMU off - mov #v..emt+2,v..emt ; restore emt catcher - clr v..emt+2 + vecclr v..emt ; restore emt catcher ; 9999$: iot ; end of test B3.1 ; @@ -484,10 +487,7 @@ tb0301: ; 1 000 110 110 ddd ddd NZ0- MTPD ; tb0302: -; set up emt handler - mov #vhuemt,v..emt - clr v..emt+2 ; pr0 kernel -; enable mmu + vecset v..emt,vhuemt ; set up emt handler, pr0 kernel mov #m3.dum,mmr3 ; user d dspace, no 22bit mov #m0.ena,mmr0 ; enable mmu ;! MMU 18 ; @@ -649,8 +649,7 @@ tb0302: ; reset ; mmu off ;! MMU off clr cp.psw ; crop pm in psw - mov #v..emt+2,v..emt ; restore emt catcher - clr v..emt+2 + vecclr v..emt ; restore emt catcher jmp 9999$ ; ; test data for m*pd tests (C=0 for T and C=1 for F) @@ -673,10 +672,7 @@ tb0302: ; Runs code vc4 with D space enabled, code in page 0 and data in page 1. ; tb0303: -; set up emt handler - mov #vhuemt,v..emt - clr v..emt+2 ; pr0 kernel -; enable mmu + vecset v..emt,vhuemt ; set up emt handler, pr0 kernel mov #m3.dum,mmr3 ; user d dspace, no 22bit mov #m0.ena,mmr0 ; enable mmu ;! MMU 18 ; set up data @@ -707,8 +703,7 @@ tb0303: ; reset ; mmu off ;! MMU off clr cp.psw ; crop pm in psw - mov #v..emt+2,v..emt ; restore emt catcher - clr v..emt+2 + vecclr v..emt ; restore emt catcher ; 9999$: iot ; end of test B3.3 ; @@ -724,8 +719,7 @@ tb0303: ; tb0401: clr mmr3 ; no d dspace, no 22bit mov #m0.ena,mmr0 ; enable mmu ;! MMU 18 -; setup catcher - mov #1000$,v..mmu + vecset v..mmu,1000$ ; set up local mmu handler ; try to run a code in mode 10 mov #^b1010000000000000,-(sp) ; next psw; cm=pm=10 mov #p6base+200,-(sp) ; start address @@ -744,8 +738,7 @@ tb0401: clr mmr3 ; no d dspace, no 22bit hcmpeq mmr2,#p6base+200 ; check mmr2 ; reset ;! MMU off - mov #v..mmu+2,v..mmu ; restore mmu catcher - clr v..mmu+2 + vecclr v..mmu ; restore mmu catcher ; 9999$: iot ; end of test B4.1 ; @@ -889,8 +882,7 @@ tc0101: mov #1000$,r1 ; ptr to abort bit table ; Test C2.1 -- test unary/binary instructions ++++++++++++++++++++++++ ; Excercise access to kernel page 6 and inspect mmr0 and mmr1 ; -tc0201: mov #vhmmua,v..mmu - clr v..mmu+2 ; pr0 kernel +tc0201: vecset v..mmu,vhmmua ; set up mmu handler, pr0 kernel reset mov #m0.ena,mmr0 ; enable mmu ;! MMU 18 ; @@ -1125,8 +1117,7 @@ tc0201: mov #vhmmua,v..mmu 9000$: reset ; mmu off ;! MMU off clr cp.psw mov #<127.*md.plf>!md.arw,kipdr6 ; restore kernel mapping - mov #v..mmu+2,v..mmu ; restore mmu catcher - clr v..mmu+2 + vecclr v..mmu ; restore mmu catcher 9999$: iot ; end of test C2.1 ; ; Test C2.2 -- test MFPI,MFPD,MTPI,MFPD dst aborts +++++++++++++++++++ @@ -1136,8 +1127,7 @@ tc0201: mov #vhmmua,v..mmu ; udpdr1 1 click up acr=2 read ; udpdr2 1 click dn acr=6 w/r ; -tc0202: mov #vhmmua,v..mmu - clr v..mmu+2 ; pr0 kernel +tc0202: vecset v..mmu,vhmmua ; set up mmu handler, pr0 kernel reset mov #cp.pmu,cp.psw ; pm to user mov #m3.dum,mmr3 ; enable user D space @@ -1284,8 +1274,7 @@ tc0202: mov #vhmmua,v..mmu clr uipdr0 ; reset user mode pdr clr udpdr1 clr udpdr2 - mov #v..mmu+2,v..mmu ; restore mmu catcher - clr v..mmu+2 + vecclr v..mmu ; restore mmu catcher 9999$: iot ; end of test C2.2 ; ; Test C2.3 -- test aborts in implied push/pop +++++++++++++++++++++++ @@ -1294,14 +1283,16 @@ tc0202: mov #vhmmua,v..mmu ; from the kernel stack used in MMU 250 vector handling ; Environment: psw cm=supervisor;pm=user ; si.0 as 1-to-1 (easy switch between kernel and supervisor) +; si.1 as 1-to-1 (easy switch between kernel and supervisor) ; si.7 as 1-to-1 (psw access) ; ui.0 as 1-to-1 (for read access) ; -tc0203: mov #vhmmua,v..mmu - clr v..mmu+2 ; pr0 kernel +tc0203: vecset v..mmu,vhmmua ; set up mmu handler, pr0 kernel reset mov kipdr0,sipdr0 ; super 0: 1-to-1 clr sipar0 + mov kipdr1,sipdr1 ; super 1: 1-to-1 + mov kipar1,sipar1 mov kipdr7,sipdr7 ; super 7: 1-to-1 mov kipar7,sipar7 mov kipdr0,uipdr0 ; user 0: 1-to-1 @@ -1316,12 +1307,12 @@ tc0203: mov #vhmmua,v..mmu ; 1100$: mfpi (r2) ; 1200$: mfpd (r2) ; -1000$: mov #020040,sp ; set SP into 1st click page 1, non-resident +1000$: mov #p2base+40,sp ; set SP into 1st click page 2, non-resident mov #1010$,vhvmmu mov #1001$,r2 jsr pc,(r2) ; will fail 1001$: halt -1010$: .word m0.anr!m0.pms!<1*m0.pno>!m0.ena ; mmr0 +1010$: .word m0.anr!m0.pms!<2*m0.pno>!m0.ena ; mmr0 ; dddddrrrdddddrrr .word ^b0000000011110110 ; mmr1 -2,6 ; @@ -1329,14 +1320,14 @@ tc0203: mov #vhmmua,v..mmu mov #swsyid,r2 ; any valid address mfpi (r2) ; will fail halt -1110$: .word m0.anr!m0.pms!<1*m0.pno>!m0.ena ; mmr0 +1110$: .word m0.anr!m0.pms!<2*m0.pno>!m0.ena ; mmr0 ; dddddrrrdddddrrr .word ^b0000000011110110 ; mmr1 -2,6 ; 1200$: mov #1210$,vhvmmu mfpd (r2) ; will fail halt -1210$: .word m0.anr!m0.pms!<1*m0.pno>!m0.ena ; mmr0 +1210$: .word m0.anr!m0.pms!<2*m0.pno>!m0.ena ; mmr0 ; dddddrrrdddddrrr .word ^b0000000011110110 ; mmr1 -2,6 ; @@ -1356,40 +1347,40 @@ tc0203: mov #vhmmua,v..mmu clr 2210$+2 ; expect mmr1 = 0 1999$: ; -2000$: mov #020040,sp ; set SP into 1st click page 1, non-resident +2000$: mov #p2base+40,sp ; set SP into 1st click page 2, non-resident mov #2010$,vhvmmu rts pc ; will fail halt -2010$: .word m0.anr!m0.pms!<1*m0.pno>!m0.ena ; mmr0 +2010$: .word m0.anr!m0.pms!<2*m0.pno>!m0.ena ; mmr0 ; dddddrrrdddddrrr .word ^b0000000000010110 ; mmr1 +2,6 ; -2100$: mov #020040,sp ; set SP into 1st click page 1, non-resident +2100$: mov #p2base+40,sp ; set SP into 1st click page 2, non-resident mov #2110$,vhvmmu mov #1,r2 ; not used mtpi (r2) ; will fail halt -2110$: .word m0.anr!m0.pms!<1*m0.pno>!m0.ena ; mmr0 +2110$: .word m0.anr!m0.pms!<2*m0.pno>!m0.ena ; mmr0 ; dddddrrrdddddrrr .word ^b0000000000010110 ; mmr1 +2,6 ; -2200$: mov #020040,sp ; set SP into 1st click page 1, non-resident +2200$: mov #p2base+40,sp ; set SP into 1st click page 1, non-resident mov #2210$,vhvmmu mov #1,r2 ; not used mtpd (r2) ; will fail halt -2210$: .word m0.anr!m0.pms!<1*m0.pno>!m0.ena ; mmr0 +2210$: .word m0.anr!m0.pms!<2*m0.pno>!m0.ena ; mmr0 ; dddddrrrdddddrrr .word ^b0000000000010110 ; mmr1 +2,6 ; 9000$: clr cp.psw reset ; mmu off ;! MMU off clr sipdr0 ; reset super/user pdf + clr sipdr1 clr sipdr7 clr sipar7 clr uipdr0 - mov #v..mmu+2,v..mmu ; restore mmu catcher - clr v..mmu+2 + vecclr v..mmu ; restore mmu catcher 9999$: iot ; end of test C2.3 ; ; Test C2.4 -- mmu abort vs nxm abort ++++++++++++++++++++++++++++++++ @@ -1409,25 +1400,25 @@ tc0204: mov cp.los,kipar6 ; map begin of non-existent memory ; part 1: MMU allows access to NXM memory --> NXM abort -------------- ; 1000$: clr cp.err ; clear CPUERR - mov #1100$,v..iit ; set vector 4 handler for NXM abort + vecset v..iit,1100$ ; set vector 4 handler for NXM abort clr @#p6p1p2 ; access halt 1100$: mov #stack,sp ; vector 4 taken hcmpeq cp.err,#cp.nxm ; NXM error seen - mov #v..iit+2,v..iit ; restore iit handler to catcher + vecclr v..iit ; restore iit handler to catcher ; ; part 2: MMU denies access to NXM memory --> MMU abort -------------- ; 2000$: mov #<127.*md.plf>!md.an7,kipdr6 ; deny access via acf=7 clr cp.err ; clear CPUERR - mov #2100$,v..mmu ; set vector 250 handler for MMU abort + vecset v..mmu,2100$ ; set vector 250 handler for MMU abort 2010$: clr @#p6p1p2 ; access halt 2100$: mov #stack,sp ; vector 250 taken htsteq cp.err ; check CPUERR: no NXM expected hcmpeq #m0.anr!<6*m0.pno>!m0.ena,mmr0 ; check mmr0 hcmpeq #2010$,mmr2 ; check mmr2: failed instruction - mov #v..mmu+2,v..mmu ; restore mmu handler to catcher + vecclr v..mmu ; restore mmu handler to catcher ; reset ; mmu off ;! MMU off mov #001400,kipar6 ; reset kipar6 @@ -1449,12 +1440,9 @@ tc0205: mov #<127.*md.plf>,kipdr5 ; page 5 non-resident (afc=0) mov #177777,p6base ; set signatures (will be overwritten) mov #177777,p6base-2 ; set signatures (will stay) mov #m0.ena,mmr0 ; enable mmu ;! MMU 18 - mov #200$,v..iit ; iit handler - mov #cp.pr1!cp000c,v..iit+2 ; use PR1+000C as signature iit - mov #110$,v..mmu ; mmu handler (catcher) - mov #cp.pr2!cp00v0,v..mmu+2 ; use PR2+00V0 as signature mmu - mov #120$,v..trp ; trap handler (catcher) - mov #cp.pr3!cp0z00,v..trp+2 ; use PR3+0Z00 as signature trp + vecset v..iit,200$,cp.pr1!cp000c ; iit handler, PR1+000C as signature + vecset v..mmu,110$,cp.pr2!cp00v0 ; mmu handler, PR2+00V0 as signature + vecset v..trp,120$,cp.pr3!cp0z00 ; trap handler,PR3+0Z00 as signature ; ; abort on 2nd push mov #p6base+2,sp ; 2nd push will fail @@ -1488,12 +1476,9 @@ tc0205: mov #<127.*md.plf>,kipdr5 ; page 5 non-resident (afc=0) ; ; restore mov #<127.*md.plf>!md.arw,kipdr5 ; reset kipdr5 - mov #v..iit+2,v..iit ; v..iit to catcher - clr v..iit+2 - mov #v..mmu+2,v..mmu ; v..mmu to catcher - clr v..mmu+2 - mov #v..trp+2,v..trp ; v..trp to catcher - clr v..trp+2 + vecclr v..iit ; v..iit to catcher + vecclr v..mmu ; v..mmu to catcher + vecclr v..trp ; v..trp to catcher mov #stack,sp ; SP to default spl 0 ; back to PR0 ; @@ -1516,10 +1501,8 @@ tc0206: mov kipdr0,sipdr0 ; super page 0 1-to-1 mov kipdr7,sipdr7 ; super page 7 1-to-1 mov kipar7,sipar7 mov #m0.ena,mmr0 ; enable mmu ;! MMU 18 - mov #200$,v..mmu ; mmu handler - mov #cp.pr7!cp000c,v..mmu+2 ; use PR7+000C as signature mmu - mov #110$,v..pir ; PIRQ handler (catcher in supervisor) - mov #cp.cms!cp.pr6!cp00v0,v..pir+2 ; use PR6+00V0 as signature pir + vecset v..mmu,200$,cp.pr7!cp000c ; mmu handler, PR7+000C as signature + vecset v..pir,110$,cp.cms!cp.pr6!cp00v0 ; PIRQ handler in supervisor ; ; abort on 2nd push ------------------------------ mov #stack,sp ; set kernel SP @@ -1579,10 +1562,8 @@ tc0206: mov kipdr0,sipdr0 ; super page 0 1-to-1 clr sipar6 clr sipdr7 clr sipar7 - mov #v..mmu+2,v..mmu ; v..mmu to catcher - clr v..mmu+2 - mov #v..pir+2,v..pir ; v..pir to catcher - clr v..pir+2 + vecclr v..mmu ; v..mmu to catcher + vecclr v..pir ; v..pir to catcher mov #stack,sp ; SP to default ; 9999$: iot ; end of test C2.6 @@ -1595,8 +1576,8 @@ tc0206: mov kipdr0,sipdr0 ; super page 0 1-to-1 ; tc0207: clr kipdr6 ; kernel page 6 non-resident mov #m0.ena,mmr0 ; enable mmu ;! MMU 18 - mov #p6base+10,v..trp ; TRAP handler in page 6 - mov #200$,v..mmu ; mmu handler + vecset v..trp,p6base+10 ; TRAP handler in page 6 + vecset v..mmu,200$ ; mmu handler 100$: trap 100 ; will fail halt 200$: hcmpeq #m0.anr!<6*m0.pno>!m0.ena,mmr0 ; check mmr0: ico=0 @@ -1605,10 +1586,8 @@ tc0207: clr kipdr6 ; kernel page 6 non-resident ; reset ; mmu off ;! MMU off mov #<127.*md.plf>!md.arw,kipdr6 ; restore kipdr6 - mov #v..mmu+2,v..mmu ; v..mmu to catcher - clr v..mmu+2 - mov #v..trp+2,v..trp ; v..trp to catcher - clr v..trp+2 + vecclr v..mmu ; v..mmu to catcher + vecclr v..trp ; v..trp to catcher mov #stack,sp ; SP to default ; 9999$: iot ; end of test C2.7 @@ -1620,7 +1599,7 @@ tc0207: clr kipdr6 ; kernel page 6 non-resident ; tc0208: clr kipdr5 ; kernel page 5 non-resident mov #m0.ena,mmr0 ; enable mmu ;! MMU 18 - mov #200$,v..mmu ; mmu handler + vecset v..mmu,200$ ; mmu handler clr r2 ; clear counter mov #100$,r3 ; ptr to failed landing jmp @#p5ce14 ; start test code @@ -1633,8 +1612,7 @@ tc0208: clr kipdr5 ; kernel page 5 non-resident ; reset ; mmu off ;! MMU off mov #<127.*md.plf>!md.arw,kipdr5 ; restore kipdr5 - mov #v..mmu+2,v..mmu ; v..mmu to catcher - clr v..mmu+2 + vecclr v..mmu ; v..mmu to catcher mov #stack,sp ; SP to default ; 9999$: iot ; end of test C2.8 @@ -1646,7 +1624,7 @@ tc0209: clr kipdr6 ; kernel page 6 non-resident mov #177777,p6base-2 ; set signatures (will be overwritten) mov #177777,p6base ; set signatures (will stay) mov #m0.ena,mmr0 ; enable mmu ;! MMU 18 - mov #200$,v..mmu ; mmu handler + vecset v..mmu,200$ ; mmu handler mov #p6base-2,r1 clr (r1)+ ; succeeds 100$: clr (r1)+ ; fails @@ -1661,8 +1639,7 @@ tc0209: clr kipdr6 ; kernel page 6 non-resident hcmpeq #177777,p6base ; check signature ; mov #<127.*md.plf>!md.arw,kipdr6 ; restore kipdr6 - mov #v..mmu+2,v..mmu ; v..mmu to catcher - clr v..mmu+2 + vecclr v..mmu ; v..mmu to catcher mov #stack,sp ; SP to default ; 9999$: iot ; end of test C2.9 @@ -1679,10 +1656,8 @@ tc0210: tstb systyp ; skip if not on w11 ; mov #<127.*md.plf>,kipdr6 ; page 6 non-resident (afc=0) mov #m0.ena,mmr0 ; enable mmu ;! MMU 18 - mov #200$,v..iit ; iit handler - mov #cp.pr1!cp000c,v..iit+2 ; use PR1+000C as signature iit - mov #110$,v..mmu ; mmu handler (catcher) - mov #cp.pr2!cp00v0,v..mmu+2 ; use PR2+00V0 as signature mmu + vecset v..iit,200$,cp.pr1!cp000c ; iit handler, PR1+000C as signature + vecset v..mmu,110$,cp.pr2!cp00v0 ; mmu handler, PR2+00V0 as signature mov #p6base,cp.slr ; red zone at 140340 mov #p6base+336,sp ; in red zone spl 4 @@ -1701,10 +1676,8 @@ tc0210: tstb systyp ; skip if not on w11 reset ; mmu off ;! MMU off mov #stack,sp ; SP to default mov #<127.*md.plf>!md.arw,kipdr6 ; reset kipdr6 - mov #v..iit+2,v..iit ; v..iit to catcher - clr v..iit+2 - mov #v..mmu+2,v..mmu ; v..mmu to catcher - clr v..mmu+2 + vecclr v..iit ; v..iit to catcher + vecclr v..mmu ; v..mmu to catcher spl 0 ; back to PR0 ; 9999$: iot ; end of test C2.10 @@ -1721,11 +1694,8 @@ tc0210: tstb systyp ; skip if not on w11 ; td0101: ; set up emt handler - mov #vhuemt,v..emt - clr v..emt+2 ; pr0 kernel -; set up mmu handler - mov #2000$,v..mmu - mov #cp.pr7,v..mmu+2 + vecset v..emt,vhuemt ; set up emt handler, pr0 kernel + vecset v..mmu,2000$,cp.pr7 ; set up mmu handler, pr7 kernel ; set up user mode pdr/par; short code/data page 0 ; short stack page 1, base 140000, length 1 click (plf=127.) --> 157700:157776 vc2sek = 157700 ; initial end of stack in kernel view @@ -1779,10 +1749,8 @@ td0101: clr udpar1 ; reset ; mmu off ;! MMU off - mov #v..emt+2,v..emt ; restore emt catcher - clr v..emt+2 - mov #v..mmu+2,v..mmu ; restore mmu catcher - clr v..mmu+2 + vecclr v..emt ; restore emt catcher + vecclr v..mmu ; restore mmu catcher jmp 9999$ ; ; the MMU trap handler @@ -1892,12 +1860,9 @@ td0201: tstb systyp ; skip if not on w11 ; ; set up handlers ; - mov #3000$,v..mmu ; MMU handler - mov #cp.pr7,v..mmu+2 ; lockout interrupts - mov #4000$,v..emt ; EMT handler - mov #cp.pr7,emt+2 ; lockout interrupts - mov #p2base,v..pir ; PIRQ handler (on page 2 in SM) - mov #cp.cms!cp.pr7,v..pir+2 ; in SM, lockout interrupts + vecset v..mmu,3000$,cp.pr7 ; MMU handler, lockout interrupts + vecset v..emt,4000$,cp.pr7 ; EMT handler, lockout interrupts + vecset v..pir,p2base,cp.cms!cp.pr7 ;PIRQ handler (on page 2 in SM,PR7) ; ; now start the game: set SM stack, set r5 and request a PIRQ 4 ; @@ -2075,12 +2040,9 @@ td0201: tstb systyp ; skip if not on w11 clr sipdr7 clr sipar7 ; - mov #v..mmu+2,v..mmu ; restore v..mmu to catcher - clr v..mmu+2 - mov #v..emt+2,v..emt ; restore v..emt to catcher - clr v..emt+2 - mov #v..pir+2,v..pir ; restore v..pir to catcher - clr v..pir+2 + vecclr v..mmu ; restore v..mmu to catcher + vecclr v..emt ; restore v..emt to catcher + vecclr v..pir ; restore v..pir to catcher ; 9999$: iot ; end of test D2.1 ; @@ -2125,8 +2087,7 @@ td0201: tstb systyp ; skip if not on w11 ; Uses page 6 with plf=1 and varying acf. ; Checks that m0.trp must be cleared before a 2nd MMU trap is taken ; -te0101: mov #vhmmut,v..mmu ; setup MMU trap handler - clr v..mmu+2 ; pr0 kernel +te0101: vecset v..mmu,vhmmut ; setup MMU trap handler, pr0 kernel reset mov #m0.ena,mmr0 ; enable mmu ;! MMU 18 mov #kipdr6,r4 ; keep in register @@ -2231,8 +2192,7 @@ te0101: mov #vhmmut,v..mmu ; setup MMU trap handler 9000$: reset ; mmu off ;! MMU off clr cp.psw mov #<127.*md.plf>!md.arw,kipdr6 ; restore kernel mapping - mov #v..mmu+2,v..mmu ; restore mmu catcher - clr v..mmu+2 + vecclr v..mmu ; restore mmu catcher 9999$: iot ; end of test E1.1 ; ; Test E1.2 -- systematic abort/trap testing for all valid afc +++++++ @@ -2251,8 +2211,7 @@ te0101: mov #vhmmut,v..mmu ; setup MMU trap handler ; 6 tst (r3) r-ok - 0 0 no ; 6 mov r0,(r3) w-ok - 0 1 no ; -te0102: mov #vhmmut,v..mmu ; setup MMU trap handler - clr v..mmu+2 ; pr0 kernel +te0102: vecset v..mmu,vhmmut ; setup MMU trap handler, pr0 kernel reset mov #m0.ent!m0.ena,mmr0 ; enable mmu with traps ;! MMU 18 clr vhvmmu ; dont expect traps initially @@ -2379,8 +2338,7 @@ te0102: mov #vhmmut,v..mmu ; setup MMU trap handler 9000$: reset ; mmu off ;! MMU off clr cp.psw mov #<127.*md.plf>!md.arw,kipdr6 ; restore kernel mapping - mov #v..mmu+2,v..mmu ; restore mmu catcher - clr v..mmu+2 + vecclr v..mmu ; restore mmu catcher 9999$: iot ; end of test E1.2 ; ; Test E1.3 -- test trap request logic (trap on non-last access) +++++ @@ -2398,7 +2356,7 @@ te0103: mov #mmr0,r2 ; ptr to mmr0 mov #<127.*md.plf>!md.att,kipdr6 ; enable traps (afc=4) mov #m0.ent!m0.ena,mmr0 ; enable mmu with traps ;! MMU 18 ; - mov #vhmmut,v..mmu ; setup MMU trap handler + vecset v..mmu,vhmmut ; setup MMU trap handler mov #1010$,vhvmmu mov (r3),r5 ; check r(p6) - trival case halt @@ -2427,7 +2385,7 @@ te0103: mov #mmr0,r2 ; ptr to mmr0 ; 2000$: reset ; mmu off ;! MMU off mov #<127.*md.plf>!md.arw,kipdr6 ; reset kipdr6 - mov #v..mmu+2,v..mmu + vecclr v..mmu ; reset v..mmu ; 9999$: iot ; end of test E1.3 ; @@ -2443,7 +2401,7 @@ te0104: mov #<127.*md.plf>!md.att,kipdr5 ; enable traps (afc=4) mov #m0.ent!m0.ena,mmr0 ; enable mmu with traps ;! MMU 18 clr r2 ; clear counter mov #1000$,r3 ; ptr to failed landing - mov #vhmmut,v..mmu ; setup MMU trap handler + vecset v..mmu,vhmmut ; setup MMU trap handler mov #1100$,vhvmmu jmp @#p5ce14 ; start test code ; @@ -2453,14 +2411,14 @@ te0104: mov #<127.*md.plf>!md.att,kipdr5 ; enable traps (afc=4) ; reset ; mmu off ;! MMU off mov #<127.*md.plf>!md.arw,kipdr5 ; reset kipdr5 - mov #v..mmu+2,v..mmu + vecclr v..mmu ; reset v..mmu ; 9999$: iot ; end of test E1.4 ; ; Test E1.5 -- test trap request after IO page access ++++++++++++++++ ; te0105: mov #<127.*md.plf>!md.att,kipdr7 ; enable traps (afc=4) - mov #vhmmut,v..mmu ; setup MMU trap handler + vecset v..mmu,vhmmut ; setup MMU trap handler mov #1000$,vhvmmu ; ; The write to mmr0 will not trigger a trap on w11 because the trap decision @@ -2472,7 +2430,7 @@ te0105: mov #<127.*md.plf>!md.att,kipdr7 ; enable traps (afc=4) ; 1000$: reset ; mmu off ;! MMU off mov #<127.*md.plf>!md.arw,kipdr7 ; reset kipdr7 - mov #v..mmu+2,v..mmu + vecclr v..mmu ; reset v..mmu ; 9999$: iot ; end of test E1.5 ; @@ -2481,10 +2439,8 @@ te0105: mov #<127.*md.plf>!md.att,kipdr7 ; enable traps (afc=4) ; ; common handler setup for trap and interrupt priority tests ; - mov #vhtmmu,v..mmu ; mmu trap handler - mov #cp.pr7,v..mmu+2 ; run at PR7 (lockout PIRQ) - mov #vhtpir,v..pir ; PIRQ handler - mov #cp.pr7,v..pir+2 ; run at PR7 (prevent retrigger) + vecset v..mmu,vhtmmu,cp.pr7 ; mmu trap handler, PR7 (lockout PIRQ) + vecset v..pir,vhtpir,cp.pr7 ; PIRQ handler, PR7 (prevent retrigger) mov #<127.*md.plf>!md.att,kipdr5 ; enable traps in page 5 (afc=4) ; ; Test E2.1 -- mmu trap + interrupt priority +++++++++++++++++++++++++ @@ -2513,10 +2469,8 @@ te0201: mov #m0.ent!m0.ena,mmr0 ; enable mmu with traps ;! MMU 18 ; common restore for section E2 -------------------------------------- ; mov #<127.*md.plf>!md.arw,kipdr5 ; reset kipdr5 - mov #v..mmu+2,v..mmu ; restore v..mmu to catcher - clr v..mmu+2 - mov #v..pir+2,v..pir ; restore v..pir to catcher - clr v..pir+2 + vecclr v..mmu ; restore v..mmu to catcher + vecclr v..pir ; restore v..pir to catcher ; ; Section F: miscellaneous =================================================== ; F1 test D-to-I mapping @@ -2587,8 +2541,7 @@ tf0101: mov #m3.dkm,mmr3 ; enable D space for kernel ; clr kdpdr6 ; reset kdpdr6 clr kdpar6 ; reset kdpar6 - mov #v..mmu+2,v..mmu ; restore mmu catcher - clr v..mmu+2 + vecclr v..mmu ; restore mmu catcher ; 9999$: iot ; end of test F1.1 ; diff --git a/tools/tcode/cpu_selftest.mac b/tools/tcode/cpu_selftest.mac index a7a389e5..cf7eb23d 100644 --- a/tools/tcode/cpu_selftest.mac +++ b/tools/tcode/cpu_selftest.mac @@ -1,9 +1,10 @@ -; $Id: cpu_selftest.mac 1351 2023-01-13 08:38:27Z mueller $ +; $Id: cpu_selftest.mac 1358 2023-01-27 10:37:36Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later ; Copyright 2022-2023 by Walter F.J. Mueller ; ; Revision History: ; Date Rev Version Comment +; 2023-01-27 1358 1.1 use .mcall and mlib ; 2023-01-04 1345 1.0 Initial version ; 2022-07-13 1254 0.1 First draft ; @@ -11,6 +12,9 @@ ; .include |lib/tcode_std_base.mac| .include |lib/defs_mmu.mac| +; + .mcall hcmpeq + .mcall vecset,vecclr ; ; Section A: self test codes ; Section B: CPU probe codes @@ -207,13 +211,11 @@ ta0201: 300$: jmp @#400$ halt 400$: mov #160000,r5 ; r5=160000 - mov #500$,v..iit ; setup iit vector - clr v..iit+2 + vecset v..iit,500$ ; setup iit handler mov #stack,sp ; sp=002000 tst (r5) ; will fail, first word of I/O page halt -500$: mov #v..iit+2,v..iit ; restore iit catcher - clr v..iit+2 +500$: vecclr v..iit ; restore iit catcher ; 9999$: iot ; end of test A2 ; @@ -225,8 +227,8 @@ ta0201: ; leading to a 11/70 detection is done, all other branches end in a halt. ; Full code is in /usr/src/sys/pdpstand/M.s starting as cpuprobe. ; -tb0101: mov #1000$,v..iit ; vector 4 handler - mov #1000$,v..rit ; vector 10 handler +tb0101: vecset v..iit,1000$ ; vector 4 handler + vecset v..rit,1000$ ; vector 10 handler ; tst @#ubmap ; look for unibus map tst @#kdpar+14 ; look for split I/D (check kdpar6) @@ -243,8 +245,8 @@ tb0101: mov #1000$,v..iit ; vector 4 handler ; 1100$: .word 0 ; catcher address ; -1200$: mov #v..iit+2,v..iit ; restore - mov #v..rit+2,v..rit ; restore +1200$: vecclr v..iit ; restore + vecclr v..rit ; restore ; 9999$: iot ; end of test B1 ;