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pdp11_mmu.vhd: BUGFIX: correct trap and PDR A logic
- tools/asm-11/lib/defs_mmu.mac: rename md.a??, saner names for ACF - tcode/cpu_mmu.mac: add E1.1, test m0.trp, pdr aia/aiw transitions (verify fix) Closes #34 Closes #33 Closes #26 Closes #25
This commit is contained in:
wfjm
@@ -1,17 +1,18 @@
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; $Id: cpu_mmu.mac 1291 2022-09-03 07:00:27Z mueller $
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; $Id: cpu_mmu.mac 1295 2022-09-07 16:28:55Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; Revision History:
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; Date Rev Version Comment
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; 2022-08-31 1291 1.0 Initial version
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; 2022-09-06 1294 1.0 Initial version
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; 2022-07-24 1262 0.1 First draft
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;
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; Test CPU MMU: all aspects of the MMU
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; Section A: pdr,par registers
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; Section B: mmr0,mmr3 registers, mapping, instructions
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; Section C: mmr1+mmr0 register, aborts and traps
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; Section C: mmr1+mmr0 register, aborts
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; Section D: mmr2+mmr1+mmr0 register, abort recovery
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; Section E: traps and pdr aia and aiw bits
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;
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.include |lib/tcode_std_base.mac|
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.include |lib/defs_mmu.mac|
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@@ -35,6 +36,21 @@
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kipar6 = kipar+14
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kipdr7 = kipdr+16
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kipar7 = kipar+16
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p0p1p2 = <1*100>+2 ; page 0, +1 click, +2
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p0p1p4 = <1*100>+4 ; page 0, +1 click, +4
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p1base = <1*20000> ; page 1
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p1p0p2 = p1base+2 ; page 1, +2
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p1m1p0 = p1base+<127.*100> ; page 1, 128-1 click
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p2base = <2*20000> ; page 2
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p2m1p0 = p2base+<127.*100> ; page 1, 128-1 click
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p2m1m4 = p2base+<127.*100>-4 ; page 1, 128-1 click, -4
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p3base = <3*20000> ; page 3
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p4base = <4*20000> ; page 4
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p5base = <5*20000> ; page 5
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p6base = <6*20000> ; page 6
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p6p1p2 = p6base+<1*100>+2 ; page 6, +1 click, +2
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p7base = <7*20000> ; page 7
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;
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; Section A: pdr,par registers ===============================================
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;
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@@ -564,7 +580,7 @@ tb0302:
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;
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9999$: iot ; end of test B3.2
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;
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; Section C: mmr1+mmr0 register, aborts and traps ============================
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; Section C: mmr1+mmr0 register, aborts ======================================
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;
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; Test C1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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;
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@@ -646,7 +662,7 @@ tc0101: mov #1000$,r1 ; ptr to abort bit table
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; Test C2.1 -- test unary/binary instructions ++++++++++++++++++++++++
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; Excercise access to kernel page 6 and inspect mmr0 and mmr1
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;
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tc0201: mov #vhemmu,v..mmu
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tc0201: mov #vhmmua,v..mmu
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clr v..mmu+2 ; pr0 kernel
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reset
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mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
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@@ -692,7 +708,7 @@ tc0201: mov #vhemmu,v..mmu
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.word ^b0000000011110100 ; mmr1 -2,4
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;
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; write abort in mapped area (write access)
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1300$: mov #<0.*md.plf>!md.aro,kipdr6 ; plf= 0.;ed=0;acf=r
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1300$: mov #<0.*md.plf>!md.ara,kipdr6 ; plf= 0.;ed=0;acf=r
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mov #140002,r2
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tstb (r2)+ ; read ok
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mov #1310$,vhvmmu
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@@ -738,7 +754,7 @@ tc0201: mov #vhemmu,v..mmu
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mov #2001$,r2
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tst @(r2)+ ; will fail
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halt
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2001$: .word 140102 ; probed address
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2001$: .word p6p1p2 ; probed address, page 6, +1 click, +2
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2010$: .word m0.ale!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000000010010 ; mmr1 +2,2
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@@ -778,7 +794,7 @@ tc0201: mov #vhemmu,v..mmu
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mov #3201$,r4
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mov @(r4)+,(r3)+ ; will fail
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halt
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3201$: .word 140102 ; probed address
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3201$: .word p6p1p2 ; probed address, page 6, +1 click, +2
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3210$: .word m0.ale!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000000010100 ; mmr1 +2,4
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@@ -820,12 +836,12 @@ tc0201: mov #vhemmu,v..mmu
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mov 4201$,r5
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cmp (r2)+,@(r5)+ ; will fail
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halt
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4201$: .word 140102 ; probed address
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4201$: .word p6p1p2 ; probed address, page 6, +1 click, +2
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4210$: .word m0.ale!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0001010100010010 ; mmr1 +2,5; +2,2
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;
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4300$: mov #<0.*md.plf>!md.aro,kipdr6 ; plf= 0.;ed=0;acf=r
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4300$: mov #<0.*md.plf>!md.ara,kipdr6 ; plf= 0.;ed=0;acf=r
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mov #4310$,vhvmmu
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mov #140010,r4
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bis -(r2),(r4)+ ; will fail
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@@ -870,7 +886,7 @@ tc0201: mov #vhemmu,v..mmu
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.word ^b0000000000010011 ; mmr1 +2,3
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;
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; length + read-only abort
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5200$: mov #<0.*md.plf>!md.aro,kipdr6 ; plf= 0.;ed=0;acf=r
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5200$: mov #<0.*md.plf>!md.ara,kipdr6 ; plf= 0.;ed=0;acf=r
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mov #5210$,vhvmmu
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mov #140102,r4
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com (r4)+ ; will fail
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@@ -893,14 +909,14 @@ tc0201: mov #vhemmu,v..mmu
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; udpdr1 1 click up acr=2 read
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; udpdr2 1 click dn acr=6 w/r
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;
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tc0202: mov #vhemmu,v..mmu
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tc0202: mov #vhmmua,v..mmu
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clr v..mmu+2 ; pr0 kernel
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reset
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mov #cp.pmu,cp.psw ; pm to user
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mov #m3.dum,mmr3 ; enable user D space
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mov #<0.*md.plf>!md.arw,kipdr6 ; plf= 0.;ed=0;acf=w/r
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mov #<0.*md.plf>!md.aro,uipdr0 ; plf= 0.;ed=0;acf=r
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mov #<0.*md.plf>!md.aro,udpdr1 ; plf= 0.;ed=0;acf=r
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mov #<0.*md.plf>!md.ara,uipdr0 ; plf= 0.;ed=0;acf=r
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mov #<0.*md.plf>!md.ara,udpdr1 ; plf= 0.;ed=0;acf=r
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mov #<127.*md.plf>!md.dwn!md.arw,udpdr2 ; plf=127.;ed=1;acf=w/r
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mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
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;
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@@ -914,7 +930,7 @@ tc0202: mov #vhemmu,v..mmu
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;
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; MPPI: I space page 1 non-resident
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1000$: mov #1010$,vhvmmu
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mov #020000,r2
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mov #p1base,r2
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mfpi (r2)+ ; will fail, page 1 unmapped
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halt
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1010$: .word m0.anr!m0.pmu!<1*m0.pno>!m0.ena ; mmr0
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@@ -923,7 +939,7 @@ tc0202: mov #vhemmu,v..mmu
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;
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; MFPI: I space page 0 length abort
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1100$: mov #1110$,vhvmmu
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mov #000102,r3
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mov #p0p1p2,r3 ; page 0, +1 click, +2
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mfpi (r3)+ ; will fail
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halt
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1110$: .word m0.ale!m0.pmu!<0*m0.pno>!m0.ena ; mmr0
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@@ -933,7 +949,7 @@ tc0202: mov #vhemmu,v..mmu
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; MFPI @(R)+: 1st access fails (in kernel space)
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1200$: mov #cp.pmu,cp.psw ; pm to user
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mov #1210$,vhvmmu
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mov #140102,r4
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mov #p6p1p2,r4 ; page 6, +1 click, +2
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mfpi @(r4)+ ; will fail
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halt
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1210$: .word m0.ale!<6*m0.pno>!m0.ena ; mmr0 -> p6 k
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@@ -946,7 +962,7 @@ tc0202: mov #vhemmu,v..mmu
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mov #1301$,r5
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mfpi @(r5)+ ; will fail
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halt
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1301$: .word 000104 ; probed address
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1301$: .word p0p1p4 ; probed address
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1310$: .word m0.ale!m0.pmu!<0*m0.pno>!m0.ena ; mmr0 -> p0 u
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; dddddrrrdddddrrr
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.word ^b0000000000010101 ; mmr1 +2,5
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@@ -954,7 +970,7 @@ tc0202: mov #vhemmu,v..mmu
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; MFPD: D space page 1 length abort (has ed=1)
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1400$: mov #cp.pmu,cp.psw ; pm to user
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mov #1410$,vhvmmu
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mov #037700,r3
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mov #p1m1p0,r3 ; page 1, 128-1 click
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mfpd -(r3) ; will fail
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halt
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1410$: .word m0.ale!m0.pmu!m0.dsp!<1*m0.pno>!m0.ena ; mmr0
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@@ -974,7 +990,7 @@ tc0202: mov #vhemmu,v..mmu
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; MTPD: D space page 3 non-resident
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2000$: mov #cp.pmu,cp.psw ; pm to user
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mov #2010$,vhvmmu
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mov #060000,r2
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mov #p3base,r2
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push #1234
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mtpd (r2)+ ; will fail, page 3 unmapped
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halt
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@@ -985,7 +1001,7 @@ tc0202: mov #vhemmu,v..mmu
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; MTPD: D space page 1 read-only
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2100$: mov #cp.pmu,cp.psw ; pm to user
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mov #2110$,vhvmmu
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mov #020002,r3
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mov #p1p0p2,r3 ; page 1, +2
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push #1234
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mtpd (r3)+ ; will fail
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halt
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@@ -995,7 +1011,7 @@ tc0202: mov #vhemmu,v..mmu
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;
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; MTPD: D space page 2 length
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2200$: mov #2210$,vhvmmu
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mov #057700,r4
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mov #p2m1p0,r4
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push #1234
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mtpd -(r4) ; will fail
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halt
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@@ -1005,7 +1021,7 @@ tc0202: mov #vhemmu,v..mmu
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;
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; MTPD @(R)+: 1st access fails (in kernel space)
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2300$: mov #2310$,vhvmmu
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mov #140102,r5
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mov #p6p1p2,r5 ; page 6, +1 click, +2
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push #1234
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mtpd @(r5)+ ; will fail
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halt
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@@ -1019,7 +1035,7 @@ tc0202: mov #vhemmu,v..mmu
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push #1234
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mtpd @(r3)+ ; will fail
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halt
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2401$: .word 057600 ; probed address
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2401$: .word p2m1m4 ; probed address, page 1, 128-1 click, -4
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2410$: .word m0.ale!m0.pmu!m0.dsp!<2*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0001001100010110 ; mmr1 +2,3; +2,6
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@@ -1054,7 +1070,7 @@ tc0202: mov #vhemmu,v..mmu
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; si.7 as 1-to-1 (psw access)
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; ui.0 as 1-to-1 (for read access)
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;
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tc0203: mov #vhemmu,v..mmu
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tc0203: mov #vhmmua,v..mmu
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clr v..mmu+2 ; pr0 kernel
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reset
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mov kipdr0,sipdr0 ; super 0: 1-to-1
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@@ -1281,26 +1297,316 @@ td0101:
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3002$: .word 0 ; save mmr2
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;
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9999$: iot ; end of test D1.1
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;
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; Section E: traps and pdr aia and aiw bits ==================================
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;
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; Test E1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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;
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; Test E1.1 -- test m0.trp, pdr aia/aiw transitions ++++++++++++++++++
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; Summary
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; PDR MMR0 action aia aiw trp Trap Comment
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; acf=6 ent=0 tst (r3) 0 0 0 no no ai, no trap
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; clr (r3) 0 1 0 no clr sets aiw
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; tst (r3) 0 1 0 no aiw stays
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; pdr->pdr 0 0 0 - any pdr write clears aia,aiw
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; clr (r3) 0 1 0 no clr sets aiw
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; pdr+1 write 0 0 0 - any pdr write clears aia,aiw
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; clr (r3) 0 1 0 no clr sets aiw
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; par->par 0 0 0 - any par write clears aia,aiw
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;
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; acf=6 ent=1 tst (r3) 0 0 0 no no trap
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; clr (r3) 0 1 0 no no trap
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;
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; acf=4 ent=0 tst (r3) 1 0 1 no trp set, aia set
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; clr (r3) 1 1 1 no trp stays, aiw set
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; trp=0;pdr 0 0 0 - any par write clears aia,aiw
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;
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; acf=4 ent=1 tst (r3) 1 0 1 yes trap taken, trp set, aia set
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; clr (r3) 1 1 1 no no trap, aia set
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; trp=0;pdr 0 0 0 - any pdr write clears aia,aiw
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; clr (r3) 1 1 1 yes trap taken, trp,aia,aiw set
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; tst (r3) 1 1 1 no no trap, no additional bits
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; trp=0;pdr 0 0 0 - any par write clears aia,aiw
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;
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; Uses page 6 with plf=1 and varying acf
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;
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te0101: mov #vhmmut,v..mmu ; setup MMU trap handler
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clr v..mmu+2 ; pr0 kernel
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reset
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mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
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mov #kipdr6,r4 ; keep in register
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mov #p6base,r3 ; probed address
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clr vhvmmu ; dont expect traps initially
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;
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; acf=6 ent=0 tst (r3) 0 0 0 no no ai, no trap
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mov #md.plf!md.arw,(r4) ; set pdr
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tst (r3) ; probe read
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hbiteq mmr0,#m0.trp ; check trp=0
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hcmpeq (r4),#md.plf!md.arw ; check aia,aiw=0
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;
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; clr (r3) 0 1 0 no clr sets aiw
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clr (r3) ; probe write
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hbiteq mmr0,#m0.trp ; check trp=0
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hcmpeq (r4),#md.plf!md.aiw!md.arw ; check aiw=1
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;
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; tst (r3) 0 1 0 no aiw stays
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tst (r3) ; probe read
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hcmpeq (r4),#md.plf!md.aiw!md.arw ; check aiw=1
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;
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; pdr->pdr 0 0 0 - any pdr write clears aia,aiw
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mov (r4),(r4) ; write pdr->pdr, should clear aiw
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hcmpeq (r4),#md.plf!md.arw ; check aiw=0
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;
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; clr (r3) 0 1 0 no clr sets aiw
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clr (r3) ; probe write
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hcmpeq (r4),#md.plf!md.aiw!md.arw ; check aiw=1
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;
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; pdr+1 write 0 0 0 - any pdr write clears aia,aiw
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movb #1,1(r4) ; write pdr+1, should clear aiw
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hcmpeq (r4),#md.plf!md.arw ; check aiw=0
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;
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; clr (r3) 0 1 0 no clr sets aiw
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clr (r3) ; probe write
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hcmpeq (r4),#md.plf!md.aiw!md.arw ; check aiw=1
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;
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; par->par 0 0 0 - any par write clears aia,aiw
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mov kipar6,kipar6 ; write par->par, should clear aiw
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hcmpeq (r4),#md.plf!md.arw ; check aiw=0
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;
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; acf=6 ent=1 tst (r3) 0 0 0 no no trap
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mov #m0.ent!m0.ena,mmr0 ; enable mmu with traps enabled
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tst (r3) ; probe read
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;
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; clr (r3) 0 1 0 no no trap
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clr (r3) ; probe write
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;
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; acf=4 ent=0 tst (r3) 1 0 1 no trp set, aia set
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mov #md.plf!md.att,(r4) ; set pdr
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mov #m0.ena,mmr0 ; enable mmu with traps disabled
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tst (r3) ; probe read
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hbitne mmr0,#m0.trp ; check trp=1
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hcmpeq (r4),#md.plf!md.aia!md.att ; check aia=1
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;
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; clr (r3) 1 1 1 no trp stays, aiw set
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clr (r3) ; probe write
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hbitne mmr0,#m0.trp ; check trp=1
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hcmpeq (r4),#md.plf!md.aia!md.aiw!md.att ; check aia=1,aiw=1
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;
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; trp=0;pdr 0 0 0 - any par write clears aia,aiw
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bic #m0.trp,mmr0 ; clear trp
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hbiteq mmr0,#m0.trp ; check trp=0
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mov (r4),(r4) ; write pdr->pdr, should clear aia and aiw
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hcmpeq (r4),#md.plf!md.att ; check aia=0,aiw=0
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;
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; acf=4 ent=1 tst (r3) 1 0 1 yes trap taken, trp set, aia set
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mov #m0.ent!m0.ena,mmr0 ; enable mmu with traps enabled
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mov #1010$,vhvmmu
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tst (r3) ; probe read
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halt ; expect trap
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1010$: hbitne mmr0,#m0.trp ; check trp=1
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hcmpeq (r4),#md.plf!md.aia!md.att ; check aia=1
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;
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; clr (r3) 1 1 1 no no trap, aia set
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clr (r3) ; probe write
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hbitne mmr0,#m0.trp ; check trp=1
|
||||
hcmpeq (r4),#md.plf!md.aia!md.aiw!md.att ; check aia=1,aiw=1
|
||||
;
|
||||
; trp=0;pdr 0 0 0 - any pdr write clears aia,aiw
|
||||
bic #m0.trp,mmr0 ; clear trp
|
||||
mov (r4),(r4) ; write pdr->pdr, should clear aia and aiw
|
||||
hcmpeq (r4),#md.plf!md.att ; check aia=0,aiw=0
|
||||
;
|
||||
; clr (r3) 1 1 1 yes trap taken, trp,aia,aiw set
|
||||
mov #1020$,vhvmmu
|
||||
clr (r3) ; probe write
|
||||
halt ; expect trap
|
||||
1020$: hbitne mmr0,#m0.trp ; check trp=1
|
||||
hcmpeq (r4),#md.plf!md.aia!md.aiw!md.att ; check aia=1,aiw=1
|
||||
;
|
||||
; tst (r3) 1 1 1 no no trap, no additional bits
|
||||
tst (r3) ; probe read
|
||||
hbitne mmr0,#m0.trp ; check trp=1
|
||||
hcmpeq (r4),#md.plf!md.aia!md.aiw!md.att ; check aia=1,aiw=1
|
||||
;
|
||||
; trp=0;pdr 0 0 0 - any par write clears aia,aiw
|
||||
bic #m0.trp,mmr0 ; clear trp
|
||||
mov (r4),(r4) ; write pdr->pdr, should clear aia and aiw
|
||||
hcmpeq (r4),#md.plf!md.att ; check aia=0,aiw=0
|
||||
;
|
||||
9000$: reset ; mmu off ;! MMU off
|
||||
clr cp.psw
|
||||
mov #<127.*md.plf>!md.arw,kipdr6 ; restore kernel mapping
|
||||
mov #v..mmu+2,v..mmu ; restore mmu catcher
|
||||
clr v..mmu+2
|
||||
9999$: iot ; end of test E1.1
|
||||
;
|
||||
; Test E1.2 -- systematic abort/trap testing for all valid afc +++++++
|
||||
; Summary
|
||||
; afc action handler abort aia aiw trap Comment
|
||||
; 0 tst (r3) r-abo anr 0 0 no
|
||||
; 0 add r0,(r3) w-abo anr 0 0 no
|
||||
; 1 tst (r3) r-trap - 1 0 yes
|
||||
; 1 add r0,(r3) w-abo ard 0 0 no
|
||||
; 2 tst (r3) r-ok - 0 0 no
|
||||
; 2 add r0,(r3) w-abo ard 0 0 no
|
||||
; 4 tst (r3) r-trap - 1 0 yes
|
||||
; 4 clr (r3) w-trap - 1 1 yes
|
||||
; 5 tst (r3) r-ok - 0 0 no
|
||||
; 5 clr (r3) w-trap - 1 1 yes
|
||||
; 6 tst (r3) r-ok - 0 0 no
|
||||
; 6 mov r0,(r3) w-ok - 0 1 no
|
||||
;
|
||||
te0102: mov #vhmmut,v..mmu ; setup MMU trap handler
|
||||
clr v..mmu+2 ; pr0 kernel
|
||||
reset
|
||||
mov #m0.ent!m0.ena,mmr0 ; enable mmu with traps ;! MMU 18
|
||||
clr vhvmmu ; dont expect traps initially
|
||||
;
|
||||
mov #3000$,r5 ; ptr to data table
|
||||
mov #kipdr6,r4 ; keep in register
|
||||
mov #p6base,r3 ; probed address
|
||||
mov #vhvmmu,r2 ; ptr to vhvmmu
|
||||
;
|
||||
1000$: mov (r5)+,(r4) ; load pdr
|
||||
jmp @(r5)+ ; execute case handler
|
||||
;
|
||||
; case r-ok: read, no abort, no trap
|
||||
1100$: clr (r2) ; no abort/trap expected
|
||||
tst (r3) ; probe read
|
||||
br 1900$ ; to ok-check
|
||||
;
|
||||
; case r-abo: read, abort
|
||||
1200$: mov #vhmmua,v..mmu ; setup MMU abort handler
|
||||
mov (r5)+,1210$
|
||||
mov #1210$,(r2)
|
||||
tst (r3) ; probe read
|
||||
halt ; expect abort
|
||||
1210$: .word 0,0
|
||||
br 1910$ ; to abo-check
|
||||
;
|
||||
; case r-trap: read, trap
|
||||
1300$: mov #vhmmut,v..mmu ; setup MMU trap handler
|
||||
mov #1900$,(r2) ; to ok-check
|
||||
tst (r3) ; probe read
|
||||
halt ; expect trap
|
||||
;
|
||||
; case w-ok: write, no abort, no trap
|
||||
1400$: clr (r2) ; no abort/trap expected
|
||||
mov r0,(r3) ; probe write
|
||||
br 1900$ ; to ok-check
|
||||
;
|
||||
; case w-abo: write, abort
|
||||
1500$: mov #vhmmua,v..mmu ; setup MMU abort handler
|
||||
mov (r5)+,1510$
|
||||
mov #1510$,(r2)
|
||||
add r0,(r3) ; probe write
|
||||
halt ; expect abort
|
||||
1510$: .word 0,0
|
||||
br 1910$ ; to tr-check
|
||||
;
|
||||
; case w-trap: write, trap
|
||||
1600$: mov #vhmmut,v..mmu ; setup MMU trap handler
|
||||
mov #1900$,(r2)
|
||||
clr (r3) ; probe write
|
||||
halt ; expect trap
|
||||
;
|
||||
1900$: tst (r5)+ ; drop unused mmr0 info
|
||||
1910$: mov (r5)+,r0 ; get pdrexp
|
||||
hcmpeq (r4),r0 ; check pdr
|
||||
mov (r4),(r4) ; clear pdr aia,aiw
|
||||
bic #m0.trp,mmr0 ; clear mmr0 trp flag
|
||||
tst (r5) ; look at next case
|
||||
beq 9000$ ; if eq end sentinel found ?
|
||||
br 1000$ ; if ne go for next case
|
||||
;
|
||||
3000$: .word md.plf ; afc=0 + read: - anr -------
|
||||
.word 1200$ ; r-abo
|
||||
.word m0.anr!m0.ent!<6*m0.pno>!m0.ena ; mmr0
|
||||
.word md.plf ; pdf: no aib
|
||||
;
|
||||
.word md.plf ; afc=0 + write: - anr -------
|
||||
.word 1500$ ; w-abo
|
||||
.word m0.anr!m0.ent!<6*m0.pno>!m0.ena ; mmr0
|
||||
.word md.plf ; pdf: no aib
|
||||
;
|
||||
.word md.plf!md.ata ; afc=1 + read: - trp aia ---
|
||||
.word 1300$ ; r-trap
|
||||
.word 0 ; mmr0
|
||||
.word md.plf!md.aia!md.ata ; pdf: aia
|
||||
;
|
||||
.word md.plf!md.ata ; afc=1 + write: - ard -------
|
||||
.word 1500$ ; w-abo
|
||||
.word m0.ard!m0.ent!<6*m0.pno>!m0.ena ; mmr0
|
||||
.word md.plf!md.ata ; pdf: no aib
|
||||
;
|
||||
.word md.plf!md.ara ; afc=2 + read: -------------
|
||||
.word 1100$ ; r-ok
|
||||
.word 0 ; mmr0
|
||||
.word md.plf!md.ara ; pdf: no aib
|
||||
;
|
||||
.word md.plf!md.ara ; afc=2 + write: - ard -------
|
||||
.word 1500$ ; w-abo
|
||||
.word m0.ard!m0.ent!<6*m0.pno>!m0.ena ; mmr0
|
||||
.word md.plf!md.ara ; pdf: no aib
|
||||
;
|
||||
.word md.plf!md.att ; afc=4 + read: - trp aia ---
|
||||
.word 1300$ ; r-trap
|
||||
.word 0 ; mmr0
|
||||
.word md.plf!md.aia!md.att ; pdf: aia
|
||||
;
|
||||
.word md.plf!md.att ; afc=4 + write - trp aia,aiw
|
||||
.word 1600$ ; w-trap
|
||||
.word 0 ; mmr0
|
||||
.word md.plf!md.aia!md.aiw!md.att ; pdf: aia aiw
|
||||
;
|
||||
.word md.plf!md.art ; afc=5 + read: -------------
|
||||
.word 1100$ ; r-ok
|
||||
.word 0 ; mmr0
|
||||
.word md.plf!md.art ; pdf: no aib
|
||||
;
|
||||
.word md.plf!md.art ; afc=5 + write: - trp aia,aiw
|
||||
.word 1600$ ; w-trap
|
||||
.word 0 ; mmr0
|
||||
.word md.plf!md.aia!md.aiw!md.art ; pdf: aia aiw
|
||||
;
|
||||
.word md.plf!md.arw ; afc=6 + read: -------------
|
||||
.word 1100$ ; r-ok
|
||||
.word 0 ; mmr0
|
||||
.word md.plf!md.arw ; pdf: no aib
|
||||
;
|
||||
.word md.plf!md.arw ; afc=6 + write: - aiw -------
|
||||
.word 1400$ ; w-ok
|
||||
.word 0 ; mmr0
|
||||
.word md.plf!md.aiw!md.arw ; pdf: aiw
|
||||
;
|
||||
.word 0 ; end sentinel ------------------------------
|
||||
;
|
||||
9000$: reset ; mmu off ;! MMU off
|
||||
clr cp.psw
|
||||
mov #<127.*md.plf>!md.arw,kipdr6 ; restore kernel mapping
|
||||
mov #v..mmu+2,v..mmu ; restore mmu catcher
|
||||
clr v..mmu+2
|
||||
9999$: iot ; end of test E1.2
|
||||
;
|
||||
; END OF ALL TESTS - loop closure ============================================
|
||||
;
|
||||
mov tstno,r0 ; hack, for easy monitoring ...
|
||||
hcmpeq tstno,#13. ; all tests done ?
|
||||
hcmpeq tstno,#15. ; all tests done ?
|
||||
;
|
||||
jmp loop
|
||||
;
|
||||
; kernel handlers ============================================================
|
||||
;
|
||||
; vhemmu - expected mmu abort/trap handler +++++++++++++++++++++++++++++++++++
|
||||
; used to catch expected MMU aborts or traps
|
||||
; vhmmua - expected mmu abort handler ++++++++++++++++++++++++++++++++++++++++
|
||||
; used to catch expected MMU aborts
|
||||
; the pointer to expected mmr0/mmr1 values must be in vhvmmu
|
||||
; code will continue after context
|
||||
; code will continue after the test value context
|
||||
; execution will clear vhvmmu
|
||||
; --> vhvmmu must be set for each execution
|
||||
; the handler uses and modifies r0,r1
|
||||
; --> tests should only use r2,...,r5
|
||||
;
|
||||
vhemmu: mov vhvmmu,r1 ; get context
|
||||
vhmmua: mov vhvmmu,r1 ; get context
|
||||
beq 1000$ ; if 0 halt
|
||||
mov mmr0,r0
|
||||
bic #m0.ico,r0 ; mask ico (for Simh compatibility)
|
||||
@@ -1313,6 +1619,24 @@ vhemmu: mov vhvmmu,r1 ; get context
|
||||
1000$: halt
|
||||
vhvmmu: .word 0 ; context pointer
|
||||
;
|
||||
; vhmmut - expected mmu trap handler +++++++++++++++++++++++++++++++++++++++++
|
||||
; used to catch expected MMU traps
|
||||
; the pointer to continuation address must be in vhvmmu
|
||||
; execution will clear vhvmmu
|
||||
; --> vhvmmu must be set for each execution
|
||||
; the handler uses and modifies r0,r1
|
||||
; --> tests should only use r2,...,r5
|
||||
;
|
||||
vhmmut: mov vhvmmu,r1 ; get context
|
||||
beq 1000$ ; if 0 halt
|
||||
mov mmr0,r0
|
||||
hbiteq r0,#m0.anr!m0.ale!m0.ard ; check abort flags 0
|
||||
hbitne r0,#m0.trp ; check trap flag 1
|
||||
mov r1,(sp) ; set up kernel return address
|
||||
clr vhvmmu ; reset context
|
||||
rti ; end return to continuation address
|
||||
1000$: halt
|
||||
;
|
||||
; vhuemt - emt handler, drop frame, continue in kernel mode ++++++++++++++++++
|
||||
; use to end user/supervisor mode code with an emt xxx
|
||||
; the kernel continution address must be written to vhustp
|
||||
|
||||
Reference in New Issue
Block a user