tcode: add tests; minor changes

- cpu_details.mac: add C1.* tests
- cpu_mmu.mac: B4.1: check stored PC in SimH and w11 case

tools/tcode/cpu_details.mac

@@ -1,4 +1,4 @@
-; $Id: cpu_details.mac 1304 2022-10-22 10:19:34Z mueller $
+; $Id: cpu_details.mac 1305 2022-10-23 07:44:21Z mueller $
 ; SPDX-License-Identifier: GPL-3.0-or-later
 ; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 ;
@@ -115,8 +115,8 @@ ta0101: mov     #1000$,v..pir     ; setup handler
         ash     r1,r2           ; r2 = pi.r00 <<(pri)
         bic     r2,(r3)         ; clear current level in pirq
         bis     1100$(r0),(r3)  ; trigger new pirqs
-        nop                     ; allow nestec interrupts to happem
-        nop                     ; "
+        nop                     ; allow nested interrupts to happen
+        nop                     ;
         dec     1300$           ; down level counter
         rti
 ;
@@ -511,10 +511,61 @@ tb0202: mov     #2,r5
 ;
 9999$:  iot                     ; end of test B2.2
 ;
+; Section C: 11/70 specifics =================================================
+;
+; Test C1:  Implementation differences +++++++++++++++++++++++++++++++++++++++
+;   This sub-section verifies that w11 shows 11/70 behavior in cases
+;   were J11 and other CPU models show different behavior
+;
+; Test C1.1 -- Register used as source and changed in dst flow +++++++
+;   OPR R,(R)+ : incremented before {J11} or after {70} use as source
+;   OPR R,-(R) : decremented before {J11} or after {70} use as source
+;
+tc0101: mov     #1000$,r4
+        mov     r4,(r4)+
+        hcmpeq  1000$,#1000$    ; check r4 prior inc stored
+        mov     r4,-(r4)
+        hcmpeq  1000$,#1000$+2  ; check r4 prior dec stored
+        br      9999$
+;
+1000$:  .word   0
+;
+9999$:  iot                     ; end of test C1.1
+;
+; Test C1.2 -- PC used as source +++++++++++++++++++++++++++++++++++++
+;    OPR PC,A(R) : store PC+2 {70} or PC+4 {J11}
+;
+tc0102: mov     #1000$,r4
+100$:   mov     pc,0(r4)
+        hcmpeq  1000$,#100$+2   ; check pc after fetch stored
+        br      9999$
+;
+1000$:  .word   0
+;
+9999$:  iot                     ; end of test C1.2
+;
+; Test C1.3 -- Registers accessible via 177700-1777717 +++++++++++++++
+;   CPU access to 177700-177717 (regs) timesout {70,J11} or not {05,10}
+;
+tc0103: mov     #vhugen,v..iit  ; set iit handler
+        clr     v..iit+2        ; pr0 kernel
+;
+        mov     #1000$,vhustp   ; continuation address
+        tst     @#177700        ; should fail
+        halt
+;
+1000$:  mov     #1100$,vhustp   ; continuation address
+        tst     @#177716        ; should fail
+        halt
+;
+1100$:  mov     v..iit+2,v..iit ; restore iit handler
+;
+9999$:  iot                     ; end of test C1.3
+;
 ; END OF ALL TESTS - loop closure ============================================
 ;
         mov     tstno,r0        ; hack, for easy monitoring ...
-        hcmpeq  tstno,#16.      ; all tests done ?
+        hcmpeq  tstno,#19.      ; all tests done ?
 ;
         jmp     loop
 ;

tools/tcode/cpu_mmu.mac

@@ -1,4 +1,4 @@
-; $Id: cpu_mmu.mac 1304 2022-10-22 10:19:34Z mueller $
+; $Id: cpu_mmu.mac 1305 2022-10-23 07:44:21Z mueller $
 ; SPDX-License-Identifier: GPL-3.0-or-later
 ; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 ;
@@ -607,6 +607,8 @@ tb0302:
 ;    Should abort with m0.anr and m0.ale for all adresses
 ;    w11 aborts with m0.anr, but sets m0.ale only when fail above 1st click
 ;    Test an address above the first click to have full 11/70 style response
+;    Note: w11 increments PC before abort (as 11/70 does)
+;          SimH increments PC after abort
 ;
 tb0401: clr     mmr3            ; no d dspace, no 22bit
         mov     #m0.ena,mmr0    ; enable mmu                    ;! MMU 18
@@ -617,9 +619,15 @@ tb0401: clr     mmr3            ; no d dspace, no 22bit
         mov     #p6base+200,-(sp)               ; start address
         rti                                     ; fake code start
         halt
+; test abort PC on stack
+1000$:  cmpb    systyp,#sy.sih                  ; on SimH ?
+        bne     1010$
+        hcmpeq  (sp)+,#p6base+200               ; SimH doesnt increment PC
+        br      1020$
+1010$:  hcmpeq  (sp)+,#p6base+200+2             ; w11 does increment PC
+; test abort PS on stack
+1020$:  hcmpeq  (sp)+,#^b1010000000000000       ; abort PS
 ;
-1000$:  tst     (sp)+                           ; w11 and Simh return PC
-        hcmpeq  (sp)+,#^b1010000000000000       ; abort PS
         mov     mmr0,r5
         bic     #m0.ico,r5
         hcmpeq  r5,#m0.anr!m0.ale!0100!<6*m0.pno>!m0.ena ; check mmr0