github.com/wfjm.w11
1
0
Fork 0
mirror of https://github.com/wfjm/w11.git synced 2026-04-26 04:08:17 +00:00
Code Issues Releases Wiki Activity

reorganize dcm/mmcm/ppl sim models

Browse Source 
- sfs_gsim_core: new common simulation core
- {dcm,s6_cmt,s7_cmt}_sfs_gsim: use now sfs_gsim_core
- s7_cmt_sfs_tb: removed, use now sfs_gsim_core
- rtl/bplib/*/tb/tb_*: use now sfs_gsim_core
- tst_serloop/nexys*/tb/tb_tst_serloop*_n*: use now sfs_gsim_core
This commit is contained in:
wfjm
2018-11-09 17:48:56 +01:00
parent 4e001adf8d
commit 22bb8e011c
40 changed files with 336 additions and 607 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
rtl/vlib/xlib/dcm_sfs_gsim.vbom
View File

@@ -1,4 +1,7 @@
# libs
../slvtypes.vhd
xlib.vhd
# components
sfs_gsim_core.vbom
# design
dcm_sfs_gsim.vhd

94
rtl/vlib/xlib/dcm_sfs_gsim.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: dcm_sfs_gsim.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: dcm_sfs_gsim.vhd 1065 2018-11-04 11:32:06Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -19,10 +19,11 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-3A,-3E
-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31
-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1065 1.1 use sfs_gsim_core
-- 2011-11-17 426 1.0.1 rename dcm_sp_sfs -> dcm_sfs
-- 2010-11-12 338 1.0 Initial version
------------------------------------------------------------------------------
@@ -31,89 +32,34 @@ library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity dcm_sfs is -- DCM for simple frequency synthesis
generic (
CLKFX_DIVIDE : positive := 1; -- FX clock divide (1-32)
CLKFX_DIVIDE : positive := 1; -- FX clock divide (1-32)
CLKFX_MULTIPLY : positive := 1; -- FX clock multiply (2-32) (1->no DCM)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- dcm locked
);
end dcm_sfs;
architecture sim of dcm_sfs is
signal CLK_DIVPULSE : slbit := '0';
signal CLKOUT_PERIOD : Delay_length := 0 ns;
signal R_CLKOUT : slbit := '0';
signal R_LOCKED : slbit := '0';
begin
proc_clkin : process (CLKIN)
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : Delay_length := 0 ns;
variable t_period : Delay_length := 0 ns;
variable nclkin : integer := 1;
begin
if CLKIN'event then
if CLKIN = '1' then -- if CLKIN rising edge
if t_lastclkin > 0 ns then
t_lastperiod := t_period;
t_period := now - t_lastclkin;
CLKOUT_PERIOD <= (t_period * CLKFX_DIVIDE) / CLKFX_MULTIPLY;
if t_lastperiod > 0 ns and abs(t_period-t_lastperiod) > 1 ps then
report "dcm_sp_sfs: CLKIN unstable" severity warning;
end if;
end if;
t_lastclkin := now;
if t_period > 0 ns then
nclkin := nclkin - 1;
if nclkin <= 0 then
nclkin := CLKFX_DIVIDE;
CLK_DIVPULSE <= '1';
R_LOCKED <= '1';
end if;
end if;
else -- if CLKIN falling edge
CLK_DIVPULSE <= '0';
end if;
end if;
end process proc_clkin;
proc_clkout : process
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : Delay_length := 0 ns;
variable t_period : Delay_length := 0 ns;
variable nclkin : integer := 1;
begin
loop
wait until CLK_DIVPULSE = '1';
for i in 1 to CLKFX_MULTIPLY loop
R_CLKOUT <= '1';
wait for CLKOUT_PERIOD/2;
R_CLKOUT <= '0';
if i /= CLKFX_MULTIPLY then
wait for CLKOUT_PERIOD/2;
end if;
end loop; -- i
end loop;
end process proc_clkout;
CLKFX <= R_CLKOUT;
LOCKED <= R_LOCKED;
-- generate clock
SFS: sfs_gsim_core
generic map (
VCO_DIVIDE => 1,
VCO_MULTIPLY => CLKFX_MULTIPLY,
OUT_DIVIDE => CLKFX_DIVIDE)
port map (
CLKIN => CLKIN,
CLKFX => CLKFX,
LOCKED => LOCKED
);
end sim;

3
rtl/vlib/xlib/s6_cmt_sfs_gsim.vbom
View File

@@ -1,4 +1,7 @@
# libs
../slvtypes.vhd
xlib.vhd
# components
sfs_gsim_core.vbom
# design
s6_cmt_sfs_gsim.vhd

101
rtl/vlib/xlib/s6_cmt_sfs_gsim.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: s6_cmt_sfs_gsim.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: s6_cmt_sfs_gsim.vhd 1065 2018-11-04 11:32:06Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -19,10 +19,11 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-6
-- Tool versions: xst 14.5-14.7; ghdl 0.29-0.33
-- Tool versions: xst 14.5-14.7; ghdl 0.29-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1065 1.1 use sfs_gsim_core
-- 2016-08-18 799 1.0.1 remove 'assert false' from report statements
-- 2013-10-06 538 1.0 Initial version (derived from s7_cmt_sfs_gsim)
------------------------------------------------------------------------------
@@ -31,31 +32,26 @@ library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end s6_cmt_sfs;
architecture sim of s6_cmt_sfs is
signal CLK_DIVPULSE : slbit := '0';
signal CLKOUT_PERIOD : Delay_length := 0 ns;
signal R_CLKOUT : slbit := '0';
signal R_LOCKED : slbit := '0';
architecture sim of s6_cmt_sfs is
begin
proc_init : process
@@ -74,9 +70,8 @@ begin
variable t_pdmax : Delay_length := 0 ns;
begin
-- validate generics
-- validate generics
if not (GEN_TYPE = "PLL" or GEN_TYPE = "DCM") then
report "assert(GEN_TYPE='PLL' or GEN_TYPE='DCM')"
severity failure;
@@ -133,66 +128,16 @@ begin
wait;
end process proc_init;
proc_clkin : process (CLKIN)
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : Delay_length := 0 ns;
variable t_period : Delay_length := 0 ns;
variable nclkin : integer := 1;
begin
if CLKIN'event then
if CLKIN = '1' then -- if CLKIN rising edge
if t_lastclkin > 0 ns then
t_lastperiod := t_period;
t_period := now - t_lastclkin;
CLKOUT_PERIOD <= (t_period * VCO_DIVIDE * OUT_DIVIDE) / VCO_MULTIPLY;
if t_lastperiod > 0 ns and abs(t_period-t_lastperiod) > 1 ps then
report "s6_cmt_sp_sfs: CLKIN unstable" severity warning;
end if;
end if;
t_lastclkin := now;
if t_period > 0 ns then
nclkin := nclkin - 1;
if nclkin <= 0 then
nclkin := VCO_DIVIDE * OUT_DIVIDE;
CLK_DIVPULSE <= '1';
R_LOCKED <= '1';
end if;
end if;
else -- if CLKIN falling edge
CLK_DIVPULSE <= '0';
end if;
end if;
end process proc_clkin;
proc_clkout : process
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : Delay_length := 0 ns;
variable t_period : Delay_length := 0 ns;
variable nclkin : integer := 1;
begin
loop
wait until CLK_DIVPULSE = '1';
for i in 1 to VCO_MULTIPLY loop
R_CLKOUT <= '1';
wait for CLKOUT_PERIOD/2;
R_CLKOUT <= '0';
if i /= VCO_MULTIPLY then
wait for CLKOUT_PERIOD/2;
end if;
end loop; -- i
end loop;
end process proc_clkout;
CLKFX <= R_CLKOUT;
LOCKED <= R_LOCKED;
-- generate clock
SFS: sfs_gsim_core
generic map (
VCO_DIVIDE => VCO_DIVIDE,
VCO_MULTIPLY => VCO_MULTIPLY,
OUT_DIVIDE => OUT_DIVIDE)
port map (
CLKIN => CLKIN,
CLKFX => CLKFX,
LOCKED => LOCKED
);
end sim;

3
rtl/vlib/xlib/s7_cmt_sfs_gsim.vbom
View File

@@ -1,4 +1,7 @@
# libs
../slvtypes.vhd
xlib.vhd
# components
sfs_gsim_core.vbom
# design
s7_cmt_sfs_gsim.vhd

104
rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: s7_cmt_sfs_gsim.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: s7_cmt_sfs_gsim.vhd 1065 2018-11-04 11:32:06Z mueller $
--
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -19,47 +19,40 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Series-7
-- Tool versions: xst 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33
-- Tool versions: xst 14.5-14.7; viv 2014.4-2018.2; ghdl 0.29-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1065 1.2 use sfs_gsim_core
-- 2016-08-18 799 1.1.1 remove 'assert false' from report statements
-- 2016-04-09 760 1.1 BUGFIX: correct mmcm range check boundaries
-- 2013-09-28 535 1.0 Initial version (derived from dcm_sfs_gsim)
------------------------------------------------------------------------------
-- Note: for test bench usage a copy of s7_cmt_sfs_gsim, with _tb instead
-- of _gsim in file name, has been created in the /tb sub folder.
-- Ensure to update the copy when this file is changed !!
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity s7_cmt_sfs is -- 7-Series CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end s7_cmt_sfs;
architecture sim of s7_cmt_sfs is
signal CLK_DIVPULSE : slbit := '0';
signal CLKOUT_PERIOD : Delay_length := 0 ns;
signal R_CLKOUT : slbit := '0';
signal R_LOCKED : slbit := '0';
architecture sim of s7_cmt_sfs is
begin
proc_init : process
@@ -83,9 +76,8 @@ begin
variable t_pdmax : Delay_length := 0 ns;
begin
-- validate generics
-- validate generics
if not (GEN_TYPE = "PLL" or GEN_TYPE = "MMCM") then
report "assert(GEN_TYPE='PLL' or GEN_TYPE='MMCM')"
severity failure;
@@ -148,66 +140,16 @@ begin
wait;
end process proc_init;
proc_clkin : process (CLKIN)
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : Delay_length := 0 ns;
variable t_period : Delay_length := 0 ns;
variable nclkin : integer := 1;
begin
if CLKIN'event then
if CLKIN = '1' then -- if CLKIN rising edge
if t_lastclkin > 0 ns then
t_lastperiod := t_period;
t_period := now - t_lastclkin;
CLKOUT_PERIOD <= (t_period * VCO_DIVIDE * OUT_DIVIDE) / VCO_MULTIPLY;
if t_lastperiod > 0 ns and abs(t_period-t_lastperiod) > 1 ps then
report "s7_cmt_sp_sfs: CLKIN unstable" severity warning;
end if;
end if;
t_lastclkin := now;
if t_period > 0 ns then
nclkin := nclkin - 1;
if nclkin <= 0 then
nclkin := VCO_DIVIDE * OUT_DIVIDE;
CLK_DIVPULSE <= '1';
R_LOCKED <= '1';
end if;
end if;
else -- if CLKIN falling edge
CLK_DIVPULSE <= '0';
end if;
end if;
end process proc_clkin;
proc_clkout : process
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : Delay_length := 0 ns;
variable t_period : Delay_length := 0 ns;
variable nclkin : integer := 1;
begin
loop
wait until CLK_DIVPULSE = '1';
for i in 1 to VCO_MULTIPLY loop
R_CLKOUT <= '1';
wait for CLKOUT_PERIOD/2;
R_CLKOUT <= '0';
if i /= VCO_MULTIPLY then
wait for CLKOUT_PERIOD/2;
end if;
end loop; -- i
end loop;
end process proc_clkout;
CLKFX <= R_CLKOUT;
LOCKED <= R_LOCKED;
-- generate clock
SFS: sfs_gsim_core
generic map (
VCO_DIVIDE => VCO_DIVIDE,
VCO_MULTIPLY => VCO_MULTIPLY,
OUT_DIVIDE => OUT_DIVIDE)
port map (
CLKIN => CLKIN,
CLKFX => CLKFX,
LOCKED => LOCKED
);
end sim;

4
rtl/vlib/xlib/sfs_gsim_core.vbom Normal file
View File

@@ -0,0 +1,4 @@
# libs
../slvtypes.vhd
# design
sfs_gsim_core.vhd

113
rtl/vlib/xlib/sfs_gsim_core.vhd Normal file
View File

@@ -0,0 +1,113 @@
-- $Id: sfs_gsim_core.vhd 1065 2018-11-04 11:32:06Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sfs_gsim_core - sim
-- Description: simple frequency synthesis (SIM only!)
-- simple vhdl model, without Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 14.7; viv 2015.4-2018.2; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.0 Initial version (derived from s7_cmt_sfs_gsim)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity sfs_gsim_core is -- frequency synthesis for simulation
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1); -- output divide
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end sfs_gsim_core;
architecture sim of sfs_gsim_core is
signal CLK_DIVPULSE : slbit := '0';
signal CLKOUT_PERIOD : Delay_length := 0 ns;
signal R_CLKOUT : slbit := '0';
signal R_LOCKED : slbit := '0';
begin
proc_clkin : process (CLKIN)
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : Delay_length := 0 ns;
variable t_period : Delay_length := 0 ns;
variable nclkin : integer := 1;
begin
if CLKIN'event then
if CLKIN = '1' then -- if CLKIN rising edge
if t_lastclkin > 0 ns then
t_lastperiod := t_period;
t_period := now - t_lastclkin;
CLKOUT_PERIOD <= (t_period * VCO_DIVIDE * OUT_DIVIDE) / VCO_MULTIPLY;
if t_lastperiod > 0 ns and abs(t_period-t_lastperiod) > 1 ps then
report "sfs_gsim_core: CLKIN unstable" severity warning;
end if;
end if;
t_lastclkin := now;
if t_period > 0 ns then
nclkin := nclkin - 1;
if nclkin <= 0 then
nclkin := VCO_DIVIDE * OUT_DIVIDE;
CLK_DIVPULSE <= '1';
R_LOCKED <= '1';
end if;
end if;
else -- if CLKIN falling edge
CLK_DIVPULSE <= '0';
end if;
end if;
end process proc_clkin;
proc_clkout : process
begin
loop
wait until CLK_DIVPULSE = '1';
for i in 1 to VCO_MULTIPLY loop
R_CLKOUT <= '1';
wait for CLKOUT_PERIOD/2;
R_CLKOUT <= '0';
if i /= VCO_MULTIPLY then
wait for CLKOUT_PERIOD/2;
end if;
end loop; -- i
end loop;
end process proc_clkout;
CLKFX <= R_CLKOUT;
LOCKED <= R_LOCKED;
end sim;

4
rtl/vlib/xlib/tb/s7_cmt_sfs_tb.vbom
View File

@@ -1,4 +0,0 @@
# libs
../../slvtypes.vhd
# design
s7_cmt_sfs_tb.vhd

211
rtl/vlib/xlib/tb/s7_cmt_sfs_tb.vhd
View File

@@ -1,211 +0,0 @@
-- $Id: s7_cmt_sfs_tb.vhd 984 2018-01-02 20:56:27Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: s7_cmt_sfs_tb - sim
-- Description: Series-7 CMT for simple frequency synthesis (SIM only!)
-- simple vhdl model, without Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Series-7
-- Tool versions: xst 14.7; viv 2015.4-2016.2; ghdl 0.31-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-08-18 799 1.1.1 remove 'assert false' from report statements
-- 2016-04-09 760 1.1 BUGFIX: correct mmcm range check boundaries
-- 2016-02-20 734 1.0 Initial version (copied from s7_cmt_sfs_gsim)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity s7_cmt_sfs_tb is -- 7-Series CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end s7_cmt_sfs_tb;
architecture sim of s7_cmt_sfs_tb is
signal CLK_DIVPULSE : slbit := '0';
signal CLKOUT_PERIOD : Delay_length := 0 ns;
signal R_CLKOUT : slbit := '0';
signal R_LOCKED : slbit := '0';
begin
proc_init : process
-- currently frequency limits taken from Artix-7 speed grade -1
constant f_vcomin_pll : integer := 800;
constant f_vcomax_pll : integer := 1600;
constant f_pdmin_pll : integer := 19;
constant f_pdmax_pll : integer := 450;
constant f_vcomin_mmcm : integer := 600;
constant f_vcomax_mmcm : integer := 1200;
constant f_pdmin_mmcm : integer := 10;
constant f_pdmax_mmcm : integer := 450;
variable t_vco : Delay_length := 0 ns;
variable t_vcomin : Delay_length := 0 ns;
variable t_vcomax : Delay_length := 0 ns;
variable t_pd : Delay_length := 0 ns;
variable t_pdmin : Delay_length := 0 ns;
variable t_pdmax : Delay_length := 0 ns;
begin
-- validate generics
if not (GEN_TYPE = "PLL" or GEN_TYPE = "MMCM") then
report "assert(GEN_TYPE='PLL' or GEN_TYPE='MMCM')"
severity failure;
end if;
if VCO_DIVIDE/=1 or VCO_MULTIPLY/=1 or OUT_DIVIDE/=1 then
if GEN_TYPE = "PLL" then
-- check DIV/MULT parameter range
if VCO_DIVIDE<1 or VCO_DIVIDE>56 or
VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or
OUT_DIVIDE<1 or OUT_DIVIDE>128
then
report
"assert(VCO_DIVIDE in 1:56 VCO_MULTIPLY in 2:64 OUT_DIVIDE in 1:128)"
severity failure;
end if;
-- setup VCO and PD range check boundaries
t_vcomin := (1000 ns / f_vcomax_pll) - 1 ps;
t_vcomax := (1000 ns / f_vcomin_pll) + 1 ps;
t_pdmin := (1000 ns / f_pdmax_pll) - 1 ps;
t_pdmax := (1000 ns / f_pdmin_pll) + 1 ps;
end if; -- GEN_TYPE = "PLL"
if GEN_TYPE = "MMCM" then
-- check DIV/MULT parameter range
if VCO_DIVIDE<1 or VCO_DIVIDE>106 or
VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or
OUT_DIVIDE<1 or OUT_DIVIDE>128
then
report
"assert(VCO_DIVIDE in 1:106 VCO_MULTIPLY in 2:64 OUT_DIVIDE in 1:128)"
severity failure;
end if;
-- setup VCO and PD range check boundaries
t_vcomin := (1000 ns / f_vcomax_mmcm) - 1 ps;
t_vcomax := (1000 ns / f_vcomin_mmcm) + 1 ps;
t_pdmin := (1000 ns / f_pdmax_mmcm) - 1 ps;
t_pdmax := (1000 ns / f_pdmin_mmcm) + 1 ps;
end if; -- GEN_TYPE = "MMCM"
-- now common check whether VCO and PD frequency is in range
t_pd := (1 ps * (1000.0*CLKIN_PERIOD)) * VCO_DIVIDE;
t_vco := t_pd / VCO_MULTIPLY;
if t_vco<t_vcomin or t_vco>t_vcomax then
report "assert(VCO frequency out of range); t_cvo: "
& time'image(t_vco)
severity failure;
end if;
if t_pd<t_pdmin or t_pd>t_pdmax then
report "assert(PD frequency out of range)"
severity failure;
end if;
end if; -- one factor /= 1
wait;
end process proc_init;
proc_clkin : process (CLKIN)
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : Delay_length := 0 ns;
variable t_period : Delay_length := 0 ns;
variable nclkin : integer := 1;
begin
if CLKIN'event then
if CLKIN = '1' then -- if CLKIN rising edge
if t_lastclkin > 0 ns then
t_lastperiod := t_period;
t_period := now - t_lastclkin;
CLKOUT_PERIOD <= (t_period * VCO_DIVIDE * OUT_DIVIDE) / VCO_MULTIPLY;
if t_lastperiod > 0 ns and abs(t_period-t_lastperiod) > 1 ps then
report "s7_cmt_sp_sfs: CLKIN unstable" severity warning;
end if;
end if;
t_lastclkin := now;
if t_period > 0 ns then
nclkin := nclkin - 1;
if nclkin <= 0 then
nclkin := VCO_DIVIDE * OUT_DIVIDE;
CLK_DIVPULSE <= '1';
R_LOCKED <= '1';
end if;
end if;
else -- if CLKIN falling edge
CLK_DIVPULSE <= '0';
end if;
end if;
end process proc_clkin;
proc_clkout : process
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : Delay_length := 0 ns;
variable t_period : Delay_length := 0 ns;
variable nclkin : integer := 1;
begin
loop
wait until CLK_DIVPULSE = '1';
for i in 1 to VCO_MULTIPLY loop
R_CLKOUT <= '1';
wait for CLKOUT_PERIOD/2;
R_CLKOUT <= '0';
if i /= VCO_MULTIPLY then
wait for CLKOUT_PERIOD/2;
end if;
end loop; -- i
end loop;
end process proc_clkout;
CLKFX <= R_CLKOUT;
LOCKED <= R_LOCKED;
end sim;

47
rtl/vlib/xlib/xlib.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: xlib.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: xlib.vhd 1065 2018-11-04 11:32:06Z mueller $
--
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,9 +16,10 @@
-- Description: Xilinx specific components
--
-- Dependencies: -
-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.2; ghdl 0.18-0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.1 add sfs_gsim_core
-- 2016-04-02 758 1.0.11 add usr_access_unisim
-- 2013-10-06 538 1.0.10 add s6_cmt_sfs
-- 2013-09-28 535 1.0.9 add s7_cmt_sfs
@@ -173,48 +174,60 @@ end component;
component dcm_sfs is -- DCM for simple frequency synthesis
generic (
CLKFX_DIVIDE : positive := 2; -- FX clock divide (1-32)
CLKFX_DIVIDE : positive := 2; -- FX clock divide (1-32)
CLKFX_MULTIPLY : positive := 2; -- FX clock multiply (2-32) (1->no DCM)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- dcm locked
);
end component;
component s7_cmt_sfs is -- 7-Series CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end component;
component s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or DCM
GEN_TYPE : string := "PLL"); -- PLL or DCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end component;
component sfs_gsim_core is -- frequency synthesis for simulation
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1); -- output divide
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- clkin locked
);
end component;
component usr_access_unisim is -- wrapper for USR_ACCESS family
port (
DATA : out slv32 -- usr_access register value