diff --git a/Makefile b/Makefile index f212c639..6c364742 100644 --- a/Makefile +++ b/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 650 2015-02-22 21:39:47Z mueller $ +# $Id: Makefile 682 2015-05-15 18:35:29Z mueller $ # # 'Meta Makefile' for whole retro project # allows to make all synthesis targets @@ -121,7 +121,7 @@ default : @echo " make -j `nproc` all_sim_ise" @echo " make -j `nproc` all_syn_ise" @echo " make -j `nproc` all_sim_viv" - @echo " make -j `nproc` all_syn_viv" + @echo " make -j 1 all_syn_viv" @echo " make clean" @echo " make clean_sim_ise" @echo " make clean_syn_ise" diff --git a/doc/FILES.txt b/doc/FILES.txt index 04db055e..d8188873 100644 --- a/doc/FILES.txt +++ b/doc/FILES.txt @@ -1,4 +1,4 @@ -$Id: FILES.txt 645 2015-02-13 21:44:03Z mueller $ +$Id: FILES.txt 681 2015-05-14 17:37:00Z mueller $ Short description of the directory layout, what is where ? diff --git a/doc/README.txt b/doc/README.txt index 5e33c652..696437c1 100644 --- a/doc/README.txt +++ b/doc/README.txt @@ -1,4 +1,4 @@ -$Id: README.txt 680 2015-05-14 13:29:46Z mueller $ +$Id: README.txt 687 2015-06-05 09:03:34Z mueller $ Release notes for w11a @@ -22,6 +22,77 @@ Release notes for w11a 2. Change Log ---------------------------------------------------------------- +- trunk (2015-06-05: svn rev 31(oc) 687(wfjm); untagged w11a_V0.66) +++++++++ + - Preface + + - Since the previous release a full set of small, medium and large sized + disks (RK,RL,RP/RM) is available, covering all use cases. Still missing + was a tape system, which allows to install systems from distribution tapes + but is also very handy for data exchange. This release adds a TM11/TU10 + tape controller emulation. This is much simpler to implement than a + massbus based TU16 or TU78 controller. Because storage is emulated there + is neither a speed nor a capacity advantage of 1600 or 6250 bpi drives, + so for all practical purposes the simple 800 bpi TU10 drive emulation is + fully adequate. + The TM11/TU10 was tested under 211bsd with creating a tape distribution + kit and building a RP06 based system from such a tape. A 211bsd_tm + oskit is provided with a recipe to restore a RP06 from tape. + + - bug fixes + - the ti_rri event loop aborted under heavy load with three devices, seen + when RP disk, TM tape and DL11 run simultaneously. Was caused by a race + condition in attention handling and dispatching. + - the boot command failed when cpu was running and the unit not decoded + properly, so boots from units other then 0 failed. + + - Summary + - added TM11/TU10 tape support + + - New features + - new modules + - rtl/ibus/ibdr_rm11 - ibus controller for RM11 + - tools/bin + - file2tap - create a tap container from disk files + - tap2file - split a tap container into disk files + - tools/src/librw11 + - Rw11(Cntl|Unit)TM11 - Controller/Unit for TM11 + - Rw11UnitTape(|Base) - support for tape units + - Rw11VirtTape(|Tap) - virtual tapes (generic and tap containers) + - tools/tcl/rw11 + - tbench.tcl - support sub directories and return in tests + - new oskits + - tools/oskit/211bsd_tm - 2.11BSD tape distribution kit (for RP06) + + - Changes + - renames + - tools/tbench - the text benches were re-organized and + grouped now in sub directories: + cp for w11a control port + w11a for w11a CPU tests + rhrp for RHRP device tests + tm11 for TM11 device tests + - functional changes + - tools/bin/create_disk - add RM80 support + + - Bug fixes + - tools/src/librlink + - RlinkServer - fix race condition in attention handling + - tools/src/librw11 + - Rw11Cpu - stop cpu before load, proper unit handling + + - Known issues + - all issues: see README_known_issues.txt + - resolved issues: -- none -- + - new issues: + - V0.66-1: the TM11 controller transfers data byte wise (all disk do it + 16bit word wise) and allows for odd byte length transfers. Odd length + transfers are currently not supported and rejected as invalid command. + Odd byte length records aren't used by OS, if at all, so in practice + this limitation isn't relevant. + - V0.66-2: using two RP06 drives in parallel under 211bsd leads to a + hangup of the system after a short time. Currently only operation + of a single drive works reliably. + - trunk (2015-05-14: svn rev 30(oc) 681(wfjm); untagged w11a_V0.65) +++++++++ - Preface @@ -79,6 +150,7 @@ Release notes for w11a - rtl/vlib/serport - serport_master - serial port module, master side - rtl/ibus/ibd_ibmon - ibus monitor + - rtl/ibus/ibdr_rhrp - ibus controller for RH70 plus RP/RM drives - rtl/w11a/pdp11_sys70 - 11/70 system - single core +rbus,debug,cache - rtl/w11a/pdp11_hio70 - hio led and dsp for sys70 - tools/src/librw11 diff --git a/doc/README_known_issues.txt b/doc/README_known_issues.txt index dd41833d..3ede5d62 100644 --- a/doc/README_known_issues.txt +++ b/doc/README_known_issues.txt @@ -1,8 +1,17 @@ -$Id: README_known_issues.txt 680 2015-05-14 13:29:46Z mueller $ +$Id: README_known_issues.txt 687 2015-06-05 09:03:34Z mueller $ Known issues for this release. The case id indicates the release when the issue was first recognized. +- V0.66-1: the TM11 controller transfers data byte wise (all disk do it 16bit + word wise) and allows for odd byte length transfers. Odd length transfers + are currently not supported and rejected as invalid command. Odd byte + length records aren't used by OS, if at all, so in practice this limitation + isn't relevant. +- V0.66-2: using two RP06 drives in parallel under 211bsd leads to a hangup of + the system after a short time. Currently only operation of a single drive + works reliably. + - V0.65-1: ti_rri sometimes crashes in normal rundown (exit or ^D) when a cuff: type rlink is active. One gets terminate called after throwing an instance of 'Retro::Rexception' @@ -22,7 +31,7 @@ The case id indicates the release when the issue was first recognized. - V0.64-4: No support for the Vivado simulator (xsim) yet. With ghdl only functional simulations, post synthesis (_ssim) fails to compile. - V0.64-3: Highest baud rate with basys3 and nexys4 is 10 MBaud. 10 MBaud is - not supported according to FTDI, but works. 12 MBaud in next release. + not supported according to FTDI, but works. 12 MBaud in an upcoming release. - V0.64-2: rlink throughput on basys3/nexys4 limited by serial port stack round trip times. Will be overcome by libusb based custom driver. - V0.64-1: The large default transfer size for disk accesses leads to bad diff --git a/doc/man/man1/create_disk.1 b/doc/man/man1/create_disk.1 index 0a8c1d8d..e431b11e 100644 --- a/doc/man/man1/create_disk.1 +++ b/doc/man/man1/create_disk.1 @@ -1,11 +1,11 @@ .\" -*- nroff -*- -.\" $Id: create_disk.1 622 2014-12-28 20:45:26Z mueller $ +.\" $Id: create_disk.1 686 2015-06-04 21:08:08Z mueller $ .\" -.\" Copyright 2013- by Walter F.J. Mueller +.\" Copyright 2013-2015 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ . -.TH CREATE_DISK 1 2013-05-20 "Retro Project" "Retro Project Manual" +.TH CREATE_DISK 1 2015-06-04 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME create_disk \- create disk container file for ti_w11 @@ -43,11 +43,16 @@ option. determines whether the container file will be initialized with specific data pattern. Note that the \fB\-\-bad\fP and \fB\-\-boot\fP options will overwrite the last track or the first sector(s) respectively. +The default without \fB\-\-ini\fR is to create a container with all zero data. +It is implemented by writing a single zero byte after positioning with +\fBlseek\fR(2) to the desired end. This creates a file with 'holes' and defers +the actual allocation of disk space to the point when sectors are written. Allowed values for \fIpat\fP are .RS .IP \fBzero\fP -creates a disk with all sectors zero'ed. This is the default when no -\fB\-\-ini\fP option is given. +creates a disk with all sectors zero'ed. In this case zero's are explicitely +written. The explicit allocation of disk space is the main effect of this +option. .IP \fBones\fP creates a disk with all data bytes set to 0xff. .IP \fBdead\fP diff --git a/doc/man/man1/file2tap.1 b/doc/man/man1/file2tap.1 new file mode 100644 index 00000000..9526f6d4 --- /dev/null +++ b/doc/man/man1/file2tap.1 @@ -0,0 +1,73 @@ +.\" -*- nroff -*- +.\" $Id: file2tap.1 686 2015-06-04 21:08:08Z mueller $ +.\" +.\" Copyright 2015- by Walter F.J. Mueller +.\" +.\" ------------------------------------------------------------------ +. +.TH FILE2TAP 1 2015-06-03 "Retro Project" "Retro Project Manual" +.\" ------------------------------------------------------------------ +.SH NAME +file2tap \- create a tap format tape container from individual files +.\" ------------------------------------------------------------------ +.SH SYNOPSIS +. +.SY file2tap +.B -c +.I TNAM +.B -b +.I n +.IR FLIST ... +.SY file2tap +.B -a +.I TNAM +.B -b +.I n +.IR FLIST ... +.YS +. +.\" ------------------------------------------------------------------ +.SH DESCRIPTION +Creates (\fB-c\fR) a new or appends (\fB-a\fR) to an existing tap format tape +container file \fTNAM\fR and adds files. The tape record size is specified +with a \fB-b\fR option followed by the record size in units 512 bytes. +Each tape file is build from a comma separated list of disk files \fIFLIST\fR, +which are concatenated and written with a record size given by the last +\fB-b\fR option. + +\fBfile2tap\fR writes to stdout a one line message for each created file which +gives the file number, number of records, the record size in bytes and the +names of the disk files used to build the tape file. +. +.\" ------------------------------------------------------------------ +.SH OPTIONS +. +.\" ---------------------------------------------- +.IP "\fB\-c \fITNAM\fR" +create a new tap format tape container with the name \fITNAM\fR. +.IP "\fB\-a \fITNAM\fR" +append to the existing tap format tape container \fITNAM\fR. +.IP "\fB\-b \fIn\fR" +gives the record size, in units of 512 bytes, for the following files. +. +.\" ------------------------------------------------------------------ +.SH EXAMPLES +.IP "\fBfile2tap -c tape.tap -b 20 patch.tar\fR" 4 +converts the \fBtar\fR(1) archive file \fIpatch.tar\fR into a tape +container file \fItape.tap\fR. The record size is 20*512 or 10240 bytes, +the standard block size of Unix V7 format tar archives. + +.IP "\fBfile2tap -c tape.tap -b 1 b0,b1,b2 -b 2 f1 f2 -b 20 f3 f4 f5\fR" 4 +creates a tape container file \fItape.tap\fR with six tape files. The first +has a record length of 512 bytes and is composed of the concatenation of the +disk files \fIb0\fR, \fIb1\fR, and \fIb2\fR. The second and third tape file +have a record length of 1024 bytes and are created from \fIf1\fR and \fIf2\fR, +respectively. The remaining three files have a record length of 10240 bytes. + +.\" ------------------------------------------------------------------ +.SH "SEE ALSO" +.BR tap2file (1) + +.\" ------------------------------------------------------------------ +.SH AUTHOR +Walter F.J. Mueller diff --git a/doc/man/man1/tap2file.1 b/doc/man/man1/tap2file.1 new file mode 100644 index 00000000..b206d99d --- /dev/null +++ b/doc/man/man1/tap2file.1 @@ -0,0 +1,76 @@ +.\" -*- nroff -*- +.\" $Id: tap2file.1 686 2015-06-04 21:08:08Z mueller $ +.\" +.\" Copyright 2015- by Walter F.J. Mueller +.\" +.\" ------------------------------------------------------------------ +. +.TH TAP2FILE 1 2015-06-03 "Retro Project" "Retro Project Manual" +.\" ------------------------------------------------------------------ +.SH NAME +tap2file \- split a tap format tape container into individual files +.\" ------------------------------------------------------------------ +.SH SYNOPSIS +. +.SY tap2file +.OP \-\-pref=p +.I FILE +. +.SY tap2file +.B \-\-help +.YS +. +.\" ------------------------------------------------------------------ +.SH DESCRIPTION +Reads the tap format tape container \fIFILE\fR and creates for tape file an +individual disk file. The created files are named \fIpref\fR_nn.dat, where +\fIpref\fR is either the prefix given with the \fB\-\-pref\fR option or the +stem of \fIFILE\fR. + +\fBtap2file\fR writes to stdout a one line message for each created file which +gives the filename, the number of tape records and the record length. In case +the record length is variable the minimal and the maximal record length is given. +. +.\" ------------------------------------------------------------------ +.SH OPTIONS +. +.\" ---------------------------------------------- +.IP "\fB\-\-pref\fR=\fIp\fR" +use \fIp\fR as prefix to generate the names of all generated file. If not +specified the stem of the input file name is taken. +. +.\" ---------------------------------------------- +.IP "\fB\-help\fR" +print full help text and exit. +. +.\" ------------------------------------------------------------------ +.SH EXAMPLES +.IP "\fBtap2file tmscptape.tap\fR" 4 +reads the file \fItmscptape.tap\fR and creates a file for each tape file. +Because no \fB\-\-pref\fR option is given the output files will be named +"tmscptape_nn.dat". The stdout output might look like + +.EX + tmscptape_00.dat: 73 records, length 512 + tmscptape_01.dat: 38 records, length 1024 + tmscptape_02.dat: 34 records, length 1024 + tmscptape_03.dat: 36 records, length 1024 + tmscptape_04.dat: 33 records, length 1024 + tmscptape_05.dat: 501 records, length 10240 + tmscptape_06.dat: 3516 records, length 10240 + tmscptape_07.dat: 903 records, length 10240 + tmscptape_08.dat: 4168 records, length 10240 +.EE + +which indicates that the first file had 512 byte records, the next four 1024 +byte records, and the remaining ones 10240 byte records. In case of a tape +generated by a Unix system a record length of 10240 is a good hint this the +file contains a \fBtar\fR(1) archive. + +.\" ------------------------------------------------------------------ +.SH "SEE ALSO" +.BR file2tap (1) + +.\" ------------------------------------------------------------------ +.SH AUTHOR +Walter F.J. Mueller diff --git a/doc/w11a_tb_guide.txt b/doc/w11a_tb_guide.txt index ef37bb90..415f3212 100644 --- a/doc/w11a_tb_guide.txt +++ b/doc/w11a_tb_guide.txt @@ -1,4 +1,4 @@ -# $Id: w11a_tb_guide.txt 660 2015-03-29 22:10:16Z mueller $ +# $Id: w11a_tb_guide.txt 687 2015-06-05 09:03:34Z mueller $ Note: Only ISE based test benches are currently documented ! The Vivado test environemnt is still in it's infancy ! @@ -259,7 +259,12 @@ Guide to running w11a test benches cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb tbrun_tbwrri --lsuf tbench_dsim --pack rw11 --cuff tb_w11a_n2 \ - "rw11::setup_cpu" "rw11::tbench @w11a_all.dat" - -> 2638820.0 ns 131930: DONE - -> real 0m24.890s user 0m25.286s sys 0m0.439s + "rw11::setup_cpu" "rw11::tbench @cpu_all.dat" + -> 2847860.0 ns 142382: DONE + -> real 0m33.013s user 0m31.870s sys 0m0.569s + + tbrun_tbwrri --lsuf tbench_dsim --pack rw11 --cuff tb_w11a_n2 \ + "rw11::setup_cpu" "rw11::tbench @dev_all.dat" + -> 1058440.0 ns 52911: DONE + -> real 0m15.249s user 0m15.195s sys 0m0.236s diff --git a/rtl/ibus/ibdlib.vhd b/rtl/ibus/ibdlib.vhd index 374bc65b..e66a4b19 100644 --- a/rtl/ibus/ibdlib.vhd +++ b/rtl/ibus/ibdlib.vhd @@ -1,6 +1,6 @@ --- $Id: ibdlib.vhd 678 2015-05-10 16:23:02Z mueller $ +-- $Id: ibdlib.vhd 682 2015-05-15 18:35:29Z mueller $ -- --- Copyright 2008-2014 by Walter F.J. Mueller +-- Copyright 2008-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free diff --git a/rtl/ibus/ibdr_maxisys.vbom b/rtl/ibus/ibdr_maxisys.vbom index 4ade6eac..4cf4ffe2 100644 --- a/rtl/ibus/ibdr_maxisys.vbom +++ b/rtl/ibus/ibdr_maxisys.vbom @@ -9,6 +9,7 @@ ibd_kw11l.vbom ibdr_rhrp.vbom ibdr_rl11.vbom ibdr_rk11.vbom +ibdr_tm11.vbom ibdr_dl11.vbom ibdr_pc11.vbom ibdr_lp11.vbom diff --git a/rtl/ibus/ibdr_maxisys.vhd b/rtl/ibus/ibdr_maxisys.vhd index 11f1e916..954d6252 100644 --- a/rtl/ibus/ibdr_maxisys.vhd +++ b/rtl/ibus/ibdr_maxisys.vhd @@ -1,4 +1,4 @@ --- $Id: ibdr_maxisys.vhd 679 2015-05-13 17:38:46Z mueller $ +-- $Id: ibdr_maxisys.vhd 683 2015-05-17 21:54:35Z mueller $ -- -- Copyright 2009-2015 by Walter F.J. Mueller -- @@ -20,6 +20,7 @@ -- ibdr_rhrp -- ibdr_rl11 -- ibdr_rk11 +-- ibdr_tm11 -- ibdr_dl11 -- ibdr_pc11 -- ibdr_lp11 @@ -41,6 +42,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-05-15 683 1.3.1 add TM11 -- 2015-05-10 678 1.3 start/stop/suspend overhaul -- 2015-04-06 664 1.2.3 rename RPRM to RHRP -- 2015-03-14 658 1.2.2 add RPRM; rearrange intmap (+rhrp,tm11,-kw11-l) @@ -294,6 +296,20 @@ begin ); end generate RK11; + TM11: if sys_conf_ibd_tm11 generate + begin + I0 : ibdr_tm11 + port map ( + CLK => CLK, + BRESET => BRESET, + RB_LAM => RB_LAM_TM11, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_TM11, + EI_REQ => EI_REQ_TM11, + EI_ACK => EI_ACK_TM11 + ); + end generate TM11; + DL11_0 : ibdr_dl11 port map ( CLK => CLK, diff --git a/rtl/ibus/ibdr_rhrp.vhd b/rtl/ibus/ibdr_rhrp.vhd index 65932458..9bacff94 100644 --- a/rtl/ibus/ibdr_rhrp.vhd +++ b/rtl/ibus/ibdr_rhrp.vhd @@ -1,4 +1,4 @@ --- $Id: ibdr_rhrp.vhd 680 2015-05-14 13:29:46Z mueller $ +-- $Id: ibdr_rhrp.vhd 682 2015-05-15 18:35:29Z mueller $ -- -- Copyright 2015- by Walter F.J. Mueller -- @@ -27,6 +27,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-05-15 682 1.0.1 correct ibsel range select logic -- 2015-05-14 680 1.0 Initial version -- 2015-03-15 658 0.1 First draft ------------------------------------------------------------------------------ @@ -463,7 +464,6 @@ begin variable iomux : slv4 := (others=>'0'); -- omux select variable iamap : slv5 := (others=>'0'); -- mem mapped address variable imask : slv16 := (others=>'0'); -- implemented bits mask - variable inxr : slbit := '0'; -- non-existent register variable imbreg : slbit := '0'; -- massbus register variable inormr : slbit := '0'; -- inhibit rmr protect @@ -506,7 +506,6 @@ begin iomux := (others=>'0'); iamap := (others=>'0'); imask := (others=>'1'); -- default: all bits ok - inxr := '0'; imbreg := '0'; inormr := '0'; @@ -527,7 +526,7 @@ begin n.ibsel := '0'; if IB_MREQ.aval = '1' and IB_MREQ.addr(12 downto 6) = ibaddr_rhrp(12 downto 6) and - unsigned(ibaddr_rhrp(5 downto 0)) <= unsigned(ibaddr_cs3) then + unsigned(IB_MREQ.addr(5 downto 1)) <= unsigned(ibaddr_cs3) then n.ibsel := '1'; end if; @@ -710,8 +709,9 @@ begin when ibaddr_cs3 => -- RxCS3 control reg 3 iomux := omux_cs3; - when others => -- unknown register - inxr := '1'; + when others => null; -- doesn't happen, ibsel only for + -- subrange up to cs3, and all + -- 22 regs are decoded above end case; -- case IB_MREQ.addr n.amap := iamap; @@ -767,15 +767,11 @@ begin end if; elsif IB_MREQ.re = '1' then -- read request - if inxr = '1' then -- unknown register - ibreq := '0'; -- suppress ack & hold --> ibus err + if ibrem='0' and imbreg='1' and ined='1' then + n.cs2ned := '1'; -- signal error else - if ibrem='0' and imbreg='1' and ined='1' then - n.cs2ned := '1'; -- signal error - else - ibhold := '1'; - n.state := s_read; - end if; + ibhold := '1'; + n.state := s_read; end if; end if; -- if IB_MREQ.we .. elsif IB_MREQ.re diff --git a/rtl/ibus/ibdr_tm11.vbom b/rtl/ibus/ibdr_tm11.vbom new file mode 100644 index 00000000..ac2ba047 --- /dev/null +++ b/rtl/ibus/ibdr_tm11.vbom @@ -0,0 +1,6 @@ +# libs +../vlib/slvtypes.vhd +iblib.vhd +# components +# design +ibdr_tm11.vhd diff --git a/rtl/ibus/ibdr_tm11.vhd b/rtl/ibus/ibdr_tm11.vhd new file mode 100644 index 00000000..c771576f --- /dev/null +++ b/rtl/ibus/ibdr_tm11.vhd @@ -0,0 +1,423 @@ +-- $Id: ibdr_tm11.vhd 686 2015-06-04 21:08:08Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: ibdr_tm11 - syn +-- Description: ibus dev(rem): TM11 +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2015-06-04 686 14.7 131013 xc6slx16-2 79 144 0 53 s 4.4 +-- 2015-05-15 682 14.7 131013 xc6slx16-2 117 209 0 76 s 3.7 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-06-04 686 1.0 Initial version +-- 2015-05-15 682 0.1 First draft +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.iblib.all; + +-- ---------------------------------------------------------------------------- +entity ibdr_tm11 is -- ibus dev(rem): TM11 + -- fixed address: 172520 + port ( + CLK : in slbit; -- clock + BRESET : in slbit; -- ibus reset + RB_LAM : out slbit; -- remote attention + IB_MREQ : in ib_mreq_type; -- ibus request + IB_SRES : out ib_sres_type; -- ibus response + EI_REQ : out slbit; -- interrupt request + EI_ACK : in slbit -- interrupt acknowledge + ); +end ibdr_tm11; + +architecture syn of ibdr_tm11 is + + constant ibaddr_tm11 : slv16 := slv(to_unsigned(8#172520#,16)); + + constant ibaddr_sr : slv3 := "000"; -- sr address offset + constant ibaddr_cr : slv3 := "001"; -- cr address offset + constant ibaddr_bc : slv3 := "010"; -- bc address offset + constant ibaddr_ba : slv3 := "011"; -- ba address offset + constant ibaddr_db : slv3 := "100"; -- db address offset + constant ibaddr_rl : slv3 := "101"; -- rl address offset + + constant sr_ibf_icmd : integer := 15; + constant sr_ibf_eof : integer := 14; + constant sr_ibf_pae : integer := 12; + constant sr_ibf_eot : integer := 10; + constant sr_ibf_rle : integer := 9; + constant sr_ibf_bte : integer := 8; + constant sr_ibf_nxm : integer := 7; + constant sr_ibf_onl : integer := 6; + constant sr_ibf_bot : integer := 5; + constant sr_ibf_wrl : integer := 2; + constant sr_ibf_rew : integer := 1; + constant sr_ibf_tur : integer := 0; + + constant cr_ibf_err : integer := 15; + subtype cr_ibf_den is integer range 14 downto 13; + constant cr_ibf_ini : integer := 12; + constant cr_ibf_pevn : integer := 11; + constant cr_ibf_unit2 : integer := 10; + subtype cr_ibf_unit is integer range 9 downto 8; + constant cr_ibf_rdy : integer := 7; + constant cr_ibf_ie : integer := 6; + subtype cr_ibf_ea is integer range 5 downto 4; + subtype cr_ibf_func is integer range 3 downto 1; + constant cr_ibf_go : integer := 0; + + subtype ba_ibf_ba is integer range 15 downto 1; + subtype db_ibf_db is integer range 7 downto 0; + + constant rl_ibf_reof : integer := 10; + constant rl_ibf_reot : integer := 9; + constant rl_ibf_ronl : integer := 8; + constant rl_ibf_rbot : integer := 7; + constant rl_ibf_rwrl : integer := 6; + constant rl_ibf_rrew : integer := 5; + subtype rl_ibf_runit is integer range 2 downto 1; + + constant func_unload : slv3 := "000"; -- func: unload + constant func_read : slv3 := "001"; -- func: read + constant func_write : slv3 := "010"; -- func: write + constant func_weof : slv3 := "011"; -- func: write eof + constant func_sforw : slv3 := "100"; -- func: space forward + constant func_sback : slv3 := "101"; -- func: space backward + constant func_wrteg : slv3 := "110"; -- func: write extend interrec gap + constant func_rewind : slv3 := "111"; -- func: rewind + + constant rfunc_wunit : slv3 := "001"; -- rem func: write runit + constant rfunc_done : slv3 := "010"; -- rem func: done (set rdy) + + -- cs1 usage for rem functions + subtype cr_ibf_runit is integer range 5 downto 4; -- new runit (_wunit) + constant cr_ibf_ricmd : integer := 15; -- new icmd (_done) + constant cr_ibf_rpae : integer := 12; -- new pae (_done) + constant cr_ibf_rrle : integer := 9; -- new rle (_done) + constant cr_ibf_rbte : integer := 8; -- new bte (_done) + constant cr_ibf_rnxm : integer := 7; -- new nxm (_done) + constant cr_ibf_reaena : integer := 6; -- ena ea (_done) + subtype cr_ibf_rea is integer range 5 downto 4; -- new ea (_done) + + type regs_type is record -- state registers + ibsel : slbit; -- ibus select + sricmd : slbit; -- sr: invalid command + srpae: slbit; -- sr: parity error + srrle: slbit; -- sr: record length error + srbte: slbit; -- sr: bad tape error + srnxm: slbit; -- sr: non-existant memory + sreof: slv4; -- sr: eof-of-file + sreot: slv4; -- sr: eof-of-tape + sronl: slv4; -- sr: online + srbot: slv4; -- sr: begin-of-tape + srwrl: slv4; -- sr: write-locked + srrew: slv4; -- sr: rewinding + crden: slv2; -- cr: density + crpevn: slbit; -- cr: even oarity + crunit2: slbit; -- cr: unit[2] + crunit: slv2; -- cr: unit[1:0] + crrdy: slbit; -- cr: controller ready + crie: slbit; -- cr: interrupt enable + crea: slv2; -- cr: address extension + crfunc: slv3; -- cr: func code + bc : slv16; -- bc: byte count + ba : slv16_1; -- ba: bus address + runit : slv2; -- rem access unit + resreq : slbit; -- reset requested + ireq : slbit; -- interrupt request flag + end record regs_type; + + constant regs_init : regs_type := ( + '0', -- ibsel + '0','0','0','0','0', -- sricmd,srpae,srrle,srbte,srnxm + (others=>'0'), -- sreof + (others=>'0'), -- sreot + (others=>'0'), -- sronl + (others=>'0'), -- srbot + (others=>'0'), -- srwrl + (others=>'0'), -- srrew + (others=>'0'), -- crden + '0','0', -- crpevn,crunit2 + (others=>'0'), -- crunit + '1','0', -- crrdy, crie + (others=>'0'), -- crea + (others=>'0'), -- crfunc + (others=>'0'), -- bc + (others=>'0'), -- ba + (others=>'0'), -- runit + '0', -- resreq + '0' -- ireq + ); + + signal R_REGS : regs_type := regs_init; + signal N_REGS : regs_type := regs_init; + +begin + + proc_regs: process (CLK) + begin + if rising_edge(CLK) then + R_REGS <= N_REGS; + end if; + end process proc_regs; + + proc_next : process (R_REGS, IB_MREQ, EI_ACK) + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + variable ibhold : slbit := '0'; + variable idout : slv16 := (others=>'0'); + variable ibrem : slbit := '0'; + variable ibreq : slbit := '0'; + variable ibrd : slbit := '0'; + variable ibw0 : slbit := '0'; + variable ibw1 : slbit := '0'; + variable ibwrem : slbit := '0'; + variable ilam : slbit := '0'; + + begin + + r := R_REGS; + n := R_REGS; + + ibhold := '0'; + idout := (others=>'0'); + ibrem := IB_MREQ.racc; + ibreq := IB_MREQ.re or IB_MREQ.we; + ibrd := IB_MREQ.re; + ibw0 := IB_MREQ.we and IB_MREQ.be0; + ibw1 := IB_MREQ.we and IB_MREQ.be1; + ibwrem := IB_MREQ.we and ibrem; + ilam := '0'; + + -- ibus address decoder + n.ibsel := '0'; + if IB_MREQ.aval = '1' and + IB_MREQ.addr(12 downto 4)=ibaddr_tm11(12 downto 4) and + unsigned(IB_MREQ.addr(3 downto 1)) <= unsigned(ibaddr_rl) then + n.ibsel := '1'; + end if; + + -- ibus transactions + + if r.ibsel='1' then -- selected + + case IB_MREQ.addr(3 downto 1) is + + when ibaddr_sr => -- SR -- status register ---------- + idout(sr_ibf_icmd) := r.sricmd; + idout(sr_ibf_pae) := r.srpae; + idout(sr_ibf_rle) := r.srrle; + idout(sr_ibf_bte) := r.srbte; + idout(sr_ibf_nxm) := r.srnxm; + idout(sr_ibf_tur) := r.crrdy; -- FIXME: is this correct ?? + -- only units 0,..3 supported, for unit 4,..,7 return 0 --> ONL=0 + if r.crunit2 = '0' then + idout(sr_ibf_eof) := r.sreof(to_integer(unsigned(r.crunit))); + idout(sr_ibf_eot) := r.sreot(to_integer(unsigned(r.crunit))); + idout(sr_ibf_onl) := r.sronl(to_integer(unsigned(r.crunit))); + idout(sr_ibf_bot) := r.srbot(to_integer(unsigned(r.crunit))); + idout(sr_ibf_wrl) := r.srwrl(to_integer(unsigned(r.crunit))); + idout(sr_ibf_rew) := r.srrew(to_integer(unsigned(r.crunit))); + end if; + + when ibaddr_cr => -- CR -- control register --------- + idout(cr_ibf_err) := r.sricmd or + r.sreof(to_integer(unsigned(r.crunit))) or + r.srpae or + r.sreot(to_integer(unsigned(r.crunit))) or + r.srrle or + r.srnxm; + idout(cr_ibf_den) := r.crden; + idout(cr_ibf_pevn) := r.crpevn; + idout(cr_ibf_unit2) := r.crunit2; + idout(cr_ibf_unit) := r.crunit; + idout(cr_ibf_rdy) := r.crrdy; + idout(cr_ibf_ie) := r.crie; + idout(cr_ibf_ea) := r.crea; + idout(cr_ibf_func) := r.crfunc; + + if IB_MREQ.we = '1' then + if ibrem = '0' then + + if r.crrdy = '1' then + if IB_MREQ.be1 = '1' then + n.crden := IB_MREQ.din(cr_ibf_den); + if IB_MREQ.din(cr_ibf_ini) = '1' then + n.resreq := '1'; + end if; + n.crpevn := IB_MREQ.din(cr_ibf_pevn); + n.crunit2 := IB_MREQ.din(cr_ibf_unit2); + n.crunit := IB_MREQ.din(cr_ibf_unit); + end if; + if IB_MREQ.be0 = '1' then + n.crie := IB_MREQ.din(cr_ibf_ie); + if n.crie = '0' then -- if IE set to 0 + n.ireq := '0'; -- cancel pending interrupt + end if; + n.crea := IB_MREQ.din(cr_ibf_ea); + n.crfunc := IB_MREQ.din(cr_ibf_func); + + if IB_MREQ.din(cr_ibf_go) = '1' then + n.sricmd := '0'; -- clear errors + n.srpae := '0'; + n.srrle := '0'; + n.srbte := '0'; + n.srnxm := '0'; + n.sreof := (others=>'0'); -- clear position status flags + n.sreot := (others=>'0'); + n.srbot := (others=>'0'); + n.srrew := (others=>'0'); + n.crrdy := '0'; -- mark busy + ilam := '1'; -- rri lam + else + if r.crie='0' and n.crie='1' then -- if IDE 0->1 transition + n.ireq := '1'; -- issue software interrupt + end if; + end if; + end if; + else + n.sricmd := '1'; + end if; + + else -- rem write access. GO not checked + -- always treated as remote function + case IB_MREQ.din(cr_ibf_func) is + when rfunc_wunit => -- rfunc: wunit ----------------- + n.runit := IB_MREQ.din(cr_ibf_runit); + + when rfunc_done => -- rfunc: done ------------------ + n.sricmd := IB_MREQ.din(cr_ibf_ricmd); + n.srpae := IB_MREQ.din(cr_ibf_rpae); + n.srrle := IB_MREQ.din(cr_ibf_rrle); + n.srbte := IB_MREQ.din(cr_ibf_rbte); + n.srnxm := IB_MREQ.din(cr_ibf_rnxm); + if IB_MREQ.din(cr_ibf_reaena) = '1' then + n.crea := IB_MREQ.din(cr_ibf_rea); + end if; + n.crrdy := '1'; + if r.crie = '1' then + n.ireq := '1'; + end if; + + when others => null; -- <> + end case; + + end if; -- if ibrem + + end if; -- if IB_MREQ.we='1' + + when ibaddr_bc => -- BC -- byte count register ------- + idout := r.bc; + if ibw1 = '1' then + n.bc(15 downto 8) := IB_MREQ.din(15 downto 8); + end if; + if ibw0 = '1' then + n.bc( 7 downto 0) := IB_MREQ.din( 7 downto 0); + end if; + + when ibaddr_ba => -- BA -- bus address register ------ + idout(ba_ibf_ba) := r.ba; + if ibw1 = '1' then + n.ba(15 downto 8) := IB_MREQ.din(15 downto 8); + end if; + if ibw0 = '1' then + n.ba( 7 downto 1) := IB_MREQ.din( 7 downto 1); + end if; + + when ibaddr_db => -- DB -- data buffer --------------- + null; + + when ibaddr_rl => -- RL -- read lines ---------------- + if ibrem = '0' then + null; + else + idout(rl_ibf_reof) := r.sreof(to_integer(unsigned(r.runit))); + idout(rl_ibf_reot) := r.sreot(to_integer(unsigned(r.runit))); + idout(rl_ibf_ronl) := r.sronl(to_integer(unsigned(r.runit))); + idout(rl_ibf_rbot) := r.srbot(to_integer(unsigned(r.runit))); + idout(rl_ibf_rwrl) := r.srwrl(to_integer(unsigned(r.runit))); + idout(rl_ibf_rrew) := r.srrew(to_integer(unsigned(r.runit))); + idout(rl_ibf_runit) := r.runit; + if IB_MREQ.we = '1' then + n.sreof(to_integer(unsigned(r.runit))) := IB_MREQ.din(rl_ibf_reof); + n.sreot(to_integer(unsigned(r.runit))) := IB_MREQ.din(rl_ibf_reot); + n.sronl(to_integer(unsigned(r.runit))) := IB_MREQ.din(rl_ibf_ronl); + n.srbot(to_integer(unsigned(r.runit))) := IB_MREQ.din(rl_ibf_rbot); + n.srwrl(to_integer(unsigned(r.runit))) := IB_MREQ.din(rl_ibf_rwrl); + n.srrew(to_integer(unsigned(r.runit))) := IB_MREQ.din(rl_ibf_rrew); + end if; + end if; + + when others => -- doesn't happen, ibsel only for + -- subrange up to rl, and all regs are + -- decoded above + null; + + end case; + end if; + + if BRESET = '1' then + n.resreq := '1'; + end if; + + if r.resreq = '1' then + n.sricmd := '0'; + n.srpae := '0'; + n.srrle := '0'; + n.srbte := '0'; + n.srnxm := '0'; + n.sreof := (others=>'0'); + n.sreot := (others=>'0'); + n.crden := (others=>'0'); + n.crpevn := '0'; + n.crunit2 := '0'; + n.crunit := (others=>'0'); + n.crrdy := '1'; + n.crie := '0'; + n.crea := (others=>'0'); + n.crfunc := (others=>'0'); + n.bc := (others=>'0'); + n.ba := (others=>'0'); + n.resreq := '0'; + n.ireq := '0'; + end if; + + if EI_ACK = '1' or n.crie = '0' then -- interrupt executed or ie disabled + n.ireq := '0'; -- cancel request + end if; + + N_REGS <= n; + + IB_SRES.dout <= idout; + IB_SRES.ack <= r.ibsel and ibreq; + IB_SRES.busy <= ibhold and ibreq; + + RB_LAM <= ilam; + EI_REQ <= r.ireq; + + end process proc_next; + + +end syn; diff --git a/rtl/sys_gen/w11a/basys3/sys_conf.vhd b/rtl/sys_gen/w11a/basys3/sys_conf.vhd index 47baf032..e0f19339 100644 --- a/rtl/sys_gen/w11a/basys3/sys_conf.vhd +++ b/rtl/sys_gen/w11a/basys3/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: sys_conf.vhd 683 2015-05-17 21:54:35Z mueller $ -- -- Copyright 2015- by Walter F.J. Mueller -- @@ -70,6 +70,7 @@ package sys_conf is constant sys_conf_ibd_rk11 : boolean := true; -- RK11 constant sys_conf_ibd_rl11 : boolean := true; -- RL11 constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 -- configure other devices constant sys_conf_ibd_iist : boolean := true; -- IIST diff --git a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd index 4bb267b6..cded624c 100644 --- a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd +++ b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_b3.vhd 677 2015-05-09 21:52:32Z mueller $ +-- $Id: sys_w11a_b3.vhd 686 2015-06-04 21:08:08Z mueller $ -- -- Copyright 2015- by Walter F.J. Mueller -- @@ -34,6 +34,8 @@ -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic +-- 2015-06-04 686 2014.4 xc7a35t-1 1919 4372 162 47.5 1408 +TM11 17% +-- 2015-05-14 680 2014.4 xc7a35t-1 1837 4304 162 47.5 1354 +RHRP 17% -- 2015-02-21 649 2014.4 xc7a35t-1 1637 3767 146 47.5 1195 -- -- Revision History: diff --git a/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd index 31ae4ae5..469d3d50 100644 --- a/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: sys_conf_sim.vhd 683 2015-05-17 21:54:35Z mueller $ -- -- Copyright 2015- by Walter F.J. Mueller -- @@ -70,6 +70,7 @@ package sys_conf is constant sys_conf_ibd_rk11 : boolean := true; -- RK11 constant sys_conf_ibd_rl11 : boolean := true; -- RL11 constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 -- configure other devices constant sys_conf_ibd_iist : boolean := true; -- IIST diff --git a/rtl/sys_gen/w11a/nexys2/sys_conf.vhd b/rtl/sys_gen/w11a/nexys2/sys_conf.vhd index 0153566f..a47744c5 100644 --- a/rtl/sys_gen/w11a/nexys2/sys_conf.vhd +++ b/rtl/sys_gen/w11a/nexys2/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: sys_conf.vhd 683 2015-05-17 21:54:35Z mueller $ -- -- Copyright 2010-2015 by Walter F.J. Mueller -- @@ -78,6 +78,7 @@ package sys_conf is constant sys_conf_ibd_rk11 : boolean := true; -- RK11 constant sys_conf_ibd_rl11 : boolean := true; -- RL11 constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 -- configure other devices constant sys_conf_ibd_iist : boolean := true; -- IIST diff --git a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd index f411a03b..4e5d5562 100644 --- a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd +++ b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_n2.vhd 677 2015-05-09 21:52:32Z mueller $ +-- $Id: sys_w11a_n2.vhd 686 2015-06-04 21:08:08Z mueller $ -- -- Copyright 2010-2015 by Walter F.J. Mueller -- @@ -34,6 +34,8 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2015-06-04 686 14.7 131013 xc3s1200e-4 2311 6725 414 4198 ok: +TM11 +-- 2015-05-14 680 14.7 131013 xc3s1200e-4 2232 6547 414 4083 ok: +RHRP -- 2015-02-21 649 14.7 131013 xc3s1200e-4 1903 5512 382 3483 ok: +RL11 -- 2014-12-22 619 14.7 131013 xc3s1200e-4 1828 5131 366 3263 ok: +rbmon -- 2014-12-20 614 14.7 131013 xc3s1200e-4 1714 4896 366 3125 ok: -RL11,rlv4 diff --git a/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd index aed25877..7fb5b168 100644 --- a/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: sys_conf_sim.vhd 683 2015-05-17 21:54:35Z mueller $ -- -- Copyright 2010-2015 by Walter F.J. Mueller -- @@ -73,6 +73,7 @@ package sys_conf is constant sys_conf_ibd_rk11 : boolean := true; -- RK11 constant sys_conf_ibd_rl11 : boolean := true; -- RL11 constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 -- configure other devices constant sys_conf_ibd_iist : boolean := true; -- IIST diff --git a/rtl/sys_gen/w11a/nexys3/sys_conf.vhd b/rtl/sys_gen/w11a/nexys3/sys_conf.vhd index edbf8842..eadd776c 100644 --- a/rtl/sys_gen/w11a/nexys3/sys_conf.vhd +++ b/rtl/sys_gen/w11a/nexys3/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: sys_conf.vhd 683 2015-05-17 21:54:35Z mueller $ -- -- Copyright 2011-2015 by Walter F.J. Mueller -- @@ -85,6 +85,7 @@ package sys_conf is constant sys_conf_ibd_rk11 : boolean := true; -- RK11 constant sys_conf_ibd_rl11 : boolean := true; -- RL11 constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 -- configure other devices constant sys_conf_ibd_iist : boolean := true; -- IIST diff --git a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd index e693733b..0ab86894 100644 --- a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd +++ b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_n3.vhd 677 2015-05-09 21:52:32Z mueller $ +-- $Id: sys_w11a_n3.vhd 686 2015-06-04 21:08:08Z mueller $ -- -- Copyright 2011-2015 by Walter F.J. Mueller -- @@ -34,7 +34,8 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri --- 2015-04-25 668 14.7 131013 xc6slx16-2 2101 4420 167 1520 ok: +ibmon 66% +-- 2015-06-04 686 14.7 131013 xc6slx16-2 2189 4492 161 1543 ok: +TM11 67% +-- 2015-05-14 680 14.7 131013 xc6slx16-2 2120 4443 161 1546 ok: +ibmon 67% -- 2015-04-06 664 14.7 131013 xc6slx16-2 1991 4350 167 1489 ok: +RHRP 65% -- 2015-02-21 649 14.7 131013 xc6slx16-2 1819 3905 160 1380 ok: +RL11 -- 2014-12-22 619 14.7 131013 xc6slx16-2 1742 3767 150 1350 ok: +rbmon diff --git a/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd index c5142c18..9a164f62 100644 --- a/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: sys_conf_sim.vhd 683 2015-05-17 21:54:35Z mueller $ -- -- Copyright 2011-2015 by Walter F.J. Mueller -- @@ -72,6 +72,7 @@ package sys_conf is constant sys_conf_ibd_rk11 : boolean := true; -- RK11 constant sys_conf_ibd_rl11 : boolean := true; -- RL11 constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 -- configure other devices constant sys_conf_ibd_iist : boolean := true; -- IIST diff --git a/rtl/sys_gen/w11a/nexys4/sys_conf.vhd b/rtl/sys_gen/w11a/nexys4/sys_conf.vhd index 2e731467..aebdfbb9 100644 --- a/rtl/sys_gen/w11a/nexys4/sys_conf.vhd +++ b/rtl/sys_gen/w11a/nexys4/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: sys_conf.vhd 683 2015-05-17 21:54:35Z mueller $ -- -- Copyright 2013-2015 by Walter F.J. Mueller -- @@ -79,6 +79,7 @@ package sys_conf is constant sys_conf_ibd_rk11 : boolean := true; -- RK11 constant sys_conf_ibd_rl11 : boolean := true; -- RL11 constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 -- configure other devices constant sys_conf_ibd_iist : boolean := true; -- IIST diff --git a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd index 87ee7dd0..6d29e378 100644 --- a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd +++ b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_n4.vhd 677 2015-05-09 21:52:32Z mueller $ +-- $Id: sys_w11a_n4.vhd 686 2015-06-04 21:08:08Z mueller $ -- -- Copyright 2013-2015 by Walter F.J. Mueller -- @@ -33,9 +33,11 @@ -- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 -- -- Synthesized: --- Date Rev viv Target flop lutl lutm bram slic --- 2015-02-22 650 2014.4 xc7a100t-1 1606 3652 146 3.5 1158 80 MHz --- 2015-02-22 650 i 17.7 xc7a100t-1 1670 3564 124 1508 80 MHz +-- Date Rev viv Target flop lutl lutm bram slic MHz +-- 2015-06-04 686 2014.4 xc7a100t-1 2111 4541 162 7.5 1469 80 +TM11 +-- 2015-05-14 680 2014.4 xc7a100t-1 2030 4459 162 7.5 1427 80 +-- 2015-02-22 650 2014.4 xc7a100t-1 1606 3652 146 3.5 1158 80 +-- 2015-02-22 650 i 17.7 xc7a100t-1 1670 3564 124 1508 80 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd index 8a7b8252..470cfb62 100644 --- a/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: sys_conf_sim.vhd 683 2015-05-17 21:54:35Z mueller $ -- -- Copyright 2013-2015 by Walter F.J. Mueller -- @@ -70,6 +70,7 @@ package sys_conf is constant sys_conf_ibd_rk11 : boolean := true; -- RK11 constant sys_conf_ibd_rl11 : boolean := true; -- RL11 constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 -- configure other devices constant sys_conf_ibd_iist : boolean := true; -- IIST diff --git a/rtl/sys_gen/w11a/s3board/sys_conf.vhd b/rtl/sys_gen/w11a/s3board/sys_conf.vhd index f25ac3c3..bc0982da 100644 --- a/rtl/sys_gen/w11a/s3board/sys_conf.vhd +++ b/rtl/sys_gen/w11a/s3board/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 673 2015-05-03 08:34:52Z mueller $ +-- $Id: sys_conf.vhd 683 2015-05-17 21:54:35Z mueller $ -- -- Copyright 2007-2015 by Walter F.J. Mueller -- @@ -56,6 +56,7 @@ package sys_conf is constant sys_conf_ibd_rk11 : boolean := true; -- RK11 constant sys_conf_ibd_rl11 : boolean := true; -- RL11 constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 -- configure other devices constant sys_conf_ibd_iist : boolean := true; -- IIST diff --git a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd index de2a9c9e..32234671 100644 --- a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd +++ b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_s3.vhd 677 2015-05-09 21:52:32Z mueller $ +-- $Id: sys_w11a_s3.vhd 686 2015-06-04 21:08:08Z mueller $ -- -- Copyright 2007-2015 by Walter F.J. Mueller -- @@ -33,7 +33,8 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri --- 2015-05-02 673 14.7 131013 xc3s1000-4 2054 6196 350 3858 OK: +RHRP 50% +-- 2015-06-04 686 14.7 131013 xc3s1000-4 2158 6453 350 3975 OK: +TM11 51% +-- 2015-05-14 680 14.7 131013 xc3s1000-4 2087 6316 350 3928 OK: +RHRP 51% -- 2015-02-21 649 14.7 131013 xc3s1000-4 1643 5124 318 3176 OK: +RL11 -- 2014-12-22 619 14.7 131013 xc3s1000-4 1569 4768 302 2994 OK: +rbmon -- 2014-12-20 614 14.7 131013 xc3s1000-4 1455 4523 302 2807 OK: -RL11,rlv4 diff --git a/rtl/sys_gen/w11a/s3board/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/s3board/tb/sys_conf_sim.vhd index f4aca269..098bd9b8 100644 --- a/rtl/sys_gen/w11a/s3board/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/s3board/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: sys_conf_sim.vhd 683 2015-05-17 21:54:35Z mueller $ -- -- Copyright 2007-2015 by Walter F.J. Mueller -- @@ -63,6 +63,7 @@ package sys_conf is constant sys_conf_ibd_rk11 : boolean := true; -- RK11 constant sys_conf_ibd_rl11 : boolean := true; -- RL11 constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 -- configure other devices constant sys_conf_ibd_iist : boolean := true; -- IIST diff --git a/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd b/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd index 0afc422f..46b3ac59 100644 --- a/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd +++ b/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd @@ -1,89 +1,89 @@ --- $Id: ram_1swar_1ar_gen.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2006-2011 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: ram_1swar_1ar_gen - syn --- Description: Dual-Port RAM with with one synchronous write and two --- asynchronius read ports (as distributed RAM). --- The code is inspired by Xilinx example rams_09.vhd. The --- 'ram_style' attribute is set to 'distributed', this will --- force in XST a synthesis as distributed RAM. --- --- Dependencies: - --- Test bench: - --- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 --- Revision History: --- Date Rev Version Comment --- 2011-11-08 422 1.0.2 now numeric_std clean --- 2008-03-08 123 1.0.1 use std_..._arith, not _unsigned; use unsigned() --- 2007-06-03 45 1.0 Initial version --- --- Some synthesis results: --- - 2010-06-03 ise 11.4 for xc3s1000-ft256-4: --- AWIDTH DWIDTH LUTl LUTm Comments --- 4 16 - 32 16*RAM16X1D --- 5 16 34 64 32*RAM16X1D --- 6 16 68 128 64*RAM16X1D, 32*MUXF5 --- 7 16 136 256 128*RAM16X1D, 64*MUXF5, 32*MUXF6 --- 8 16 292 512 256*RAM16X1D,144*MUXF5, 64*MUXF6, 32*MUXF7 --- - 2007-12-31 ise 8.2.03 for xc3s1000-ft256-4: --- {same results as above for AW=4 and 6} ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; - -entity ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port - generic ( - AWIDTH : positive := 4; -- address port width - DWIDTH : positive := 16); -- data port width - port ( - CLK : in slbit; -- clock - WE : in slbit; -- write enable (port A) - ADDRA : in slv(AWIDTH-1 downto 0); -- address port A - ADDRB : in slv(AWIDTH-1 downto 0); -- address port B - DI : in slv(DWIDTH-1 downto 0); -- data in (port A) - DOA : out slv(DWIDTH-1 downto 0); -- data out port A - DOB : out slv(DWIDTH-1 downto 0) -- data out port B - ); -end ram_1swar_1ar_gen; - - -architecture syn of ram_1swar_1ar_gen is - constant memsize : positive := 2**AWIDTH; - constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0'); - type ram_type is array (memsize-1 downto 0) of slv (DWIDTH-1 downto 0); - signal RAM : ram_type := (others=>datzero); - - attribute ram_style : string; - attribute ram_style of RAM : signal is "distributed"; - -begin - - proc_clk: process (CLK) - begin - if rising_edge(CLK) then - if WE = '1' then - RAM(to_integer(unsigned(ADDRA))) <= DI; - end if; - end if; - end process proc_clk; - - DOA <= RAM(to_integer(unsigned(ADDRA))); - DOB <= RAM(to_integer(unsigned(ADDRB))); - -end syn; +-- $Id: ram_1swar_1ar_gen.vhd 686 2015-06-04 21:08:08Z mueller $ +-- +-- Copyright 2006-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: ram_1swar_1ar_gen - syn +-- Description: Dual-Port RAM with with one synchronous write and two +-- asynchronius read ports (as distributed RAM). +-- The code is inspired by Xilinx example rams_09.vhd. The +-- 'ram_style' attribute is set to 'distributed', this will +-- force in XST a synthesis as distributed RAM. +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic Spartan, Virtex +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-08 422 1.0.2 now numeric_std clean +-- 2008-03-08 123 1.0.1 use std_..._arith, not _unsigned; use unsigned() +-- 2007-06-03 45 1.0 Initial version +-- +-- Some synthesis results: +-- - 2010-06-03 ise 11.4 for xc3s1000-ft256-4: +-- AWIDTH DWIDTH LUTl LUTm Comments +-- 4 16 - 32 16*RAM16X1D +-- 5 16 34 64 32*RAM16X1D +-- 6 16 68 128 64*RAM16X1D, 32*MUXF5 +-- 7 16 136 256 128*RAM16X1D, 64*MUXF5, 32*MUXF6 +-- 8 16 292 512 256*RAM16X1D,144*MUXF5, 64*MUXF6, 32*MUXF7 +-- - 2007-12-31 ise 8.2.03 for xc3s1000-ft256-4: +-- {same results as above for AW=4 and 6} +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; + +entity ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port + generic ( + AWIDTH : positive := 4; -- address port width + DWIDTH : positive := 16); -- data port width + port ( + CLK : in slbit; -- clock + WE : in slbit; -- write enable (port A) + ADDRA : in slv(AWIDTH-1 downto 0); -- address port A + ADDRB : in slv(AWIDTH-1 downto 0); -- address port B + DI : in slv(DWIDTH-1 downto 0); -- data in (port A) + DOA : out slv(DWIDTH-1 downto 0); -- data out port A + DOB : out slv(DWIDTH-1 downto 0) -- data out port B + ); +end ram_1swar_1ar_gen; + + +architecture syn of ram_1swar_1ar_gen is + constant memsize : positive := 2**AWIDTH; + constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0'); + type ram_type is array (memsize-1 downto 0) of slv (DWIDTH-1 downto 0); + signal RAM : ram_type := (others=>datzero); + + attribute ram_style : string; + attribute ram_style of RAM : signal is "distributed"; + +begin + + proc_clk: process (CLK) + begin + if rising_edge(CLK) then + if WE = '1' then + RAM(to_integer(unsigned(ADDRA))) <= DI; + end if; + end if; + end process proc_clk; + + DOA <= RAM(to_integer(unsigned(ADDRA))); + DOB <= RAM(to_integer(unsigned(ADDRB))); + +end syn; diff --git a/rtl/vlib/memlib/ram_1swar_1ar_gen_unisim.vhd b/rtl/vlib/memlib/ram_1swar_1ar_gen_unisim.vhd index d46694b6..bd6563d5 100644 --- a/rtl/vlib/memlib/ram_1swar_1ar_gen_unisim.vhd +++ b/rtl/vlib/memlib/ram_1swar_1ar_gen_unisim.vhd @@ -1,170 +1,170 @@ --- $Id: ram_1swar_1ar_gen_unisim.vhd 641 2015-02-01 22:12:15Z mueller $ --- --- Copyright 2008-2010 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: ram_1swar_1ar_gen - syn --- Description: Dual-Port RAM with with one synchronous write and two --- asynchronius read ports (as distributed RAM). --- Direct instantiation of Xilinx UNISIM primitives --- --- Dependencies: - --- Test bench: - --- Target Devices: generic Spartan, Virtex --- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 --- Revision History: --- Date Rev Version Comment --- 2010-06-03 300 1.1 add hack for AW=5 for Spartan's --- 2008-03-08 123 1.0.1 use shorter label names --- 2008-03-02 122 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -library unisim; -use unisim.vcomponents.ALL; - -use work.slvtypes.all; - -entity ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port - generic ( - AWIDTH : positive := 4; -- address port width - DWIDTH : positive := 16); -- data port width - port ( - CLK : in slbit; -- clock - WE : in slbit; -- write enable (port A) - ADDRA : in slv(AWIDTH-1 downto 0); -- address port A - ADDRB : in slv(AWIDTH-1 downto 0); -- address port B - DI : in slv(DWIDTH-1 downto 0); -- data in (port A) - DOA : out slv(DWIDTH-1 downto 0); -- data out port A - DOB : out slv(DWIDTH-1 downto 0) -- data out port B - ); -end ram_1swar_1ar_gen; - - -architecture syn of ram_1swar_1ar_gen is - -begin - - assert AWIDTH>=4 and AWIDTH<=5 - report "assert(AWIDTH>=4 and AWIDTH<=5): only 4..5 bit AWIDTH supported" - severity failure; - - AW_4: if AWIDTH = 4 generate - GL: for i in DWIDTH-1 downto 0 generate - MEM : RAM16X1D - generic map ( - INIT => X"0000") - port map ( - DPO => DOB(i), - SPO => DOA(i), - A0 => ADDRA(0), - A1 => ADDRA(1), - A2 => ADDRA(2), - A3 => ADDRA(3), - D => DI(i), - DPRA0 => ADDRB(0), - DPRA1 => ADDRB(1), - DPRA2 => ADDRB(2), - DPRA3 => ADDRB(3), - WCLK => CLK, - WE => WE - ); - end generate GL; - end generate AW_4; - - -- Note: Spartan-3 doesn't support RAM32X1D, therefore this kludge.. - AW_5: if AWIDTH = 5 generate - signal WE0 : slbit := '0'; - signal WE1 : slbit := '0'; - signal DOA0 : slv(DWIDTH-1 downto 0) := (others=>'0'); - signal DOA1 : slv(DWIDTH-1 downto 0) := (others=>'0'); - signal DOB0 : slv(DWIDTH-1 downto 0) := (others=>'0'); - signal DOB1 : slv(DWIDTH-1 downto 0) := (others=>'0'); - begin - WE0 <= WE and not ADDRA(4); - WE1 <= WE and ADDRA(4); - GL: for i in DWIDTH-1 downto 0 generate - MEM0 : RAM16X1D - generic map ( - INIT => X"0000") - port map ( - DPO => DOB0(i), - SPO => DOA0(i), - A0 => ADDRA(0), - A1 => ADDRA(1), - A2 => ADDRA(2), - A3 => ADDRA(3), - D => DI(i), - DPRA0 => ADDRB(0), - DPRA1 => ADDRB(1), - DPRA2 => ADDRB(2), - DPRA3 => ADDRB(3), - WCLK => CLK, - WE => WE0 - ); - MEM1 : RAM16X1D - generic map ( - INIT => X"0000") - port map ( - DPO => DOB1(i), - SPO => DOA1(i), - A0 => ADDRA(0), - A1 => ADDRA(1), - A2 => ADDRA(2), - A3 => ADDRA(3), - D => DI(i), - DPRA0 => ADDRB(0), - DPRA1 => ADDRB(1), - DPRA2 => ADDRB(2), - DPRA3 => ADDRB(3), - WCLK => CLK, - WE => WE1 - ); - DOA <= DOA0 when ADDRA(4)='0' else DOA1; - DOB <= DOB0 when ADDRB(4)='0' else DOB1; - end generate GL; - end generate AW_5; - --- AW_6: if AWIDTH = 6 generate --- GL: for i in DWIDTH-1 downto 0 generate --- MEM : RAM64X1D --- generic map ( --- INIT => X"0000000000000000") --- port map ( --- DPO => DOB(i), --- SPO => DOA(i), --- A0 => ADDRA(0), --- A1 => ADDRA(1), --- A2 => ADDRA(2), --- A3 => ADDRA(3), --- A4 => ADDRA(4), --- A5 => ADDRA(5), --- D => DI(i), --- DPRA0 => ADDRB(0), --- DPRA1 => ADDRB(1), --- DPRA2 => ADDRB(2), --- DPRA3 => ADDRB(3), --- DPRA4 => ADDRB(4), --- DPRA5 => ADDRB(5), --- WCLK => CLK, --- WE => WE --- ); --- end generate GL; --- end generate AW_6; - -end syn; - --- Note: The VHDL instantiation example in the 8.1i Librariers Guide is wrong. --- The annotation states that DPO is the port A output and SPO is port B --- output. The text before is correct, DPO is port B and SPO is port A. +-- $Id: ram_1swar_1ar_gen_unisim.vhd 686 2015-06-04 21:08:08Z mueller $ +-- +-- Copyright 2008-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: ram_1swar_1ar_gen - syn +-- Description: Dual-Port RAM with with one synchronous write and two +-- asynchronius read ports (as distributed RAM). +-- Direct instantiation of Xilinx UNISIM primitives +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic Spartan, Virtex +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2010-06-03 300 1.1 add hack for AW=5 for Spartan's +-- 2008-03-08 123 1.0.1 use shorter label names +-- 2008-03-02 122 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +use unisim.vcomponents.ALL; + +use work.slvtypes.all; + +entity ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port + generic ( + AWIDTH : positive := 4; -- address port width + DWIDTH : positive := 16); -- data port width + port ( + CLK : in slbit; -- clock + WE : in slbit; -- write enable (port A) + ADDRA : in slv(AWIDTH-1 downto 0); -- address port A + ADDRB : in slv(AWIDTH-1 downto 0); -- address port B + DI : in slv(DWIDTH-1 downto 0); -- data in (port A) + DOA : out slv(DWIDTH-1 downto 0); -- data out port A + DOB : out slv(DWIDTH-1 downto 0) -- data out port B + ); +end ram_1swar_1ar_gen; + + +architecture syn of ram_1swar_1ar_gen is + +begin + + assert AWIDTH>=4 and AWIDTH<=5 + report "assert(AWIDTH>=4 and AWIDTH<=5): only 4..5 bit AWIDTH supported" + severity failure; + + AW_4: if AWIDTH = 4 generate + GL: for i in DWIDTH-1 downto 0 generate + MEM : RAM16X1D + generic map ( + INIT => X"0000") + port map ( + DPO => DOB(i), + SPO => DOA(i), + A0 => ADDRA(0), + A1 => ADDRA(1), + A2 => ADDRA(2), + A3 => ADDRA(3), + D => DI(i), + DPRA0 => ADDRB(0), + DPRA1 => ADDRB(1), + DPRA2 => ADDRB(2), + DPRA3 => ADDRB(3), + WCLK => CLK, + WE => WE + ); + end generate GL; + end generate AW_4; + + -- Note: Spartan-3 doesn't support RAM32X1D, therefore this kludge.. + AW_5: if AWIDTH = 5 generate + signal WE0 : slbit := '0'; + signal WE1 : slbit := '0'; + signal DOA0 : slv(DWIDTH-1 downto 0) := (others=>'0'); + signal DOA1 : slv(DWIDTH-1 downto 0) := (others=>'0'); + signal DOB0 : slv(DWIDTH-1 downto 0) := (others=>'0'); + signal DOB1 : slv(DWIDTH-1 downto 0) := (others=>'0'); + begin + WE0 <= WE and not ADDRA(4); + WE1 <= WE and ADDRA(4); + GL: for i in DWIDTH-1 downto 0 generate + MEM0 : RAM16X1D + generic map ( + INIT => X"0000") + port map ( + DPO => DOB0(i), + SPO => DOA0(i), + A0 => ADDRA(0), + A1 => ADDRA(1), + A2 => ADDRA(2), + A3 => ADDRA(3), + D => DI(i), + DPRA0 => ADDRB(0), + DPRA1 => ADDRB(1), + DPRA2 => ADDRB(2), + DPRA3 => ADDRB(3), + WCLK => CLK, + WE => WE0 + ); + MEM1 : RAM16X1D + generic map ( + INIT => X"0000") + port map ( + DPO => DOB1(i), + SPO => DOA1(i), + A0 => ADDRA(0), + A1 => ADDRA(1), + A2 => ADDRA(2), + A3 => ADDRA(3), + D => DI(i), + DPRA0 => ADDRB(0), + DPRA1 => ADDRB(1), + DPRA2 => ADDRB(2), + DPRA3 => ADDRB(3), + WCLK => CLK, + WE => WE1 + ); + DOA <= DOA0 when ADDRA(4)='0' else DOA1; + DOB <= DOB0 when ADDRB(4)='0' else DOB1; + end generate GL; + end generate AW_5; + +-- AW_6: if AWIDTH = 6 generate +-- GL: for i in DWIDTH-1 downto 0 generate +-- MEM : RAM64X1D +-- generic map ( +-- INIT => X"0000000000000000") +-- port map ( +-- DPO => DOB(i), +-- SPO => DOA(i), +-- A0 => ADDRA(0), +-- A1 => ADDRA(1), +-- A2 => ADDRA(2), +-- A3 => ADDRA(3), +-- A4 => ADDRA(4), +-- A5 => ADDRA(5), +-- D => DI(i), +-- DPRA0 => ADDRB(0), +-- DPRA1 => ADDRB(1), +-- DPRA2 => ADDRB(2), +-- DPRA3 => ADDRB(3), +-- DPRA4 => ADDRB(4), +-- DPRA5 => ADDRB(5), +-- WCLK => CLK, +-- WE => WE +-- ); +-- end generate GL; +-- end generate AW_6; + +end syn; + +-- Note: The VHDL instantiation example in the 8.1i Librariers Guide is wrong. +-- The annotation states that DPO is the port A output and SPO is port B +-- output. The text before is correct, DPO is port B and SPO is port A. diff --git a/rtl/vlib/memlib/ram_1swar_gen.vhd b/rtl/vlib/memlib/ram_1swar_gen.vhd index e73d2df4..113b455a 100644 --- a/rtl/vlib/memlib/ram_1swar_gen.vhd +++ b/rtl/vlib/memlib/ram_1swar_gen.vhd @@ -1,82 +1,82 @@ --- $Id: ram_1swar_gen.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2006-2011 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: ram_1swar_gen - syn --- Description: Single-Port RAM with with one synchronous write and one --- asynchronius read port (as distributed RAM). --- The code is inspired by Xilinx example rams_04.vhd. The --- 'ram_style' attribute is set to 'distributed', this will --- force in XST a synthesis as distributed RAM. --- --- Dependencies: - --- Test bench: - --- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 --- Revision History: --- Date Rev Version Comment --- 2011-11-08 422 1.0.2 now numeric_std clean --- 2008-03-08 123 1.0.1 use std_..._arith, not _unsigned; use unsigned() --- 2007-06-03 45 1.0 Initial version --- --- Some synthesis results: --- - 2007-12-31 ise 8.2.03 for xc3s1000-ft256-4: --- AWIDTH DWIDTH LUTl LUTm Comments --- 4 16 - 16 16*RAM16X1S --- 5 16 - 32 16*RAM32X1S --- 6 16 18 64 32*RAM32X1S Note: A(4) via F5MUX, A(5) via LUT ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; - -entity ram_1swar_gen is -- RAM, 1 sync w asyn r port - generic ( - AWIDTH : positive := 4; -- address port width - DWIDTH : positive := 16); -- data port width - port ( - CLK : in slbit; -- clock - WE : in slbit; -- write enable - ADDR : in slv(AWIDTH-1 downto 0); -- address port - DI : in slv(DWIDTH-1 downto 0); -- data in port - DO : out slv(DWIDTH-1 downto 0) -- data out port - ); -end ram_1swar_gen; - - -architecture syn of ram_1swar_gen is - constant memsize : positive := 2**AWIDTH; - constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0'); - type ram_type is array (memsize-1 downto 0) of slv (DWIDTH-1 downto 0); - signal RAM : ram_type := (others=>datzero); - - attribute ram_style : string; - attribute ram_style of RAM : signal is "distributed"; - -begin - - proc_clk: process (CLK) - begin - if rising_edge(CLK) then - if WE = '1' then - RAM(to_integer(unsigned(ADDR))) <= DI; - end if; - end if; - end process proc_clk; - - DO <= RAM(to_integer(unsigned(ADDR))); - -end syn; +-- $Id: ram_1swar_gen.vhd 686 2015-06-04 21:08:08Z mueller $ +-- +-- Copyright 2006-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: ram_1swar_gen - syn +-- Description: Single-Port RAM with with one synchronous write and one +-- asynchronius read port (as distributed RAM). +-- The code is inspired by Xilinx example rams_04.vhd. The +-- 'ram_style' attribute is set to 'distributed', this will +-- force in XST a synthesis as distributed RAM. +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic Spartan, Virtex +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-08 422 1.0.2 now numeric_std clean +-- 2008-03-08 123 1.0.1 use std_..._arith, not _unsigned; use unsigned() +-- 2007-06-03 45 1.0 Initial version +-- +-- Some synthesis results: +-- - 2007-12-31 ise 8.2.03 for xc3s1000-ft256-4: +-- AWIDTH DWIDTH LUTl LUTm Comments +-- 4 16 - 16 16*RAM16X1S +-- 5 16 - 32 16*RAM32X1S +-- 6 16 18 64 32*RAM32X1S Note: A(4) via F5MUX, A(5) via LUT +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; + +entity ram_1swar_gen is -- RAM, 1 sync w asyn r port + generic ( + AWIDTH : positive := 4; -- address port width + DWIDTH : positive := 16); -- data port width + port ( + CLK : in slbit; -- clock + WE : in slbit; -- write enable + ADDR : in slv(AWIDTH-1 downto 0); -- address port + DI : in slv(DWIDTH-1 downto 0); -- data in port + DO : out slv(DWIDTH-1 downto 0) -- data out port + ); +end ram_1swar_gen; + + +architecture syn of ram_1swar_gen is + constant memsize : positive := 2**AWIDTH; + constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0'); + type ram_type is array (memsize-1 downto 0) of slv (DWIDTH-1 downto 0); + signal RAM : ram_type := (others=>datzero); + + attribute ram_style : string; + attribute ram_style of RAM : signal is "distributed"; + +begin + + proc_clk: process (CLK) + begin + if rising_edge(CLK) then + if WE = '1' then + RAM(to_integer(unsigned(ADDR))) <= DI; + end if; + end if; + end process proc_clk; + + DO <= RAM(to_integer(unsigned(ADDR))); + +end syn; diff --git a/rtl/vlib/memlib/ram_1swar_gen_unisim.vhd b/rtl/vlib/memlib/ram_1swar_gen_unisim.vhd index a264f489..ff2a942b 100644 --- a/rtl/vlib/memlib/ram_1swar_gen_unisim.vhd +++ b/rtl/vlib/memlib/ram_1swar_gen_unisim.vhd @@ -1,118 +1,118 @@ --- $Id: ram_1swar_gen_unisim.vhd 641 2015-02-01 22:12:15Z mueller $ --- --- Copyright 2008- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: ram_1swar_gen_unisim - syn --- Description: Single-Port RAM with with one synchronous write and one --- asynchronius read port (as distributed RAM). --- Direct instantiation of Xilinx UNISIM primitives --- --- Dependencies: - --- Test bench: - --- Target Devices: generic Spartan, Virtex --- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 --- Revision History: --- Date Rev Version Comment --- 2008-03-08 123 1.0.1 use shorter label names --- 2008-03-02 122 1.0 Initial version --- ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -library unisim; -use unisim.vcomponents.ALL; - -use work.slvtypes.all; - -entity ram_1swar_gen is -- RAM, 1 sync w asyn r port - generic ( - AWIDTH : positive := 4; -- address port width - DWIDTH : positive := 16); -- data port width - port ( - CLK : in slbit; -- clock - WE : in slbit; -- write enable - ADDR : in slv(AWIDTH-1 downto 0); -- address port - DI : in slv(DWIDTH-1 downto 0); -- data in port - DO : out slv(DWIDTH-1 downto 0) -- data out port - ); -end ram_1swar_gen; - - -architecture syn of ram_1swar_gen is - -begin - - assert AWIDTH>=4 and AWIDTH<=6 - report "assert(AWIDTH>=4 and AWIDTH<=6): only 4..6 bit AWIDTH supported" - severity failure; - - AW_4: if AWIDTH = 4 generate - GL: for i in DWIDTH-1 downto 0 generate - MEM : RAM16X1S - generic map ( - INIT => X"0000") - port map ( - O => DO(i), - A0 => ADDR(0), - A1 => ADDR(1), - A2 => ADDR(2), - A3 => ADDR(3), - D => DI(i), - WCLK => CLK, - WE => WE - ); - end generate GL; - end generate AW_4; - - AW_5: if AWIDTH = 5 generate - GL: for i in DWIDTH-1 downto 0 generate - MEM : RAM32X1S - generic map ( - INIT => X"00000000") - port map ( - O => DO(i), - A0 => ADDR(0), - A1 => ADDR(1), - A2 => ADDR(2), - A3 => ADDR(3), - A4 => ADDR(4), - D => DI(i), - WCLK => CLK, - WE => WE - ); - end generate GL; - end generate AW_5; - - AW_6: if AWIDTH = 6 generate - GL: for i in DWIDTH-1 downto 0 generate - MEM : RAM64X1S - generic map ( - INIT => X"0000000000000000") - port map ( - O => DO(i), - A0 => ADDR(0), - A1 => ADDR(1), - A2 => ADDR(2), - A3 => ADDR(3), - A4 => ADDR(4), - A5 => ADDR(5), - D => DI(i), - WCLK => CLK, - WE => WE - ); - end generate GL; - end generate AW_6; - -end syn; +-- $Id: ram_1swar_gen_unisim.vhd 686 2015-06-04 21:08:08Z mueller $ +-- +-- Copyright 2008- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: ram_1swar_gen_unisim - syn +-- Description: Single-Port RAM with with one synchronous write and one +-- asynchronius read port (as distributed RAM). +-- Direct instantiation of Xilinx UNISIM primitives +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic Spartan, Virtex +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2008-03-08 123 1.0.1 use shorter label names +-- 2008-03-02 122 1.0 Initial version +-- +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +use unisim.vcomponents.ALL; + +use work.slvtypes.all; + +entity ram_1swar_gen is -- RAM, 1 sync w asyn r port + generic ( + AWIDTH : positive := 4; -- address port width + DWIDTH : positive := 16); -- data port width + port ( + CLK : in slbit; -- clock + WE : in slbit; -- write enable + ADDR : in slv(AWIDTH-1 downto 0); -- address port + DI : in slv(DWIDTH-1 downto 0); -- data in port + DO : out slv(DWIDTH-1 downto 0) -- data out port + ); +end ram_1swar_gen; + + +architecture syn of ram_1swar_gen is + +begin + + assert AWIDTH>=4 and AWIDTH<=6 + report "assert(AWIDTH>=4 and AWIDTH<=6): only 4..6 bit AWIDTH supported" + severity failure; + + AW_4: if AWIDTH = 4 generate + GL: for i in DWIDTH-1 downto 0 generate + MEM : RAM16X1S + generic map ( + INIT => X"0000") + port map ( + O => DO(i), + A0 => ADDR(0), + A1 => ADDR(1), + A2 => ADDR(2), + A3 => ADDR(3), + D => DI(i), + WCLK => CLK, + WE => WE + ); + end generate GL; + end generate AW_4; + + AW_5: if AWIDTH = 5 generate + GL: for i in DWIDTH-1 downto 0 generate + MEM : RAM32X1S + generic map ( + INIT => X"00000000") + port map ( + O => DO(i), + A0 => ADDR(0), + A1 => ADDR(1), + A2 => ADDR(2), + A3 => ADDR(3), + A4 => ADDR(4), + D => DI(i), + WCLK => CLK, + WE => WE + ); + end generate GL; + end generate AW_5; + + AW_6: if AWIDTH = 6 generate + GL: for i in DWIDTH-1 downto 0 generate + MEM : RAM64X1S + generic map ( + INIT => X"0000000000000000") + port map ( + O => DO(i), + A0 => ADDR(0), + A1 => ADDR(1), + A2 => ADDR(2), + A3 => ADDR(3), + A4 => ADDR(4), + A5 => ADDR(5), + D => DI(i), + WCLK => CLK, + WE => WE + ); + end generate GL; + end generate AW_6; + +end syn; diff --git a/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd b/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd index ee9f3044..4a453326 100644 --- a/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd +++ b/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd @@ -1,90 +1,90 @@ --- $Id: ram_1swsr_wfirst_gen.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2006-2011 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: ram_1swsr_rfirst_gen - syn --- Description: Single-Port RAM with with one synchronous read/write port --- and 'read-through' semantics (as block RAM). --- The 'ram_style' attribute is set to 'block', this will --- force in XST a synthesis as block RAM. --- --- Notes: For xst 8.1.03i: can be written with a signal or a shared --- variable declared at the architecture level. Use variable --- because this seemed better for simulation. Using a simple --- variable declared at process level leads to an array of --- registers and a big mux. --- --- Dependencies: - --- Test bench: - --- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 --- Revision History: --- Date Rev Version Comment --- 2011-11-08 422 1.0.4 now numeric_std clean --- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables --- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned(); --- 2008-03-02 122 1.0.1 change generic default for BRAM models --- 2007-06-03 45 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; - -entity ram_1swsr_wfirst_gen is -- RAM, 1 sync r/w ports, write first - generic ( - AWIDTH : positive := 11; -- address port width - DWIDTH : positive := 9); -- data port width - port( - CLK : in slbit; -- clock - EN : in slbit; -- enable - WE : in slbit; -- write enable - ADDR : in slv(AWIDTH-1 downto 0); -- address port - DI : in slv(DWIDTH-1 downto 0); -- data in port - DO : out slv(DWIDTH-1 downto 0) -- data out port - ); -end ram_1swsr_wfirst_gen; - - -architecture syn of ram_1swsr_wfirst_gen is - - constant memsize : positive := 2**AWIDTH; - constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0'); - type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0); - shared variable sv_ram : ram_type := (others=>datzero); - - attribute ram_style : string; - attribute ram_style of sv_ram : variable is "block"; - - signal R_DO : slv(DWIDTH-1 downto 0) := datzero; - -begin - - proc_clk: process (CLK) - begin - if rising_edge(CLK) then - if EN = '1' then - if WE = '1' then - sv_ram(to_integer(unsigned(ADDR))) := DI; - end if; - R_DO <= sv_ram(to_integer(unsigned(ADDR))); - end if; - end if; - end process proc_clk; - - DO <= R_DO; - -end syn; - +-- $Id: ram_1swsr_wfirst_gen.vhd 686 2015-06-04 21:08:08Z mueller $ +-- +-- Copyright 2006-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: ram_1swsr_rfirst_gen - syn +-- Description: Single-Port RAM with with one synchronous read/write port +-- and 'read-through' semantics (as block RAM). +-- The 'ram_style' attribute is set to 'block', this will +-- force in XST a synthesis as block RAM. +-- +-- Notes: For xst 8.1.03i: can be written with a signal or a shared +-- variable declared at the architecture level. Use variable +-- because this seemed better for simulation. Using a simple +-- variable declared at process level leads to an array of +-- registers and a big mux. +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic Spartan, Virtex +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-08 422 1.0.4 now numeric_std clean +-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables +-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned(); +-- 2008-03-02 122 1.0.1 change generic default for BRAM models +-- 2007-06-03 45 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; + +entity ram_1swsr_wfirst_gen is -- RAM, 1 sync r/w ports, write first + generic ( + AWIDTH : positive := 11; -- address port width + DWIDTH : positive := 9); -- data port width + port( + CLK : in slbit; -- clock + EN : in slbit; -- enable + WE : in slbit; -- write enable + ADDR : in slv(AWIDTH-1 downto 0); -- address port + DI : in slv(DWIDTH-1 downto 0); -- data in port + DO : out slv(DWIDTH-1 downto 0) -- data out port + ); +end ram_1swsr_wfirst_gen; + + +architecture syn of ram_1swsr_wfirst_gen is + + constant memsize : positive := 2**AWIDTH; + constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0'); + type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0); + shared variable sv_ram : ram_type := (others=>datzero); + + attribute ram_style : string; + attribute ram_style of sv_ram : variable is "block"; + + signal R_DO : slv(DWIDTH-1 downto 0) := datzero; + +begin + + proc_clk: process (CLK) + begin + if rising_edge(CLK) then + if EN = '1' then + if WE = '1' then + sv_ram(to_integer(unsigned(ADDR))) := DI; + end if; + R_DO <= sv_ram(to_integer(unsigned(ADDR))); + end if; + end if; + end process proc_clk; + + DO <= R_DO; + +end syn; + diff --git a/rtl/vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd b/rtl/vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd index 7eafdfd1..e5166a5b 100644 --- a/rtl/vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd +++ b/rtl/vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd @@ -1,70 +1,70 @@ --- $Id: ram_1swsr_wfirst_gen_unisim.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2008- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: ram_1swsr_wfirst_gen - syn --- Description: Single-Port RAM with with one synchronous read/write port --- and 'read-through' semantics (as block RAM). --- Direct instantiation of Xilinx UNISIM primitives --- --- Dependencies: - --- Test bench: - --- Target Devices: Spartan-3, Virtex-2,-4 --- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 --- Revision History: --- Date Rev Version Comment --- 2008-03-08 123 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -library unisim; -use unisim.vcomponents.ALL; - -use work.slvtypes.all; -use work.memlib.all; - -entity ram_1swsr_wfirst_gen is -- RAM, 1 sync r/w port, write first - generic ( - AWIDTH : positive := 11; -- address port width - DWIDTH : positive := 9); -- data port width - port( - CLK : in slbit; -- clock - EN : in slbit; -- enable - WE : in slbit; -- write enable - ADDR : in slv(AWIDTH-1 downto 0); -- address - DI : in slv(DWIDTH-1 downto 0); -- data in - DO : out slv(DWIDTH-1 downto 0) -- data out - ); -end ram_1swsr_wfirst_gen; - - -architecture syn of ram_1swsr_wfirst_gen is -begin - - UMEM: ram_1swsr_xfirst_gen_unisim - generic map ( - AWIDTH => AWIDTH, - DWIDTH => DWIDTH, - WRITE_MODE => "WRITE_FIRST") - port map ( - CLK => CLK, - EN => EN, - WE => WE, - ADDR => ADDR, - DI => DI, - DO => DO - ); - -end syn; +-- $Id: ram_1swsr_wfirst_gen_unisim.vhd 686 2015-06-04 21:08:08Z mueller $ +-- +-- Copyright 2008- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: ram_1swsr_wfirst_gen - syn +-- Description: Single-Port RAM with with one synchronous read/write port +-- and 'read-through' semantics (as block RAM). +-- Direct instantiation of Xilinx UNISIM primitives +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: Spartan-3, Virtex-2,-4 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2008-03-08 123 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +use unisim.vcomponents.ALL; + +use work.slvtypes.all; +use work.memlib.all; + +entity ram_1swsr_wfirst_gen is -- RAM, 1 sync r/w port, write first + generic ( + AWIDTH : positive := 11; -- address port width + DWIDTH : positive := 9); -- data port width + port( + CLK : in slbit; -- clock + EN : in slbit; -- enable + WE : in slbit; -- write enable + ADDR : in slv(AWIDTH-1 downto 0); -- address + DI : in slv(DWIDTH-1 downto 0); -- data in + DO : out slv(DWIDTH-1 downto 0) -- data out + ); +end ram_1swsr_wfirst_gen; + + +architecture syn of ram_1swsr_wfirst_gen is +begin + + UMEM: ram_1swsr_xfirst_gen_unisim + generic map ( + AWIDTH => AWIDTH, + DWIDTH => DWIDTH, + WRITE_MODE => "WRITE_FIRST") + port map ( + CLK => CLK, + EN => EN, + WE => WE, + ADDR => ADDR, + DI => DI, + DO => DO + ); + +end syn; diff --git a/rtl/vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd b/rtl/vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd index 541c2f79..065e2908 100644 --- a/rtl/vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd +++ b/rtl/vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd @@ -1,323 +1,323 @@ --- $Id: ram_1swsr_xfirst_gen_unisim.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2008-2011 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: ram_1swsr_xfirst_gen_unisim - syn --- Description: Single-Port RAM with with one synchronous read/write port --- Direct instantiation of Xilinx UNISIM primitives --- --- Dependencies: - --- Test bench: - --- Target Devices: Spartan-3, Virtex-2,-4 --- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 --- Revision History: --- Date Rev Version Comment --- 2011-08-14 406 1.0.2 cleaner code for L_DI initialization --- 2008-04-13 135 1.0.1 fix range error for AW_14_S1 --- 2008-03-08 123 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -library unisim; -use unisim.vcomponents.ALL; - -use work.slvtypes.all; - -entity ram_1swsr_xfirst_gen_unisim is -- RAM, 1 sync r/w ports - generic ( - AWIDTH : positive := 11; -- address port width - DWIDTH : positive := 9; -- data port width - WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST - port( - CLK : in slbit; -- clock - EN : in slbit; -- enable - WE : in slbit; -- write enable - ADDR : in slv(AWIDTH-1 downto 0); -- address - DI : in slv(DWIDTH-1 downto 0); -- data in - DO : out slv(DWIDTH-1 downto 0) -- data out - ); -end ram_1swsr_xfirst_gen_unisim; - - -architecture syn of ram_1swsr_xfirst_gen_unisim is - - constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and - ((DWIDTH+35)/36)=((DWIDTH+31)/32); - constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and - ((DWIDTH+17)/18)=((DWIDTH+16)/16); - constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and - ((DWIDTH+8)/9)=((DWIDTH+7)/8); - -begin - - assert AWIDTH>=9 and AWIDTH<=14 - report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor" - severity failure; - - AW_09_S36: if AWIDTH=9 and not ok_mod32 generate - constant dw_mem : positive := ((DWIDTH+35)/36)*36; - signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0'); - begin - - DI_PAD: if dw_mem>DWIDTH generate - L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0'); - end generate DI_PAD; - L_DI(DI'range) <= DI; - - GL: for i in dw_mem/36-1 downto 0 generate - MEM : RAMB16_S36 - generic map ( - INIT => O"000000000000", - SRVAL => O"000000000000", - WRITE_MODE => WRITE_MODE) - port map ( - DO => L_DO(36*i+31 downto 36*i), - DOP => L_DO(36*i+35 downto 36*i+32), - ADDR => ADDR, - CLK => CLK, - DI => L_DI(36*i+31 downto 36*i), - DIP => L_DI(36*i+35 downto 36*i+32), - EN => EN, - SSR => '0', - WE => WE - ); - end generate GL; - - DO <= L_DO(DO'range); - - end generate AW_09_S36; - - AW_09_S32: if AWIDTH=9 and ok_mod32 generate - GL: for i in DWIDTH/32-1 downto 0 generate - MEM : RAMB16_S36 - generic map ( - INIT => X"00000000", - SRVAL => X"00000000", - WRITE_MODE => WRITE_MODE) - port map ( - DO => DO(32*i+31 downto 32*i), - DOP => open, - ADDR => ADDR, - CLK => CLK, - DI => DI(32*i+31 downto 32*i), - DIP => "0000", - EN => EN, - SSR => '0', - WE => WE - ); - end generate GL; - end generate AW_09_S32; - - AW_10_S18: if AWIDTH=10 and not ok_mod16 generate - constant dw_mem : positive := ((DWIDTH+17)/18)*18; - signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0'); - begin - - DI_PAD: if dw_mem>DWIDTH generate - L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0'); - end generate DI_PAD; - L_DI(DI'range) <= DI; - - GL: for i in dw_mem/18-1 downto 0 generate - MEM : RAMB16_S18 - generic map ( - INIT => O"000000", - SRVAL => O"000000", - WRITE_MODE => WRITE_MODE) - port map ( - DO => L_DO(18*i+15 downto 18*i), - DOP => L_DO(18*i+17 downto 18*i+16), - ADDR => ADDR, - CLK => CLK, - DI => L_DI(18*i+15 downto 18*i), - DIP => L_DI(18*i+17 downto 18*i+16), - EN => EN, - SSR => '0', - WE => WE - ); - end generate GL; - - DO <= L_DO(DO'range); - - end generate AW_10_S18; - - AW_10_S16: if AWIDTH=10 and ok_mod16 generate - GL: for i in DWIDTH/16-1 downto 0 generate - MEM : RAMB16_S18 - generic map ( - INIT => X"0000", - SRVAL => X"0000", - WRITE_MODE => WRITE_MODE) - port map ( - DO => DO(16*i+15 downto 16*i), - DOP => open, - ADDR => ADDR, - CLK => CLK, - DI => DI(16*i+15 downto 16*i), - DIP => "00", - EN => EN, - SSR => '0', - WE => WE - ); - end generate GL; - end generate AW_10_S16; - - AW_11_S9: if AWIDTH=11 and not ok_mod08 generate - constant dw_mem : positive := ((DWIDTH+8)/9)*9; - signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0'); - begin - - DI_PAD: if dw_mem>DWIDTH generate - L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0'); - end generate DI_PAD; - L_DI(DI'range) <= DI; - - GL: for i in dw_mem/9-1 downto 0 generate - MEM : RAMB16_S9 - generic map ( - INIT => O"000", - SRVAL => O"000", - WRITE_MODE => WRITE_MODE) - port map ( - DO => L_DO(9*i+7 downto 9*i), - DOP => L_DO(9*i+8 downto 9*i+8), - ADDR => ADDR, - CLK => CLK, - DI => L_DI(9*i+7 downto 9*i), - DIP => L_DI(9*i+8 downto 9*i+8), - EN => EN, - SSR => '0', - WE => WE - ); - end generate GL; - - DO <= L_DO(DO'range); - - end generate AW_11_S9; - - AW_11_S8: if AWIDTH=11 and ok_mod08 generate - GL: for i in DWIDTH/8-1 downto 0 generate - MEM : RAMB16_S9 - generic map ( - INIT => X"00", - SRVAL => X"00", - WRITE_MODE => WRITE_MODE) - port map ( - DO => DO(8*i+7 downto 8*i), - DOP => open, - ADDR => ADDR, - CLK => CLK, - DI => DI(8*i+7 downto 8*i), - DIP => "0", - EN => EN, - SSR => '0', - WE => WE - ); - end generate GL; - end generate AW_11_S8; - - AW_12_S4: if AWIDTH = 12 generate - constant dw_mem : positive := ((DWIDTH+3)/4)*4; - signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0'); - begin - - DI_PAD: if dw_mem>DWIDTH generate - L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0'); - end generate DI_PAD; - L_DI(DI'range) <= DI; - - GL: for i in dw_mem/4-1 downto 0 generate - MEM : RAMB16_S4 - generic map ( - INIT => X"0", - SRVAL => X"0", - WRITE_MODE => WRITE_MODE) - port map ( - DO => L_DO(4*i+3 downto 4*i), - ADDR => ADDR, - CLK => CLK, - DI => L_DI(4*i+3 downto 4*i), - EN => EN, - SSR => '0', - WE => WE - ); - end generate GL; - - DO <= L_DO(DO'range); - - end generate AW_12_S4; - - AW_13_S2: if AWIDTH = 13 generate - constant dw_mem : positive := ((DWIDTH+1)/2)*2; - signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0'); - begin - - DI_PAD: if dw_mem>DWIDTH generate - L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0'); - end generate DI_PAD; - L_DI(DI'range) <= DI; - - GL: for i in dw_mem/2-1 downto 0 generate - MEM : RAMB16_S2 - generic map ( - INIT => "00", - SRVAL => "00", - WRITE_MODE => WRITE_MODE) - port map ( - DO => L_DO(2*i+1 downto 2*i), - ADDR => ADDR, - CLK => CLK, - DI => L_DI(2*i+1 downto 2*i), - EN => EN, - SSR => '0', - WE => WE - ); - end generate GL; - - DO <= L_DO(DO'range); - - end generate AW_13_S2; - - AW_14_S1: if AWIDTH = 14 generate - GL: for i in DWIDTH-1 downto 0 generate - MEM : RAMB16_S1 - generic map ( - INIT => "0", - SRVAL => "0", - WRITE_MODE => WRITE_MODE) - port map ( - DO => DO(i downto i), - ADDR => ADDR, - CLK => CLK, - DI => DI(i downto i), - EN => EN, - SSR => '0', - WE => WE - ); - end generate GL; - end generate AW_14_S1; - - -end syn; - --- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are --- nonsense: INIT_A : bit_vector := X"000"; --- This is a 12 bit value, while a 9 bit one is needed. Thus the --- explicit definition above. +-- $Id: ram_1swsr_xfirst_gen_unisim.vhd 686 2015-06-04 21:08:08Z mueller $ +-- +-- Copyright 2008-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: ram_1swsr_xfirst_gen_unisim - syn +-- Description: Single-Port RAM with with one synchronous read/write port +-- Direct instantiation of Xilinx UNISIM primitives +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: Spartan-3, Virtex-2,-4 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2011-08-14 406 1.0.2 cleaner code for L_DI initialization +-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1 +-- 2008-03-08 123 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +use unisim.vcomponents.ALL; + +use work.slvtypes.all; + +entity ram_1swsr_xfirst_gen_unisim is -- RAM, 1 sync r/w ports + generic ( + AWIDTH : positive := 11; -- address port width + DWIDTH : positive := 9; -- data port width + WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST + port( + CLK : in slbit; -- clock + EN : in slbit; -- enable + WE : in slbit; -- write enable + ADDR : in slv(AWIDTH-1 downto 0); -- address + DI : in slv(DWIDTH-1 downto 0); -- data in + DO : out slv(DWIDTH-1 downto 0) -- data out + ); +end ram_1swsr_xfirst_gen_unisim; + + +architecture syn of ram_1swsr_xfirst_gen_unisim is + + constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and + ((DWIDTH+35)/36)=((DWIDTH+31)/32); + constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and + ((DWIDTH+17)/18)=((DWIDTH+16)/16); + constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and + ((DWIDTH+8)/9)=((DWIDTH+7)/8); + +begin + + assert AWIDTH>=9 and AWIDTH<=14 + report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor" + severity failure; + + AW_09_S36: if AWIDTH=9 and not ok_mod32 generate + constant dw_mem : positive := ((DWIDTH+35)/36)*36; + signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0'); + begin + + DI_PAD: if dw_mem>DWIDTH generate + L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0'); + end generate DI_PAD; + L_DI(DI'range) <= DI; + + GL: for i in dw_mem/36-1 downto 0 generate + MEM : RAMB16_S36 + generic map ( + INIT => O"000000000000", + SRVAL => O"000000000000", + WRITE_MODE => WRITE_MODE) + port map ( + DO => L_DO(36*i+31 downto 36*i), + DOP => L_DO(36*i+35 downto 36*i+32), + ADDR => ADDR, + CLK => CLK, + DI => L_DI(36*i+31 downto 36*i), + DIP => L_DI(36*i+35 downto 36*i+32), + EN => EN, + SSR => '0', + WE => WE + ); + end generate GL; + + DO <= L_DO(DO'range); + + end generate AW_09_S36; + + AW_09_S32: if AWIDTH=9 and ok_mod32 generate + GL: for i in DWIDTH/32-1 downto 0 generate + MEM : RAMB16_S36 + generic map ( + INIT => X"00000000", + SRVAL => X"00000000", + WRITE_MODE => WRITE_MODE) + port map ( + DO => DO(32*i+31 downto 32*i), + DOP => open, + ADDR => ADDR, + CLK => CLK, + DI => DI(32*i+31 downto 32*i), + DIP => "0000", + EN => EN, + SSR => '0', + WE => WE + ); + end generate GL; + end generate AW_09_S32; + + AW_10_S18: if AWIDTH=10 and not ok_mod16 generate + constant dw_mem : positive := ((DWIDTH+17)/18)*18; + signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0'); + begin + + DI_PAD: if dw_mem>DWIDTH generate + L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0'); + end generate DI_PAD; + L_DI(DI'range) <= DI; + + GL: for i in dw_mem/18-1 downto 0 generate + MEM : RAMB16_S18 + generic map ( + INIT => O"000000", + SRVAL => O"000000", + WRITE_MODE => WRITE_MODE) + port map ( + DO => L_DO(18*i+15 downto 18*i), + DOP => L_DO(18*i+17 downto 18*i+16), + ADDR => ADDR, + CLK => CLK, + DI => L_DI(18*i+15 downto 18*i), + DIP => L_DI(18*i+17 downto 18*i+16), + EN => EN, + SSR => '0', + WE => WE + ); + end generate GL; + + DO <= L_DO(DO'range); + + end generate AW_10_S18; + + AW_10_S16: if AWIDTH=10 and ok_mod16 generate + GL: for i in DWIDTH/16-1 downto 0 generate + MEM : RAMB16_S18 + generic map ( + INIT => X"0000", + SRVAL => X"0000", + WRITE_MODE => WRITE_MODE) + port map ( + DO => DO(16*i+15 downto 16*i), + DOP => open, + ADDR => ADDR, + CLK => CLK, + DI => DI(16*i+15 downto 16*i), + DIP => "00", + EN => EN, + SSR => '0', + WE => WE + ); + end generate GL; + end generate AW_10_S16; + + AW_11_S9: if AWIDTH=11 and not ok_mod08 generate + constant dw_mem : positive := ((DWIDTH+8)/9)*9; + signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0'); + begin + + DI_PAD: if dw_mem>DWIDTH generate + L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0'); + end generate DI_PAD; + L_DI(DI'range) <= DI; + + GL: for i in dw_mem/9-1 downto 0 generate + MEM : RAMB16_S9 + generic map ( + INIT => O"000", + SRVAL => O"000", + WRITE_MODE => WRITE_MODE) + port map ( + DO => L_DO(9*i+7 downto 9*i), + DOP => L_DO(9*i+8 downto 9*i+8), + ADDR => ADDR, + CLK => CLK, + DI => L_DI(9*i+7 downto 9*i), + DIP => L_DI(9*i+8 downto 9*i+8), + EN => EN, + SSR => '0', + WE => WE + ); + end generate GL; + + DO <= L_DO(DO'range); + + end generate AW_11_S9; + + AW_11_S8: if AWIDTH=11 and ok_mod08 generate + GL: for i in DWIDTH/8-1 downto 0 generate + MEM : RAMB16_S9 + generic map ( + INIT => X"00", + SRVAL => X"00", + WRITE_MODE => WRITE_MODE) + port map ( + DO => DO(8*i+7 downto 8*i), + DOP => open, + ADDR => ADDR, + CLK => CLK, + DI => DI(8*i+7 downto 8*i), + DIP => "0", + EN => EN, + SSR => '0', + WE => WE + ); + end generate GL; + end generate AW_11_S8; + + AW_12_S4: if AWIDTH = 12 generate + constant dw_mem : positive := ((DWIDTH+3)/4)*4; + signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0'); + begin + + DI_PAD: if dw_mem>DWIDTH generate + L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0'); + end generate DI_PAD; + L_DI(DI'range) <= DI; + + GL: for i in dw_mem/4-1 downto 0 generate + MEM : RAMB16_S4 + generic map ( + INIT => X"0", + SRVAL => X"0", + WRITE_MODE => WRITE_MODE) + port map ( + DO => L_DO(4*i+3 downto 4*i), + ADDR => ADDR, + CLK => CLK, + DI => L_DI(4*i+3 downto 4*i), + EN => EN, + SSR => '0', + WE => WE + ); + end generate GL; + + DO <= L_DO(DO'range); + + end generate AW_12_S4; + + AW_13_S2: if AWIDTH = 13 generate + constant dw_mem : positive := ((DWIDTH+1)/2)*2; + signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0'); + begin + + DI_PAD: if dw_mem>DWIDTH generate + L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0'); + end generate DI_PAD; + L_DI(DI'range) <= DI; + + GL: for i in dw_mem/2-1 downto 0 generate + MEM : RAMB16_S2 + generic map ( + INIT => "00", + SRVAL => "00", + WRITE_MODE => WRITE_MODE) + port map ( + DO => L_DO(2*i+1 downto 2*i), + ADDR => ADDR, + CLK => CLK, + DI => L_DI(2*i+1 downto 2*i), + EN => EN, + SSR => '0', + WE => WE + ); + end generate GL; + + DO <= L_DO(DO'range); + + end generate AW_13_S2; + + AW_14_S1: if AWIDTH = 14 generate + GL: for i in DWIDTH-1 downto 0 generate + MEM : RAMB16_S1 + generic map ( + INIT => "0", + SRVAL => "0", + WRITE_MODE => WRITE_MODE) + port map ( + DO => DO(i downto i), + ADDR => ADDR, + CLK => CLK, + DI => DI(i downto i), + EN => EN, + SSR => '0', + WE => WE + ); + end generate GL; + end generate AW_14_S1; + + +end syn; + +-- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are +-- nonsense: INIT_A : bit_vector := X"000"; +-- This is a 12 bit value, while a 9 bit one is needed. Thus the +-- explicit definition above. diff --git a/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd b/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd index f8702916..a2b358fa 100644 --- a/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd +++ b/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd @@ -1,104 +1,104 @@ --- $Id: ram_2swsr_rfirst_gen.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2006-2011 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: ram_2swsr_rfirst_gen - syn --- Description: Dual-Port RAM with with two synchronous read/write ports --- and 'read-before-write' semantics (as block RAM). --- The code is inspired by Xilinx example rams_16.vhd. The --- 'ram_style' attribute is set to 'block', this will --- force in XST a synthesis as block RAM. --- --- Dependencies: - --- Test bench: - --- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 --- Revision History: --- Date Rev Version Comment --- 2011-11-08 422 1.0.4 now numeric_std clean --- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables --- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned(); --- now initialize DO to all '0' at start --- 2008-03-02 122 1.0.1 change generic default for BRAM models --- 2007-06-03 45 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; - -entity ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first - generic ( - AWIDTH : positive := 11; -- address port width - DWIDTH : positive := 9); -- data port width - port( - CLKA : in slbit; -- clock port A - CLKB : in slbit; -- clock port B - ENA : in slbit; -- enable port A - ENB : in slbit; -- enable port B - WEA : in slbit; -- write enable port A - WEB : in slbit; -- write enable port B - ADDRA : in slv(AWIDTH-1 downto 0); -- address port A - ADDRB : in slv(AWIDTH-1 downto 0); -- address port B - DIA : in slv(DWIDTH-1 downto 0); -- data in port A - DIB : in slv(DWIDTH-1 downto 0); -- data in port B - DOA : out slv(DWIDTH-1 downto 0); -- data out port A - DOB : out slv(DWIDTH-1 downto 0) -- data out port B - ); -end ram_2swsr_rfirst_gen; - - -architecture syn of ram_2swsr_rfirst_gen is - constant memsize : positive := 2**AWIDTH; - constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0'); - type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0); - shared variable sv_ram : ram_type := (others=>datzero); - - attribute ram_style : string; - attribute ram_style of sv_ram : variable is "block"; - - signal R_DOA : slv(DWIDTH-1 downto 0) := datzero; - signal R_DOB : slv(DWIDTH-1 downto 0) := datzero; - -begin - - proc_clka: process (CLKA) - begin - if rising_edge(CLKA) then - if ENA = '1' then - R_DOA <= sv_ram(to_integer(unsigned(ADDRA))); - if WEA = '1' then - sv_ram(to_integer(unsigned(ADDRA))) := DIA; - end if; - end if; - end if; - end process proc_clka; - - proc_clkb: process (CLKB) - begin - if rising_edge(CLKB) then - if ENB = '1' then - R_DOB <= sv_ram(to_integer(unsigned(ADDRB))); - if WEB = '1' then - sv_ram(to_integer(unsigned(ADDRB))) := DIB; - end if; - end if; - end if; - end process proc_clkb; - - DOA <= R_DOA; - DOB <= R_DOB; - -end syn; +-- $Id: ram_2swsr_rfirst_gen.vhd 686 2015-06-04 21:08:08Z mueller $ +-- +-- Copyright 2006-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: ram_2swsr_rfirst_gen - syn +-- Description: Dual-Port RAM with with two synchronous read/write ports +-- and 'read-before-write' semantics (as block RAM). +-- The code is inspired by Xilinx example rams_16.vhd. The +-- 'ram_style' attribute is set to 'block', this will +-- force in XST a synthesis as block RAM. +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic Spartan, Virtex +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-08 422 1.0.4 now numeric_std clean +-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables +-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned(); +-- now initialize DO to all '0' at start +-- 2008-03-02 122 1.0.1 change generic default for BRAM models +-- 2007-06-03 45 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; + +entity ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first + generic ( + AWIDTH : positive := 11; -- address port width + DWIDTH : positive := 9); -- data port width + port( + CLKA : in slbit; -- clock port A + CLKB : in slbit; -- clock port B + ENA : in slbit; -- enable port A + ENB : in slbit; -- enable port B + WEA : in slbit; -- write enable port A + WEB : in slbit; -- write enable port B + ADDRA : in slv(AWIDTH-1 downto 0); -- address port A + ADDRB : in slv(AWIDTH-1 downto 0); -- address port B + DIA : in slv(DWIDTH-1 downto 0); -- data in port A + DIB : in slv(DWIDTH-1 downto 0); -- data in port B + DOA : out slv(DWIDTH-1 downto 0); -- data out port A + DOB : out slv(DWIDTH-1 downto 0) -- data out port B + ); +end ram_2swsr_rfirst_gen; + + +architecture syn of ram_2swsr_rfirst_gen is + constant memsize : positive := 2**AWIDTH; + constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0'); + type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0); + shared variable sv_ram : ram_type := (others=>datzero); + + attribute ram_style : string; + attribute ram_style of sv_ram : variable is "block"; + + signal R_DOA : slv(DWIDTH-1 downto 0) := datzero; + signal R_DOB : slv(DWIDTH-1 downto 0) := datzero; + +begin + + proc_clka: process (CLKA) + begin + if rising_edge(CLKA) then + if ENA = '1' then + R_DOA <= sv_ram(to_integer(unsigned(ADDRA))); + if WEA = '1' then + sv_ram(to_integer(unsigned(ADDRA))) := DIA; + end if; + end if; + end if; + end process proc_clka; + + proc_clkb: process (CLKB) + begin + if rising_edge(CLKB) then + if ENB = '1' then + R_DOB <= sv_ram(to_integer(unsigned(ADDRB))); + if WEB = '1' then + sv_ram(to_integer(unsigned(ADDRB))) := DIB; + end if; + end if; + end if; + end process proc_clkb; + + DOA <= R_DOA; + DOB <= R_DOB; + +end syn; diff --git a/rtl/vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd b/rtl/vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd index a7d2e135..d05844da 100644 --- a/rtl/vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd +++ b/rtl/vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd @@ -1,83 +1,83 @@ --- $Id: ram_2swsr_rfirst_gen_unisim.vhd 641 2015-02-01 22:12:15Z mueller $ --- --- Copyright 2008- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: ram_2swsr_rfirst_gen - syn --- Description: Dual-Port RAM with with two synchronous read/write ports --- and 'read-before-write' semantics (as block RAM). --- Direct instantiation of Xilinx UNISIM primitives --- --- Dependencies: - --- Test bench: - --- Target Devices: Spartan-3, Virtex-2,-4 --- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 --- Revision History: --- Date Rev Version Comment --- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim --- 2008-03-02 122 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -library unisim; -use unisim.vcomponents.ALL; - -use work.slvtypes.all; -use work.memlib.all; - -entity ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first - generic ( - AWIDTH : positive := 13; -- address port width 11/9 or 13/8 - DWIDTH : positive := 8); -- data port width - port( - CLKA : in slbit; -- clock port A - CLKB : in slbit; -- clock port B - ENA : in slbit; -- enable port A - ENB : in slbit; -- enable port B - WEA : in slbit; -- write enable port A - WEB : in slbit; -- write enable port B - ADDRA : in slv(AWIDTH-1 downto 0); -- address port A - ADDRB : in slv(AWIDTH-1 downto 0); -- address port B - DIA : in slv(DWIDTH-1 downto 0); -- data in port A - DIB : in slv(DWIDTH-1 downto 0); -- data in port B - DOA : out slv(DWIDTH-1 downto 0); -- data out port A - DOB : out slv(DWIDTH-1 downto 0) -- data out port B - ); -end ram_2swsr_rfirst_gen; - - -architecture syn of ram_2swsr_rfirst_gen is -begin - - UMEM: ram_2swsr_xfirst_gen_unisim - generic map ( - AWIDTH => AWIDTH, - DWIDTH => DWIDTH, - WRITE_MODE => "READ_FIRST") - port map ( - CLKA => CLKA, - CLKB => CLKB, - ENA => ENA, - ENB => ENB, - WEA => WEA, - WEB => WEB, - ADDRA => ADDRA, - ADDRB => ADDRB, - DIA => DIA, - DIB => DIB, - DOA => DOA, - DOB => DOB - ); - -end syn; +-- $Id: ram_2swsr_rfirst_gen_unisim.vhd 686 2015-06-04 21:08:08Z mueller $ +-- +-- Copyright 2008- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: ram_2swsr_rfirst_gen - syn +-- Description: Dual-Port RAM with with two synchronous read/write ports +-- and 'read-before-write' semantics (as block RAM). +-- Direct instantiation of Xilinx UNISIM primitives +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: Spartan-3, Virtex-2,-4 +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim +-- 2008-03-02 122 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +use unisim.vcomponents.ALL; + +use work.slvtypes.all; +use work.memlib.all; + +entity ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first + generic ( + AWIDTH : positive := 13; -- address port width 11/9 or 13/8 + DWIDTH : positive := 8); -- data port width + port( + CLKA : in slbit; -- clock port A + CLKB : in slbit; -- clock port B + ENA : in slbit; -- enable port A + ENB : in slbit; -- enable port B + WEA : in slbit; -- write enable port A + WEB : in slbit; -- write enable port B + ADDRA : in slv(AWIDTH-1 downto 0); -- address port A + ADDRB : in slv(AWIDTH-1 downto 0); -- address port B + DIA : in slv(DWIDTH-1 downto 0); -- data in port A + DIB : in slv(DWIDTH-1 downto 0); -- data in port B + DOA : out slv(DWIDTH-1 downto 0); -- data out port A + DOB : out slv(DWIDTH-1 downto 0) -- data out port B + ); +end ram_2swsr_rfirst_gen; + + +architecture syn of ram_2swsr_rfirst_gen is +begin + + UMEM: ram_2swsr_xfirst_gen_unisim + generic map ( + AWIDTH => AWIDTH, + DWIDTH => DWIDTH, + WRITE_MODE => "READ_FIRST") + port map ( + CLKA => CLKA, + CLKB => CLKB, + ENA => ENA, + ENB => ENB, + WEA => WEA, + WEB => WEB, + ADDRA => ADDRA, + ADDRB => ADDRB, + DIA => DIA, + DIB => DIB, + DOA => DOA, + DOB => DOB + ); + +end syn; diff --git a/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd b/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd index b5b7f1af..f28276a1 100644 --- a/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd +++ b/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd @@ -1,102 +1,102 @@ --- $Id: ram_2swsr_wfirst_gen.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2006-2011 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: ram_2swsr_wfirst_gen - syn --- Description: Dual-Port RAM with with two synchronous read/write ports --- and 'read-through' semantics (as block RAM). --- The code is inspired by Xilinx example rams_16.vhd. The --- 'ram_style' attribute is set to 'block', this will --- force in XST a synthesis as block RAM. --- --- Dependencies: - --- Test bench: - --- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 --- Revision History: --- Date Rev Version Comment --- 2011-11-08 422 1.0.4 now numeric_std clean --- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables --- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned(); --- 2008-03-02 122 1.0.1 change generic default for BRAM models --- 2007-06-03 45 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; - -entity ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first - generic ( - AWIDTH : positive := 11; -- address port width - DWIDTH : positive := 9); -- data port width - port( - CLKA : in slbit; -- clock port A - CLKB : in slbit; -- clock port B - ENA : in slbit; -- enable port A - ENB : in slbit; -- enable port B - WEA : in slbit; -- write enable port A - WEB : in slbit; -- write enable port B - ADDRA : in slv(AWIDTH-1 downto 0); -- address port A - ADDRB : in slv(AWIDTH-1 downto 0); -- address port B - DIA : in slv(DWIDTH-1 downto 0); -- data in port A - DIB : in slv(DWIDTH-1 downto 0); -- data in port B - DOA : out slv(DWIDTH-1 downto 0); -- data out port A - DOB : out slv(DWIDTH-1 downto 0) -- data out port B - ); -end ram_2swsr_wfirst_gen; - - -architecture syn of ram_2swsr_wfirst_gen is - constant memsize : positive := 2**AWIDTH; - constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0'); - type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0); - shared variable sv_ram : ram_type := (others=>datzero); - - attribute ram_style : string; - attribute ram_style of sv_ram : variable is "block"; - - signal R_DOA : slv(DWIDTH-1 downto 0) := datzero; - signal R_DOB : slv(DWIDTH-1 downto 0) := datzero; -begin - - proc_clka: process (CLKA) - begin - if rising_edge(CLKA) then - if ENA = '1' then - if WEA = '1' then - sv_ram(to_integer(unsigned(ADDRA))) := DIA; - end if; - R_DOA <= sv_ram(to_integer(unsigned(ADDRA))); - end if; - end if; - end process proc_clka; - - proc_clkb: process (CLKB) - begin - if rising_edge(CLKB) then - if ENB = '1' then - if WEB = '1' then - sv_ram(to_integer(unsigned(ADDRB))) := DIB; - end if; - R_DOB <= sv_ram(to_integer(unsigned(ADDRB))); - end if; - end if; - end process proc_clkb; - - DOA <= R_DOA; - DOB <= R_DOB; - -end syn; +-- $Id: ram_2swsr_wfirst_gen.vhd 686 2015-06-04 21:08:08Z mueller $ +-- +-- Copyright 2006-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: ram_2swsr_wfirst_gen - syn +-- Description: Dual-Port RAM with with two synchronous read/write ports +-- and 'read-through' semantics (as block RAM). +-- The code is inspired by Xilinx example rams_16.vhd. The +-- 'ram_style' attribute is set to 'block', this will +-- force in XST a synthesis as block RAM. +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic Spartan, Virtex +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-08 422 1.0.4 now numeric_std clean +-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables +-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned(); +-- 2008-03-02 122 1.0.1 change generic default for BRAM models +-- 2007-06-03 45 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; + +entity ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first + generic ( + AWIDTH : positive := 11; -- address port width + DWIDTH : positive := 9); -- data port width + port( + CLKA : in slbit; -- clock port A + CLKB : in slbit; -- clock port B + ENA : in slbit; -- enable port A + ENB : in slbit; -- enable port B + WEA : in slbit; -- write enable port A + WEB : in slbit; -- write enable port B + ADDRA : in slv(AWIDTH-1 downto 0); -- address port A + ADDRB : in slv(AWIDTH-1 downto 0); -- address port B + DIA : in slv(DWIDTH-1 downto 0); -- data in port A + DIB : in slv(DWIDTH-1 downto 0); -- data in port B + DOA : out slv(DWIDTH-1 downto 0); -- data out port A + DOB : out slv(DWIDTH-1 downto 0) -- data out port B + ); +end ram_2swsr_wfirst_gen; + + +architecture syn of ram_2swsr_wfirst_gen is + constant memsize : positive := 2**AWIDTH; + constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0'); + type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0); + shared variable sv_ram : ram_type := (others=>datzero); + + attribute ram_style : string; + attribute ram_style of sv_ram : variable is "block"; + + signal R_DOA : slv(DWIDTH-1 downto 0) := datzero; + signal R_DOB : slv(DWIDTH-1 downto 0) := datzero; +begin + + proc_clka: process (CLKA) + begin + if rising_edge(CLKA) then + if ENA = '1' then + if WEA = '1' then + sv_ram(to_integer(unsigned(ADDRA))) := DIA; + end if; + R_DOA <= sv_ram(to_integer(unsigned(ADDRA))); + end if; + end if; + end process proc_clka; + + proc_clkb: process (CLKB) + begin + if rising_edge(CLKB) then + if ENB = '1' then + if WEB = '1' then + sv_ram(to_integer(unsigned(ADDRB))) := DIB; + end if; + R_DOB <= sv_ram(to_integer(unsigned(ADDRB))); + end if; + end if; + end process proc_clkb; + + DOA <= R_DOA; + DOB <= R_DOB; + +end syn; diff --git a/rtl/vlib/memlib/ram_2swsr_wfirst_gen_unisim.vhd b/rtl/vlib/memlib/ram_2swsr_wfirst_gen_unisim.vhd index 3262e377..24c505a8 100644 --- a/rtl/vlib/memlib/ram_2swsr_wfirst_gen_unisim.vhd +++ b/rtl/vlib/memlib/ram_2swsr_wfirst_gen_unisim.vhd @@ -1,83 +1,83 @@ --- $Id: ram_2swsr_wfirst_gen_unisim.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2008- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: ram_2swsr_wfirst_gen - syn --- Description: Dual-Port RAM with with two synchronous read/write ports --- and 'read-through' semantics (as block RAM). --- Direct instantiation of Xilinx UNISIM primitives --- --- Dependencies: - --- Test bench: - --- Target Devices: Spartan-3, Virtex-2,-4 --- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 --- Revision History: --- Date Rev Version Comment --- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim --- 2008-03-02 122 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -library unisim; -use unisim.vcomponents.ALL; - -use work.slvtypes.all; -use work.memlib.all; - -entity ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first - generic ( - AWIDTH : positive := 11; -- address port width - DWIDTH : positive := 9); -- data port width - port( - CLKA : in slbit; -- clock port A - CLKB : in slbit; -- clock port B - ENA : in slbit; -- enable port A - ENB : in slbit; -- enable port B - WEA : in slbit; -- write enable port A - WEB : in slbit; -- write enable port B - ADDRA : in slv(AWIDTH-1 downto 0); -- address port A - ADDRB : in slv(AWIDTH-1 downto 0); -- address port B - DIA : in slv(DWIDTH-1 downto 0); -- data in port A - DIB : in slv(DWIDTH-1 downto 0); -- data in port B - DOA : out slv(DWIDTH-1 downto 0); -- data out port A - DOB : out slv(DWIDTH-1 downto 0) -- data out port B - ); -end ram_2swsr_wfirst_gen; - - -architecture syn of ram_2swsr_wfirst_gen is -begin - - UMEM: ram_2swsr_xfirst_gen_unisim - generic map ( - AWIDTH => AWIDTH, - DWIDTH => DWIDTH, - WRITE_MODE => "WRITE_FIRST") - port map ( - CLKA => CLKA, - CLKB => CLKB, - ENA => ENA, - ENB => ENB, - WEA => WEA, - WEB => WEB, - ADDRA => ADDRA, - ADDRB => ADDRB, - DIA => DIA, - DIB => DIB, - DOA => DOA, - DOB => DOB - ); - -end syn; +-- $Id: ram_2swsr_wfirst_gen_unisim.vhd 686 2015-06-04 21:08:08Z mueller $ +-- +-- Copyright 2008- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: ram_2swsr_wfirst_gen - syn +-- Description: Dual-Port RAM with with two synchronous read/write ports +-- and 'read-through' semantics (as block RAM). +-- Direct instantiation of Xilinx UNISIM primitives +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: Spartan-3, Virtex-2,-4 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim +-- 2008-03-02 122 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +use unisim.vcomponents.ALL; + +use work.slvtypes.all; +use work.memlib.all; + +entity ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first + generic ( + AWIDTH : positive := 11; -- address port width + DWIDTH : positive := 9); -- data port width + port( + CLKA : in slbit; -- clock port A + CLKB : in slbit; -- clock port B + ENA : in slbit; -- enable port A + ENB : in slbit; -- enable port B + WEA : in slbit; -- write enable port A + WEB : in slbit; -- write enable port B + ADDRA : in slv(AWIDTH-1 downto 0); -- address port A + ADDRB : in slv(AWIDTH-1 downto 0); -- address port B + DIA : in slv(DWIDTH-1 downto 0); -- data in port A + DIB : in slv(DWIDTH-1 downto 0); -- data in port B + DOA : out slv(DWIDTH-1 downto 0); -- data out port A + DOB : out slv(DWIDTH-1 downto 0) -- data out port B + ); +end ram_2swsr_wfirst_gen; + + +architecture syn of ram_2swsr_wfirst_gen is +begin + + UMEM: ram_2swsr_xfirst_gen_unisim + generic map ( + AWIDTH => AWIDTH, + DWIDTH => DWIDTH, + WRITE_MODE => "WRITE_FIRST") + port map ( + CLKA => CLKA, + CLKB => CLKB, + ENA => ENA, + ENB => ENB, + WEA => WEA, + WEB => WEB, + ADDRA => ADDRA, + ADDRB => ADDRB, + DIA => DIA, + DIB => DIB, + DOA => DOA, + DOB => DOB + ); + +end syn; diff --git a/rtl/vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd b/rtl/vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd index 8a316b73..426c5e4b 100644 --- a/rtl/vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd +++ b/rtl/vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd @@ -1,456 +1,456 @@ --- $Id: ram_2swsr_xfirst_gen_unisim.vhd 641 2015-02-01 22:12:15Z mueller $ --- --- Copyright 2008-2011 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: ram_2swsr_xfirst_gen_unisim - syn --- Description: Dual-Port RAM with with two synchronous read/write ports --- Direct instantiation of Xilinx UNISIM primitives --- --- Dependencies: - --- Test bench: - --- Target Devices: Spartan-3, Virtex-2,-4 --- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 --- Revision History: --- Date Rev Version Comment --- 2011-08-14 406 1.0.2 cleaner code for L_DI(A|B) initialization --- 2008-04-13 135 1.0.1 fix range error for AW_14_S1 --- 2008-03-08 123 1.0 Initial version (merged from _rfirst/_wfirst) ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -library unisim; -use unisim.vcomponents.ALL; - -use work.slvtypes.all; - -entity ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports - generic ( - AWIDTH : positive := 11; -- address port width - DWIDTH : positive := 9; -- data port width - WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST - port( - CLKA : in slbit; -- clock port A - CLKB : in slbit; -- clock port B - ENA : in slbit; -- enable port A - ENB : in slbit; -- enable port B - WEA : in slbit; -- write enable port A - WEB : in slbit; -- write enable port B - ADDRA : in slv(AWIDTH-1 downto 0); -- address port A - ADDRB : in slv(AWIDTH-1 downto 0); -- address port B - DIA : in slv(DWIDTH-1 downto 0); -- data in port A - DIB : in slv(DWIDTH-1 downto 0); -- data in port B - DOA : out slv(DWIDTH-1 downto 0); -- data out port A - DOB : out slv(DWIDTH-1 downto 0) -- data out port B - ); -end ram_2swsr_xfirst_gen_unisim; - - -architecture syn of ram_2swsr_xfirst_gen_unisim is - - constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and - ((DWIDTH+35)/36)=((DWIDTH+31)/32); - constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and - ((DWIDTH+17)/18)=((DWIDTH+16)/16); - constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and - ((DWIDTH+8)/9)=((DWIDTH+7)/8); - -begin - - assert AWIDTH>=9 and AWIDTH<=14 - report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor" - severity failure; - - AW_09_S36: if AWIDTH=9 and not ok_mod32 generate - constant dw_mem : positive := ((DWIDTH+35)/36)*36; - signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0'); - begin - - DI_PAD: if dw_mem>DWIDTH generate - L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0'); - L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0'); - end generate DI_PAD; - L_DIA(DIA'range) <= DIA; - L_DIB(DIB'range) <= DIB; - - GL: for i in dw_mem/36-1 downto 0 generate - MEM : RAMB16_S36_S36 - generic map ( - INIT_A => O"000000000000", - INIT_B => O"000000000000", - SRVAL_A => O"000000000000", - SRVAL_B => O"000000000000", - WRITE_MODE_A => WRITE_MODE, - WRITE_MODE_B => WRITE_MODE) - port map ( - DOA => L_DOA(36*i+31 downto 36*i), - DOB => L_DOB(36*i+31 downto 36*i), - DOPA => L_DOA(36*i+35 downto 36*i+32), - DOPB => L_DOB(36*i+35 downto 36*i+32), - ADDRA => ADDRA, - ADDRB => ADDRB, - CLKA => CLKA, - CLKB => CLKB, - DIA => L_DIA(36*i+31 downto 36*i), - DIB => L_DIB(36*i+31 downto 36*i), - DIPA => L_DIA(36*i+35 downto 36*i+32), - DIPB => L_DIB(36*i+35 downto 36*i+32), - ENA => ENA, - ENB => ENB, - SSRA => '0', - SSRB => '0', - WEA => WEA, - WEB => WEB - ); - end generate GL; - - DOA <= L_DOA(DOA'range); - DOB <= L_DOB(DOB'range); - - end generate AW_09_S36; - - AW_09_S32: if AWIDTH=9 and ok_mod32 generate - GL: for i in DWIDTH/32-1 downto 0 generate - MEM : RAMB16_S36_S36 - generic map ( - INIT_A => X"00000000", - INIT_B => X"00000000", - SRVAL_A => X"00000000", - SRVAL_B => X"00000000", - WRITE_MODE_A => WRITE_MODE, - WRITE_MODE_B => WRITE_MODE) - port map ( - DOA => DOA(32*i+31 downto 32*i), - DOB => DOB(32*i+31 downto 32*i), - DOPA => open, - DOPB => open, - ADDRA => ADDRA, - ADDRB => ADDRB, - CLKA => CLKA, - CLKB => CLKB, - DIA => DIA(32*i+31 downto 32*i), - DIB => DIB(32*i+31 downto 32*i), - DIPA => "0000", - DIPB => "0000", - ENA => ENA, - ENB => ENB, - SSRA => '0', - SSRB => '0', - WEA => WEA, - WEB => WEB - ); - end generate GL; - end generate AW_09_S32; - - AW_10_S18: if AWIDTH=10 and not ok_mod16 generate - constant dw_mem : positive := ((DWIDTH+17)/18)*18; - signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0'); - begin - - DI_PAD: if dw_mem>DWIDTH generate - L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0'); - L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0'); - end generate DI_PAD; - L_DIA(DIA'range) <= DIA; - L_DIB(DIB'range) <= DIB; - - GL: for i in dw_mem/18-1 downto 0 generate - MEM : RAMB16_S18_S18 - generic map ( - INIT_A => O"000000", - INIT_B => O"000000", - SRVAL_A => O"000000", - SRVAL_B => O"000000", - WRITE_MODE_A => WRITE_MODE, - WRITE_MODE_B => WRITE_MODE) - port map ( - DOA => L_DOA(18*i+15 downto 18*i), - DOB => L_DOB(18*i+15 downto 18*i), - DOPA => L_DOA(18*i+17 downto 18*i+16), - DOPB => L_DOB(18*i+17 downto 18*i+16), - ADDRA => ADDRA, - ADDRB => ADDRB, - CLKA => CLKA, - CLKB => CLKB, - DIA => L_DIA(18*i+15 downto 18*i), - DIB => L_DIB(18*i+15 downto 18*i), - DIPA => L_DIA(18*i+17 downto 18*i+16), - DIPB => L_DIB(18*i+17 downto 18*i+16), - ENA => ENA, - ENB => ENB, - SSRA => '0', - SSRB => '0', - WEA => WEA, - WEB => WEB - ); - end generate GL; - - DOA <= L_DOA(DOA'range); - DOB <= L_DOB(DOB'range); - - end generate AW_10_S18; - - AW_10_S16: if AWIDTH=10 and ok_mod16 generate - GL: for i in DWIDTH/16-1 downto 0 generate - MEM : RAMB16_S18_S18 - generic map ( - INIT_A => X"0000", - INIT_B => X"0000", - SRVAL_A => X"0000", - SRVAL_B => X"0000", - WRITE_MODE_A => WRITE_MODE, - WRITE_MODE_B => WRITE_MODE) - port map ( - DOA => DOA(16*i+15 downto 16*i), - DOB => DOB(16*i+15 downto 16*i), - DOPA => open, - DOPB => open, - ADDRA => ADDRA, - ADDRB => ADDRB, - CLKA => CLKA, - CLKB => CLKB, - DIA => DIA(16*i+15 downto 16*i), - DIB => DIB(16*i+15 downto 16*i), - DIPA => "00", - DIPB => "00", - ENA => ENA, - ENB => ENB, - SSRA => '0', - SSRB => '0', - WEA => WEA, - WEB => WEB - ); - end generate GL; - end generate AW_10_S16; - - AW_11_S9: if AWIDTH=11 and not ok_mod08 generate - constant dw_mem : positive := ((DWIDTH+8)/9)*9; - signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0'); - begin - - DI_PAD: if dw_mem>DWIDTH generate - L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0'); - L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0'); - end generate DI_PAD; - L_DIA(DIA'range) <= DIA; - L_DIB(DIB'range) <= DIB; - - GL: for i in dw_mem/9-1 downto 0 generate - MEM : RAMB16_S9_S9 - generic map ( - INIT_A => O"000", - INIT_B => O"000", - SRVAL_A => O"000", - SRVAL_B => O"000", - WRITE_MODE_A => WRITE_MODE, - WRITE_MODE_B => WRITE_MODE) - port map ( - DOA => L_DOA(9*i+7 downto 9*i), - DOB => L_DOB(9*i+7 downto 9*i), - DOPA => L_DOA(9*i+8 downto 9*i+8), - DOPB => L_DOB(9*i+8 downto 9*i+8), - ADDRA => ADDRA, - ADDRB => ADDRB, - CLKA => CLKA, - CLKB => CLKB, - DIA => L_DIA(9*i+7 downto 9*i), - DIB => L_DIB(9*i+7 downto 9*i), - DIPA => L_DIA(9*i+8 downto 9*i+8), - DIPB => L_DIB(9*i+8 downto 9*i+8), - ENA => ENA, - ENB => ENB, - SSRA => '0', - SSRB => '0', - WEA => WEA, - WEB => WEB - ); - end generate GL; - - DOA <= L_DOA(DOA'range); - DOB <= L_DOB(DOB'range); - - end generate AW_11_S9; - - AW_11_S8: if AWIDTH=11 and ok_mod08 generate - GL: for i in DWIDTH/8-1 downto 0 generate - MEM : RAMB16_S9_S9 - generic map ( - INIT_A => X"00", - INIT_B => X"00", - SRVAL_A => X"00", - SRVAL_B => X"00", - WRITE_MODE_A => WRITE_MODE, - WRITE_MODE_B => WRITE_MODE) - port map ( - DOA => DOA(8*i+7 downto 8*i), - DOB => DOB(8*i+7 downto 8*i), - DOPA => open, - DOPB => open, - ADDRA => ADDRA, - ADDRB => ADDRB, - CLKA => CLKA, - CLKB => CLKB, - DIA => DIA(8*i+7 downto 8*i), - DIB => DIB(8*i+7 downto 8*i), - DIPA => "0", - DIPB => "0", - ENA => ENA, - ENB => ENB, - SSRA => '0', - SSRB => '0', - WEA => WEA, - WEB => WEB - ); - end generate GL; - end generate AW_11_S8; - - AW_12_S4: if AWIDTH = 12 generate - constant dw_mem : positive := ((DWIDTH+3)/4)*4; - signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0'); - begin - - DI_PAD: if dw_mem>DWIDTH generate - L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0'); - L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0'); - end generate DI_PAD; - L_DIA(DIA'range) <= DIA; - L_DIB(DIB'range) <= DIB; - - GL: for i in dw_mem/4-1 downto 0 generate - MEM : RAMB16_S4_S4 - generic map ( - INIT_A => X"0", - INIT_B => X"0", - SRVAL_A => X"0", - SRVAL_B => X"0", - WRITE_MODE_A => WRITE_MODE, - WRITE_MODE_B => WRITE_MODE) - port map ( - DOA => L_DOA(4*i+3 downto 4*i), - DOB => L_DOB(4*i+3 downto 4*i), - ADDRA => ADDRA, - ADDRB => ADDRB, - CLKA => CLKA, - CLKB => CLKB, - DIA => L_DIA(4*i+3 downto 4*i), - DIB => L_DIB(4*i+3 downto 4*i), - ENA => ENA, - ENB => ENB, - SSRA => '0', - SSRB => '0', - WEA => WEA, - WEB => WEB - ); - end generate GL; - - DOA <= L_DOA(DOA'range); - DOB <= L_DOB(DOB'range); - - end generate AW_12_S4; - - AW_13_S2: if AWIDTH = 13 generate - constant dw_mem : positive := ((DWIDTH+1)/2)*2; - signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0'); - signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0'); - begin - - DI_PAD: if dw_mem>DWIDTH generate - L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0'); - L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0'); - end generate DI_PAD; - L_DIA(DIA'range) <= DIA; - L_DIB(DIB'range) <= DIB; - - GL: for i in dw_mem/2-1 downto 0 generate - MEM : RAMB16_S2_S2 - generic map ( - INIT_A => "00", - INIT_B => "00", - SRVAL_A => "00", - SRVAL_B => "00", - WRITE_MODE_A => WRITE_MODE, - WRITE_MODE_B => WRITE_MODE) - port map ( - DOA => L_DOA(2*i+1 downto 2*i), - DOB => L_DOB(2*i+1 downto 2*i), - ADDRA => ADDRA, - ADDRB => ADDRB, - CLKA => CLKA, - CLKB => CLKB, - DIA => L_DIA(2*i+1 downto 2*i), - DIB => L_DIB(2*i+1 downto 2*i), - ENA => ENA, - ENB => ENB, - SSRA => '0', - SSRB => '0', - WEA => WEA, - WEB => WEB - ); - end generate GL; - - DOA <= L_DOA(DOA'range); - DOB <= L_DOB(DOB'range); - - end generate AW_13_S2; - - AW_14_S1: if AWIDTH = 14 generate - GL: for i in DWIDTH-1 downto 0 generate - MEM : RAMB16_S1_S1 - generic map ( - INIT_A => "0", - INIT_B => "0", - SRVAL_A => "0", - SRVAL_B => "0", - WRITE_MODE_A => WRITE_MODE, - WRITE_MODE_B => WRITE_MODE) - port map ( - DOA => DOA(i downto i), - DOB => DOB(i downto i), - ADDRA => ADDRA, - ADDRB => ADDRB, - CLKA => CLKA, - CLKB => CLKB, - DIA => DIA(i downto i), - DIB => DIB(i downto i), - ENA => ENA, - ENB => ENB, - SSRA => '0', - SSRB => '0', - WEA => WEA, - WEB => WEB - ); - end generate GL; - end generate AW_14_S1; - - -end syn; - --- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are --- nonsense: INIT_A : bit_vector := X"000"; --- This is a 12 bit value, while a 9 bit one is needed. Thus the --- explicit definition above. +-- $Id: ram_2swsr_xfirst_gen_unisim.vhd 686 2015-06-04 21:08:08Z mueller $ +-- +-- Copyright 2008-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: ram_2swsr_xfirst_gen_unisim - syn +-- Description: Dual-Port RAM with with two synchronous read/write ports +-- Direct instantiation of Xilinx UNISIM primitives +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: Spartan-3, Virtex-2,-4 +-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2011-08-14 406 1.0.2 cleaner code for L_DI(A|B) initialization +-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1 +-- 2008-03-08 123 1.0 Initial version (merged from _rfirst/_wfirst) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +use unisim.vcomponents.ALL; + +use work.slvtypes.all; + +entity ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports + generic ( + AWIDTH : positive := 11; -- address port width + DWIDTH : positive := 9; -- data port width + WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST + port( + CLKA : in slbit; -- clock port A + CLKB : in slbit; -- clock port B + ENA : in slbit; -- enable port A + ENB : in slbit; -- enable port B + WEA : in slbit; -- write enable port A + WEB : in slbit; -- write enable port B + ADDRA : in slv(AWIDTH-1 downto 0); -- address port A + ADDRB : in slv(AWIDTH-1 downto 0); -- address port B + DIA : in slv(DWIDTH-1 downto 0); -- data in port A + DIB : in slv(DWIDTH-1 downto 0); -- data in port B + DOA : out slv(DWIDTH-1 downto 0); -- data out port A + DOB : out slv(DWIDTH-1 downto 0) -- data out port B + ); +end ram_2swsr_xfirst_gen_unisim; + + +architecture syn of ram_2swsr_xfirst_gen_unisim is + + constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and + ((DWIDTH+35)/36)=((DWIDTH+31)/32); + constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and + ((DWIDTH+17)/18)=((DWIDTH+16)/16); + constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and + ((DWIDTH+8)/9)=((DWIDTH+7)/8); + +begin + + assert AWIDTH>=9 and AWIDTH<=14 + report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor" + severity failure; + + AW_09_S36: if AWIDTH=9 and not ok_mod32 generate + constant dw_mem : positive := ((DWIDTH+35)/36)*36; + signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0'); + begin + + DI_PAD: if dw_mem>DWIDTH generate + L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0'); + L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0'); + end generate DI_PAD; + L_DIA(DIA'range) <= DIA; + L_DIB(DIB'range) <= DIB; + + GL: for i in dw_mem/36-1 downto 0 generate + MEM : RAMB16_S36_S36 + generic map ( + INIT_A => O"000000000000", + INIT_B => O"000000000000", + SRVAL_A => O"000000000000", + SRVAL_B => O"000000000000", + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE) + port map ( + DOA => L_DOA(36*i+31 downto 36*i), + DOB => L_DOB(36*i+31 downto 36*i), + DOPA => L_DOA(36*i+35 downto 36*i+32), + DOPB => L_DOB(36*i+35 downto 36*i+32), + ADDRA => ADDRA, + ADDRB => ADDRB, + CLKA => CLKA, + CLKB => CLKB, + DIA => L_DIA(36*i+31 downto 36*i), + DIB => L_DIB(36*i+31 downto 36*i), + DIPA => L_DIA(36*i+35 downto 36*i+32), + DIPB => L_DIB(36*i+35 downto 36*i+32), + ENA => ENA, + ENB => ENB, + SSRA => '0', + SSRB => '0', + WEA => WEA, + WEB => WEB + ); + end generate GL; + + DOA <= L_DOA(DOA'range); + DOB <= L_DOB(DOB'range); + + end generate AW_09_S36; + + AW_09_S32: if AWIDTH=9 and ok_mod32 generate + GL: for i in DWIDTH/32-1 downto 0 generate + MEM : RAMB16_S36_S36 + generic map ( + INIT_A => X"00000000", + INIT_B => X"00000000", + SRVAL_A => X"00000000", + SRVAL_B => X"00000000", + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE) + port map ( + DOA => DOA(32*i+31 downto 32*i), + DOB => DOB(32*i+31 downto 32*i), + DOPA => open, + DOPB => open, + ADDRA => ADDRA, + ADDRB => ADDRB, + CLKA => CLKA, + CLKB => CLKB, + DIA => DIA(32*i+31 downto 32*i), + DIB => DIB(32*i+31 downto 32*i), + DIPA => "0000", + DIPB => "0000", + ENA => ENA, + ENB => ENB, + SSRA => '0', + SSRB => '0', + WEA => WEA, + WEB => WEB + ); + end generate GL; + end generate AW_09_S32; + + AW_10_S18: if AWIDTH=10 and not ok_mod16 generate + constant dw_mem : positive := ((DWIDTH+17)/18)*18; + signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0'); + begin + + DI_PAD: if dw_mem>DWIDTH generate + L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0'); + L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0'); + end generate DI_PAD; + L_DIA(DIA'range) <= DIA; + L_DIB(DIB'range) <= DIB; + + GL: for i in dw_mem/18-1 downto 0 generate + MEM : RAMB16_S18_S18 + generic map ( + INIT_A => O"000000", + INIT_B => O"000000", + SRVAL_A => O"000000", + SRVAL_B => O"000000", + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE) + port map ( + DOA => L_DOA(18*i+15 downto 18*i), + DOB => L_DOB(18*i+15 downto 18*i), + DOPA => L_DOA(18*i+17 downto 18*i+16), + DOPB => L_DOB(18*i+17 downto 18*i+16), + ADDRA => ADDRA, + ADDRB => ADDRB, + CLKA => CLKA, + CLKB => CLKB, + DIA => L_DIA(18*i+15 downto 18*i), + DIB => L_DIB(18*i+15 downto 18*i), + DIPA => L_DIA(18*i+17 downto 18*i+16), + DIPB => L_DIB(18*i+17 downto 18*i+16), + ENA => ENA, + ENB => ENB, + SSRA => '0', + SSRB => '0', + WEA => WEA, + WEB => WEB + ); + end generate GL; + + DOA <= L_DOA(DOA'range); + DOB <= L_DOB(DOB'range); + + end generate AW_10_S18; + + AW_10_S16: if AWIDTH=10 and ok_mod16 generate + GL: for i in DWIDTH/16-1 downto 0 generate + MEM : RAMB16_S18_S18 + generic map ( + INIT_A => X"0000", + INIT_B => X"0000", + SRVAL_A => X"0000", + SRVAL_B => X"0000", + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE) + port map ( + DOA => DOA(16*i+15 downto 16*i), + DOB => DOB(16*i+15 downto 16*i), + DOPA => open, + DOPB => open, + ADDRA => ADDRA, + ADDRB => ADDRB, + CLKA => CLKA, + CLKB => CLKB, + DIA => DIA(16*i+15 downto 16*i), + DIB => DIB(16*i+15 downto 16*i), + DIPA => "00", + DIPB => "00", + ENA => ENA, + ENB => ENB, + SSRA => '0', + SSRB => '0', + WEA => WEA, + WEB => WEB + ); + end generate GL; + end generate AW_10_S16; + + AW_11_S9: if AWIDTH=11 and not ok_mod08 generate + constant dw_mem : positive := ((DWIDTH+8)/9)*9; + signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0'); + begin + + DI_PAD: if dw_mem>DWIDTH generate + L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0'); + L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0'); + end generate DI_PAD; + L_DIA(DIA'range) <= DIA; + L_DIB(DIB'range) <= DIB; + + GL: for i in dw_mem/9-1 downto 0 generate + MEM : RAMB16_S9_S9 + generic map ( + INIT_A => O"000", + INIT_B => O"000", + SRVAL_A => O"000", + SRVAL_B => O"000", + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE) + port map ( + DOA => L_DOA(9*i+7 downto 9*i), + DOB => L_DOB(9*i+7 downto 9*i), + DOPA => L_DOA(9*i+8 downto 9*i+8), + DOPB => L_DOB(9*i+8 downto 9*i+8), + ADDRA => ADDRA, + ADDRB => ADDRB, + CLKA => CLKA, + CLKB => CLKB, + DIA => L_DIA(9*i+7 downto 9*i), + DIB => L_DIB(9*i+7 downto 9*i), + DIPA => L_DIA(9*i+8 downto 9*i+8), + DIPB => L_DIB(9*i+8 downto 9*i+8), + ENA => ENA, + ENB => ENB, + SSRA => '0', + SSRB => '0', + WEA => WEA, + WEB => WEB + ); + end generate GL; + + DOA <= L_DOA(DOA'range); + DOB <= L_DOB(DOB'range); + + end generate AW_11_S9; + + AW_11_S8: if AWIDTH=11 and ok_mod08 generate + GL: for i in DWIDTH/8-1 downto 0 generate + MEM : RAMB16_S9_S9 + generic map ( + INIT_A => X"00", + INIT_B => X"00", + SRVAL_A => X"00", + SRVAL_B => X"00", + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE) + port map ( + DOA => DOA(8*i+7 downto 8*i), + DOB => DOB(8*i+7 downto 8*i), + DOPA => open, + DOPB => open, + ADDRA => ADDRA, + ADDRB => ADDRB, + CLKA => CLKA, + CLKB => CLKB, + DIA => DIA(8*i+7 downto 8*i), + DIB => DIB(8*i+7 downto 8*i), + DIPA => "0", + DIPB => "0", + ENA => ENA, + ENB => ENB, + SSRA => '0', + SSRB => '0', + WEA => WEA, + WEB => WEB + ); + end generate GL; + end generate AW_11_S8; + + AW_12_S4: if AWIDTH = 12 generate + constant dw_mem : positive := ((DWIDTH+3)/4)*4; + signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0'); + begin + + DI_PAD: if dw_mem>DWIDTH generate + L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0'); + L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0'); + end generate DI_PAD; + L_DIA(DIA'range) <= DIA; + L_DIB(DIB'range) <= DIB; + + GL: for i in dw_mem/4-1 downto 0 generate + MEM : RAMB16_S4_S4 + generic map ( + INIT_A => X"0", + INIT_B => X"0", + SRVAL_A => X"0", + SRVAL_B => X"0", + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE) + port map ( + DOA => L_DOA(4*i+3 downto 4*i), + DOB => L_DOB(4*i+3 downto 4*i), + ADDRA => ADDRA, + ADDRB => ADDRB, + CLKA => CLKA, + CLKB => CLKB, + DIA => L_DIA(4*i+3 downto 4*i), + DIB => L_DIB(4*i+3 downto 4*i), + ENA => ENA, + ENB => ENB, + SSRA => '0', + SSRB => '0', + WEA => WEA, + WEB => WEB + ); + end generate GL; + + DOA <= L_DOA(DOA'range); + DOB <= L_DOB(DOB'range); + + end generate AW_12_S4; + + AW_13_S2: if AWIDTH = 13 generate + constant dw_mem : positive := ((DWIDTH+1)/2)*2; + signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0'); + signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0'); + begin + + DI_PAD: if dw_mem>DWIDTH generate + L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0'); + L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0'); + end generate DI_PAD; + L_DIA(DIA'range) <= DIA; + L_DIB(DIB'range) <= DIB; + + GL: for i in dw_mem/2-1 downto 0 generate + MEM : RAMB16_S2_S2 + generic map ( + INIT_A => "00", + INIT_B => "00", + SRVAL_A => "00", + SRVAL_B => "00", + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE) + port map ( + DOA => L_DOA(2*i+1 downto 2*i), + DOB => L_DOB(2*i+1 downto 2*i), + ADDRA => ADDRA, + ADDRB => ADDRB, + CLKA => CLKA, + CLKB => CLKB, + DIA => L_DIA(2*i+1 downto 2*i), + DIB => L_DIB(2*i+1 downto 2*i), + ENA => ENA, + ENB => ENB, + SSRA => '0', + SSRB => '0', + WEA => WEA, + WEB => WEB + ); + end generate GL; + + DOA <= L_DOA(DOA'range); + DOB <= L_DOB(DOB'range); + + end generate AW_13_S2; + + AW_14_S1: if AWIDTH = 14 generate + GL: for i in DWIDTH-1 downto 0 generate + MEM : RAMB16_S1_S1 + generic map ( + INIT_A => "0", + INIT_B => "0", + SRVAL_A => "0", + SRVAL_B => "0", + WRITE_MODE_A => WRITE_MODE, + WRITE_MODE_B => WRITE_MODE) + port map ( + DOA => DOA(i downto i), + DOB => DOB(i downto i), + ADDRA => ADDRA, + ADDRB => ADDRB, + CLKA => CLKA, + CLKB => CLKB, + DIA => DIA(i downto i), + DIB => DIB(i downto i), + ENA => ENA, + ENB => ENB, + SSRA => '0', + SSRB => '0', + WEA => WEA, + WEB => WEB + ); + end generate GL; + end generate AW_14_S1; + + +end syn; + +-- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are +-- nonsense: INIT_A : bit_vector := X"000"; +-- This is a 12 bit value, while a 9 bit one is needed. Thus the +-- explicit definition above. diff --git a/tools/asm-11/lib/defs_tm.mac b/tools/asm-11/lib/defs_tm.mac new file mode 100644 index 00000000..1012e8be --- /dev/null +++ b/tools/asm-11/lib/defs_tm.mac @@ -0,0 +1,38 @@ +; $Id: defs_tm.mac 683 2015-05-17 21:54:35Z mueller $ +; Copyright 2015- by Walter F.J. Mueller +; License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +; +; definitions for RK11 controler +; +; register addresses +; + tm.sr =172520 + tm.cr =172522 + tm.bc =172524 + tm.ba =172526 + tm.db =172530 + tm.rl =172532 +; +; symbol definitions for tm.sr +; + tm.icm=100000 + tm.eof=040000 + tm.pae=010000 + tm.eot=002000 + tm.rle=001000 + tm.bte=000400 + tm.nxm=000200 + tm.onl=000100 + tm.bot=000040 + tm.wrl=000004 + tm.rew=000002 + tm.tur=000001 +; +; symbol definitions for tm.cr +; + tm.err=100000 + tm.ini=010000 + tm.pev=004000 + tm.rdy=000200 + tm.ie =000100 + tm.go =000001 diff --git a/tools/bin/create_disk b/tools/bin/create_disk index 82f49434..22f72d94 100755 --- a/tools/bin/create_disk +++ b/tools/bin/create_disk @@ -1,5 +1,5 @@ #!/usr/bin/perl -w -# $Id: create_disk 679 2015-05-13 17:38:46Z mueller $ +# $Id: create_disk 686 2015-06-04 21:08:08Z mueller $ # # Copyright 2013-2014 by Walter F.J. Mueller # @@ -14,6 +14,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-06-04 686 1.1.2 use sysseek rather seek; add RM80 # 2015-04-06 665 1.1.1 add alias RM03 (for RM02) and RP05 (for RP04) # 2014-06-14 562 1.1 BUGFIX: repair --boot; add RM02,RM05,RP04,RP07 # 2013-05-20 521 1.0 First draft @@ -44,6 +45,7 @@ my %disktype = ( RL02 => {cyl=> 512, hd=> 2, sec=> 40, bps=> 256, bad=>1}, RM02 => {cyl=> 823, hd=> 5, sec=> 32, bps=> 512, bad=>1}, RM05 => {cyl=> 823, hd=> 19, sec=> 32, bps=> 512, bad=>1}, + RM80 => {cyl=> 559, hd=> 14, sec=> 31, bps=> 512, bad=>1}, RP04 => {cyl=> 411, hd=> 19, sec=> 22, bps=> 512, bad=>1}, RP06 => {cyl=> 815, hd=> 19, sec=> 22, bps=> 512, bad=>1}, RP07 => {cyl=> 630, hd=> 32, sec=> 50, bps=> 512, bad=>1} @@ -97,8 +99,8 @@ my $fh = new FileHandle; sysopen($fh, $fnam, O_RDWR|O_CREAT) or die "failed to create '$fnam': $!"; -# seek to end, wrte 1 byte at end -my $rc = $fh->seek($cap-1, SEEK_SET); +# seek to end, write 1 byte at end +my $rc = sysseek($fh, $cap-1, SEEK_SET); if (not $rc) {die "seek failed: $!";} my $buf = pack('C1',0); $rc = syswrite($fh, $buf, length($buf)); @@ -118,7 +120,7 @@ do_boot if $opts{boot}; sub do_inipatt { my $ini = $opts{ini}; - if ($ini eq 'zero' ||$ini eq 'ones' || $ini eq 'dead') { + if ($ini eq 'zero' || $ini eq 'ones' || $ini eq 'dead') { my @dat; for (my $i=0; $i<$bps/4; $i++) { push @dat, 0,0 if $ini eq 'zero'; @@ -271,7 +273,7 @@ sub print_help { print "\n"; print "currently supported initialization patterns:\n"; - print " zero all zero (the default anyway if no -ini given)\n"; + print " zero all zero (will cause explicit disk space allocation)\n"; print " ones all ones\n"; print " dead alternating 0xdead 0xbeaf pattern\n"; print " test writes unique groups of 8 16bit words\n"; diff --git a/tools/bin/file2tap b/tools/bin/file2tap new file mode 100755 index 00000000..9e6b906f --- /dev/null +++ b/tools/bin/file2tap @@ -0,0 +1,119 @@ +#!/usr/bin/perl -w +# $Id: file2tap 686 2015-06-04 21:08:08Z mueller $ +# +# Copyright 2008-2015 by Walter F.J. Mueller +# +# This program is free software; you may redistribute and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation, either version 2, or at your option any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for complete details. +# +# Revision History: +# Date Rev Version Comment +# 2015-06-03 686 1.1 fix -a option; support eom at end +# 2008-12-07 175 1.0.1 remove some upperfluous 'my' +# 2008-11-29 174 1.0 Initial version (import from tbird backup) +# +# +# Create a simh tape container file (.tap) from a set of files +# +# Usage: file2tap -c name -b n file1 ... filen +# +# if -c name is omitted, stdout is used +# + +use strict; +use Fcntl qw(:seek O_RDWR); + +my $arg; +my $cdone; +my $blocksize = 512; +my $nfile = 0; + +while ($arg = shift) { + + if ($arg eq "-c") { + if (@ARGV) { + $arg = shift; + open(OFILE, ">$arg") || die ("Can't open output file $arg: $!"); + $cdone = 1; + } + + } elsif ($arg eq "-a") { + if (@ARGV) { + $arg = shift; + sysopen OFILE, $arg, O_RDWR || die ("Can't open output file $arg: $!"); + my $buf; + my $len; + + # check for EOM mark at end, if found, truncate it away + sysseek OFILE, -4, SEEK_END; + $len = sysread OFILE, $buf, 4; + if ($buf eq "\xff\xff\xff\xff") { + truncate OFILE, sysseek(OFILE, -4, SEEK_END); + } + + # check for two EOF marks at end, if found, truncate 2nd away + sysseek OFILE, -8, SEEK_END; + $len = sysread OFILE, $buf, 8; + if ($buf ne "\x00\x00\x00\x00\x00\x00\x00\x00") { + die ("Didn't find double EOF at end of tap file"); + } + truncate OFILE, sysseek(OFILE, -4, SEEK_END); + + close OFILE; + open(OFILE, ">>$arg") || die ("Can't append to output file $arg: $!"); + $cdone = 1; + } + + } elsif ($arg eq "-b") { + if (@ARGV) { + $arg = shift; + $blocksize = 512 * int $arg; + } + + } else { + if (!$cdone) { + open(OFILE, ">-") || die ("Can't open stdout: $!"); + } + + my @flist = split(",",$arg); + my $file; + foreach $file (@flist) { + add_file($file, $blocksize); + } + $nfile += 1; + end_file(); + } +} +end_file(); + +# ---------------------------------------------------------------------------- +sub end_file { + print OFILE "\x00\x00\x00\x00"; +} + +# ---------------------------------------------------------------------------- +sub add_file { + my($filename, $blocksize) = @_; + my($block, $bytes_read, $length, $nb); + + open(FILE, $filename) || die("Can't open $filename: $!"); + while($bytes_read = read(FILE, $block, $blocksize)) { + if($bytes_read < $blocksize) { + $block .= "\x00" x ($blocksize - $bytes_read); + } + $length = pack("V", $blocksize); + print OFILE $length, $block, $length; + $nb += 1; + } + close(FILE); + if ($cdone) { + printf "file: %3d records: %5d length: %5d file: $filename\n", + $nfile, $nb, $blocksize; + } +} diff --git a/tools/bin/tap2file b/tools/bin/tap2file new file mode 100755 index 00000000..45992825 --- /dev/null +++ b/tools/bin/tap2file @@ -0,0 +1,129 @@ +#!/usr/bin/perl -w +# $Id: tap2file 686 2015-06-04 21:08:08Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# +# This program is free software; you may redistribute and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation, either version 2, or at your option any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for complete details. +# +# Revision History: +# Date Rev Version Comment +# 2015-06-03 686 1.0.1 add print_usage; cleanups +# 2015-05-24 684 1.0 Initial version +# +# Expand a simh tape container file (.tap) to a set of files +# +# Usage: tap2file [--pref=pref] file +# +use 5.14.0; # require Perl 5.14 or higher +use strict; # require strict checking + +use Getopt::Long; + +my %opts = (); + +GetOptions(\%opts, "pref=s", "help") + or die "bad options"; + +sub close_ofile; +sub print_usage; + +if (scalar(@ARGV) == 0 || exists $opts{help}) { + print_usage; + exit 0; +} + +my $ifile = shift @ARGV; +exit 0 unless defined $ifile; + +open(IFILE, "<$ifile") || die("Can't open $ifile: $!"); + +my $basename = $ifile; +$basename = $1 if $ifile =~ m|.*/(.*)|; +my $fstem = $basename; +$fstem = $1 if $basename =~ m|(.*)\..*|; + +my $pref = (exists $opts{pref}) ? $opts{pref} : "${fstem}_"; + +my $nfile = 0; +my $nrec = 0; +my $rlmin = 0; +my $rlmax = 0; +my $ofile = ""; + +my $block; +my $nb; + +while ($nb = read(IFILE, $block, 4)) { + my $metabeg = unpack("V", $block); + + if ($metabeg == 0x00000000) { + close_ofile; + $nfile += 1; + next; + } + if ($metabeg == 0xffffffff) { + last; + } + + unless (defined fileno OFILE) { + $ofile = sprintf("%s%02d.dat", $pref,$nfile); + open(OFILE, ">$ofile") || die("Can't open $ofile: $!"); + } + + $nb = read(IFILE, $block, $metabeg); + print OFILE $block; + if ($nrec == 0) { + $rlmin = $metabeg; + $rlmax = $metabeg; + } else { + $rlmin = $metabeg if $metabeg < $rlmin; + $rlmax = $metabeg if $metabeg > $rlmin; + } + $nrec += 1; + + $nb = read(IFILE, $block, 4); + my $metaend = unpack("V", $block); + if ($nb != 4 || not defined $metaend) { + printf "bad meta tag: beg=%8.8x\n", $metabeg; + last; + } + if ($metaend != $metabeg) { + printf "bad meta tags: beg=%8.8x end=%8.8x\n", $metabeg,$metaend; + last; + } +} + +close_ofile; +exit 0; + +# ---------------------------------------------------------------------------- +sub close_ofile { + return unless (defined fileno OFILE); + close(OFILE); + if ($rlmin == $rlmax) { + printf "%s: %6d records, length %5d\n", + $ofile, $nrec, $rlmin; + } else { + printf "%s: %6d records, length min=%5d, max=%5d\n", + $ofile, $nrec, $rlmin, $rlmax; + } + $nrec = 0; + $rlmin = 0; + $rlmax = 0; +} + +# ---------------------------------------------------------------------------- +sub print_usage { + print "usage: tap2file [options] ifile\n"; + print " ifile input tap file\n"; + print " Options\n"; + print " --pref=p use p as prefix for generated files\n"; + print " --help this message\n"; +} diff --git a/tools/dox/w11_cpp.Doxyfile b/tools/dox/w11_cpp.Doxyfile index 698d2438..e0dc7277 100644 --- a/tools/dox/w11_cpp.Doxyfile +++ b/tools/dox/w11_cpp.Doxyfile @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - cpp" -PROJECT_NUMBER = 0.65 +PROJECT_NUMBER = 0.66 PROJECT_BRIEF = "Backend server for Rlink and w11" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/cpp diff --git a/tools/dox/w11_tcl.Doxyfile b/tools/dox/w11_tcl.Doxyfile index 9bca05f6..17167f9e 100644 --- a/tools/dox/w11_tcl.Doxyfile +++ b/tools/dox/w11_tcl.Doxyfile @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - tcl" -PROJECT_NUMBER = 0.65 +PROJECT_NUMBER = 0.66 PROJECT_BRIEF = "Backend server for Rlink and w11" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/tcl diff --git a/tools/dox/w11_vhd_all.Doxyfile b/tools/dox/w11_vhd_all.Doxyfile index 84faf754..3f753d55 100644 --- a/tools/dox/w11_vhd_all.Doxyfile +++ b/tools/dox/w11_vhd_all.Doxyfile @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - vhd" -PROJECT_NUMBER = 0.65 +PROJECT_NUMBER = 0.66 PROJECT_BRIEF = "W11 CPU core and support modules" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/vhd diff --git a/tools/oskit/211bsd_rk/README_211bsd_rkset.txt b/tools/oskit/211bsd_rk/README_211bsd_rkset.txt index 156b3e6a..709dc0a7 100644 --- a/tools/oskit/211bsd_rk/README_211bsd_rkset.txt +++ b/tools/oskit/211bsd_rk/README_211bsd_rkset.txt @@ -58,7 +58,7 @@ Notes on oskit: 2.11BSD system on RK05 volumes lp 0 csr 177514 vector 200 attached rk 0 csr 177400 vector 220 attached rl 0 csr 174400 vector 160 attached - tm ? csr 172520 vector 224 skipped: No CSR. + tm 0 csr 172520 vector 224 attached xp 0 csr 176700 vector 254 attached cn 1 csr 176500 vector 300 attached erase, kill ^U, intr ^C diff --git a/tools/oskit/211bsd_rl/README_211bsd_rlset.txt b/tools/oskit/211bsd_rl/README_211bsd_rlset.txt index 8cd0aaff..65f21f01 100644 --- a/tools/oskit/211bsd_rl/README_211bsd_rlset.txt +++ b/tools/oskit/211bsd_rl/README_211bsd_rlset.txt @@ -58,7 +58,7 @@ Notes on oskit: 2.11BSD system on RL02 volumes lp 0 csr 177514 vector 200 attached rk 0 csr 177400 vector 220 attached rl 0 csr 174400 vector 160 attached - tm ? csr 172520 vector 224 skipped: No CSR. + tm 0 csr 172520 vector 224 attached xp 0 csr 176700 vector 254 attached cn 1 csr 176500 vector 300 attached erase, kill ^U, intr ^C diff --git a/tools/oskit/211bsd_rp/.cvsignore b/tools/oskit/211bsd_rp/.cvsignore index d9d13510..b3264455 100644 --- a/tools/oskit/211bsd_rp/.cvsignore +++ b/tools/oskit/211bsd_rp/.cvsignore @@ -1,5 +1,6 @@ *.dat *.dsk *.log +*.tgz *license.txt *license.pdf diff --git a/tools/oskit/211bsd_rp/211bsd_rp_boot.scmd b/tools/oskit/211bsd_rp/211bsd_rp_boot.scmd index e7b8bb9f..89692399 100644 --- a/tools/oskit/211bsd_rp/211bsd_rp_boot.scmd +++ b/tools/oskit/211bsd_rp/211bsd_rp_boot.scmd @@ -1,4 +1,4 @@ -; $Id: 211bsd_rp_boot.scmd 666 2015-04-12 21:17:54Z mueller $ +; $Id: 211bsd_rp_boot.scmd 686 2015-06-04 21:08:08Z mueller $ ; ; Setup file for 211bsd RP06 based system ; @@ -19,6 +19,5 @@ set rl2 rl02 set rl3 rl02 ; att rp0 211bsd_rp.dsk -att rk6 rk_home.dsk ; boo rp0 diff --git a/tools/oskit/211bsd_rp/211bsd_rp_boot.tcl b/tools/oskit/211bsd_rp/211bsd_rp_boot.tcl index d93403a5..4566b825 100644 --- a/tools/oskit/211bsd_rp/211bsd_rp_boot.tcl +++ b/tools/oskit/211bsd_rp/211bsd_rp_boot.tcl @@ -1,4 +1,4 @@ -# $Id: 211bsd_rp_boot.tcl 679 2015-05-13 17:38:46Z mueller $ +# $Id: 211bsd_rp_boot.tcl 686 2015-06-04 21:08:08Z mueller $ # # Setup file for 211bsd RP06 based system # diff --git a/tools/oskit/211bsd_rp/README_211bsd_rpset.txt b/tools/oskit/211bsd_rp/README_211bsd_rpset.txt index a63b5da7..cae4bc86 100644 --- a/tools/oskit/211bsd_rp/README_211bsd_rpset.txt +++ b/tools/oskit/211bsd_rp/README_211bsd_rpset.txt @@ -60,7 +60,7 @@ Notes on oskit: 2.11BSD system on a RP06 volume lp 0 csr 177514 vector 200 attached rk 0 csr 177400 vector 220 attached rl 0 csr 174400 vector 160 attached - tm ? csr 172520 vector 224 skipped: No CSR. + tm 0 csr 172520 vector 224 attached xp 0 csr 176700 vector 254 attached cn 1 csr 176500 vector 300 attached erase, kill ^U, intr ^C diff --git a/tools/oskit/211bsd_tm/.cvsignore b/tools/oskit/211bsd_tm/.cvsignore new file mode 100644 index 00000000..8397b0ca --- /dev/null +++ b/tools/oskit/211bsd_tm/.cvsignore @@ -0,0 +1,7 @@ +*.dat +*.dsk +*.log +*.tap +*.tgz +*license.txt +*license.pdf diff --git a/tools/oskit/211bsd_tm/211bsd_tm_boot.scmd b/tools/oskit/211bsd_tm/211bsd_tm_boot.scmd new file mode 100644 index 00000000..94c7bfea --- /dev/null +++ b/tools/oskit/211bsd_tm/211bsd_tm_boot.scmd @@ -0,0 +1,26 @@ +; $Id: $ +; +; Setup file for creating a 211bsd RP06 system from a TM11 dist kit +; +; Usage: +; +; pdp11 211bsd_tm_boot.scmd +; +do ../../simh/setup_w11a_max.scmd +set tto 7b +set dlo0 7b +; +set rp0 rp06 +set rp1 rp06 +; +set rl0 rl02 +set rl1 rl02 +set rl2 rl02 +set rl3 rl02 +; +set tm0 locked +; +att rp0 211bsd_rp06.dsk +att tm0 211bsd_tm.tap +; +boo tm0 diff --git a/tools/oskit/211bsd_tm/211bsd_tm_boot.tcl b/tools/oskit/211bsd_tm/211bsd_tm_boot.tcl new file mode 100644 index 00000000..e6b3235d --- /dev/null +++ b/tools/oskit/211bsd_tm/211bsd_tm_boot.tcl @@ -0,0 +1,32 @@ +# $Id: $ +# +# Setup file for creating a 211bsd RP06 system from a TM11 dist kit +# +# Usage: +# +# console_starter -d DL0 & +# console_starter -d DL1 & +# create_disk --typ=rp06 --bad 211bsd_rp06.dsk +# ti_w11 -xxx @211bsd_tm_boot.tcl ( -xxx depends on sim or fpga connect) +# + +# setup w11 cpu +puts [rlw] + +# setup tt,lp (211bsd uses parity -> use 7 bit mode) +rw11::setup_tt "cpu0" {to7bit 1} +rw11::setup_lp + +# mount disks +cpu0rpa0 set type rp06 +cpu0rpa1 set type rp06 + +cpu0rpa0 att 211bsd_rp06.dsk + +# mount tapes +cpu0tma0 att 211bsd_tm.tap?wpro + +# and boot +rw11::cpumon +rw11::cpucons +cpu0 boot tma0 diff --git a/tools/oskit/211bsd_tm/README_211bsd_tmset.txt b/tools/oskit/211bsd_tm/README_211bsd_tmset.txt new file mode 100644 index 00000000..853a6cc8 --- /dev/null +++ b/tools/oskit/211bsd_tm/README_211bsd_tmset.txt @@ -0,0 +1,274 @@ +# $Id: README_211bsd_rpset.txt 680 2015-05-14 13:29:46Z mueller $ + +Notes on oskit: 2.11BSD system on a TM11 tape distribution kit + + Table of content: + + 1. General remarks + 2. Installation + 3. Usage + 4. Install 211bsd from tape on a RP06 disk + +1. General remarks --------------------------------------------------- + + See notes on + + 1. I/O emulation setup + 2. FPGA Board setup + 3. Rlink and Backend Server setup + 4. Legal terms + + in $RETROBASE/doc/w11a_os_guide.txt + +2. Installation ------------------------------------------------------ + + - A tape set is available from + http://www.retro11.de/data/oc_w11/oskits/211bsd_tmset.tgz + Download, unpack and copy the tape images (*.tap), e.g. + + cd $RETROBASE/tools/oskit/211bsd_tm/ + wget http://www.retro11.de/data/oc_w11/oskits/211bsd_tmset.tgz + tar -xzf 211bsd_tmset.tgz + +3. Usage ------------------------------------------------------------- + + - This is a tape distribution kit and tailoed to be installed on RP06 disks. + So first step is to create a disk image which will hold the system + + create_disk --typ=rp06 --bad 211bsd_rp06.dsk + + - Start backend server and boot system (see section 3 in w11a_os_guide.txt) + boot script: 211bsd_tm_boot.tcl + example: ti_w11 @211bsd_tm_boot.tcl + where is the proper option set for the board. + + - Hit in the xterm window to connnect to backend server. + The boot dialog in the console xterm window will look like + (required input is in {..}, with {} denoting a carriage return: + + 70Boot from tm(0,0,0) at 0172522 + : + + This prompt of the 'mtboot' monitor, from which the different steps of + the installation procedure can be started. + +4. Install 211bsd from tape on a RP06 disk --------------------------- + + The tape distribution contains 8 files + + file #records length Contents + 0 73 512 tape boot (twice) and boot handler + 1 38 1024 standalone disklabel + 2 34 1024 standalone mkfs + 3 36 1024 standalone restor + 4 33 1024 standalone icheck + 5 501 10240 dump of root file system + 6 3516 10240 tar of adm bin crash ... + 7 903 10240 tar of sys include + 8 4168 10240 tar of remaining directories + + The installation will + - partition the disk with disklabel + - create the root file system with mkfs + - re-store the root file system with restor + - than boot 211bsd from disk into single user mode + - write the boot block + - create the /usr file system + - load the /usr file with tar from tape (three steps) + +4.1 Install 211bsd, tape phase --------------------------------------- + + The following shows the full dialogue, the input is after a '##' separator + +70Boot from tm(0,0,0) at 0172522 +: ## tm(0,1) +Boot: bootdev=0401 bootcsr=0172522 +disklabel +Disk? ## xp(0,0) +'xp(0,0)' is unlabeled or the label is corrupt. +Proceed? [y/n] ## y +d(isplay) D(efault) m(odify) w(rite) q(uit)? ## m +modify +d(isplay) g(eometry) m(isc) p(artitions) q(uit)? ## p +modify partitions +d(isplay) n(umber) s(elect) q(uit)? ## n +Number of partitions (8 max) [1]? ## 3 +modify partitions +d(isplay) n(umber) s(elect) q(uit)? ## s +a b c d e f g h q(uit)? ## a +sizes and offsets may be given as sectors, cylinders +or cylinders plus sectors: 6200, 32c, 19c10s respectively +modify partition 'a' +d(isplay) z(ero) t(ype) o(ffset) s(ize) f(rag) F(size) q(uit)? ## t +'a' fstype [2.11BSD]: ## 2.11BSD +modify partition 'a' +d(isplay) z(ero) t(ype) o(ffset) s(ize) f(rag) F(size) q(uit)? ## o +'a' offset [0]: ## +modify partition 'a' +d(isplay) z(ero) t(ype) o(ffset) s(ize) f(rag) F(size) q(uit)? ## s +'a' size [340670]: ## 50c +modify partition 'a' +d(isplay) z(ero) t(ype) o(ffset) s(ize) f(rag) F(size) q(uit)? ## q +modify partitions +d(isplay) n(umber) s(elect) q(uit)? ## s +a b c d e f g h q(uit)? ## b +sizes and offsets may be given as sectors, cylinders +or cylinders plus sectors: 6200, 32c, 19c10s respectively +modify partition 'b' +d(isplay) z(ero) t(ype) o(ffset) s(ize) f(rag) F(size) q(uit)? ## t +'b' fstype [unused]: ## swap +modify partition 'b' +d(isplay) z(ero) t(ype) o(ffset) s(ize) f(rag) F(size) q(uit)? ## o +'b' offset [0]: ## 50c +modify partition 'b' +d(isplay) z(ero) t(ype) o(ffset) s(ize) f(rag) F(size) q(uit)? ## s +'b' size [0]: ## 15c +modify partition 'b' +d(isplay) z(ero) t(ype) o(ffset) s(ize) f(rag) F(size) q(uit)? ## q +modify partitions +d(isplay) n(umber) s(elect) q(uit)? ## s +a b c d e f g h q(uit)? ## c +sizes and offsets may be given as sectors, cylinders +or cylinders plus sectors: 6200, 32c, 19c10s respectively +modify partition 'c' +d(isplay) z(ero) t(ype) o(ffset) s(ize) f(rag) F(size) q(uit)? ## t +'c' fstype [unused]: ## 2.11BSD +modify partition 'c' +d(isplay) z(ero) t(ype) o(ffset) s(ize) f(rag) F(size) q(uit)? ## o +'c' offset [0]: ## 65c +modify partition 'c' +d(isplay) z(ero) t(ype) o(ffset) s(ize) f(rag) F(size) q(uit)? ## s +'c' size [0]: ## 749c +modify partition 'c' +d(isplay) z(ero) t(ype) o(ffset) s(ize) f(rag) F(size) q(uit)? ## q +modify partitions +d(isplay) n(umber) s(elect) q(uit)? ## d + +type: SMD +disk: SMD +label: DEFAULT +flags: +bytes/sector: 512 +sectors/track: 22 +tracks/cylinder: 19 +sectors/cylinder: 418 +cylinders: 815 +rpm: 3600 +drivedata: 1 0 0 0 0 + +3 partitions: +# size offset fstype [fsize bsize] + a: 20900 0 2.11BSD 1024 1024 # (Cyl. 0 - 49) + b: 6270 20900 swap # (Cyl. 50 - 64) + c: 313082 27170 2.11BSD 1024 1024 # (Cyl. 65 - 813) + +modify partitions +d(isplay) n(umber) s(elect) q(uit)? ## q +modify +d(isplay) g(eometry) m(isc) p(artitions) q(uit)? ## q +d(isplay) D(efault) m(odify) w(rite) q(uit)? ## w +d(isplay) D(efault) m(odify) w(rite) q(uit)? ## q + +70Boot from tm(0,0,1) at 0172522 +: ## tm(0,2) +Boot: bootdev=0402 bootcsr=0172522 +Mkfs +file system: ## xp(0,0) +file sys size [10450]: ## +bytes per inode [4096]: ## +interleaving factor (m; 2 default): ## +interleaving modulus (n; 209 default): ## +isize = 2608 +m/n = 2 209 +Exit called + +70Boot from tm(0,0,2) at 0172522 +: ## tm(0,3) +Boot: bootdev=0403 bootcsr=0172522 +Restor +Tape? ## tm(0,5) +Disk? ## xp(0,0) +Last chance before scribbling on disk. ## +End of tape + +70Boot from tm(0,0,3) at 0172522 +: ## xp(0,0)unix + +4.2 Install 211bsd, disk phase --------------------------------------- + + The last command boots 211bsd form the just setup disk, which has now + a root file system, but not yet a hardward boot block. + '#' is now the shell prompt + '!!' indicates comments + indented lines show output + + Boot: bootdev=05000 bootcsr=0176700 + + 2.11 BSD UNIX #9: Wed Dec 10 06:24:37 PST 2008 + root@curly.2bsd.com:/usr/src/sys/RETRONFPNW + + attaching lo0 + + phys mem = 3932160 + avail mem = 3461952 + user mem = 307200 + + June 8 21:21:24 init: configure system + + dz ? csr 160100 vector 310 skipped: No CSR. + lp 0 csr 177514 vector 200 attached + rk 0 csr 177400 vector 220 attached + rl 0 csr 174400 vector 160 attached + tm 0 csr 172520 vector 224 attached + xp 0 csr 176700 vector 254 attached + cn 1 csr 176500 vector 300 attached + + erase, kill ^U, intr ^C + +!! make system bootable +# dd if=/mdec/hpuboot of=/dev/rxp0a count=1 + 1+0 records in + 1+0 records out + +!! create file system on partition c +# mkfs -s 156541 -i 4096 -m 2 -n 209 /dev/rxp0c + isize = 39120 + m/n = 2 209 + +!! now load the /usr files + +# mount /dev/xp0c /usr + +# cd /usr +# mt rew +# mt fsf 6 +# tar xpbf 20 /dev/rmt12 +# sync + +!! now load the /usr/src files +# mkdir /usr/src +# cd /usr/src +# mt -f /dev/rmt12 fsf +# tar xpbf 20 /dev/rmt12 +# sync +# mt -f /dev/rmt12 fsf +# tar xpbf 20 /dev/rmt12 +# cd / +# chmod 755 / /usr /usr/src /usr/src/sys +# sync +# df + Filesystem 1K-blocks Used Avail Capacity Mounted on + root 10285 4503 5782 44% / + /dev/xp0c 154094 87043 67051 56% /usr + +4.3 test boot created sysyem ----------------------------------------- + +# halt + +on ti_w11 prompt + cpu0 boot rpa0 + +70Boot from xp(0,0,0) at 0176700 +: ## + +from now on like for README_211bsd_rpset.txt diff --git a/tools/src/librlink/ReventLoop.cpp b/tools/src/librlink/ReventLoop.cpp index 1ab43faf..3ddfc94a 100644 --- a/tools/src/librlink/ReventLoop.cpp +++ b/tools/src/librlink/ReventLoop.cpp @@ -1,4 +1,4 @@ -// $Id: ReventLoop.cpp 662 2015-04-05 08:02:54Z mueller $ +// $Id: ReventLoop.cpp 686 2015-06-04 21:08:08Z mueller $ // // Copyright 2013-2015 by Walter F.J. Mueller // @@ -23,7 +23,7 @@ /*! \file - \version $Id: ReventLoop.cpp 662 2015-04-05 08:02:54Z mueller $ + \version $Id: ReventLoop.cpp 686 2015-06-04 21:08:08Z mueller $ \brief Implemenation of class ReventLoop. */ @@ -242,7 +242,7 @@ int ReventLoop::DoPoll(int timeout) if (fspLog && fTraceLevel >= 2) { RlogMsg lmsg(*fspLog, 'I'); - lmsg << "eloop: poll(): "; + lmsg << "eloop: poll(): rc=" << irc; for (size_t i=0; i // @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-06-05 686 1.2.1 BUGFIX: CallAttnHandler(): fix race in hnext // 2015-04-04 662 1.2 BUGFIX: fix race in Stop(), use UnStop() // 2015-01-10 632 2.2 Exec() without emsg now void, will throw // 2014-12-30 625 2.1 adopt to Rlink V4 attn logic @@ -26,7 +27,7 @@ /*! \file - \version $Id: RlinkServer.cpp 662 2015-04-05 08:02:54Z mueller $ + \version $Id: RlinkServer.cpp 686 2015-06-04 21:08:08Z mueller $ \brief Implemenation of RlinkServer. */ @@ -435,11 +436,20 @@ void RlinkServer::StartOrResume(bool resume) void RlinkServer::CallAttnHandler() { fStats.Inc(kStatNAttnHdl); + if (fTraceLevel>0) { + RlogMsg lmsg(LogFile()); + lmsg << "-I attnhdl-beg: patt=" << RosPrintBvi(fAttnPatt,8); + } // if notifier pending, transfer it to current attn pattern if (fAttnNotiPatt) { boost::lock_guard lock(*fspConn); fStats.Inc(kStatNAttnNoti); + if (fTraceLevel>0) { + RlogMsg lmsg(LogFile()); + lmsg << "-I attnhdl-add: patt=" << RosPrintBvi(fAttnPatt,8) + << " noti=" << RosPrintBvi(fAttnNotiPatt,8); + } fAttnPatt |= fAttnNotiPatt; fAttnNotiPatt = 0; } @@ -458,15 +468,32 @@ void RlinkServer::CallAttnHandler() AttnArgs args(fAttnPatt, fAttnDsc[i].fId.fMask); boost::lock_guard lock(*fspConn); + if (fTraceLevel>0) { + RlogMsg lmsg(LogFile()); + lmsg << "-I attnhdl-bef: patt=" << RosPrintBvi(fAttnPatt,8) + << " hmat=" << RosPrintBvi(hmatch,8); + } + // FIXME_code: return code not used, yet fAttnDsc[i].fHandler(args); if (!args.fHarvestDone) Rexception("RlinkServer::CallAttnHandler()", - "Handler didn't set fHarvestDone"); + "Handler didn't set fHarvestDone"); uint16_t hnew = args.fAttnHarvest & ~fAttnDsc[i].fId.fMask; - hnext |= hnew; - hdone |= hmatch; + hnext |= hnew; + hnext &= ~hmatch; // FIXME_code: this is a patch + // works for single lam handlers only + // ok for now, but will not work in general !! + hdone |= hmatch; + + if (fTraceLevel>0) { + RlogMsg lmsg(LogFile()); + lmsg << "-I attnhdl-aft: patt=" << RosPrintBvi(fAttnPatt,8) + << " done=" << RosPrintBvi(hdone,8) + << " next=" << RosPrintBvi(hnext,8); + } + } } fAttnPatt &= ~hdone; // clear handled bits diff --git a/tools/src/librtools/RparseUrl.cpp b/tools/src/librtools/RparseUrl.cpp index 671c4cb7..81161022 100644 --- a/tools/src/librtools/RparseUrl.cpp +++ b/tools/src/librtools/RparseUrl.cpp @@ -1,6 +1,6 @@ -// $Id: RparseUrl.cpp 516 2013-05-05 21:24:52Z mueller $ +// $Id: RparseUrl.cpp 686 2015-06-04 21:08:08Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,13 +13,14 @@ // // Revision History: // Date Rev Version Comment +// 2015-06-04 686 1.0.2 Set(): add check that optlist is enclosed by '|' // 2013-02-23 492 1.0.1 add static FindScheme(); allow no or empty scheme // 2013-02-03 481 1.0 Initial version, extracted from RlinkPort // --------------------------------------------------------------------------- /*! \file - \version $Id: RparseUrl.cpp 516 2013-05-05 21:24:52Z mueller $ + \version $Id: RparseUrl.cpp 686 2015-06-04 21:08:08Z mueller $ \brief Implemenation of RparseUrl. */ @@ -67,6 +68,15 @@ bool RparseUrl::Set(const std::string& url, const std::string& optlist, fPath.clear(); fOptMap.clear(); + // check that optlist is empty or starts and ends with '|' + if (optlist.length() > 0 && + (optlist.length()<2 || + optlist[0]!='|' || optlist[optlist.length()-1]!='|') ) { + emsg.Init("RparseUrl::Set()", string("optlist \"") + optlist + + "\" not enclosed in '|'"); + return false; + } + size_t pdel = fScheme.length(); if (pdel == 0 && url.length()>0 && url[0] != ':') pdel = -1; size_t odel = url.find_first_of('?', fScheme.length()); @@ -96,7 +106,7 @@ bool RparseUrl::Set(const std::string& url, const std::string& optlist, } else { if (c == '\\') { if (i+1 >= url.length()) { - emsg.Init("RparseUrl::ParseUrl()", + emsg.Init("RparseUrl::Set()", string("invalid trailing \\ in url '") + url + "'"); return false; } @@ -104,7 +114,7 @@ bool RparseUrl::Set(const std::string& url, const std::string& optlist, switch (url[i]) { case '\\' : c = '\\'; break; case ';' : c = ';'; break; - default : emsg.Init("RparseUrl::ParseUrl()", + default : emsg.Init("RparseUrl::Set()", string("invalid \\ escape in url '") + url + "'"); return false; diff --git a/tools/src/librw11/Makefile b/tools/src/librw11/Makefile index f06d01f8..e34b3554 100644 --- a/tools/src/librw11/Makefile +++ b/tools/src/librw11/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 664 2015-04-06 12:02:17Z mueller $ +# $Id: Makefile 685 2015-05-25 12:18:36Z mueller $ # # Revision History: # Date Rev Version Comment @@ -26,6 +26,7 @@ OBJ_all += Rw11Probe.o OBJ_all += Rw11Cntl.o Rw11Unit.o OBJ_all += Rw11UnitTerm.o OBJ_all += Rw11UnitDisk.o +OBJ_all += Rw11UnitTape.o OBJ_all += Rw11UnitStream.o OBJ_all += Rw11CntlDL11.o Rw11UnitDL11.o OBJ_all += Rw11CntlLP11.o Rw11UnitLP11.o @@ -33,9 +34,11 @@ OBJ_all += Rw11CntlPC11.o Rw11UnitPC11.o OBJ_all += Rw11CntlRL11.o Rw11UnitRL11.o OBJ_all += Rw11CntlRK11.o Rw11UnitRK11.o OBJ_all += Rw11CntlRHRP.o Rw11UnitRHRP.o +OBJ_all += Rw11CntlTM11.o Rw11UnitTM11.o OBJ_all += Rw11Virt.o OBJ_all += Rw11VirtTerm.o Rw11VirtTermPty.o Rw11VirtTermTcp.o OBJ_all += Rw11VirtDisk.o Rw11VirtDiskFile.o +OBJ_all += Rw11VirtTape.o Rw11VirtTapeTap.o OBJ_all += Rw11VirtStream.o OBJ_all += Rw11Rdma.o Rw11RdmaDisk.o # diff --git a/tools/src/librw11/Rw11Cntl.cpp b/tools/src/librw11/Rw11Cntl.cpp index f3ab2175..5c42bdb7 100644 --- a/tools/src/librw11/Rw11Cntl.cpp +++ b/tools/src/librw11/Rw11Cntl.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11Cntl.cpp 631 2015-01-09 21:36:51Z mueller $ +// $Id: Rw11Cntl.cpp 682 2015-05-15 18:35:29Z mueller $ // // Copyright 2013-2014 by Walter F.J. Mueller // @@ -20,7 +20,7 @@ /*! \file - \version $Id: Rw11Cntl.cpp 631 2015-01-09 21:36:51Z mueller $ + \version $Id: Rw11Cntl.cpp 682 2015-05-15 18:35:29Z mueller $ \brief Implemenation of Rw11Cntl. */ @@ -97,6 +97,14 @@ void Rw11Cntl::Start() //------------------------------------------+----------------------------------- //! FIXME_docs +size_t Rw11Cntl::NUnit() const +{ + return 0; // real values from devived classes +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + bool Rw11Cntl::BootCode(size_t unit, std::vector& code, uint16_t& aload, uint16_t& astart) { diff --git a/tools/src/librw11/Rw11Cntl.hpp b/tools/src/librw11/Rw11Cntl.hpp index 1d66354f..8ba54806 100644 --- a/tools/src/librw11/Rw11Cntl.hpp +++ b/tools/src/librw11/Rw11Cntl.hpp @@ -1,6 +1,6 @@ -// $Id: Rw11Cntl.hpp 625 2014-12-30 16:17:45Z mueller $ +// $Id: Rw11Cntl.hpp 682 2015-05-15 18:35:29Z mueller $ // -// Copyright 2013-2014 by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-05-15 680 1.1.1 add NUnit() as virtual // 2014-12-30 625 1.1 adopt to Rlink V4 attn logic // 2013-03-06 495 1.0 Initial version // 2013-02-05 483 0.1 First draft @@ -21,7 +22,7 @@ /*! \file - \version $Id: Rw11Cntl.hpp 625 2014-12-30 16:17:45Z mueller $ + \version $Id: Rw11Cntl.hpp 682 2015-05-15 18:35:29Z mueller $ \brief Declaration of class Rw11Cntl. */ @@ -69,6 +70,7 @@ namespace Retro { virtual void Start(); bool IsStarted() const; + virtual size_t NUnit() const; virtual bool BootCode(size_t unit, std::vector& code, uint16_t& aload, uint16_t& astart); diff --git a/tools/src/librw11/Rw11CntlBase.hpp b/tools/src/librw11/Rw11CntlBase.hpp index 03d5f83c..1641fa71 100644 --- a/tools/src/librw11/Rw11CntlBase.hpp +++ b/tools/src/librw11/Rw11CntlBase.hpp @@ -1,4 +1,4 @@ -// $Id: Rw11CntlBase.hpp 495 2013-03-06 17:13:48Z mueller $ +// $Id: Rw11CntlBase.hpp 682 2015-05-15 18:35:29Z mueller $ // // Copyright 2013- by Walter F.J. Mueller // @@ -20,7 +20,7 @@ /*! \file - \version $Id: Rw11CntlBase.hpp 495 2013-03-06 17:13:48Z mueller $ + \version $Id: Rw11CntlBase.hpp 682 2015-05-15 18:35:29Z mueller $ \brief Declaration of class Rw11CntlBase. */ @@ -40,7 +40,7 @@ namespace Retro { explicit Rw11CntlBase(const std::string& type); ~Rw11CntlBase(); - size_t NUnit() const; + virtual size_t NUnit() const; TU& Unit(size_t index) const; const boost::shared_ptr& UnitSPtr(size_t index) const; diff --git a/tools/src/librw11/Rw11CntlRHRP.cpp b/tools/src/librw11/Rw11CntlRHRP.cpp index a5f72823..aecc798d 100644 --- a/tools/src/librw11/Rw11CntlRHRP.cpp +++ b/tools/src/librw11/Rw11CntlRHRP.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11CntlRHRP.cpp 680 2015-05-14 13:29:46Z mueller $ +// $Id: Rw11CntlRHRP.cpp 686 2015-06-04 21:08:08Z mueller $ // // Copyright 2015- by Walter F.J. Mueller // Other credits: @@ -15,13 +15,15 @@ // // Revision History: // Date Rev Version Comment +// 2015-06-04 686 1.0.2 check for spurious lams +// 2015-05-24 684 1.0.1 fixed rpcs2 update for wcheck and nem aborts // 2015-05-14 680 1.0 Initial version // 2015-03-21 659 0.1 First draft // --------------------------------------------------------------------------- /*! \file - \version $Id: Rw11CntlRHRP.cpp 680 2015-05-14 13:29:46Z mueller $ + \version $Id: Rw11CntlRHRP.cpp 686 2015-06-04 21:08:08Z mueller $ \brief Implemenation of Rw11CntlRHRP. */ @@ -457,6 +459,16 @@ int Rw11CntlRHRP::AttnHandler(RlinkServer::AttnArgs& args) if (rpcs3 & kRPCS3_M_RPACKDONE) fStats.Inc(kStatNFuncPack); if (rpcs3 & kRPCS3_M_RSEEKDONE) fStats.Inc(kStatNFuncSeek); + // check for spurious interrupts (either RDY=1 or RDY=0 and rdma busy) + if ((rpcs1 & kRPCS1_M_RDY) || fRdma.IsActive()) { + RlogMsg lmsg(LogFile()); + lmsg << "-E RHRP err " + << " cs=" << RosPrintBvi(rpcs1,8) + << " spurious lam: " + << (fRdma.IsActive() ? "RDY=0 and Rdma busy" : "RDY=1"); + return 0; + } + // check for overrun (read/write beyond last track // if found, truncate request length bool ovr = lba + nblk > unit.NBlock(); @@ -556,14 +568,14 @@ void Rw11CntlRHRP::RdmaPostExecCB(int stat, size_t ndone, if (fRd_fu == kFUNC_WCD) { size_t nwcok = fRdma.WriteCheck(ndone); if (nwcok != ndone) { // if mismatch found - rpcs2 = kRPCS2_M_WCE; - if (ndone & 0x1) rpcs2 = kRPCS2_M_RWCO; // failed in odd word ! + rpcs2 |= kRPCS2_M_WCE; + if (ndone & 0x1) rpcs2 |= kRPCS2_M_RWCO; // failed in odd word ! ndone = nwcok; // truncate word count } } // handle Rdma aborts - if (stat == Rw11Rdma::kStatusFailRdma) rpcs2 = kRPCS2_M_NEM; + if (stat == Rw11Rdma::kStatusFailRdma) rpcs2 |= kRPCS2_M_NEM; // check for fused csr updates if (clist.Size() > ncmd) { diff --git a/tools/src/librw11/Rw11CntlRK11.cpp b/tools/src/librw11/Rw11CntlRK11.cpp index ffbfcccb..e8cb36c2 100644 --- a/tools/src/librw11/Rw11CntlRK11.cpp +++ b/tools/src/librw11/Rw11CntlRK11.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11CntlRK11.cpp 669 2015-04-26 21:20:32Z mueller $ +// $Id: Rw11CntlRK11.cpp 686 2015-06-04 21:08:08Z mueller $ // // Copyright 2013-2015 by Walter F.J. Mueller // Other credits: @@ -15,6 +15,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-06-04 686 2.0.2 check for spurious lams // 2015-02-17 647 2.0.1 use Nwrd2Nblk(); BUGFIX: revise RdmaPostExecCB() // 2015-01-04 628 2.0 use Rw11RdmaDisk // 2014-12-30 625 1.2 adopt to Rlink V4 attn logic @@ -26,7 +27,7 @@ /*! \file - \version $Id: Rw11CntlRK11.cpp 669 2015-04-26 21:20:32Z mueller $ + \version $Id: Rw11CntlRK11.cpp 686 2015-06-04 21:08:08Z mueller $ \brief Implemenation of Rw11CntlRK11. */ @@ -98,6 +99,7 @@ const uint16_t Rw11CntlRK11::kRKCS_M_IBA; const uint16_t Rw11CntlRK11::kRKCS_M_FMT; const uint16_t Rw11CntlRK11::kRKCS_M_RWA; const uint16_t Rw11CntlRK11::kRKCS_M_SSE; +const uint16_t Rw11CntlRK11::kRKCS_M_RDY; const uint16_t Rw11CntlRK11::kRKCS_M_MEX; const uint16_t Rw11CntlRK11::kRKCS_V_MEX; const uint16_t Rw11CntlRK11::kRKCS_B_MEX; @@ -372,6 +374,16 @@ int Rw11CntlRK11::AttnHandler(RlinkServer::AttnArgs& args) << "," << RosPrintf(nwrd,"d",5); } + // check for spurious interrupts (either RDY=1 or RDY=0 and rdma busy) + if ((rkcs & kRKCS_M_RDY) || fRdma.IsActive()) { + RlogMsg lmsg(LogFile()); + lmsg << "-E RK11 err " + << " cr=" << RosPrintBvi(rkcs,8) + << " spurious lam: " + << (fRdma.IsActive() ? "RDY=0 and Rdma busy" : "RDY=1"); + return 0; + } + // check for general abort conditions if (fu != kFUNC_CRESET && // function not control reset (!unit.Virt())) { // and drive not attached diff --git a/tools/src/librw11/Rw11CntlRK11.hpp b/tools/src/librw11/Rw11CntlRK11.hpp index 10cbe122..bf90c9ac 100644 --- a/tools/src/librw11/Rw11CntlRK11.hpp +++ b/tools/src/librw11/Rw11CntlRK11.hpp @@ -1,4 +1,4 @@ -// $Id: Rw11CntlRK11.hpp 665 2015-04-07 07:13:49Z mueller $ +// $Id: Rw11CntlRK11.hpp 686 2015-06-04 21:08:08Z mueller $ // // Copyright 2013-2015 by Walter F.J. Mueller // @@ -23,7 +23,7 @@ /*! \file - \version $Id: Rw11CntlRK11.hpp 665 2015-04-07 07:13:49Z mueller $ + \version $Id: Rw11CntlRK11.hpp 686 2015-06-04 21:08:08Z mueller $ \brief Declaration of class Rw11CntlRK11. */ @@ -102,6 +102,7 @@ namespace Retro { static const uint16_t kRKCS_M_FMT = kWBit10; static const uint16_t kRKCS_M_RWA = kWBit09; static const uint16_t kRKCS_M_SSE = kWBit08; + static const uint16_t kRKCS_M_RDY = kWBit07; static const uint16_t kRKCS_M_MEX = 000060; static const uint16_t kRKCS_V_MEX = 4; static const uint16_t kRKCS_B_MEX = 0003; diff --git a/tools/src/librw11/Rw11CntlRL11.cpp b/tools/src/librw11/Rw11CntlRL11.cpp index 22cb9461..8cfb37be 100644 --- a/tools/src/librw11/Rw11CntlRL11.cpp +++ b/tools/src/librw11/Rw11CntlRL11.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11CntlRL11.cpp 669 2015-04-26 21:20:32Z mueller $ +// $Id: Rw11CntlRL11.cpp 686 2015-06-04 21:08:08Z mueller $ // // Copyright 2014-2015 by Walter F.J. Mueller // Other credits: @@ -16,6 +16,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-06-04 686 1.0.2 check for spurious lams // 2015-03-04 655 1.0.1 use original boot code again // 2015-03-01 653 1.0 Initial version // 2014-06-08 561 0.1 First draft @@ -23,7 +24,7 @@ /*! \file - \version $Id: Rw11CntlRL11.cpp 669 2015-04-26 21:20:32Z mueller $ + \version $Id: Rw11CntlRL11.cpp 686 2015-06-04 21:08:08Z mueller $ \brief Implemenation of Rw11CntlRL11. */ @@ -440,6 +441,16 @@ int Rw11CntlRL11::AttnHandler(RlinkServer::AttnArgs& args) if (ovr) lmsg << "!"; } + // check for spurious interrupts (either RDY=1 or RDY=0 and rdma busy) + if ((rlcs & kRLCS_M_CRDY) || fRdma.IsActive()) { + RlogMsg lmsg(LogFile()); + lmsg << "-E RL11 err " + << " cr=" << RosPrintBvi(rlcs,8) + << " spurious lam: " + << (fRdma.IsActive() ? "RDY=0 and Rdma busy" : "RDY=1"); + return 0; + } + // remember request parameters for call back and error exit handling fRd_rlcs = rlcs; fRd_rlda = rlda; diff --git a/tools/src/librw11/Rw11CntlTM11.cpp b/tools/src/librw11/Rw11CntlTM11.cpp new file mode 100644 index 00000000..5a8d04c0 --- /dev/null +++ b/tools/src/librw11/Rw11CntlTM11.cpp @@ -0,0 +1,638 @@ +// $Id: Rw11CntlTM11.cpp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// Other credits: +// the boot code is from the simh project and Copyright Robert M Supnik +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-06-04 686 1.0 Initial version +// 2015-05-17 683 0.1 First draft +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11CntlTM11.cpp 686 2015-06-04 21:08:08Z mueller $ + \brief Implemenation of Rw11CntlTM11. +*/ + +#include "boost/bind.hpp" +#include "boost/foreach.hpp" +#define foreach_ BOOST_FOREACH + +#include "librtools/RosFill.hpp" +#include "librtools/RosPrintBvi.hpp" +#include "librtools/RosPrintf.hpp" +#include "librtools/Rexception.hpp" +#include "librtools/RlogMsg.hpp" + +#include "Rw11CntlTM11.hpp" + +using namespace std; + +/*! + \class Retro::Rw11CntlTM11 + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +// constants definitions + +const uint16_t Rw11CntlTM11::kIbaddr; +const int Rw11CntlTM11::kLam; + +const uint16_t Rw11CntlTM11::kTMSR; +const uint16_t Rw11CntlTM11::kTMCR; +const uint16_t Rw11CntlTM11::kTMBC; +const uint16_t Rw11CntlTM11::kTMBA; +const uint16_t Rw11CntlTM11::kTMDB; +const uint16_t Rw11CntlTM11::kTMRL; + +const uint16_t Rw11CntlTM11::kProbeOff; +const bool Rw11CntlTM11::kProbeInt; +const bool Rw11CntlTM11::kProbeRem; + +const uint16_t Rw11CntlTM11::kTMSR_M_ICMD; +const uint16_t Rw11CntlTM11::kTMSR_M_EOF; +const uint16_t Rw11CntlTM11::kTMSR_M_PAE; +const uint16_t Rw11CntlTM11::kTMSR_M_EOT; +const uint16_t Rw11CntlTM11::kTMSR_M_RLE; +const uint16_t Rw11CntlTM11::kTMSR_M_BTE; +const uint16_t Rw11CntlTM11::kTMSR_M_NXM; +const uint16_t Rw11CntlTM11::kTMSR_M_ONL; +const uint16_t Rw11CntlTM11::kTMSR_M_BOT; +const uint16_t Rw11CntlTM11::kTMSR_M_WRL; +const uint16_t Rw11CntlTM11::kTMSR_M_REW; +const uint16_t Rw11CntlTM11::kTMSR_M_TUR; + +const uint16_t Rw11CntlTM11::kTMCR_V_ERR; +const uint16_t Rw11CntlTM11::kTMCR_V_DEN; +const uint16_t Rw11CntlTM11::kTMCR_B_DEN; +const uint16_t Rw11CntlTM11::kTMCR_V_UNIT; +const uint16_t Rw11CntlTM11::kTMCR_B_UNIT; +const uint16_t Rw11CntlTM11::kTMCR_M_RDY; +const uint16_t Rw11CntlTM11::kTMCR_V_EA; +const uint16_t Rw11CntlTM11::kTMCR_B_EA; +const uint16_t Rw11CntlTM11::kTMCR_V_FUNC; +const uint16_t Rw11CntlTM11::kTMCR_B_FUNC; +const uint16_t Rw11CntlTM11::kTMCR_M_GO; + +const uint16_t Rw11CntlTM11::kFUNC_UNLOAD; +const uint16_t Rw11CntlTM11::kFUNC_READ; +const uint16_t Rw11CntlTM11::kFUNC_WRITE ; +const uint16_t Rw11CntlTM11::kFUNC_WEOF; +const uint16_t Rw11CntlTM11::kFUNC_SFORW; +const uint16_t Rw11CntlTM11::kFUNC_SBACK; +const uint16_t Rw11CntlTM11::kFUNC_WEIRG; +const uint16_t Rw11CntlTM11::kFUNC_REWIND; + +const uint16_t Rw11CntlTM11::kRFUNC_WUNIT; +const uint16_t Rw11CntlTM11::kRFUNC_DONE; + +const uint16_t Rw11CntlTM11::kTMCR_M_RICMD; +const uint16_t Rw11CntlTM11::kTMCR_M_RPAE; +const uint16_t Rw11CntlTM11::kTMCR_M_RRLE; +const uint16_t Rw11CntlTM11::kTMCR_M_RBTE; +const uint16_t Rw11CntlTM11::kTMCR_M_RNXM; +const uint16_t Rw11CntlTM11::kTMCR_M_REAENA; +const uint16_t Rw11CntlTM11::kTMCR_V_REA; +const uint16_t Rw11CntlTM11::kTMCR_B_REA; + +const uint16_t Rw11CntlTM11::kTMRL_M_EOF; +const uint16_t Rw11CntlTM11::kTMRL_M_EOT; +const uint16_t Rw11CntlTM11::kTMRL_M_ONL; +const uint16_t Rw11CntlTM11::kTMRL_M_BOT; +const uint16_t Rw11CntlTM11::kTMRL_M_WRL; +const uint16_t Rw11CntlTM11::kTMRL_M_REW; + +//------------------------------------------+----------------------------------- +//! Default constructor + +Rw11CntlTM11::Rw11CntlTM11() + : Rw11CntlBase("tm11"), + fPC_tmcr(0), + fPC_tmsr(0), + fPC_tmbc(0), + fPC_tmba(0), + fRd_tmcr(0), + fRd_tmsr(0), + fRd_tmbc(0), + fRd_tmba(0), + fRd_bc(0), + fRd_addr(0), + fRd_nwrd(0), + fRd_fu(0), + fRd_opcode(0), + fBuf(), + fRdma(this, + boost::bind(&Rw11CntlTM11::RdmaPreExecCB, this, _1, _2, _3, _4), + boost::bind(&Rw11CntlTM11::RdmaPostExecCB, this, _1, _2, _3, _4)) +{ + // must be here because Units have a back-ptr (not available at Rw11CntlBase) + for (size_t i=0; iWProt()) tmds |= kTMRL_M_WRL; + if (unit.Virt()->Bot()) tmds |= kTMRL_M_BOT; + } + unit.SetTmds(tmds); + cpu.AddWibr(clist, fBase+kTMCR, (uint16_t(ind)<& code, + uint16_t& aload, uint16_t& astart) +{ + uint16_t kBOOT_START = 02000; + uint16_t bootcode[] = { // tm11 boot loader - from simh pdp11_tm.c (v3.9) + 0046524, // boot_start: "TM" + 0012706, kBOOT_START, // mov #boot_start, sp + 0012700, uint16_t(unit), // mov #unit_num, r0 + 0012701, 0172526, // mov #172526, r1 ; mtcma + 0005011, // clr (r1) + 0012741, 0177777, // mov #-1, -(r1) ; mtbrc + 0010002, // mov r0,r2 + 0000302, // swab r2 + 0062702, 0060011, // add #60011, r2 + 0010241, // mov r2, -(r1) ; space + go + 0105711, // tstb (r1) ; mtc + 0100376, // bpl .-2 + 0010002, // mov r0,r2 + 0000302, // swab r2 + 0062702, 0060003, // add #60003, r2 + 0010211, // mov r2, (r1) ; read + go + 0105711, // tstb (r1) ; mtc + 0100376, // bpl .-2 + 0005002, // clr r2 + 0005003, // clr r3 + 0012704, uint16_t(kBOOT_START+020), // mov #boot_start+20, r4 + 0005005, // clr r5 + 0005007 // clr r7 + }; + + code.clear(); + foreach_ (uint16_t& w, bootcode) code.push_back(w); + aload = kBOOT_START; + astart = kBOOT_START+2; + return true; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11CntlTM11::Dump(std::ostream& os, int ind, const char* text) const +{ + RosFill bl(ind); + os << bl << (text?text:"--") << "Rw11CntlTM11 @ " << this << endl; + os << bl << " fPC_tmcr: " << RosPrintf(fPC_tmcr,"d",6) << endl; + os << bl << " fPC_tmsr: " << RosPrintf(fPC_tmsr,"d",6) << endl; + os << bl << " fPC_tmbc: " << RosPrintf(fPC_tmbc,"d",6) << endl; + os << bl << " fPC_tmba: " << RosPrintf(fPC_tmba,"d",6) << endl; + os << bl << " fRd_tmcr: " << RosPrintBvi(fRd_tmcr,8) << endl; + os << bl << " fRd_tmsr: " << RosPrintBvi(fRd_tmsr,8) << endl; + os << bl << " fRd_tmbc: " << RosPrintBvi(fRd_tmbc,8) << endl; + os << bl << " fRd_tmba: " << RosPrintBvi(fRd_tmba,8) << endl; + os << bl << " fRd_bc: " << RosPrintf(fRd_bc,"d",6) << endl; + os << bl << " fRd_addr: " << RosPrintBvi(fRd_addr,8,18) << endl; + os << bl << " fRd_nwrd: " << RosPrintf(fRd_nwrd,"d",6) << endl; + os << bl << " fRd_fu: " << fRd_fu << endl; + os << bl << " fRd_opcode: " << fRd_opcode << endl; + os << bl << " fBuf.size() " << RosPrintf(fBuf.size(),"d",6) << endl; + fRdma.Dump(os, ind+2, "fRdma: "); + Rw11CntlBase::Dump(os, ind, " ^"); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +int Rw11CntlTM11::AttnHandler(RlinkServer::AttnArgs& args) +{ + fStats.Inc(kStatNAttnHdl); + Server().GetAttnInfo(args, fPrimClist); + + uint16_t tmcr = fPrimClist[fPC_tmcr].Data(); + uint16_t tmsr = fPrimClist[fPC_tmsr].Data(); + uint16_t tmbc = fPrimClist[fPC_tmbc].Data(); + uint16_t tmba = fPrimClist[fPC_tmba].Data(); + + uint16_t unum = (tmcr>>kTMCR_V_UNIT) & kTMCR_B_UNIT; + uint16_t ea = (tmcr>>kTMCR_V_EA) & kTMCR_B_EA; + uint16_t fu = (tmcr>>kTMCR_V_FUNC) & kTMCR_B_FUNC; + + uint32_t addr = uint32_t(ea)<<16 | uint32_t(tmba); + + uint32_t nbyt = (~uint32_t(tmbc)&0xffff) + 1; // transfer size in bytes + + //Rw11Cpu& cpu = Cpu(); + RlinkCommandList clist; + + if (fTraceLevel>0) { + RlogMsg lmsg(LogFile()); + static const char* fumnemo[8] = + {"un ","rd ","wr ","we ","sf ","sb ","wi ","re "}; + lmsg << "-I TM11" + << " fu=" << fumnemo[fu&07] + << " un=" << unum + << " cr=" << RosPrintBvi(tmcr,8) + << " ad=" << RosPrintBvi(addr,8,18) + << " bc=" << RosPrintBvi(tmbc,8) + << " nb="; + if (nbyt==65536) lmsg << " (0)"; else lmsg << RosPrintf(nbyt,"d",5); + } + + // check for spurious interrupts (either RDY=1 or RDY=0 and rdma busy) + if ((tmcr & kTMCR_M_RDY) || fRdma.IsActive()) { + RlogMsg lmsg(LogFile()); + lmsg << "-E TM11 err " + << " cr=" << RosPrintBvi(tmcr,8) + << " spurious lam: " + << (fRdma.IsActive() ? "RDY=0 and Rdma busy" : "RDY=1"); + return 0; + } + + // check for general abort conditions: invalid unit number + if (unum > NUnit()) { + AddErrorExit(clist, kTMCR_M_RICMD); + Server().Exec(clist); + return 0; + } + + Rw11UnitTM11& unit = *fspUnit[unum]; + + // check for general abort conditions: + // - unit not attached + // - write to a write locked unit + bool wcmd = fu == kFUNC_WRITE || + fu == kFUNC_WEIRG || + fu == kFUNC_WEOF; + + if ((!unit.Virt()) || (wcmd && unit.Virt()->WProt()) ) { + AddErrorExit(clist, kTMCR_M_RICMD); + Server().Exec(clist); + return 0; + } + + // remember request parameters for call back and error exit handling + fRd_tmcr = tmcr; + fRd_tmsr = tmsr; + fRd_tmbc = tmbc; + fRd_tmba = tmba; + fRd_addr = addr; + fRd_fu = fu; + + // now handle the functions + int opcode = Rw11VirtTape::kOpCodeOK; + RerrMsg emsg; + + if (fu == kFUNC_UNLOAD) { // Unload ------------------------ + fStats.Inc(kStatNFuncUnload); + unit.Detach(); + AddFastExit(clist, opcode, 0); + RlogMsg lmsg(LogFile()); + lmsg << "-I TM11" + << " unit " << unum << "unload"; + + } else if (fu == kFUNC_READ) { // Read -------------------------- + fStats.Inc(kStatNFuncRead); + size_t nwalloc = (nbyt+1)/2; + if (fBuf.size() < nwalloc) fBuf.resize(nwalloc); + size_t ndone; + bool rc = unit.VirtReadRecord(nbyt, reinterpret_cast(fBuf.data()), + ndone, fRd_opcode, emsg); + if (!rc) WriteLog("read", emsg); + if ((!rc) || ndone == 0) { + AddFastExit(clist, fRd_opcode, 0); + } else if (ndone&0x1) { // FIXME_code: add odd rlen handling + AddErrorExit(clist, kTMCR_M_RICMD|kTMSR_M_BTE); // now just bail out !! + } else { + size_t nwdma = ndone/2; + fRdma.QueueWMem(addr, fBuf.data(), nwdma, + Rw11Cpu::kCPAH_M_22BIT|Rw11Cpu::kCPAH_M_UBMAP); + } + + } else if (fu == kFUNC_WRITE || // Write ------------------------- + fu == kFUNC_WEIRG) { + fStats.Inc((fu==kFUNC_WRITE) ? kStatNFuncWrite : kStatNFuncWrteg); + size_t nwdma = (nbyt+1)/2; + if (fBuf.size() < nwdma) fBuf.resize(nwdma); + if (nbyt&0x1) { // FIXME_code: add odd rlen handling + AddErrorExit(clist, kTMCR_M_RICMD|kTMSR_M_BTE); // now just bail out !! + } else { + fRdma.QueueRMem(addr, fBuf.data(), nwdma, + Rw11Cpu::kCPAH_M_22BIT|Rw11Cpu::kCPAH_M_UBMAP); + } + + } else if (fu == kFUNC_WEOF) { // Write Eof --------------------- + fStats.Inc(kStatNFuncWeof); + if (!unit.VirtWriteEof(emsg)) WriteLog("weof", emsg); + AddFastExit(clist, opcode, 0); + + } else if (fu == kFUNC_SFORW) { // Space forward ----------------- + fStats.Inc(kStatNFuncSforw); + size_t ndone; + if (!unit.VirtSpaceForw(nbyt, ndone, opcode, emsg)) WriteLog("sback", emsg); + AddFastExit(clist, opcode, ndone); + + } else if (fu == kFUNC_SBACK) { // Space Backward ---------------- + fStats.Inc(kStatNFuncSback); + size_t ndone; + if (!unit.VirtSpaceBack(nbyt, ndone, opcode, emsg)) WriteLog("sback", emsg); + AddFastExit(clist, opcode, ndone); + + } else if (fu == kFUNC_REWIND) { // Rewind ------------------------ + fStats.Inc(kStatNFuncRewind); + if (!unit.VirtRewind(opcode, emsg)) WriteLog("rewind", emsg); + AddFastExit(clist, opcode, 0); + } + + if (clist.Size()) { // if handled directly + Server().Exec(clist); // doit + } + + return 0; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11CntlTM11::RdmaPreExecCB(int stat, size_t nwdone, size_t nwnext, + RlinkCommandList& clist) +{ + // noop for TM11 + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11CntlTM11::RdmaPostExecCB(int stat, size_t ndone, + RlinkCommandList& clist, size_t ncmd) +{ + if (stat == Rw11Rdma::kStatusBusy) return; + + uint16_t tmcr = 0; + // handle Rdma aborts + if (stat == Rw11Rdma::kStatusFailRdma) tmcr |= kTMCR_M_RNXM; + + // finally to TM11 register update + RlinkCommandList clist1; + AddNormalExit(clist1, ndone, tmcr); + Server().Exec(clist1); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11CntlTM11::AddErrorExit(RlinkCommandList& clist, uint16_t tmcr) +{ + Rw11Cpu& cpu = Cpu(); + + tmcr |= (kRFUNC_DONE<1) { + RlogMsg lmsg(LogFile()); + lmsg << "-I TM11" + << " err " + << " " + << " cr=" << RosPrintBvi(tmcr,8); + } + + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11CntlTM11::AddFastExit(RlinkCommandList& clist, int opcode, size_t ndone) +{ + uint16_t unum = (fRd_tmcr>>kTMCR_V_UNIT) & kTMCR_B_UNIT; + Rw11UnitTM11& unit = *fspUnit[unum]; + Rw11Cpu& cpu = Cpu(); + + uint16_t tmcr = 0; + uint16_t tmds = kTMRL_M_ONL; + if (unit.Virt()->WProt()) tmds |= kTMRL_M_WRL; + if (unit.Virt()->Bot()) tmds |= kTMRL_M_BOT; + if (unit.Virt()->Eot()) tmds |= kTMRL_M_EOT; + + switch (opcode) { + + case Rw11VirtTape::kOpCodeOK: + case Rw11VirtTape::kOpCodeBot: + break; + + case Rw11VirtTape::kOpCodeEof: + tmds |= kTMRL_M_EOF; + break; + + default: + tmcr |= kTMCR_M_RBTE; + break; + } + + uint16_t tmbc = fRd_tmbc + uint16_t(ndone); + + unit.SetTmds(tmds); + cpu.AddWibr(clist, fBase+kTMCR, (uint16_t(unum)<1) { + RlogMsg lmsg(LogFile()); + bool err = tmcr & (kTMCR_M_RBTE); + lmsg << "-I TM11" + << (err ? " err " :" ok ") + << " un=" << unum + << " cr=" << RosPrintBvi(tmcr,8) + << " ds=" << RosPrintBvi(tmds,8) + << " bc=" << RosPrintBvi(tmbc,8); + } + + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11CntlTM11::AddNormalExit(RlinkCommandList& clist, size_t ndone, + uint16_t tmcr) +{ + uint16_t unum = (fRd_tmcr>>kTMCR_V_UNIT) & kTMCR_B_UNIT; + Rw11UnitTM11& unit = *fspUnit[unum]; + Rw11Cpu& cpu = Cpu(); + + uint16_t tmds = kTMRL_M_ONL; + if (unit.Virt()->WProt()) tmds |= kTMRL_M_WRL; + if (unit.Virt()->Bot()) tmds |= kTMRL_M_BOT; + if (unit.Virt()->Eot()) tmds |= kTMRL_M_EOT; + + uint32_t addr = fRd_addr + 2*ndone; + uint16_t tmbc = fRd_tmbc + 2*uint16_t(ndone); + + if (fRd_fu == kFUNC_READ) { // handle READ + switch (fRd_opcode) { + + case Rw11VirtTape::kOpCodeOK: + break; + + case Rw11VirtTape::kOpCodeRecLenErr: + tmcr |= kTMCR_M_RRLE; + break; + + case Rw11VirtTape::kOpCodeBadParity: + tmcr |= kTMCR_M_RPAE; + break; + + default: + tmcr |= kTMCR_M_RBTE; + break; + } + + } else { // handle WRITE or WEIRG + int opcode; + RerrMsg emsg; + size_t nbyt = 2*ndone; + if (!unit.VirtWriteRecord(nbyt, reinterpret_cast(fBuf.data()), + opcode, emsg)) + WriteLog("write", emsg); + } + + uint16_t tmba = uint16_t(addr & 0xfffe); + uint16_t ea = uint16_t((addr>>16)&0x0003); + tmcr |= kTMCR_M_REAENA | (ea<1) { + RlogMsg lmsg(LogFile()); + bool err = tmcr & (kTMCR_M_RPAE|kTMCR_M_RRLE|kTMCR_M_RBTE|kTMCR_M_RNXM); + lmsg << "-I TM11" + << (err ? " err " :" ok ") + << " un=" << unum + << " cr=" << RosPrintBvi(tmcr,8) + << " ad=" << RosPrintBvi(addr,8,18) + << " bc=" << RosPrintBvi(tmbc,8) + << " ds=" << RosPrintBvi(tmds,8); + } + + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11CntlTM11::WriteLog(const char* func, RerrMsg& emsg) +{ + RlogMsg lmsg(LogFile()); + lmsg << "-E TM11" + << " error for func=" << func + << ":" << emsg; + + return; +} + + +} // end namespace Retro diff --git a/tools/src/librw11/Rw11CntlTM11.hpp b/tools/src/librw11/Rw11CntlTM11.hpp new file mode 100644 index 00000000..cb491a08 --- /dev/null +++ b/tools/src/librw11/Rw11CntlTM11.hpp @@ -0,0 +1,180 @@ +// $Id: Rw11CntlTM11.hpp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-06-04 686 1.0 Initial version +// 2015-05-17 683 0.1 First draft +// --------------------------------------------------------------------------- + + +/*! + \file + \version $Id: Rw11CntlTM11.hpp 686 2015-06-04 21:08:08Z mueller $ + \brief Declaration of class Rw11CntlTM11. +*/ + +#ifndef included_Retro_Rw11CntlTM11 +#define included_Retro_Rw11CntlTM11 1 + +#include "Rw11CntlBase.hpp" +#include "Rw11UnitTM11.hpp" +#include "Rw11Rdma.hpp" + +namespace Retro { + + class Rw11CntlTM11 : public Rw11CntlBase { + public: + + Rw11CntlTM11(); + ~Rw11CntlTM11(); + + void Config(const std::string& name, uint16_t base, int lam); + + virtual void Start(); + + virtual bool BootCode(size_t unit, std::vector& code, + uint16_t& aload, uint16_t& astart); + + virtual void UnitSetup(size_t ind); + + void SetChunkSize(size_t chunk); + size_t ChunkSize() const; + + const Rstats& RdmaStats() const; + + virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; + + // some constants (also defined in cpp) + static const uint16_t kIbaddr = 0172520; //!< TM11 default address + static const int kLam = 7; //!< TM11 default lam + + static const uint16_t kTMSR = 000; //!< TMSR reg offset + static const uint16_t kTMCR = 002; //!< TMCR reg offset + static const uint16_t kTMBC = 004; //!< TMBC reg offset + static const uint16_t kTMBA = 006; //!< TMBA reg offset + static const uint16_t kTMDB = 010; //!< TMDB reg offset + static const uint16_t kTMRL = 012; //!< TMRL reg offset + + static const uint16_t kProbeOff = kTMCR; //!< probe address offset (tmcr) + static const bool kProbeInt = true; //!< probe int active + static const bool kProbeRem = true; //!< probr rem active + + static const uint16_t kTMSR_M_ICMD = kWBit15; //!< ICMD: invalid cmd + static const uint16_t kTMSR_M_EOF = kWBit14; //!< EOF: end-of-file seen + static const uint16_t kTMSR_M_PAE = kWBit12; //!< PAE: parity error + static const uint16_t kTMSR_M_EOT = kWBit10; //!< EOT: end-of-tape seen + static const uint16_t kTMSR_M_RLE = kWBit09; //!< RLE: record lgth error + static const uint16_t kTMSR_M_BTE = kWBit08; //!< BTE: bad tape error + static const uint16_t kTMSR_M_NXM = kWBit07; //!< NXM: non-existant mem + static const uint16_t kTMSR_M_ONL = kWBit06; //!< ONL: online + static const uint16_t kTMSR_M_BOT = kWBit05; //!< BOT: at begin-of-tape + static const uint16_t kTMSR_M_WRL = kWBit02; //!< WRL: write locked + static const uint16_t kTMSR_M_REW = kWBit01; //!< REW: tape rewound + static const uint16_t kTMSR_M_TUR = kWBit00; //!< TUR: unit ready + + static const uint16_t kTMCR_V_ERR = 15; + static const uint16_t kTMCR_V_DEN = 13; + static const uint16_t kTMCR_B_DEN = 0003; + static const uint16_t kTMCR_V_UNIT = 8; + static const uint16_t kTMCR_B_UNIT = 0007; + static const uint16_t kTMCR_M_RDY = kWBit07; + static const uint16_t kTMCR_V_EA = 4; + static const uint16_t kTMCR_B_EA = 0003; + static const uint16_t kTMCR_V_FUNC = 1; + static const uint16_t kTMCR_B_FUNC = 0007; + static const uint16_t kTMCR_M_GO = kWBit00; + + static const uint16_t kFUNC_UNLOAD = 0; + static const uint16_t kFUNC_READ = 1; + static const uint16_t kFUNC_WRITE = 2; + static const uint16_t kFUNC_WEOF = 3; + static const uint16_t kFUNC_SFORW = 4; + static const uint16_t kFUNC_SBACK = 5; + static const uint16_t kFUNC_WEIRG = 6; + static const uint16_t kFUNC_REWIND = 7; + // remote function codes + static const uint16_t kRFUNC_WUNIT = 1; + static const uint16_t kRFUNC_DONE = 2; + + // cr usage or rem func=wunit + static const uint16_t kTMCR_V_RUNIT = 4; + static const uint16_t kTMCR_B_RUNIT = 0003; + // cr usage or rem func=done + static const uint16_t kTMCR_M_RICMD = kWBit15; + static const uint16_t kTMCR_M_RPAE = kWBit12; + static const uint16_t kTMCR_M_RRLE = kWBit09; + static const uint16_t kTMCR_M_RBTE = kWBit08; + static const uint16_t kTMCR_M_RNXM = kWBit07; + static const uint16_t kTMCR_M_REAENA = kWBit06; + static const uint16_t kTMCR_V_REA = 4; + static const uint16_t kTMCR_B_REA = 0003; + + // rem usage of TMRL (used to access unit specific TMSR fields) + static const uint16_t kTMRL_M_EOF = kWBit10; //!< EOF: end-of-file seen + static const uint16_t kTMRL_M_EOT = kWBit09; //!< EOT: end-of-tape seen + static const uint16_t kTMRL_M_ONL = kWBit08; //!< ONL: online + static const uint16_t kTMRL_M_BOT = kWBit07; //!< BOT: at begin-of-tape + static const uint16_t kTMRL_M_WRL = kWBit06; //!< WRL: write locked + static const uint16_t kTMRL_M_REW = kWBit05; //!< REW: tape rewinding + + // statistics counter indices + enum stats { + kStatNFuncUnload= Rw11Cntl::kDimStat, //!< func UNLOAD + kStatNFuncRead, //!< func READ + kStatNFuncWrite, //!< func WRITE + kStatNFuncWeof, //!< func WEOF + kStatNFuncSforw, //!< func SFORW + kStatNFuncSback, //!< func SBACK + kStatNFuncWrteg, //!< func WRTEG + kStatNFuncRewind, //!< func REWIND + kDimStat + }; + + protected: + int AttnHandler(RlinkServer::AttnArgs& args); + void RdmaPreExecCB(int stat, size_t nwdone, size_t nwnext, + RlinkCommandList& clist); + void RdmaPostExecCB(int stat, size_t ndone, + RlinkCommandList& clist, size_t ncmd); + void AddErrorExit(RlinkCommandList& clist, uint16_t tmcr); + void AddFastExit(RlinkCommandList& clist, int opcode, + size_t ndone); + void AddNormalExit(RlinkCommandList& clist, size_t ndone, + uint16_t tmcr=0); + void WriteLog(const char* func, RerrMsg& emsg); + + protected: + size_t fPC_tmcr; //!< PrimClist: tmcr index + size_t fPC_tmsr; //!< PrimClist: tmsr index + size_t fPC_tmbc; //!< PrimClist: tmbc index + size_t fPC_tmba; //!< PrimClist: tmba index + + uint16_t fRd_tmcr; //!< Rdma: request tmcr + uint16_t fRd_tmsr; //!< Rdma: request tmsr + uint16_t fRd_tmbc; //!< Rdma: request tmbc + uint16_t fRd_tmba; //!< Rdma: request tmba + uint32_t fRd_bc; //!< Rdma: request bc + uint32_t fRd_addr; //!< Rdma: current addr + uint32_t fRd_nwrd; //!< Rdma: current nwrd + uint16_t fRd_fu; //!< Rdma: request fu code + int fRd_opcode; //!< Rdma: read opcode + std::vector fBuf; //!< data buffer + Rw11Rdma fRdma; //!< Rdma controller + }; + +} // end namespace Retro + +#include "Rw11CntlTM11.ipp" + +#endif diff --git a/tools/src/librw11/Rw11CntlTM11.ipp b/tools/src/librw11/Rw11CntlTM11.ipp new file mode 100644 index 00000000..2b8eb7d2 --- /dev/null +++ b/tools/src/librw11/Rw11CntlTM11.ipp @@ -0,0 +1,55 @@ +// $Id: Rw11CntlTM11.ipp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-17 683 1.0 Initial version +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11CntlTM11.ipp 686 2015-06-04 21:08:08Z mueller $ + \brief Implemenation (inline) of Rw11CntlTM11. +*/ + + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline void Rw11CntlTM11::SetChunkSize(size_t chunk) +{ + fRdma.SetChunkSize(chunk); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline size_t Rw11CntlTM11::ChunkSize() const +{ + return fRdma.ChunkSize(); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline const Rstats& Rw11CntlTM11::RdmaStats() const +{ + return fRdma.Stats(); +} + + +} // end namespace Retro diff --git a/tools/src/librw11/Rw11Cpu.cpp b/tools/src/librw11/Rw11Cpu.cpp index 5c86ac94..5a3ff084 100644 --- a/tools/src/librw11/Rw11Cpu.cpp +++ b/tools/src/librw11/Rw11Cpu.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11Cpu.cpp 675 2015-05-08 21:05:08Z mueller $ +// $Id: Rw11Cpu.cpp 682 2015-05-15 18:35:29Z mueller $ // // Copyright 2013-2015 by Walter F.J. Mueller // @@ -13,6 +13,8 @@ // // Revision History: // Date Rev Version Comment +// 2015-05-15 682 1.2.4 BUGFIX: Boot(): extract unit number properly +// Boot(): stop cpu before load, check unit number // 2015-05-08 675 1.2.3 w11a start/stop/suspend overhaul // 2015-04-25 668 1.2.2 add AddRbibr(), AddWbibr() // 2015-04-03 661 1.2.1 add kStat_M_* defs @@ -27,7 +29,7 @@ /*! \file - \version $Id: Rw11Cpu.cpp 675 2015-05-08 21:05:08Z mueller $ + \version $Id: Rw11Cpu.cpp 682 2015-05-15 18:35:29Z mueller $ \brief Implemenation of Rw11Cpu. */ #include @@ -678,7 +680,7 @@ bool Rw11Cpu::Boot(const std::string& uname, RerrMsg& emsg) for (size_t i=0; i= '0' && c <= '9') { - string unum = cname.substr(i); + string unum = uname.substr(i); uind = ::atoi(unum.c_str()); break; } else { @@ -691,9 +693,11 @@ bool Rw11Cpu::Boot(const std::string& uname, RerrMsg& emsg) return false; } - // FIXME_code: unit number not checked. Cntl doesn't even know about ... - Rw11Cntl& cntl = Cntl(cname); + if (uind >= cntl.NUnit()) { + emsg.Init("Rw11Cpu::Boot", string("unit number '") + uname + "' invalid"); + return false; + } vector code; uint16_t aload = 0; @@ -705,11 +709,17 @@ bool Rw11Cpu::Boot(const std::string& uname, RerrMsg& emsg) return false; } + // stop and reset cpu, just in case + RlinkCommandList clist; + clist.AddWreg(fBase+kCPCNTL, kCPFUNC_STOP); // stop cpu + clist.AddWreg(fBase+kCPCNTL, kCPFUNC_CRESET); // init cpu and bus + if (!Server().Exec(clist, emsg)) return false; + + // load boot code if (!MemWrite(aload, code, emsg)) return false; - RlinkCommandList clist; - clist.AddWreg(fBase+kCPCNTL, kCPFUNC_STOP); // stop, just in case - clist.AddWreg(fBase+kCPCNTL, kCPFUNC_CRESET); // init cpu and bus + // and start cpu at boot loader start address + clist.Clear(); clist.AddWreg(fBase+kCPPC, astart); // load PC clist.AddWreg(fBase+kCPCNTL, kCPFUNC_START); // and start SetCpuGoUp(); diff --git a/tools/src/librw11/Rw11UnitTM11.cpp b/tools/src/librw11/Rw11UnitTM11.cpp new file mode 100644 index 00000000..004fabdb --- /dev/null +++ b/tools/src/librw11/Rw11UnitTM11.cpp @@ -0,0 +1,73 @@ +// $Id: Rw11UnitTM11.cpp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-17 683 1.0 Initial version +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11UnitTM11.cpp 686 2015-06-04 21:08:08Z mueller $ + \brief Implemenation of Rw11UnitTM11. +*/ + +#include "boost/bind.hpp" + +#include "librtools/RosFill.hpp" +#include "Rw11CntlTM11.hpp" + +#include "Rw11UnitTM11.hpp" + +using namespace std; + +/*! + \class Retro::Rw11UnitTM11 + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! Constructor + +Rw11UnitTM11::Rw11UnitTM11(Rw11CntlTM11* pcntl, size_t index) + : Rw11UnitTapeBase(pcntl, index), + fTmds(0) +{ + // setup disk geometry: only rk05 supported, no rk05f ! + fType = "tu10"; + fEnabled = true; +} + +//------------------------------------------+----------------------------------- +//! Destructor + +Rw11UnitTM11::~Rw11UnitTM11() +{} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11UnitTM11::Dump(std::ostream& os, int ind, const char* text) const +{ + RosFill bl(ind); + os << bl << (text?text:"--") << "Rw11UnitTM11 @ " << this << endl; + os << bl << " fTmds: " << fTmds << endl; + + Rw11UnitTapeBase::Dump(os, ind, " ^"); + return; +} + +} // end namespace Retro diff --git a/tools/src/librw11/Rw11UnitTM11.hpp b/tools/src/librw11/Rw11UnitTM11.hpp new file mode 100644 index 00000000..71f09ce2 --- /dev/null +++ b/tools/src/librw11/Rw11UnitTM11.hpp @@ -0,0 +1,53 @@ +// $Id: Rw11UnitTM11.hpp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-17 683 1.0 Initial version +// --------------------------------------------------------------------------- + + +/*! + \file + \version $Id: Rw11UnitTM11.hpp 686 2015-06-04 21:08:08Z mueller $ + \brief Declaration of class Rw11UnitTM11. +*/ + +#ifndef included_Retro_Rw11UnitTM11 +#define included_Retro_Rw11UnitTM11 1 + +#include "Rw11UnitTapeBase.hpp" + +namespace Retro { + + class Rw11CntlTM11; // forw decl to avoid circular incl + + class Rw11UnitTM11 : public Rw11UnitTapeBase { + public: + Rw11UnitTM11(Rw11CntlTM11* pcntl, size_t index); + ~Rw11UnitTM11(); + + void SetTmds(uint16_t tmds); + uint16_t Tmds() const; + + virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; + + protected: + uint16_t fTmds; + }; + +} // end namespace Retro + +#include "Rw11UnitTM11.ipp" + +#endif diff --git a/tools/src/librw11/Rw11UnitTM11.ipp b/tools/src/librw11/Rw11UnitTM11.ipp new file mode 100644 index 00000000..4c27c36d --- /dev/null +++ b/tools/src/librw11/Rw11UnitTM11.ipp @@ -0,0 +1,52 @@ +// $Id: Rw11UnitTM11.ipp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-17 683 1.0 Initial version +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11UnitTM11.ipp 686 2015-06-04 21:08:08Z mueller $ + \brief Implemenation (inline) of Rw11UnitTM11. +*/ + +#include "Rw11UnitTM11.hpp" + +/*! + \class Retro::Rw11UnitTM11 + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline void Rw11UnitTM11::SetTmds(uint16_t tmds) +{ + fTmds = tmds; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline uint16_t Rw11UnitTM11::Tmds() const +{ + return fTmds; +} + +} // end namespace Retro diff --git a/tools/src/librw11/Rw11UnitTape.cpp b/tools/src/librw11/Rw11UnitTape.cpp new file mode 100644 index 00000000..4b6279f0 --- /dev/null +++ b/tools/src/librw11/Rw11UnitTape.cpp @@ -0,0 +1,249 @@ +// $Id: Rw11UnitTape.cpp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-06-04 686 1.0 Initial version +// 2015-05-17 683 0.1 First draft +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11UnitTape.cpp 686 2015-06-04 21:08:08Z mueller $ + \brief Implemenation of Rw11UnitTape. +*/ + +#include "librtools/Rexception.hpp" + +#include "Rw11UnitTape.hpp" + +using namespace std; + +/*! + \class Retro::Rw11UnitTape + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! Constructor + +Rw11UnitTape::Rw11UnitTape(Rw11Cntl* pcntl, size_t index) + : Rw11UnitVirt(pcntl, index), + fType(), + fEnabled(false), + fWProt(false), + fCapacity(0) +{} + +//------------------------------------------+----------------------------------- +//! Destructor + +Rw11UnitTape::~Rw11UnitTape() +{} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11UnitTape::SetType(const std::string& type) +{ + throw Rexception("Rw11UnitTape::SetType", + string("Bad args: only type '") + fType + "' supported"); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11UnitTape::SetWProt(bool wprot) +{ + if (Virt()) throw Rexception("Rw11UnitTape::SetWProt", + "not allowed when tape attached"); + fWProt = wprot; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11UnitTape::SetCapacity(size_t nbyte) +{ + if (Virt()) throw Rexception("Rw11UnitTape::SetCapacity", + "not allowed when tape attached"); + fCapacity = nbyte; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11UnitTape::SetPosFile(int posfile) +{ + if (!Virt()) throw Rexception("Rw11UnitTape::SetPosFile", + "no tape attached"); + Virt()->SetPosFile(posfile); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11UnitTape::SetPosRecord(int posrec) +{ + if (!Virt()) throw Rexception("Rw11UnitTape::SetPosRecord", + "no tape attached"); + Virt()->SetPosRecord(posrec); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11UnitTape::Bot() const +{ + if (!Virt()) return false; + return Virt()->Bot(); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11UnitTape::Eot() const +{ + if (!Virt()) return false; + return Virt()->Eot(); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11UnitTape::Eom() const +{ + if (!Virt()) return false; + return Virt()->Eom(); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +int Rw11UnitTape::PosFile() const +{ + if (!Virt()) return -1; + return Virt()->PosFile(); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +int Rw11UnitTape::PosRecord() const +{ + if (!Virt()) return -1; + return Virt()->PosRecord(); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11UnitTape::VirtReadRecord(size_t nbyte, uint8_t* data, size_t& ndone, + int& opcode, RerrMsg& emsg) +{ + if (!Virt()) { + emsg.Init("Rw11UnitTape::VirtReadRecord", "no tape attached"); + return false; + } + return Virt()->ReadRecord(nbyte, data, ndone, opcode, emsg); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11UnitTape::VirtWriteRecord(size_t nbyte, const uint8_t* data, + int& opcode, RerrMsg& emsg) +{ + if (!Virt()) { + emsg.Init("Rw11UnitTape::VirtWriteRecord", "no tape attached"); + return false; + } + return Virt()->WriteRecord(nbyte, data, opcode, emsg); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11UnitTape::VirtWriteEof(RerrMsg& emsg) +{ + if (!Virt()) { + emsg.Init("Rw11UnitTape::VirtWriteEof", "no tape attached"); + return false; + } + return Virt()->WriteEof(emsg); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11UnitTape::VirtSpaceForw(size_t nrec, size_t& ndone, + int& opcode, RerrMsg& emsg) +{ + if (!Virt()) { + emsg.Init("Rw11UnitTape::VirtSpaceForw", "no tape attached"); + return false; + } + return Virt()->SpaceForw(nrec, ndone, opcode, emsg); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11UnitTape::VirtSpaceBack(size_t nrec, size_t& ndone, + int& opcode, RerrMsg& emsg) +{ + if (!Virt()) { + emsg.Init("Rw11UnitTape::VirtSpaceBack", "no tape attached"); + return false; + } + return Virt()->SpaceBack(nrec, ndone, opcode, emsg); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11UnitTape::VirtRewind(int& opcode, RerrMsg& emsg) +{ + if (!Virt()) { + emsg.Init("Rw11UnitTape::VirtRewind", "no tape attached"); + return false; + } + return Virt()->Rewind(opcode, emsg); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11UnitTape::Dump(std::ostream& os, int ind, const char* text) const +{ + RosFill bl(ind); + os << bl << (text?text:"--") << "Rw11UnitTape @ " << this << endl; + os << bl << " fType: " << fType << endl; + os << bl << " fEnabled: " << fEnabled << endl; + os << bl << " fWProt: " << fWProt << endl; + os << bl << " fCapacity: " << fCapacity << endl; + + Rw11UnitVirt::Dump(os, ind, " ^"); + return; +} + + +} // end namespace Retro diff --git a/tools/src/librw11/Rw11UnitTape.hpp b/tools/src/librw11/Rw11UnitTape.hpp new file mode 100644 index 00000000..f3c610b4 --- /dev/null +++ b/tools/src/librw11/Rw11UnitTape.hpp @@ -0,0 +1,85 @@ +// $Id: Rw11UnitTape.hpp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-06-04 686 1.0 Initial version +// 2015-05-17 683 0.1 First draft +// --------------------------------------------------------------------------- + + +/*! + \file + \version $Id: Rw11UnitTape.hpp 686 2015-06-04 21:08:08Z mueller $ + \brief Declaration of class Rw11UnitTape. +*/ + +#ifndef included_Retro_Rw11UnitTape +#define included_Retro_Rw11UnitTape 1 + +#include "Rw11VirtTape.hpp" + +#include "Rw11UnitVirt.hpp" + +namespace Retro { + + class Rw11UnitTape : public Rw11UnitVirt { + public: + Rw11UnitTape(Rw11Cntl* pcntl, size_t index); + ~Rw11UnitTape(); + + virtual void SetType(const std::string& type); + + const std::string& Type() const; + virtual bool Enabled() const; + + void SetWProt(bool wprot); + void SetCapacity(size_t nbyte); + bool WProt() const; + size_t Capacity() const; + + void SetPosFile(int posfile); + void SetPosRecord(int posrec); + + bool Bot() const; + bool Eot() const; + bool Eom() const; + + int PosFile() const; + int PosRecord() const; + + bool VirtReadRecord(size_t nbyte, uint8_t* data, size_t& ndone, + int& opcode, RerrMsg& emsg); + bool VirtWriteRecord(size_t nbyte, const uint8_t* data, + int& opcode, RerrMsg& emsg); + bool VirtWriteEof(RerrMsg& emsg); + bool VirtSpaceForw(size_t nrec, size_t& ndone, + int& opcode, RerrMsg& emsg); + bool VirtSpaceBack(size_t nrec, size_t& ndone, + int& opcode, RerrMsg& emsg); + bool VirtRewind(int& opcode, RerrMsg& emsg); + + virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; + + protected: + std::string fType; //!< drive type + bool fEnabled; //!< unit enabled + bool fWProt; //!< unit write protected + size_t fCapacity; // +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-06-04 686 1.0 Initial version +// 2015-05-17 683 0.1 First draft +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11UnitTape.ipp 686 2015-06-04 21:08:08Z mueller $ + \brief Implemenation (inline) of Rw11UnitTape. +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline const std::string& Rw11UnitTape::Type() const +{ + return fType; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline bool Rw11UnitTape::Enabled() const +{ + return fEnabled; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline bool Rw11UnitTape::WProt() const +{ + return Virt() ? Virt()->WProt() : fWProt; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline size_t Rw11UnitTape::Capacity() const +{ + return Virt() ? Virt()->Capacity() : fCapacity; +} + + +} // end namespace Retro diff --git a/tools/src/librw11/Rw11UnitTapeBase.hpp b/tools/src/librw11/Rw11UnitTapeBase.hpp new file mode 100644 index 00000000..84842d99 --- /dev/null +++ b/tools/src/librw11/Rw11UnitTapeBase.hpp @@ -0,0 +1,56 @@ +// $Id: Rw11UnitTapeBase.hpp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-17 683 1.0 Initial version +// --------------------------------------------------------------------------- + + +/*! + \file + \version $Id: Rw11UnitTapeBase.hpp 686 2015-06-04 21:08:08Z mueller $ + \brief Declaration of class Rw11UnitTapeBase. +*/ + +#ifndef included_Retro_Rw11UnitTapeBase +#define included_Retro_Rw11UnitTapeBase 1 + +#include "Rw11UnitTape.hpp" + +namespace Retro { + + template + class Rw11UnitTapeBase : public Rw11UnitTape { + public: + + Rw11UnitTapeBase(TC* pcntl, size_t index); + ~Rw11UnitTapeBase(); + + TC& Cntl() const; + + virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; + + protected: + virtual void AttachDone(); + virtual void DetachDone(); + + protected: + TC* fpCntl; + }; + +} // end namespace Retro + +#include "Rw11UnitTapeBase.ipp" + +#endif diff --git a/tools/src/librw11/Rw11UnitTapeBase.ipp b/tools/src/librw11/Rw11UnitTapeBase.ipp new file mode 100644 index 00000000..6a1f96f0 --- /dev/null +++ b/tools/src/librw11/Rw11UnitTapeBase.ipp @@ -0,0 +1,99 @@ +// $Id: Rw11UnitTapeBase.ipp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-06-04 686 1.0 Initial version +// 2015-05-17 683 0.1 First draft +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11UnitTapeBase.ipp 686 2015-06-04 21:08:08Z mueller $ + \brief Implemenation (inline) of Rw11UnitTapeBase. +*/ + +#include "Rw11UnitTapeBase.hpp" + +/*! + \class Retro::Rw11UnitTapeBase + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! Default constructor + +template +Rw11UnitTapeBase::Rw11UnitTapeBase(TC* pcntl, size_t index) + : Rw11UnitTape(pcntl, index), + fpCntl(pcntl) +{} + +//------------------------------------------+----------------------------------- +//! Destructor + +template +Rw11UnitTapeBase::~Rw11UnitTapeBase() +{} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +template +inline TC& Rw11UnitTapeBase::Cntl() const +{ + return *fpCntl; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +template +void Rw11UnitTapeBase::Dump(std::ostream& os, int ind, + const char* text) const +{ + RosFill bl(ind); + os << bl << (text?text:"--") << "Rw11UnitTapeBase @ " << this << std::endl; + os << bl << " fpCntl: " << fpCntl << std::endl; + Rw11UnitTape::Dump(os, ind, " ^"); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +template +void Rw11UnitTapeBase::AttachDone() +{ + // transfer, if defined, wprot and capacity from unit to virt + if (WProt()) Virt()->SetWProt(true); + if (Capacity()!=0 && Virt()->Capacity()==0) Virt()->SetCapacity(Capacity()); + Cntl().UnitSetup(Index()); + return; +} + + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +template +void Rw11UnitTapeBase::DetachDone() +{ + Cntl().UnitSetup(Index()); + return; +} + +} // end namespace Retro diff --git a/tools/src/librw11/Rw11VirtDiskFile.cpp b/tools/src/librw11/Rw11VirtDiskFile.cpp index 845b19ab..1da51f5c 100644 --- a/tools/src/librw11/Rw11VirtDiskFile.cpp +++ b/tools/src/librw11/Rw11VirtDiskFile.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11VirtDiskFile.cpp 516 2013-05-05 21:24:52Z mueller $ +// $Id: Rw11VirtDiskFile.cpp 684 2015-05-24 14:10:59Z mueller $ // // Copyright 2013- by Walter F.J. Mueller // @@ -19,7 +19,7 @@ /*! \file - \version $Id: Rw11VirtDiskFile.cpp 516 2013-05-05 21:24:52Z mueller $ + \version $Id: Rw11VirtDiskFile.cpp 684 2015-05-24 14:10:59Z mueller $ \brief Implemenation of Rw11VirtDiskFile. */ @@ -148,6 +148,20 @@ bool Rw11VirtDiskFile::Write(size_t lba, size_t nblk, const uint8_t* data, //------------------------------------------+----------------------------------- //! FIXME_docs +void Rw11VirtDiskFile::Dump(std::ostream& os, int ind, const char* text) const +{ + RosFill bl(ind); + os << bl << (text?text:"--") << "Rw11VirtDiskFile @ " << this << endl; + + os << bl << " fFd: " << fFd << endl; + os << bl << " fSize: " << fSize << endl; + Rw11VirtDisk::Dump(os, ind, " ^"); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + bool Rw11VirtDiskFile::Seek(size_t seekpos, RerrMsg& emsg) { if (::lseek(fFd, seekpos, SEEK_SET) < 0) { @@ -158,17 +172,4 @@ bool Rw11VirtDiskFile::Seek(size_t seekpos, RerrMsg& emsg) return true; } -//------------------------------------------+----------------------------------- -//! FIXME_docs - -void Rw11VirtDiskFile::Dump(std::ostream& os, int ind, const char* text) const -{ - RosFill bl(ind); - os << bl << (text?text:"--") << "Rw11VirtDiskFile @ " << this << endl; - - os << bl << " fFd: " << fFd << endl; - Rw11VirtDisk::Dump(os, ind, " ^"); - return; -} - } // end namespace Retro diff --git a/tools/src/librw11/Rw11VirtTape.cpp b/tools/src/librw11/Rw11VirtTape.cpp new file mode 100644 index 00000000..894ee7f9 --- /dev/null +++ b/tools/src/librw11/Rw11VirtTape.cpp @@ -0,0 +1,172 @@ +// $Id: Rw11VirtTape.cpp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-06-04 686 1.0 Initial version +// 2015-05-17 683 0.1 First draft +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11VirtTape.cpp 686 2015-06-04 21:08:08Z mueller $ + \brief Implemenation of Rw11VirtTape. +*/ +#include + +#include "librtools/RosFill.hpp" +#include "librtools/RparseUrl.hpp" +#include "librtools/Rexception.hpp" +#include "Rw11VirtTapeTap.hpp" + +#include "Rw11VirtTape.hpp" + +using namespace std; + +/*! + \class Retro::Rw11VirtTape + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! Default constructor + +Rw11VirtTape::Rw11VirtTape(Rw11Unit* punit) + : Rw11Virt(punit), + fWProt(false), + fCapacity(0), + fBot(false), + fEot(false), + fEom(true), + fPosFile(-1), + fPosRecord(-1) +{ + fStats.Define(kStatNVTReadRec, "NVTReadRec", "ReadRecord() calls"); + fStats.Define(kStatNVTReadByt, "NVTReadByt", "bytes read"); + fStats.Define(kStatNVTReadEof, "NVTReadEof", "eof read"); + fStats.Define(kStatNVTReadEom, "NVTReadEom", "eom read"); + fStats.Define(kStatNVTReadPErr, "NVTReadPErr", "parity error read"); + fStats.Define(kStatNVTReadLErr, "NVTReadLErr", "length error read"); + fStats.Define(kStatNVTWriteRec, "NVTWriteRec", "WriteRecord() calls"); + fStats.Define(kStatNVTWriteByt, "NVTWriteByt", "bytes written"); + fStats.Define(kStatNVTWriteEof, "NVTWriteEof", "WriteEof() calls"); + fStats.Define(kStatNVTSpaForw, "NVTSpaForw", "SpaceForw() calls"); + fStats.Define(kStatNVTSpaBack, "NVTSpaBack", "SpaceBack() calls"); + fStats.Define(kStatNVTRewind, "NVTRewind", "Rewind() calls"); +} + +//------------------------------------------+----------------------------------- +//! Destructor + +Rw11VirtTape::~Rw11VirtTape() +{} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +Rw11VirtTape* Rw11VirtTape::New(const std::string& url, Rw11Unit* punit, + RerrMsg& emsg) +{ + string scheme = RparseUrl::FindScheme(url, "tap"); + unique_ptr p; + + if (scheme == "tap") { // scheme -> tap: + p.reset(new Rw11VirtTapeTap(punit)); + if (p->Open(url, emsg)) return p.release(); + + } else { // scheme -> no match + emsg.Init("Rw11VirtTape::New", string("Scheme '") + scheme + + "' is not supported"); + } + + return 0; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11VirtTape::SetPosFile(int posfile) +{ + if (posfile < 0) posfile = 0; + + RerrMsg emsg; + int opcode; + size_t ndone; + bool rc = Rewind(opcode, emsg); + + while (rc && posfile != fPosFile) { + rc = SpaceForw(1000000000, ndone, opcode, emsg); + if (rc && opcode == kOpCodeEom) return; + } + + if (!rc) throw Rexception("Rw11VirtTape::SetPosFile", emsg.Text()); + + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11VirtTape::SetPosRecord(int posrec) +{ + if (posrec < 0) posrec = 0; + + RerrMsg emsg; + int opcode; + size_t ndone; + + // space back to begin of current file (works even when fPosRecord is -1!) + bool rc = SpaceBack(1000000000, ndone, opcode, emsg); + // if eof was spaced over backwards, space forward over eof + if (rc && opcode == kOpCodeEof) rc = SpaceForw(1, ndone, opcode, emsg); + // now space forward to find record + if (rc && posrec != 0) { + rc = SpaceForw(posrec, ndone, opcode, emsg); + // if eof was spaced over, space backward over eof to stay in file + // the number of records spaced is used to setup fPosRecord + if (rc && opcode == kOpCodeEof) { + size_t ndoneeof; + rc = SpaceBack(1, ndoneeof, opcode, emsg); + if (rc) fPosRecord = ndone; + } + } + + if (!rc) throw Rexception("Rw11VirtTape::SetPosFile", emsg.Text()); + + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11VirtTape::Dump(std::ostream& os, int ind, const char* text) const +{ + RosFill bl(ind); + os << bl << (text?text:"--") << "Rw11VirtTape @ " << this << endl; + + os << bl << " fWProt: " << fWProt << endl; + os << bl << " fCapacity: " << fCapacity << endl; + os << bl << " fBot: " << fBot << endl; + os << bl << " fEot: " << fEot << endl; + os << bl << " fEom: " << fEom << endl; + os << bl << " fPosFile: " << fPosFile << endl; + os << bl << " fPosRecord: " << fPosRecord << endl; + Rw11Virt::Dump(os, ind, " ^"); + return; +} + + +} // end namespace Retro diff --git a/tools/src/librw11/Rw11VirtTape.hpp b/tools/src/librw11/Rw11VirtTape.hpp new file mode 100644 index 00000000..be4774f0 --- /dev/null +++ b/tools/src/librw11/Rw11VirtTape.hpp @@ -0,0 +1,112 @@ +// $Id: Rw11VirtTape.hpp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-06-04 686 1.0 Initial version +// 2015-05-17 683 0.1 First draft +// --------------------------------------------------------------------------- + + +/*! + \file + \version $Id: Rw11VirtTape.hpp 686 2015-06-04 21:08:08Z mueller $ + \brief Declaration of class Rw11VirtTape. +*/ + +#ifndef included_Retro_Rw11VirtTape +#define included_Retro_Rw11VirtTape 1 + +#include "Rw11Virt.hpp" + +namespace Retro { + + class Rw11VirtTape : public Rw11Virt { + public: + explicit Rw11VirtTape(Rw11Unit* punit); + ~Rw11VirtTape(); + + void SetWProt(bool wprot); + void SetCapacity(size_t nbyte); + bool WProt() const; + size_t Capacity() const; + + virtual bool ReadRecord(size_t nbyte, uint8_t* data, size_t& ndone, + int& opcode, RerrMsg& emsg) = 0; + virtual bool WriteRecord(size_t nbyte, const uint8_t* data, + int& opcode, RerrMsg& emsg) = 0; + virtual bool WriteEof(RerrMsg& emsg) = 0; + virtual bool SpaceForw(size_t nrec, size_t& ndone, + int& opcode, RerrMsg& emsg) = 0; + virtual bool SpaceBack(size_t nrec, size_t& ndone, + int& opcode, RerrMsg& emsg) = 0; + virtual bool Rewind(int& opcode, RerrMsg& emsg) = 0; + + void SetPosFile(int posfile); + void SetPosRecord(int posrec); + + bool Bot() const; + bool Eot() const; + bool Eom() const; + + int PosFile() const; + int PosRecord() const; + + virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; + + static Rw11VirtTape* New(const std::string& url, Rw11Unit* punit, + RerrMsg& emsg); + + // statistics counter indices + enum stats { + kStatNVTReadRec = Rw11Virt::kDimStat, + kStatNVTReadByt, + kStatNVTReadEof, + kStatNVTReadEom, + kStatNVTReadPErr, + kStatNVTReadLErr, + kStatNVTWriteRec, + kStatNVTWriteByt, + kStatNVTWriteEof, + kStatNVTSpaForw, + kStatNVTSpaBack, + kStatNVTRewind, + kDimStat + }; + + // operation code + enum OpCode { + kOpCodeOK = 0, // +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-06-04 686 1.0 Initial version +// 2015-05-17 683 0.1 First draft +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11VirtTape.ipp 686 2015-06-04 21:08:08Z mueller $ + \brief Implemenation (inline) of Rw11VirtTape. +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline void Rw11VirtTape::SetWProt(bool wprot) +{ + fWProt = wprot; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline void Rw11VirtTape::SetCapacity(size_t nbyte) +{ + fCapacity = nbyte; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline bool Rw11VirtTape::WProt() const +{ + return fWProt; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline size_t Rw11VirtTape::Capacity() const +{ + return fCapacity; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline bool Rw11VirtTape::Bot() const +{ + return fBot; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline bool Rw11VirtTape::Eot() const +{ + return fEot; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline bool Rw11VirtTape::Eom() const +{ + return fEom; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline int Rw11VirtTape::PosFile() const +{ + return fPosFile; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline int Rw11VirtTape::PosRecord() const +{ + return fPosRecord; +} + +} // end namespace Retro diff --git a/tools/src/librw11/Rw11VirtTapeTap.cpp b/tools/src/librw11/Rw11VirtTapeTap.cpp new file mode 100644 index 00000000..f80f3b19 --- /dev/null +++ b/tools/src/librw11/Rw11VirtTapeTap.cpp @@ -0,0 +1,589 @@ +// $Id: Rw11VirtTapeTap.cpp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-06-04 686 1.0 Initial version +// 2015-05-17 683 0.1 First draft +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11VirtTapeTap.cpp 686 2015-06-04 21:08:08Z mueller $ + \brief Implemenation of Rw11VirtTapeTap. +*/ + +#include +#include +#include +#include + +#include "librtools/RosFill.hpp" +#include "librtools/Rtools.hpp" + +#include "Rw11VirtTapeTap.hpp" + +using namespace std; + +/*! + \class Retro::Rw11VirtTapeTap + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +// constants definitions + +const uint32_t Rw11VirtTapeTap::kMetaEof; +const uint32_t Rw11VirtTapeTap::kMetaEom; +const uint32_t Rw11VirtTapeTap::kMeta_M_Perr; +const uint32_t Rw11VirtTapeTap::kMeta_M_Mbz; +const uint32_t Rw11VirtTapeTap::kMeta_B_Rlen; + +//------------------------------------------+----------------------------------- +//! Default constructor + +Rw11VirtTapeTap::Rw11VirtTapeTap(Rw11Unit* punit) + : Rw11VirtTape(punit), + fFd(0), + fSize(0), + fPos(0), + fBad(true), + fPadOdd(false), + fTruncPend(false) +{} + +//------------------------------------------+----------------------------------- +//! Destructor + +Rw11VirtTapeTap::~Rw11VirtTapeTap() +{ + if (fFd > 2) ::close(fFd); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11VirtTapeTap::Open(const std::string& url, RerrMsg& emsg) +{ + if (!fUrl.Set(url, "|wpro|e11|cap=|", emsg)) return false; + + fWProt = fUrl.FindOpt("wpro"); + fPadOdd = fUrl.FindOpt("e11"); + + string str_cap; + unsigned long capacity=0; + if (fUrl.FindOpt("cap",str_cap)) { + if (str_cap.length() > 0) { + unsigned long scale = 1; + string str_conv = str_cap; + char clast = str_cap[str_cap.length()-1]; + bool ok = true; + + if (! (clast >= '0' && clast <= '9') ) { + str_conv = str_cap.substr(0,str_cap.length()-1); + switch(str_cap[str_cap.length()-1]) { + case 'k': + case 'K': + scale = 1024; + break; + case 'm': + case 'M': + scale = 1024*1024; + break; + default: + ok = false; + break; + } + } + if (ok) { + RerrMsg emsg_conv; + ok = Rtools::String2Long(str_conv, capacity, emsg_conv); + } + if (!ok) { + emsg.Init("Rw11VirtTapeTap::Open()", + string("bad capacity option '")+str_cap+"'"); + return false; + } + capacity *= scale; + } + } + + int fd = ::open(fUrl.Path().c_str(), fWProt ? O_RDONLY : O_CREAT|O_RDWR, + S_IRUSR|S_IWUSR|S_IRGRP); + if (fd < 0) { + emsg.InitErrno("Rw11VirtTapeTap::Open()", + string("open() for '") + fUrl.Path() + "' failed: ", errno); + return false; + } + + struct stat sbuf; + if (::fstat(fd, &sbuf) < 0) { + emsg.InitErrno("Rw11VirtTapeTap::Open()", + string("stat() for '") + fUrl.Path() + "' failed: ", errno); + return false; + } + + if ((sbuf.st_mode & S_IWUSR) == 0) fWProt = true; + + fFd = fd; + fSize = sbuf.st_size; + fPos = 0; + fBad = false; + fTruncPend = true; + + fCapacity = capacity; + fBot = true; + fEot = false; + fEom = false; + fPosFile = 0; + fPosRecord = 0; + return true; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11VirtTapeTap::ReadRecord(size_t nbyt, uint8_t* data, size_t& ndone, + int& opcode, RerrMsg& emsg) +{ + fStats.Inc(kStatNVTReadRec); + + opcode = kOpCodeBadFormat; + ndone = 0; + if (fBad) return BadTapeMsg("ReadRecord()", emsg); + + if (fPos == fSize) { + fEom = true; + opcode = kOpCodeEom; + return true; + } + + uint32_t metabeg; + uint32_t metaend; + + if (!CheckSizeForw(sizeof(metabeg), "missed metabeg", emsg)) return SetBad(); + if (!Read(sizeof(metabeg), reinterpret_cast(&metabeg), + emsg)) return SetBad(); + + if (metabeg == kMetaEof) { + fStats.Inc(kStatNVTReadEof); + opcode = kOpCodeEof; + fPosFile += 1; + fPosRecord = 0; + return true; + } + + if (metabeg == kMetaEom) { + if (!Seek(sizeof(metabeg), -1, emsg)) return SetBad(); + fStats.Inc(kStatNVTReadEom); + fEom = true; + opcode = kOpCodeEom; + return true; + } + + size_t rlen; + bool perr; + if (!ParseMeta(metabeg, rlen, perr, emsg)) return SetBad(); + size_t rlenpad = BytePadding(rlen); + + if (!CheckSizeForw(rlenpad, "missed data", emsg)) return SetBad(); + + ndone = (rlen <= nbyt) ? rlen : nbyt; + if (!Read(ndone, data, emsg)) return SetBad(); + if (ndone < rlenpad) { + if (!Seek(rlenpad, +1, emsg)) return SetBad(); + } + + if (!CheckSizeForw(sizeof(metaend), "missed metaend", emsg)) return SetBad(); + if (!Read(sizeof(metaend), reinterpret_cast(&metaend), + emsg)) return SetBad(); + + if (metabeg != metaend) { + emsg.Init("Rw11VirtTapeTap::ReadRecord", "metabeg metaend mismatch"); + ndone = 0; + return SetBad(); + } + + IncPosRecord(+1); + opcode = kOpCodeOK; + if (perr) { + fStats.Inc(kStatNVTReadPErr); + opcode = kOpCodeBadParity; + } + if (ndone < rlen) { + fStats.Inc(kStatNVTReadLErr); + opcode = kOpCodeRecLenErr; + } + + fStats.Inc(kStatNVTReadByt, ndone); + + return true; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11VirtTapeTap::WriteRecord(size_t nbyt, const uint8_t* data, + int& opcode, RerrMsg& emsg) +{ + fStats.Inc(kStatNVTWriteRec); + fStats.Inc(kStatNVTWriteByt, nbyt); + + opcode = kOpCodeBadFormat; + if (fBad) return BadTapeMsg("WriteRecord()", emsg); + + fEom = false; + + uint32_t meta = nbyt; + uint8_t zero = 0x00; + + if (!Write(sizeof(meta), reinterpret_cast(&meta), + false, emsg)) return SetBad(); + + if (!Write(nbyt, data, + false, emsg)) return SetBad(); + if (fPadOdd && (nbyt&0x01)) { + if (!Write(sizeof(zero), &zero, false, emsg)) return SetBad(); + } + + if (!Write(sizeof(meta), reinterpret_cast(&meta), + false, emsg)) return SetBad(); + if (!Write(sizeof(kMetaEom), reinterpret_cast(&kMetaEom), + true, emsg)) return SetBad(); + + IncPosRecord(+1); + opcode = kOpCodeOK; + + return true; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11VirtTapeTap::WriteEof(RerrMsg& emsg) +{ + fStats.Inc(kStatNVTWriteEof); + + if (fBad) return BadTapeMsg("WriteEof()", emsg); + + fEom = false; + + if (!Write(sizeof(kMetaEof), reinterpret_cast(&kMetaEof), + false, emsg)) return SetBad(); + if (!Write(sizeof(kMetaEom), reinterpret_cast(&kMetaEom), + true, emsg)) return SetBad(); + + fPosFile += 1; + fPosRecord = 0; + + return true; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11VirtTapeTap::SpaceForw(size_t nrec, size_t& ndone, + int& opcode, RerrMsg& emsg) +{ + fStats.Inc(kStatNVTSpaForw); + + opcode = kOpCodeBadFormat; + ndone = 0; + if (fBad) return BadTapeMsg("SpaceForw()", emsg); + + while (nrec > 0) { + + if (fPos == fSize) { + fEom = true; + opcode = kOpCodeEom; + return true; + } + + uint32_t metabeg; + + if (!CheckSizeForw(sizeof(metabeg), "missed metabeg", emsg)) return SetBad(); + if (!Read(sizeof(metabeg), reinterpret_cast(&metabeg), + emsg)) return SetBad(); + + if (metabeg == kMetaEof) { + opcode = kOpCodeEof; + fPosFile += 1; + fPosRecord = 0; + return true; + } + + if (metabeg == kMetaEom) { + if (!Seek(sizeof(metabeg), -1, emsg)) return SetBad(); + fEom = true; + opcode = kOpCodeEom; + return true; + } + + size_t rlen; + bool perr; + if (!ParseMeta(metabeg, rlen, perr, emsg)) return SetBad(); + size_t rlenpad = BytePadding(rlen); + + if (!CheckSizeForw(sizeof(metabeg)+rlenpad, "missed data or metaend", emsg)) + return SetBad(); + if (!Seek(sizeof(metabeg)+rlenpad, +1, emsg)) return SetBad(); + + IncPosRecord(+1); + nrec -= 1; + ndone += 1; + } + + opcode = kOpCodeOK; + + return true; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11VirtTapeTap::SpaceBack(size_t nrec, size_t& ndone, + int& opcode, RerrMsg& emsg) +{ + fStats.Inc(kStatNVTSpaBack); + + opcode = kOpCodeBadFormat; + ndone = 0; + if (fBad) return BadTapeMsg("SpaceBack()", emsg); + + fEom = false; + fTruncPend = true; + + while (nrec > 0) { + + if (fPos == 0) { + opcode = kOpCodeBot; + fPosFile = 0; + fPosRecord = 0; + return true; + } + + uint32_t metaend; + + if (!CheckSizeBack(sizeof(metaend), "missed metaend", emsg)) return SetBad(); + if (!Seek(sizeof(metaend), -1, emsg)) return SetBad(); + if (!Read(sizeof(metaend), reinterpret_cast(&metaend), + emsg)) return SetBad(); + + if (metaend == kMetaEof) { + if (!Seek(sizeof(metaend), -1, emsg)) return SetBad(); + opcode = kOpCodeEof; + fPosFile -= 1; + fPosRecord = -1; + return true; + } + + if (metaend == kMetaEom) { + emsg.Init("Rw11VirtTapeTap::SpaceBack()","unexpected EOM marker"); + return SetBad(); + } + + size_t rlen; + bool perr; + if (!ParseMeta(metaend, rlen, perr, emsg)) return SetBad(); + size_t rlenpad = BytePadding(rlen); + + if (!CheckSizeBack(2*sizeof(metaend)+rlenpad, + "missed data or metabeg", emsg)) return SetBad(); + if (!Seek(2*sizeof(metaend)+rlenpad, -1, emsg)) return SetBad(); + + IncPosRecord(-1); + nrec -= 1; + ndone += 1; + } + + opcode = kOpCodeOK; + + return true; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11VirtTapeTap::Rewind(int& opcode, RerrMsg& emsg) +{ + fStats.Inc(kStatNVTRewind); + + opcode = kOpCodeBadFormat; + if (Seek(0, 0, emsg) <0) return SetBad(); + + fBot = true; + fEot = false; + fEom = false; + fPosFile = 0; + fPosRecord = 0; + fBad = false; + fTruncPend = true; + + opcode = kOpCodeOK; + return true; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11VirtTapeTap::Dump(std::ostream& os, int ind, const char* text) const +{ + RosFill bl(ind); + os << bl << (text?text:"--") << "Rw11VirtTapeTap @ " << this << endl; + + os << bl << " fFd: " << fFd << endl; + os << bl << " fSize: " << fSize << endl; + os << bl << " fPos: " << fPos << endl; + os << bl << " fBad: " << fBad << endl; + os << bl << " fPadOdd: " << fPadOdd << endl; + Rw11VirtTape::Dump(os, ind, " ^"); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11VirtTapeTap::Seek(size_t seekpos, int dir, RerrMsg& emsg) +{ + off_t offset = seekpos; + int whence = SEEK_SET; + if (dir > 0) { + whence = SEEK_CUR; + } else if (dir < 0) { + whence = SEEK_CUR; + offset = -offset; + } + if (::lseek(fFd, offset, whence) < 0) { + emsg.InitErrno("Rw11VirtTapeTap::Seek()", "seek() failed: ", errno); + return false; + } + + UpdatePos(seekpos, dir); + + return true; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11VirtTapeTap::Read(size_t nbyt, uint8_t* data, RerrMsg& emsg) +{ + ssize_t irc = ::read(fFd, data, nbyt); + if (irc < 0) { + emsg.InitErrno("Rw11VirtTapeTap::Read()", "read() failed: ", errno); + return false; + } + UpdatePos(nbyt, +1); + return true; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11VirtTapeTap::Write(size_t nbyt, const uint8_t* data, bool back, + RerrMsg& emsg) +{ + if (fTruncPend) { + if (ftruncate(fFd, fPos) < 0) { + emsg.InitErrno("Rw11VirtTapeTap::Write()", "ftruncate() failed: ", errno); + return false; + } + fTruncPend = false; + fSize = fPos; + } + + ssize_t irc = ::write(fFd, data, nbyt); + if (irc < 0) { + emsg.InitErrno("Rw11VirtTapeTap::Write()", "write() failed: ", errno); + return false; + } + + UpdatePos(nbyt, +1); + if (fPos > fSize) fSize = fPos; + + if (back) { + if (!Seek(nbyt, -1, emsg)) return false; + } + + return true; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11VirtTapeTap::CheckSizeForw(size_t nbyt, const char* text, + RerrMsg& emsg) +{ + if (fPos+nbyt <= fSize) return true; + emsg.Init("Rw11VirtTapeTap::CheckSizeForw()", text); + return false; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11VirtTapeTap::CheckSizeBack(size_t nbyt, const char* text, + RerrMsg& emsg) +{ + if (nbyt <= fPos) return true; + emsg.Init("Rw11VirtTapeTap::CheckSizeBack()", text); + return false; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11VirtTapeTap::UpdatePos(size_t nbyt, int dir) +{ + if (dir == 0) { + fPos = nbyt; + } else if (dir > 0) { + fPos += nbyt; + } else { + fPos -= nbyt; + } + + fBot = (fPos == 0); + fEot = (fCapacity == 0) ? false : (fPos > fCapacity); + + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11VirtTapeTap::ParseMeta(uint32_t meta, size_t& rlen, bool& perr, + RerrMsg& emsg) +{ + rlen = meta & kMeta_B_Rlen; + perr = meta & kMeta_M_Perr; + if (meta & kMeta_M_Mbz) { + emsg.Init("Rw11VirtTapeTap::ParseMeta", "bad meta tag"); + return false; + } + return true; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11VirtTapeTap::BadTapeMsg(const char* meth, RerrMsg& emsg) +{ + emsg.Init(string("Rw11VirtTapeTap::")+meth, "bad tape format"); + return false; +} + +} // end namespace Retro diff --git a/tools/src/librw11/Rw11VirtTapeTap.hpp b/tools/src/librw11/Rw11VirtTapeTap.hpp new file mode 100644 index 00000000..592ec30b --- /dev/null +++ b/tools/src/librw11/Rw11VirtTapeTap.hpp @@ -0,0 +1,90 @@ +// $Id: Rw11VirtTapeTap.hpp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-06-04 686 1.0 Initial version +// 2015-05-17 683 0.1 First draft +// --------------------------------------------------------------------------- + + +/*! + \file + \version $Id: Rw11VirtTapeTap.hpp 686 2015-06-04 21:08:08Z mueller $ + \brief Declaration of class Rw11VirtTapeTap. +*/ + +#ifndef included_Retro_Rw11VirtTapeTap +#define included_Retro_Rw11VirtTapeTap 1 + +#include "Rw11VirtTape.hpp" + +namespace Retro { + + class Rw11VirtTapeTap : public Rw11VirtTape { + public: + + explicit Rw11VirtTapeTap(Rw11Unit* punit); + ~Rw11VirtTapeTap(); + + bool Open(const std::string& url, RerrMsg& emsg); + + virtual bool ReadRecord(size_t nbyt, uint8_t* data, size_t& ndone, + int& opcode, RerrMsg& emsg); + virtual bool WriteRecord(size_t nbyt, const uint8_t* data, + int& opcode, RerrMsg& emsg); + virtual bool WriteEof(RerrMsg& emsg); + virtual bool SpaceForw(size_t nrec, size_t& ndone, + int& opcode, RerrMsg& emsg); + virtual bool SpaceBack(size_t nrec, size_t& ndone, + int& opcode, RerrMsg& emsg); + virtual bool Rewind(int& opcode, RerrMsg& emsg); + + virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; + + // some constants (also defined in cpp) + static const uint32_t kMetaEof = 0x00000000; //!< EOF marker + static const uint32_t kMetaEom = 0xffffffff; //!< EOM marker + static const uint32_t kMeta_M_Perr = 0x80000000; + static const uint32_t kMeta_M_Mbz = 0x7fff0000; + static const uint32_t kMeta_B_Rlen = 0x0000ffff; + + protected: + bool Seek(size_t seekpos, int dir, RerrMsg& emsg); + bool Read(size_t nbyt, uint8_t* data, RerrMsg& emsg); + bool Write(size_t nbyt, const uint8_t* data, bool back, + RerrMsg& emsg); + bool CheckSizeForw(size_t nbyt, const char* text, RerrMsg& emsg); + bool CheckSizeBack(size_t nbyt, const char* text, RerrMsg& emsg); + void UpdatePos(size_t nbyt, int dir); + bool ParseMeta(uint32_t meta, size_t& rlen, bool& perr, + RerrMsg& emsg); + size_t BytePadding(size_t rlen); + bool SetBad(); + bool BadTapeMsg(const char* meth, RerrMsg& emsg); + void IncPosRecord(int delta); + + protected: + int fFd; //!< file number + size_t fSize; //!< file size + size_t fPos; //!< file position + bool fBad; //!< BAD file format flag + bool fPadOdd; //!< do odd byte padding + bool fTruncPend; //!< truncate on next write + }; + +} // end namespace Retro + +#include "Rw11VirtTapeTap.ipp" + +#endif diff --git a/tools/src/librw11/Rw11VirtTapeTap.ipp b/tools/src/librw11/Rw11VirtTapeTap.ipp new file mode 100644 index 00000000..c5c6d402 --- /dev/null +++ b/tools/src/librw11/Rw11VirtTapeTap.ipp @@ -0,0 +1,56 @@ +// $Id: Rw11VirtTapeTap.ipp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-06-04 686 1.0 Initial version +// 2015-05-17 683 0.1 First draft +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11VirtTapeTap.ipp 686 2015-06-04 21:08:08Z mueller $ + \brief Implemenation (inline) of Rw11VirtTapeTap. +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline size_t Rw11VirtTapeTap::BytePadding(size_t rlen) +{ + return fPadOdd ? ((rlen+1) & 0xfffe) : rlen; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline bool Rw11VirtTapeTap::SetBad() +{ + fBad = true; + return false; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline void Rw11VirtTapeTap::IncPosRecord(int delta) +{ + if (fPosRecord != -1) fPosRecord += delta; + return; +} + + +} // end namespace Retro diff --git a/tools/src/librwxxtpp/Makefile b/tools/src/librwxxtpp/Makefile index d454a6a9..8837413e 100644 --- a/tools/src/librwxxtpp/Makefile +++ b/tools/src/librwxxtpp/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 664 2015-04-06 12:02:17Z mueller $ +# $Id: Makefile 683 2015-05-17 21:54:35Z mueller $ # # Revision History: # Date Rev Version Comment @@ -31,6 +31,7 @@ OBJ_all += RtclRw11Cntl.o RtclRw11CntlFactory.o OBJ_all += RtclRw11Unit.o OBJ_all += RtclRw11UnitTerm.o OBJ_all += RtclRw11UnitDisk.o +OBJ_all += RtclRw11UnitTape.o OBJ_all += RtclRw11UnitStream.o OBJ_all += RtclRw11CntlDL11.o RtclRw11UnitDL11.o OBJ_all += RtclRw11CntlLP11.o RtclRw11UnitLP11.o @@ -38,7 +39,8 @@ OBJ_all += RtclRw11CntlPC11.o RtclRw11UnitPC11.o OBJ_all += RtclRw11CntlRK11.o RtclRw11UnitRK11.o OBJ_all += RtclRw11CntlRL11.o RtclRw11UnitRL11.o OBJ_all += RtclRw11CntlRHRP.o RtclRw11UnitRHRP.o -# +OBJ_all += RtclRw11CntlTM11.o RtclRw11UnitTM11.o +# DEP_all = $(OBJ_all:.o=.dep) # #- generic part ---------------------------------------------------------------- diff --git a/tools/src/librwxxtpp/RtclRw11CntlFactory.cpp b/tools/src/librwxxtpp/RtclRw11CntlFactory.cpp index b3571a47..dbb71bf6 100644 --- a/tools/src/librwxxtpp/RtclRw11CntlFactory.cpp +++ b/tools/src/librwxxtpp/RtclRw11CntlFactory.cpp @@ -1,4 +1,4 @@ -// $Id: RtclRw11CntlFactory.cpp 664 2015-04-06 12:02:17Z mueller $ +// $Id: RtclRw11CntlFactory.cpp 683 2015-05-17 21:54:35Z mueller $ // // Copyright 2013-2015 by Walter F.J. Mueller // @@ -24,7 +24,7 @@ /*! \file - \version $Id: RtclRw11CntlFactory.cpp 664 2015-04-06 12:02:17Z mueller $ + \version $Id: RtclRw11CntlFactory.cpp 683 2015-05-17 21:54:35Z mueller $ \brief Implemenation of global function RtclRw11CntlFactory. */ @@ -36,6 +36,7 @@ #include "RtclRw11CntlRK11.hpp" #include "RtclRw11CntlRL11.hpp" #include "RtclRw11CntlRHRP.hpp" +#include "RtclRw11CntlTM11.hpp" #include "RtclRw11CntlLP11.hpp" #include "RtclRw11CntlPC11.hpp" @@ -73,6 +74,11 @@ int RtclRw11CntlFactory(RtclArgs& args, RtclRw11Cpu& cpu) if(pobj->FactoryCmdConfig(args, cpu) != TCL_OK) return TCL_ERROR; pobj.release(); + } else if (type == "tm11") { // tm11 -------------------------- + unique_ptr pobj(new RtclRw11CntlTM11()); + if(pobj->FactoryCmdConfig(args, cpu) != TCL_OK) return TCL_ERROR; + pobj.release(); + } else if (type == "lp11") { // lp11 -------------------------- unique_ptr pobj(new RtclRw11CntlLP11()); if(pobj->FactoryCmdConfig(args, cpu) != TCL_OK) return TCL_ERROR; diff --git a/tools/src/librwxxtpp/RtclRw11CntlTM11.cpp b/tools/src/librwxxtpp/RtclRw11CntlTM11.cpp new file mode 100644 index 00000000..7816e45a --- /dev/null +++ b/tools/src/librwxxtpp/RtclRw11CntlTM11.cpp @@ -0,0 +1,112 @@ +// $Id: RtclRw11CntlTM11.cpp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-17 683 1.0 Initial version +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: RtclRw11CntlTM11.cpp 686 2015-06-04 21:08:08Z mueller $ + \brief Implemenation of RtclRw11CntlTM11. +*/ + +#include "librtcltools/RtclNameSet.hpp" + +#include "RtclRw11CntlTM11.hpp" +#include "RtclRw11UnitTM11.hpp" + +using namespace std; + +/*! + \class Retro::RtclRw11CntlTM11 + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! Constructor + +RtclRw11CntlTM11::RtclRw11CntlTM11() + : RtclRw11CntlBase("Rw11CntlTM11") +{ + Rw11CntlTM11* pobj = &Obj(); + fGets.Add ("chunksize", + boost::bind(&Rw11CntlTM11::ChunkSize, pobj)); + fSets.Add ("chunksize", + boost::bind(&Rw11CntlTM11::SetChunkSize, pobj, _1)); +} + +//------------------------------------------+----------------------------------- +//! Destructor + +RtclRw11CntlTM11::~RtclRw11CntlTM11() +{} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +int RtclRw11CntlTM11::FactoryCmdConfig(RtclArgs& args, RtclRw11Cpu& cpu) +{ + static RtclNameSet optset("-base|-lam"); + + string cntlname(cpu.Obj().NextCntlName("tm")); + string cntlcmd = cpu.CommandName() + cntlname; + + uint16_t base = Rw11CntlTM11::kIbaddr; + int lam = Rw11CntlTM11::kLam; + + string opt; + while (args.NextOpt(opt, optset)) { + if (opt == "-base") { + if (!args.GetArg("base", base, 0177776, 0160000)) return kERR; + } else if (opt == "-lam") { + if (!args.GetArg("lam", lam, 0, 15)) return kERR; + } + } + if (!args.AllDone()) return kERR; + + // configure controller + Obj().Config(cntlname, base, lam); + + // install in CPU + cpu.Obj().AddCntl(dynamic_pointer_cast(ObjSPtr())); + // finally create tcl command + CreateObjectCmd(args.Interp(), cntlcmd.c_str()); + + // and create unit commands + for (size_t i=0; i +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-17 683 1.0 Initial version +// --------------------------------------------------------------------------- + + +/*! + \file + \version $Id: RtclRw11CntlTM11.hpp 686 2015-06-04 21:08:08Z mueller $ + \brief Declaration of class RtclRw11CntlTM11. +*/ + +#ifndef included_Retro_RtclRw11CntlTM11 +#define included_Retro_RtclRw11CntlTM11 1 + +#include "RtclRw11CntlBase.hpp" +#include "librw11/Rw11CntlTM11.hpp" + +namespace Retro { + + class RtclRw11CntlTM11 : public RtclRw11CntlBase { + public: + RtclRw11CntlTM11(); + ~RtclRw11CntlTM11(); + + virtual int FactoryCmdConfig(RtclArgs& args, RtclRw11Cpu& cpu); + + protected: + virtual int M_stats(RtclArgs& args); + }; + +} // end namespace Retro + +//#include "RtclRw11CntlTM11.ipp" + +#endif diff --git a/tools/src/librwxxtpp/RtclRw11Cpu.cpp b/tools/src/librwxxtpp/RtclRw11Cpu.cpp index 2620ece4..76c0c95a 100644 --- a/tools/src/librwxxtpp/RtclRw11Cpu.cpp +++ b/tools/src/librwxxtpp/RtclRw11Cpu.cpp @@ -1,4 +1,4 @@ -// $Id: RtclRw11Cpu.cpp 675 2015-05-08 21:05:08Z mueller $ +// $Id: RtclRw11Cpu.cpp 682 2015-05-15 18:35:29Z mueller $ // // Copyright 2013-2015 by Walter F.J. Mueller // @@ -33,7 +33,7 @@ /*! \file - \version $Id: RtclRw11Cpu.cpp 675 2015-05-08 21:05:08Z mueller $ + \version $Id: RtclRw11Cpu.cpp 682 2015-05-15 18:35:29Z mueller $ \brief Implemenation of RtclRw11Cpu. */ @@ -1125,7 +1125,7 @@ int RtclRw11Cpu::M_ldasm(RtclArgs& args) if (!Rtcl::SetVar(interp, varlst, Rtcl::NewLinesObj(los))) return kERR; } - // now, finally, iterate of cmap and write code to memory + // now, finally, iterate over cmap and write code to memory vector block; uint16_t base = 0; diff --git a/tools/src/librwxxtpp/RtclRw11UnitTM11.cpp b/tools/src/librwxxtpp/RtclRw11UnitTM11.cpp new file mode 100644 index 00000000..fc895576 --- /dev/null +++ b/tools/src/librwxxtpp/RtclRw11UnitTM11.cpp @@ -0,0 +1,55 @@ +// $Id: RtclRw11UnitTM11.cpp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-17 683 1.0 Initial version +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: RtclRw11UnitTM11.cpp 686 2015-06-04 21:08:08Z mueller $ + \brief Implemenation of RtclRw11UnitTM11. +*/ + +#include "RtclRw11UnitTM11.hpp" + +using namespace std; + +/*! + \class Retro::RtclRw11UnitTM11 + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! Constructor + +RtclRw11UnitTM11::RtclRw11UnitTM11( + Tcl_Interp* interp, const std::string& unitcmd, + const boost::shared_ptr& spunit) + : RtclRw11UnitBase("Rw11UnitTM11", spunit), + RtclRw11UnitTape(this, spunit.get()) +{ + CreateObjectCmd(interp, unitcmd.c_str()); +} + +//------------------------------------------+----------------------------------- +//! Destructor + +RtclRw11UnitTM11::~RtclRw11UnitTM11() +{} + +} // end namespace Retro diff --git a/tools/src/librwxxtpp/RtclRw11UnitTM11.hpp b/tools/src/librwxxtpp/RtclRw11UnitTM11.hpp new file mode 100644 index 00000000..cb0c39da --- /dev/null +++ b/tools/src/librwxxtpp/RtclRw11UnitTM11.hpp @@ -0,0 +1,52 @@ +// $Id: RtclRw11UnitTM11.hpp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-17 683 1.0 Initial version +// --------------------------------------------------------------------------- + + +/*! + \file + \version $Id: RtclRw11UnitTM11.hpp 686 2015-06-04 21:08:08Z mueller $ + \brief Declaration of class RtclRw11UnitTM11. +*/ + +#ifndef included_Retro_RtclRw11UnitTM11 +#define included_Retro_RtclRw11UnitTM11 1 + +#include "librw11/Rw11UnitTM11.hpp" +#include "librw11/Rw11CntlTM11.hpp" + +#include "RtclRw11UnitTape.hpp" +#include "RtclRw11UnitBase.hpp" + +namespace Retro { + + class RtclRw11UnitTM11 : public RtclRw11UnitBase, + public RtclRw11UnitTape { + public: + RtclRw11UnitTM11(Tcl_Interp* interp, + const std::string& unitcmd, + const boost::shared_ptr& spunit); + ~RtclRw11UnitTM11(); + + protected: + }; + +} // end namespace Retro + +//#include "RtclRw11UnitTM11.ipp" + +#endif diff --git a/tools/src/librwxxtpp/RtclRw11UnitTape.cpp b/tools/src/librwxxtpp/RtclRw11UnitTape.cpp new file mode 100644 index 00000000..88710448 --- /dev/null +++ b/tools/src/librwxxtpp/RtclRw11UnitTape.cpp @@ -0,0 +1,83 @@ +// $Id: RtclRw11UnitTape.cpp 686 2015-06-04 21:08:08Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-06-04 686 1.0 Initial version +// 2015-05-17 683 0.1 First draft +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: RtclRw11UnitTape.cpp 686 2015-06-04 21:08:08Z mueller $ + \brief Implemenation of RtclRw11UnitTape. +*/ + +using namespace std; + +#include "RtclRw11UnitTape.hpp" + +/*! + \class Retro::RtclRw11UnitTape + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! Constructor + +RtclRw11UnitTape::RtclRw11UnitTape(RtclRw11Unit* ptcl, Rw11UnitTape* pobj) + : fpTcl(ptcl), + fpObj(pobj) +{ + RtclGetList& gets = ptcl->GetList(); + RtclSetList& sets = ptcl->SetList(); + gets.Add ("type", + boost::bind(&Rw11UnitTape::Type, pobj)); + gets.Add ("wprot", + boost::bind(&Rw11UnitTape::WProt, pobj)); + gets.Add ("capacity", + boost::bind(&Rw11UnitTape::Capacity, pobj)); + gets.Add ("bot", + boost::bind(&Rw11UnitTape::Bot, pobj)); + gets.Add ("eot", + boost::bind(&Rw11UnitTape::Eot, pobj)); + gets.Add ("eom", + boost::bind(&Rw11UnitTape::Eom, pobj)); + gets.Add ("posfile", + boost::bind(&Rw11UnitTape::PosFile, pobj)); + gets.Add ("posrecord", + boost::bind(&Rw11UnitTape::PosRecord, pobj)); + + sets.Add ("type", + boost::bind(&Rw11UnitTape::SetType,pobj, _1)); + sets.Add ("wprot", + boost::bind(&Rw11UnitTape::SetWProt,pobj, _1)); + sets.Add ("capacity", + boost::bind(&Rw11UnitTape::SetCapacity,pobj, _1)); + sets.Add ("posfile", + boost::bind(&Rw11UnitTape::SetPosFile,pobj, _1)); + sets.Add ("posrecord", + boost::bind(&Rw11UnitTape::SetPosRecord,pobj, _1)); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +RtclRw11UnitTape::~RtclRw11UnitTape() +{} + + +} // end namespace Retro diff --git a/tools/src/librwxxtpp/RtclRw11UnitTape.hpp b/tools/src/librwxxtpp/RtclRw11UnitTape.hpp new file mode 100644 index 00000000..69669e16 --- /dev/null +++ b/tools/src/librwxxtpp/RtclRw11UnitTape.hpp @@ -0,0 +1,51 @@ +// $Id: RtclRw11UnitTape.hpp 683 2015-05-17 21:54:35Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-17 683 0.1 First draft +// --------------------------------------------------------------------------- + + +/*! + \file + \version $Id: RtclRw11UnitTape.hpp 683 2015-05-17 21:54:35Z mueller $ + \brief Declaration of class RtclRw11UnitTape. +*/ + +#ifndef included_Retro_RtclRw11UnitTape +#define included_Retro_RtclRw11UnitTape 1 + +#include "librw11/Rw11UnitTape.hpp" + +#include "RtclRw11Unit.hpp" + +namespace Retro { + + class RtclRw11UnitTape { + public: + RtclRw11UnitTape(RtclRw11Unit* ptcl, Rw11UnitTape* pobj); + ~RtclRw11UnitTape(); + + protected: + + protected: + RtclRw11Unit* fpTcl; + Rw11UnitTape* fpObj; + }; + +} // end namespace Retro + +//#include "RtclRw11UnitTape.ipp" + +#endif diff --git a/tools/tbench/all.dat b/tools/tbench/all.dat new file mode 100644 index 00000000..cfc5a507 --- /dev/null +++ b/tools/tbench/all.dat @@ -0,0 +1,7 @@ +# $Id: all.dat 683 2015-05-17 21:54:35Z mueller $ +# +## steering file for all tests +# +@cpu_all.dat +@dev_all.dat +# diff --git a/tools/tbench/cp/cp_all.dat b/tools/tbench/cp/cp_all.dat new file mode 100644 index 00000000..0d125fa5 --- /dev/null +++ b/tools/tbench/cp/cp_all.dat @@ -0,0 +1,10 @@ +# $Id: cp_all.dat 683 2015-05-17 21:54:35Z mueller $ +# +## steering file for all cp tests +# +test_cp_gpr.tcl +test_cp_psw.tcl +test_cp_membasics.tcl +test_cp_ibrbasics.tcl +test_cp_cpubasics.tcl +# diff --git a/tools/tbench/test_cp_cpubasics.tcl b/tools/tbench/cp/test_cp_cpubasics.tcl similarity index 98% rename from tools/tbench/test_cp_cpubasics.tcl rename to tools/tbench/cp/test_cp_cpubasics.tcl index 77edbc55..dbec036a 100644 --- a/tools/tbench/test_cp_cpubasics.tcl +++ b/tools/tbench/cp/test_cp_cpubasics.tcl @@ -1,4 +1,4 @@ -# $Id: test_cp_cpubasics.tcl 676 2015-05-09 16:31:54Z mueller $ +# $Id: test_cp_cpubasics.tcl 683 2015-05-17 21:54:35Z mueller $ # # Copyright 2013-2015 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory diff --git a/tools/tbench/test_cp_gpr.tcl b/tools/tbench/cp/test_cp_gpr.tcl similarity index 97% rename from tools/tbench/test_cp_gpr.tcl rename to tools/tbench/cp/test_cp_gpr.tcl index 76106b0d..94e13e0e 100644 --- a/tools/tbench/test_cp_gpr.tcl +++ b/tools/tbench/cp/test_cp_gpr.tcl @@ -1,4 +1,4 @@ -# $Id: test_cp_gpr.tcl 676 2015-05-09 16:31:54Z mueller $ +# $Id: test_cp_gpr.tcl 683 2015-05-17 21:54:35Z mueller $ # # Copyright 2013- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory diff --git a/tools/tbench/test_cp_ibrbasics.tcl b/tools/tbench/cp/test_cp_ibrbasics.tcl similarity index 97% rename from tools/tbench/test_cp_ibrbasics.tcl rename to tools/tbench/cp/test_cp_ibrbasics.tcl index 361d669d..81b5c615 100644 --- a/tools/tbench/test_cp_ibrbasics.tcl +++ b/tools/tbench/cp/test_cp_ibrbasics.tcl @@ -1,4 +1,4 @@ -# $Id: test_cp_ibrbasics.tcl 676 2015-05-09 16:31:54Z mueller $ +# $Id: test_cp_ibrbasics.tcl 683 2015-05-17 21:54:35Z mueller $ # # Copyright 2014- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory diff --git a/tools/tbench/test_cp_membasics.tcl b/tools/tbench/cp/test_cp_membasics.tcl similarity index 96% rename from tools/tbench/test_cp_membasics.tcl rename to tools/tbench/cp/test_cp_membasics.tcl index 68cf50f6..cfc212fc 100644 --- a/tools/tbench/test_cp_membasics.tcl +++ b/tools/tbench/cp/test_cp_membasics.tcl @@ -1,4 +1,4 @@ -# $Id: test_cp_membasics.tcl 676 2015-05-09 16:31:54Z mueller $ +# $Id: test_cp_membasics.tcl 683 2015-05-17 21:54:35Z mueller $ # # Copyright 2014- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory diff --git a/tools/tbench/test_cp_psw.tcl b/tools/tbench/cp/test_cp_psw.tcl similarity index 95% rename from tools/tbench/test_cp_psw.tcl rename to tools/tbench/cp/test_cp_psw.tcl index ea11b577..0eda53a5 100644 --- a/tools/tbench/test_cp_psw.tcl +++ b/tools/tbench/cp/test_cp_psw.tcl @@ -1,4 +1,4 @@ -# $Id: test_cp_psw.tcl 676 2015-05-09 16:31:54Z mueller $ +# $Id: test_cp_psw.tcl 683 2015-05-17 21:54:35Z mueller $ # # Copyright 2013-2014 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory diff --git a/tools/tbench/cpu_all.dat b/tools/tbench/cpu_all.dat new file mode 100644 index 00000000..82ff098d --- /dev/null +++ b/tools/tbench/cpu_all.dat @@ -0,0 +1,7 @@ +# $Id: cpu_all.dat 683 2015-05-17 21:54:35Z mueller $ +# +## steering file for all cpu tests +# +@cp/cp_all.dat +@w11a/w11a_all.dat +# diff --git a/tools/tbench/dev_all.dat b/tools/tbench/dev_all.dat new file mode 100644 index 00000000..1abdfbac --- /dev/null +++ b/tools/tbench/dev_all.dat @@ -0,0 +1,7 @@ +# $Id: dev_all.dat 687 2015-06-05 09:03:34Z mueller $ +# +## steering file for all devices tests +# +@rhrp/rhrp_all.dat +@tm11/tm11_all.dat +# diff --git a/tools/tbench/rhrp_all.dat b/tools/tbench/rhrp/rhrp_all.dat similarity index 68% rename from tools/tbench/rhrp_all.dat rename to tools/tbench/rhrp/rhrp_all.dat index 91757a04..52086e42 100644 --- a/tools/tbench/rhrp_all.dat +++ b/tools/tbench/rhrp/rhrp_all.dat @@ -1,4 +1,4 @@ -# $Id: rhrp_all.dat 668 2015-04-25 14:31:19Z mueller $ +# $Id: rhrp_all.dat 683 2015-05-17 21:54:35Z mueller $ # ## steering file for all rhrp tests # diff --git a/tools/tbench/test_rhrp_basics.tcl b/tools/tbench/rhrp/test_rhrp_basics.tcl similarity index 99% rename from tools/tbench/test_rhrp_basics.tcl rename to tools/tbench/rhrp/test_rhrp_basics.tcl index 24a0501d..539eed83 100644 --- a/tools/tbench/test_rhrp_basics.tcl +++ b/tools/tbench/rhrp/test_rhrp_basics.tcl @@ -1,4 +1,4 @@ -# $Id: test_rhrp_basics.tcl 667 2015-04-18 20:16:05Z mueller $ +# $Id: test_rhrp_basics.tcl 683 2015-05-17 21:54:35Z mueller $ # # Copyright 2015- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory diff --git a/tools/tbench/test_rhrp_func_reg.tcl b/tools/tbench/rhrp/test_rhrp_func_reg.tcl similarity index 98% rename from tools/tbench/test_rhrp_func_reg.tcl rename to tools/tbench/rhrp/test_rhrp_func_reg.tcl index c4ebc754..ea728225 100644 --- a/tools/tbench/test_rhrp_func_reg.tcl +++ b/tools/tbench/rhrp/test_rhrp_func_reg.tcl @@ -1,4 +1,4 @@ -# $Id: test_rhrp_func_reg.tcl 668 2015-04-25 14:31:19Z mueller $ +# $Id: test_rhrp_func_reg.tcl 683 2015-05-17 21:54:35Z mueller $ # # Copyright 2015- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory diff --git a/tools/tbench/test_rhrp_int.tcl b/tools/tbench/rhrp/test_rhrp_int.tcl similarity index 99% rename from tools/tbench/test_rhrp_int.tcl rename to tools/tbench/rhrp/test_rhrp_int.tcl index 82439e33..c54db90e 100644 --- a/tools/tbench/test_rhrp_int.tcl +++ b/tools/tbench/rhrp/test_rhrp_int.tcl @@ -1,4 +1,4 @@ -# $Id: test_rhrp_int.tcl 678 2015-05-10 16:23:02Z mueller $ +# $Id: test_rhrp_int.tcl 683 2015-05-17 21:54:35Z mueller $ # # Copyright 2015- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory diff --git a/tools/tbench/test_rhrp_regs.tcl b/tools/tbench/rhrp/test_rhrp_regs.tcl similarity index 99% rename from tools/tbench/test_rhrp_regs.tcl rename to tools/tbench/rhrp/test_rhrp_regs.tcl index 00c12a7c..97a2e1ce 100644 --- a/tools/tbench/test_rhrp_regs.tcl +++ b/tools/tbench/rhrp/test_rhrp_regs.tcl @@ -1,4 +1,4 @@ -# $Id: test_rhrp_regs.tcl 678 2015-05-10 16:23:02Z mueller $ +# $Id: test_rhrp_regs.tcl 683 2015-05-17 21:54:35Z mueller $ # # Copyright 2015- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory diff --git a/tools/tbench/tm11/test_tm11_int.tcl b/tools/tbench/tm11/test_tm11_int.tcl new file mode 100644 index 00000000..2cbfe0b3 --- /dev/null +++ b/tools/tbench/tm11/test_tm11_int.tcl @@ -0,0 +1,162 @@ +# $Id: test_tm11_int.tcl 683 2015-05-17 21:54:35Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-05-17 683 1.0 Initial version +# +# Test interrupt response +# A: + +# ---------------------------------------------------------------------------- +rlc log "test_tm11_int: test interrupt response ------------------------------" +rlc log " setup: all units online" +package require ibd_tm11 +ibd_tm11::setup + +rlc set statmask $rw11::STAT_DEFMASK +rlc set statvalue 0 + +# configure drives +set rsronl [regbld ibd_tm11::RRL {onl 1} {bot 1}] +$cpu cp -wibr "tma.cr" [ibd_tm11::rcr_wunit 0] \ + -wibr "tma.rl" $rsronl \ + -wibr "tma.cr" [ibd_tm11::rcr_wunit 1] \ + -wibr "tma.rl" $rsronl \ + -wibr "tma.cr" [ibd_tm11::rcr_wunit 2] \ + -wibr "tma.rl" $rsronl \ + -wibr "tma.cr" [ibd_tm11::rcr_wunit 3] \ + -wibr "tma.rl" $rsronl + +# load test code +$cpu ldasm -lst lst -sym sym { + .include |lib/defs_cpu.mac| + .include |lib/defs_tm.mac| +; + .include |lib/vec_cpucatch.mac| +; + . = 000224 ; setup TM11 interrupt vector +v..tm: .word vh.tm + .word cp.pr7 +; + . = 1000 ; data area +stack: +ibuf: .blkw 3. ; input buffer +obuf: .blkw 5. ; output buffer +fbuf: .blkw 4. ; final buffer +; + . = 2000 ; code area +start: spl 7 ; lock out interrupts +; + mov #obuf,r0 ; clear obuf + clr (r0)+ + clr (r0)+ + clr (r0)+ + clr (r0)+ + clr (r0)+ +; + mov #ibuf,r0 ; setup regs from ibuf + mov (r0)+,@#tm.bc ; bc + mov (r0)+,@#tm.ba ; ba + mov (r0)+,@#tm.cr ; cr + spl 0 ; allow interrupts +; +poll: tstb @#tm.cr ; check cr + bpl poll ; if rdy=0 keep polling +; +4$: mov #fbuf,r0 ; store final regs in fbuf + mov @#tm.sr,(r0)+ ; sr + mov @#tm.cr,(r0)+ ; cr + mov @#tm.bc,(r0)+ ; bc + mov @#tm.ba,(r0)+ ; ba + + halt ; halt if done +stop: + +; TM11 interrupt handler +vh.tm: mov #obuf,r0 ; store regs in obuf + mov #1,(r0)+ ; flag + mov @#tm.sr,(r0)+ ; sr + mov @#tm.cr,(r0)+ ; cr + mov @#tm.bc,(r0)+ ; bc + mov @#tm.ba,(r0)+ ; ba + rti ; and return +} + +##puts $lst + +# define tmpproc for readback checks +proc tmpproc_dotest {cpu symName opts} { + upvar 1 $symName sym + + set tout 10.; # FIXME_code: parameter ?? + +# setup defs hash, first defaults, than write over concrete run values + array set defs { i.cr 0 \ + i.bc 0 \ + i.ba 0 \ + o.sr 0 \ + o.cr 0 \ + o.bc 0 \ + o.ba 0 \ + do.lam 0 + } + array set defs $opts + + # build ibuf + set ibuf [list $defs(i.bc) $defs(i.ba) $defs(i.cr)] + + # setup write ibuf, setup stack, and start cpu at start: + $cpu cp -wal $sym(ibuf) \ + -bwm $ibuf \ + -wsp $sym(stack) \ + -stapc $sym(start) + + # here do minimal lam handling (harvest + send DONE) + if {$defs(do.lam)} { + rlc wtlam $tout apat + $cpu cp -attn \ + -wibr tma.cs [ibd_rhrp::cr_func $ibd_tm11::RFUNC_DONE] + } + + $cpu wtcpu -reset $tout + + # determine regs after cleanup + $cpu cp -rpc -edata $sym(stop) \ + -rsp -edata $sym(stack) \ + -wal $sym(obuf) \ + -rmi -edata 1 \ + -rmi -edata $defs(o.sr) \ + -rmi -edata $defs(o.cr) \ + -rmi -edata $defs(o.bc) \ + -rmi -edata $defs(o.ba) \ + -wal $sym(fbuf) \ + -rmi -edata $defs(o.sr) \ + -rmi -edata $defs(o.cr) \ + -rmi -edata $defs(o.bc) \ + -rmi -edata $defs(o.ba) + + return "" +} + +# discard pending attn to be on save side +rlc wtlam 0. +rlc exec -attn + +# -- Section A --------------------------------------------------------------- +rlc log " A1.1 set cr.ie=1 -> software interrupt -------------" + +set opts [list \ + i.cr [regbld ibd_tm11::CR ie] \ + i.bc 0xff00 \ + i.ba 0x8800 \ + o.sr [regbld ibd_tm11::SR onl bot tur] \ + o.cr [regbld ibd_tm11::CR rdy ie] \ + o.bc 0xff00 \ + o.ba 0x8800 + ] + +tmpproc_dotest $cpu sym $opts + diff --git a/tools/tbench/tm11/test_tm11_regs.tcl b/tools/tbench/tm11/test_tm11_regs.tcl new file mode 100644 index 00000000..5b341970 --- /dev/null +++ b/tools/tbench/tm11/test_tm11_regs.tcl @@ -0,0 +1,175 @@ +# $Id: test_tm11_regs.tcl 683 2015-05-17 21:54:35Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-05-17 683 1.0 Initial version +# +# Test register response +# A: register basics + +# ---------------------------------------------------------------------------- +rlc log "test_tm11_regs: test register response ------------------------------" +package require ibd_tm11 +ibd_tm11::setup + +rlc set statmask $rw11::STAT_DEFMASK +rlc set statvalue 0 + +# -- Section A --------------------------------------------------------------- +rlc log " A1: test read ---------------------------------------------" +rlc log " A1.1: loc read sr,...,rl ---------------------------" + +$cpu cp -rma tma.sr \ + -rma tma.cr \ + -rma tma.bc \ + -rma tma.ba \ + -rma tma.db \ + -rma tma.rl + +rlc log " A1.2: rem read sr,...,rl ---------------------------" + +$cpu cp -ribr tma.sr \ + -ribr tma.cr \ + -ribr tma.bc \ + -ribr tma.ba \ + -ribr tma.db \ + -ribr tma.rl + +rlc log " A1.3: test that rl+2,+4 gives no ack (loc) ---------" + +set iaddr2 [expr {[cpu0 imap tma.rl] + 2}] +set iaddr4 [expr {[cpu0 imap tma.rl] + 4}] + +$cpu cp -ribr $iaddr2 -estaterr \ + -ribr $iaddr4 -estaterr + +# -- Section B --------------------------------------------------------------- +rlc log " B1: test sr setup -------------------------------------------------" + +rlc log " B1.1: rem write via rl -----------------------------" +# setup units with eof=!u1 eot=!u0 onl=1 bot=u0 wrl=u1 +set rsr0 [regbld ibd_tm11::RRL {eof 1} {eot 1} {onl 1} {bot 0} {wrl 0} {unit 0}] +set rsr1 [regbld ibd_tm11::RRL {eof 1} {eot 0} {onl 1} {bot 1} {wrl 0} {unit 1}] +set rsr2 [regbld ibd_tm11::RRL {eof 0} {eot 1} {onl 1} {bot 0} {wrl 1} {unit 2}] +set rsr3 [regbld ibd_tm11::RRL {eof 0} {eot 0} {onl 1} {bot 1} {wrl 1} {unit 3}] +# on readback SR has tur=1 +set sr0 [regbld ibd_tm11::SR {eof 1} {eot 1} {onl 1} {bot 0} {wrl 0} {tur 1}] +set sr1 [regbld ibd_tm11::SR {eof 1} {eot 0} {onl 1} {bot 1} {wrl 0} {tur 1}] +set sr2 [regbld ibd_tm11::SR {eof 0} {eot 1} {onl 1} {bot 0} {wrl 1} {tur 1}] +set sr3 [regbld ibd_tm11::SR {eof 0} {eot 0} {onl 1} {bot 1} {wrl 1} {tur 1}] +set sr7 [regbld ibd_tm11::SR {tur 1}] + +$cpu cp -wibr "tma.cr" [ibd_tm11::rcr_wunit 0] \ + -wibr "tma.rl" $rsr0 \ + -wibr "tma.cr" [ibd_tm11::rcr_wunit 1] \ + -wibr "tma.rl" $rsr1 \ + -wibr "tma.cr" [ibd_tm11::rcr_wunit 2] \ + -wibr "tma.rl" $rsr2 \ + -wibr "tma.cr" [ibd_tm11::rcr_wunit 3] \ + -wibr "tma.rl" $rsr3 + +rlc log " B1.2: rem read via rl ------------------------------" + +$cpu cp -wibr "tma.cr" [ibd_tm11::rcr_wunit 0] \ + -ribr "tma.rl" -edata $rsr0 \ + -wibr "tma.cr" [ibd_tm11::rcr_wunit 1] \ + -ribr "tma.rl" -edata $rsr1 \ + -wibr "tma.cr" [ibd_tm11::rcr_wunit 2] \ + -ribr "tma.rl" -edata $rsr2 \ + -wibr "tma.cr" [ibd_tm11::rcr_wunit 3] \ + -ribr "tma.rl" -edata $rsr3 + +rlc log " B1.3: loc read via sr ------------------------------" + +$cpu cp -wma "tma.cr" [regbld ibd_tm11::CR {unit 0}]\ + -rma "tma.sr" -edata $sr0 \ + -wma "tma.cr" [regbld ibd_tm11::CR {unit 1}]\ + -rma "tma.sr" -edata $sr1 \ + -wma "tma.cr" [regbld ibd_tm11::CR {unit 2}]\ + -rma "tma.sr" -edata $sr2 \ + -wma "tma.cr" [regbld ibd_tm11::CR {unit 3}]\ + -rma "tma.sr" -edata $sr3 + +rlc log " B1.4: ensure unit 4,..,7 signal offline ------------" + +$cpu cp -wma "tma.cr" [regbld ibd_tm11::CR {unit 4}]\ + -rma "tma.sr" -edata $sr7 \ + -wma "tma.cr" [regbld ibd_tm11::CR {unit 5}]\ + -rma "tma.sr" -edata $sr7 \ + -wma "tma.cr" [regbld ibd_tm11::CR {unit 6}]\ + -rma "tma.sr" -edata $sr7 \ + -wma "tma.cr" [regbld ibd_tm11::CR {unit 7}]\ + -rma "tma.sr" -edata $sr7 + +rlc log " B1.5: setup unit 0:3 as onl=1 bot=1 ----------------" + +# use use ONL=1 BOT=1 for all units -> no error flags +set rsr0 [regbld ibd_tm11::RRL {onl 1} {bot 1} {unit 0}] +set rsr1 [regbld ibd_tm11::RRL {onl 1} {bot 1} {unit 1}] +set rsr2 [regbld ibd_tm11::RRL {onl 1} {bot 1} {unit 2}] +set rsr3 [regbld ibd_tm11::RRL {onl 1} {bot 1} {unit 3}] +# on readback SR has tur=1 +set sr0 [regbld ibd_tm11::SR {onl 1} {bot 1} {tur 1}] +set sr1 [regbld ibd_tm11::SR {onl 1} {bot 1} {tur 1}] +set sr2 [regbld ibd_tm11::SR {onl 1} {bot 1} {tur 1}] +set sr3 [regbld ibd_tm11::SR {onl 1} {bot 1} {tur 1}] +$cpu cp -wibr "tma.cr" [ibd_tm11::rcr_wunit 0] \ + -wibr "tma.rl" $rsr0 \ + -wibr "tma.cr" [ibd_tm11::rcr_wunit 1] \ + -wibr "tma.rl" $rsr1 \ + -wibr "tma.cr" [ibd_tm11::rcr_wunit 2] \ + -wibr "tma.rl" $rsr2 \ + -wibr "tma.cr" [ibd_tm11::rcr_wunit 3] \ + -wibr "tma.rl" $rsr3 + +rlc log " B2.1: loc write loc/rem read of cr -----------------" +# test all cr fields except ie and go (no interrupts and functions yet) +set crlist [list \ + [regbld ibd_tm11::CR {den 0} {pevn 0} {unit 0} {ea 0} {func 0}] \ + [regbld ibd_tm11::CR {den 3} {pevn 0} {unit 0} {ea 0} {func 0}] \ + [regbld ibd_tm11::CR {den 3} {pevn 1} {unit 0} {ea 0} {func 0}] \ + [regbld ibd_tm11::CR {den 3} {pevn 1} {unit 7} {ea 0} {func 0}] \ + [regbld ibd_tm11::CR {den 3} {pevn 1} {unit 3} {ea 3} {func 0}] \ + [regbld ibd_tm11::CR {den 3} {pevn 1} {unit 3} {ea 3} {func 7}] \ + ] + +foreach cr $crlist { + # on cr read here always rdy=1 + set crread [expr {$cr | [regbld ibd_tm11::CR {rdy 1}] } ] + $cpu cp -wma "tma.cr" $cr \ + -rma "tma.cr" -edata $crread \ + -ribr "tma.cr" -edata $crread +} + +rlc log " B3.1: loc write loc/rem read for bc,ba -------------" +# Note: ba ignores bit 0, only word addresses +$cpu cp -wma "tma.bc" 0x0010 \ + -wma "tma.ba" 0x0020 \ + -rma "tma.bc" -edata 0x0010 \ + -rma "tma.ba" -edata 0x0020 \ + -ribr "tma.bc" -edata 0x0010 \ + -ribr "tma.ba" -edata 0x0020 +$cpu cp -wma "tma.bc" 0x8888 \ + -wma "tma.ba" 0x7777 \ + -rma "tma.bc" -edata 0x8888 \ + -rma "tma.ba" -edata 0x7776 \ + -ribr "tma.bc" -edata 0x8888 \ + -ribr "tma.ba" -edata 0x7776 + +rlc log " B3.2: rem write loc/rem read for bc,ba -------------" + +$cpu cp -wibr "tma.bc" 0x1234 \ + -wibr "tma.ba" 0x4321 \ + -rma "tma.bc" -edata 0x1234 \ + -rma "tma.ba" -edata 0x4320 \ + -ribr "tma.bc" -edata 0x1234 \ + -ribr "tma.ba" -edata 0x4320 +$cpu cp -wibr "tma.bc" 0x0000 \ + -wibr "tma.ba" 0x0000 \ + -rma "tma.bc" -edata 0x0000 \ + -rma "tma.ba" -edata 0x0000 \ + -ribr "tma.bc" -edata 0x0000 \ + -ribr "tma.ba" -edata 0x0000 diff --git a/tools/tbench/tm11/tm11_all.dat b/tools/tbench/tm11/tm11_all.dat new file mode 100644 index 00000000..bb849195 --- /dev/null +++ b/tools/tbench/tm11/tm11_all.dat @@ -0,0 +1,6 @@ +# $Id: tm11_all.dat 683 2015-05-17 21:54:35Z mueller $ +# +## steering file for all tm11 tests +# +test_tm11_regs.tcl +test_tm11_int.tcl diff --git a/tools/tbench/test_w11a_div.tcl b/tools/tbench/w11a/test_w11a_div.tcl similarity index 99% rename from tools/tbench/test_w11a_div.tcl rename to tools/tbench/w11a/test_w11a_div.tcl index 4ab1d29f..bf8aca0f 100644 --- a/tools/tbench/test_w11a_div.tcl +++ b/tools/tbench/w11a/test_w11a_div.tcl @@ -1,4 +1,4 @@ -# $Id: test_w11a_div.tcl 575 2014-07-27 20:55:41Z mueller $ +# $Id: test_w11a_div.tcl 683 2015-05-17 21:54:35Z mueller $ # # Copyright 2014- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory diff --git a/tools/tbench/test_w11a_dsta_flow.tcl b/tools/tbench/w11a/test_w11a_dsta_flow.tcl similarity index 98% rename from tools/tbench/test_w11a_dsta_flow.tcl rename to tools/tbench/w11a/test_w11a_dsta_flow.tcl index 43f431b5..69fed016 100644 --- a/tools/tbench/test_w11a_dsta_flow.tcl +++ b/tools/tbench/w11a/test_w11a_dsta_flow.tcl @@ -1,4 +1,4 @@ -# $Id: test_w11a_dsta_flow.tcl 575 2014-07-27 20:55:41Z mueller $ +# $Id: test_w11a_dsta_flow.tcl 683 2015-05-17 21:54:35Z mueller $ # # Copyright 2013-2014 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory diff --git a/tools/tbench/test_w11a_dstm_word_flow.tcl b/tools/tbench/w11a/test_w11a_dstm_word_flow.tcl similarity index 97% rename from tools/tbench/test_w11a_dstm_word_flow.tcl rename to tools/tbench/w11a/test_w11a_dstm_word_flow.tcl index 2b09cc76..c912e8b2 100644 --- a/tools/tbench/test_w11a_dstm_word_flow.tcl +++ b/tools/tbench/w11a/test_w11a_dstm_word_flow.tcl @@ -1,4 +1,4 @@ -# $Id: test_w11a_dstm_word_flow.tcl 575 2014-07-27 20:55:41Z mueller $ +# $Id: test_w11a_dstm_word_flow.tcl 683 2015-05-17 21:54:35Z mueller $ # # Copyright 2013-2014 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory diff --git a/tools/tbench/test_w11a_dstw_word_flow.tcl b/tools/tbench/w11a/test_w11a_dstw_word_flow.tcl similarity index 97% rename from tools/tbench/test_w11a_dstw_word_flow.tcl rename to tools/tbench/w11a/test_w11a_dstw_word_flow.tcl index 2c9c0371..f18b5ac1 100644 --- a/tools/tbench/test_w11a_dstw_word_flow.tcl +++ b/tools/tbench/w11a/test_w11a_dstw_word_flow.tcl @@ -1,4 +1,4 @@ -# $Id: test_w11a_dstw_word_flow.tcl 575 2014-07-27 20:55:41Z mueller $ +# $Id: test_w11a_dstw_word_flow.tcl 683 2015-05-17 21:54:35Z mueller $ # # Copyright 2013-2014 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory diff --git a/tools/tbench/test_w11a_inst_traps.tcl b/tools/tbench/w11a/test_w11a_inst_traps.tcl similarity index 97% rename from tools/tbench/test_w11a_inst_traps.tcl rename to tools/tbench/w11a/test_w11a_inst_traps.tcl index f862501e..111e3267 100644 --- a/tools/tbench/test_w11a_inst_traps.tcl +++ b/tools/tbench/w11a/test_w11a_inst_traps.tcl @@ -1,4 +1,4 @@ -# $Id: test_w11a_inst_traps.tcl 575 2014-07-27 20:55:41Z mueller $ +# $Id: test_w11a_inst_traps.tcl 683 2015-05-17 21:54:35Z mueller $ # # Copyright 2013-2014 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory diff --git a/tools/tbench/test_w11a_srcr_word_flow.tcl b/tools/tbench/w11a/test_w11a_srcr_word_flow.tcl similarity index 98% rename from tools/tbench/test_w11a_srcr_word_flow.tcl rename to tools/tbench/w11a/test_w11a_srcr_word_flow.tcl index 7eca1111..fa159a89 100644 --- a/tools/tbench/test_w11a_srcr_word_flow.tcl +++ b/tools/tbench/w11a/test_w11a_srcr_word_flow.tcl @@ -1,4 +1,4 @@ -# $Id: test_w11a_srcr_word_flow.tcl 575 2014-07-27 20:55:41Z mueller $ +# $Id: test_w11a_srcr_word_flow.tcl 683 2015-05-17 21:54:35Z mueller $ # # Copyright 2013- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory diff --git a/tools/tbench/w11a_all.dat b/tools/tbench/w11a/w11a_all.dat similarity index 56% rename from tools/tbench/w11a_all.dat rename to tools/tbench/w11a/w11a_all.dat index a60b8a6c..8e6a35e5 100644 --- a/tools/tbench/w11a_all.dat +++ b/tools/tbench/w11a/w11a_all.dat @@ -1,12 +1,7 @@ -# $Id: w11a_all.dat 569 2014-07-13 14:36:32Z mueller $ +# $Id: w11a_all.dat 683 2015-05-17 21:54:35Z mueller $ # ## steering file for all w11a tests # -test_cp_gpr.tcl -test_cp_psw.tcl -test_cp_membasics.tcl -test_cp_ibrbasics.tcl -test_cp_cpubasics.tcl test_w11a_srcr_word_flow.tcl test_w11a_dstw_word_flow.tcl test_w11a_dstm_word_flow.tcl diff --git a/tools/tcl/ibd_tm11/.cvsignore b/tools/tcl/ibd_tm11/.cvsignore new file mode 100644 index 00000000..fc959ab2 --- /dev/null +++ b/tools/tcl/ibd_tm11/.cvsignore @@ -0,0 +1 @@ +pkgIndex.tcl diff --git a/tools/tcl/ibd_tm11/util.tcl b/tools/tcl/ibd_tm11/util.tcl new file mode 100644 index 00000000..36bcd81c --- /dev/null +++ b/tools/tcl/ibd_tm11/util.tcl @@ -0,0 +1,113 @@ +# $Id: $ +# +# Copyright 2015- by Walter F.J. Mueller +# +# This program is free software; you may redistribute and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation, either version 2, or at your option any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for complete details. +# +# Revision History: +# Date Rev Version Comment +# 2015-05-17 683 1.0 Initial version +# + +package provide ibd_tm11 1.0 + +package require rlink +package require rw11 + +namespace eval ibd_tm11 { + # + # setup register descriptions for ibd_tm11 --------------------------------- + # + + regdsc SR {icmd 15} {eof 14} {pae 12} {eot 10} {rle 9} {bte 8} {nxm 7} \ + {onl 6} {bot 5} {wrl 2} {rew 1} {tur 0} + + regdsc CR {err 15} {den 14 2} {ini 12} {pevn 11} {unit 10 3} \ + {rdy 7} {ie 6} {ea 5 2} {func 3 3} {go 0} + variable FUNC_UNLOAD [bvi b3 "000"] + variable FUNC_READ [bvi b3 "001"] + variable FUNC_WRITE [bvi b3 "010"] + variable FUNC_WEOF [bvi b3 "011"] + variable FUNC_SFORW [bvi b3 "100"] + variable FUNC_SBACK [bvi b3 "101"] + variable FUNC_WRTEG [bvi b3 "110"] + variable FUNC_REWIND [bvi b3 "111"] + + regdsc RCR {icmd 15} {pae 12} {rle 9} {bte 8} {nxm 7} \ + {unit 5 2} {func 3 3} {go 0} + variable RFUNC_WUNIT [bvi b3 "001"] + variable RFUNC_DONE [bvi b3 "010"] + + regdsc RRL {eof 10} {eot 9} {onl 8} {bot 7} {wrl 6} {rew 5} {unit 2 2} + + variable ANUM 7 + + # + # setup: create controller with default attributes ------------------------- + # + proc setup {{cpu "cpu0"}} { + return [rw11::setup_cntl $cpu "tm11" "tma"] + } + + # + # rcr_wunit: value for rem CR WUNIT function ----------------------------- + # + proc rcr_wunit {unit} { + return [regbld ibd_tm11::RCR [list unit $unit] \ + [list func $ibd_tm11::RFUNC_WUNIT] ] + } + + # + # cr_func: value for loc CR function start ------------------------------- + # + proc cr_func {func} { + return [regbld ibd_tm11::CR \ + [list func $func] {go 1}] + } + + # + # rdump: register dump - rem view ------------------------------------------ + # + proc rdump {{cpu "cpu0"}} { + set rval {} + $cpu cp -ribr "tma.sr" sr \ + -ribr "tma.cr" cr \ + -ribr "tma.bc" bc \ + -ribr "tma.ba" ba \ + -wibr "tma.cr" [rcr_wunit 0] \ + -ribr "tma.rl" sr0 \ + -wibr "tma.cr" [rcr_wunit 1] \ + -ribr "tma.rl" sr1 \ + -wibr "tma.cr" [rcr_wunit 2] \ + -ribr "tma.rl" sr2 \ + -wibr "tma.cr" [rcr_wunit 3] \ + -ribr "tma.rl" sr3 \ + + if {$bc} { + set fbc [format "%d" [expr {64 * 1024 - $bc}]] + } else { + set fbc "(0)" + } + + append rval "Controller registers:" + append rval [format "\n sr: %6.6o %s" $sr [regtxt ibd_tm11::SR $sr]] + append rval [format "\n cr: %6.6o %s" $cr [regtxt ibd_tm11::CR $cr]] + append rval [format "\n bc: %6.6o nw=%s" $bc $fbc] + append rval [format "\n ba: %6.6o" $ba] + + append rval "\nUnit registers:" + append rval [format "\n sr0: %6.6o %s" $sr0 [regtxt ibd_tm11::RRL $sr0 ]] + append rval [format "\n sr1: %6.6o %s" $sr1 [regtxt ibd_tm11::RRL $sr1 ]] + append rval [format "\n sr2: %6.6o %s" $sr2 [regtxt ibd_tm11::RRL $sr2 ]] + append rval [format "\n sr3: %6.6o %s" $sr3 [regtxt ibd_tm11::RRL $sr3 ]] + + return $rval + } +} diff --git a/tools/tcl/rw11/tbench.tcl b/tools/tcl/rw11/tbench.tcl index 86ca8fa2..d010fc37 100644 --- a/tools/tcl/rw11/tbench.tcl +++ b/tools/tcl/rw11/tbench.tcl @@ -1,4 +1,4 @@ -# $Id: tbench.tcl 676 2015-05-09 16:31:54Z mueller $ +# $Id: tbench.tcl 683 2015-05-17 21:54:35Z mueller $ # # Copyright 2013-2015 by Walter F.J. Mueller # @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-05-17 683 2.2 support sub directories and return in tests # 2015-05-09 676 2.1 use 'rlc log -bare' instead of 'puts' # 2014-11-30 607 2.0 use new rlink v4 iface # 2013-04-26 510 1.0 Initial version (extracted from util.tcl) @@ -28,45 +29,97 @@ namespace eval rw11 { # # tbench: driver for tbench scripts # - proc tbench {fname} { + proc tbench {tname} { + set fname $tname + set tbase "." + if {[string match "@*" $tname]} { + set fname [string range $tname 1 end] + } + if {![file exists $fname]} {set tbase "$::env(RETROBASE)/tools/tbench"} + rlink::anena 1; # enable attn notify - set errcnt [tbench_list $fname] + set errcnt [tbench_list $tname $tbase] return $errcnt } # # tbench_file: execute list of tbench steps # - proc tbench_list {lname} { + proc tbench_list {tname tbase} { set errcnt 0 - if {[string match "@*" $lname]} { - set fname [string range $lname 1 end] - set fh [open "$::env(RETROBASE)/tools/tbench/$fname"] + + set rname $tname + set islist 0 + if {[string match "@*" $tname]} { + set islist 1 + set rname [string range $tname 1 end] + } + + set dname [file dirname $rname] + set fname [file tail $rname] + if {$dname ne "."} { + set tbase [file join $tbase $dname] + } + + if {![file readable "$tbase/$fname"]} { + error "-E: file $tbase/$fname not found or readable" + } + + if {$islist} { + set fh [open "$tbase/$fname"] while {[gets $fh line] >= 0} { if {[string match "#*" $line]} { if {[string match "##*" $line]} { rlc log -bare $line } } elseif {[string match "@*" $line]} { - incr errcnt [tbench_list $line] + incr errcnt [tbench_list $line $tbase] } else { - incr errcnt [tbench_step $line] + incr errcnt [tbench_step $line $tbase] } } close $fh + } else { - incr errcnt [tbench_step $lname] + incr errcnt [tbench_step $fname $tbase] + } + + if {$islist} { + rlc log -bare [format "%s: %s" $tname [rutil::errcnt2txt $errcnt]] } - rlc log -bare [format "%s: %s" $lname [rutil::errcnt2txt $errcnt]] return $errcnt } # # tbench_step: execute single tbench step # - proc tbench_step {fname} { + proc tbench_step {fname tbase} { + if {![file readable "$tbase/$fname"]} { + error "-E: file $tbase/$fname not found or readable" + } + + # cleanup any remaining temporary procs with names tmpproc_* + foreach pname [info procs tmpproc_*] { rename $pname "" } + rlc errcnt -clear - set cpu cpu0 - source "$::env(RETROBASE)/tools/tbench/$fname" + set cpu "cpu0" + set ecode [catch "source $tbase/$fname" resmsg] set errcnt [rlc errcnt] + + switch $ecode { + 0 {} + 1 { puts "-E: test execution FAILED with error message:" + if {[info exists errorInfo]} {puts $errorInfo} else {puts $resmsg} + incr errcnt + } + 2 { puts "-I: test ended by return: $resmsg"} + default { + puts "-E: test execution FAILED with catch code $ecode" + incr errcnt + } + } + + # remove temporary procs with names tmpproc_* + foreach pname [info procs tmpproc_*] { rename $pname "" } + rlc log -bare [format "%s: %s" $fname [rutil::errcnt2txt $errcnt]] return $errcnt } diff --git a/tools/tcl/rw11/util.tcl b/tools/tcl/rw11/util.tcl index ac547693..e8dc3db2 100644 --- a/tools/tcl/rw11/util.tcl +++ b/tools/tcl/rw11/util.tcl @@ -1,4 +1,4 @@ -# $Id: util.tcl 675 2015-05-08 21:05:08Z mueller $ +# $Id: util.tcl 683 2015-05-17 21:54:35Z mueller $ # # Copyright 2013-2015 by Walter F.J. Mueller # @@ -13,6 +13,8 @@ # # Revision History: # Date Rev Version Comment +# 2015-05-17 683 1.3.4 setup_sys: add TM11 +# 2015-05-15 682 1.3.3 BUGFIX: setup_cpu: fix cpu reset (now -stop -creset) # 2015-05-08 675 1.3.2 w11a start/stop/suspend overhaul # 2015-03-28 660 1.3.1 add setup_cntl # 2015-03-21 659 1.3 setup_sys: add RPRM (later renamed to RHRP) @@ -52,7 +54,7 @@ namespace eval rw11 { rlc set basestat 2 rlink::setup; # basic rlink defs rw11 rlw rls w11a 1; # create 1 w11a cpu - cpu0 cp -creset; # reset CPU + cpu0 cp -stop -creset; # stop and reset CPU return "" } @@ -68,6 +70,7 @@ namespace eval rw11 { cpu0 add rk11 cpu0 add rl11 cpu0 add rhrp + cpu0 add tm11 cpu0 add lp11 cpu0 add pc11 rlw start diff --git a/tools/tcl/setup_packages b/tools/tcl/setup_packages index 801c7dca..bfa63eef 100755 --- a/tools/tcl/setup_packages +++ b/tools/tcl/setup_packages @@ -1,5 +1,5 @@ #! /usr/bin/env tclshcpp -# $Id: setup_packages 668 2015-04-25 14:31:19Z mueller $ +# $Id: setup_packages 683 2015-05-17 21:54:35Z mueller $ # pkg_mkIndex -verbose ../lib \ librlinktpp.so \ @@ -19,5 +19,6 @@ pkg_mkIndex -verbose rw11 *.tcl # pkg_mkIndex -verbose ibd_ibmon *.tcl pkg_mkIndex -verbose ibd_rhrp *.tcl +pkg_mkIndex -verbose ibd_tm11 *.tcl # pkg_mkIndex -verbose tst_rlink *.tcl