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ibdr_{pc11,dl11}: changes for buffered version compat

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- ibdr_dl11
  - now xbuf.val in bit 15 and 8;
  - use rbuf instead xbuf for rdry reporting
  - remove maintenance mode
  - use ib_rlim_slv; add RLIM_CEV, drop CE_USEC
- ibdr_pc11
  - pbuf.pval in bit 15 and 8
  - move rbusy reporting from pbuf to rbuf register
- ibdr_maxisys,ibdr_minisys: adapt to new ibdr_dl11 iface
- tb_rlink_tba_pdp11core_ibdr.dat: adapt to new ibdr_dl11 iface
- tcl/rw11/util.tcl: setup_tt: rename dlrlim to dlrrlim
- oskit/*/*_boot.tcl: use dlrrlim instead of dlrlim
- Rw11CntlDL11,Rw11CntlPC11: adapt to new dl11,pc11 iface
- tools/asm-11/lib/defs_{dl,pc}.mac: added definition file
- tools/oskit/hook/hook_ibmon_{pca,tta}.tcl: added imon hook file
This commit is contained in:
wfjm
2019-04-07 15:43:27 +02:00
parent 895755ef72
commit 2ae1055ee5
27 changed files with 351 additions and 192 deletions
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5
rtl/ibus/ibdlib.vhd
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@@ -1,4 +1,4 @@
-- $Id: ibdlib.vhd 1123 2019-03-17 17:55:12Z mueller $
-- $Id: ibdlib.vhd 1128 2019-04-07 13:12:47Z mueller $
--
-- Copyright 2008-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -19,6 +19,7 @@
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-07 1128 1.3.4 ibdr_dl11: use RLIM_CEV, drop CE_USEC
-- 2019-03-09 1121 1.3.3 add ibdr_lp11_buf
-- 2018-10-13 1055 1.3.2 update ibdr_maxisys (add IDEC port)
-- 2018-09-08 1043 1.3.1 update ibd_kw11p
@@ -224,9 +225,9 @@ component ibdr_dl11 is -- ibus dev(rem): DL11-A/B
IB_ADDR : slv16 := ibaddr_dl11);
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RLIM_CEV : in slv7; -- clock enable vector
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response

2
rtl/ibus/ibdr_dl11.vbom
View File

@@ -1,5 +1,7 @@
# libs
../vlib/slvtypes.vhd
iblib.vhd
# components
ib_rlim_slv.vbom
# design
ibdr_dl11.vhd

148
rtl/ibus/ibdr_dl11.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibdr_dl11.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: ibdr_dl11.vhd 1128 2019-04-07 13:12:47Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -15,10 +15,10 @@
-- Module Name: ibdr_dl11 - syn
-- Description: ibus dev(rem): DL11-A/B
--
-- Dependencies: -
-- Dependencies: ib_rlim_slv
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
-- Tool versions: ise 8.2-14.7; viv 2017.2; ghdl 0.18-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -28,6 +28,9 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-07 1127 1.3 for dl11_buf compat: xbuf.val in bit 15 and 8;
-- use rbuf instead xbuf for rdry reporting; remove
-- maintenance mode; use ib_rlim_slv; drop CE_USEC
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
@@ -56,9 +59,9 @@ entity ibdr_dl11 is -- ibus dev(rem): DL11-A/B
IB_ADDR : slv16 := slv(to_unsigned(8#177560#,16)));
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RLIM_CEV : in slv7; -- clock enable vector
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
@@ -80,12 +83,13 @@ architecture syn of ibdr_dl11 is
constant rcsr_ibf_rdone : integer := 7;
constant rcsr_ibf_rie : integer := 6;
constant rbuf_ibf_rrdy : integer := 15;
constant xcsr_ibf_xrdy : integer := 7;
constant xcsr_ibf_xie : integer := 6;
constant xcsr_ibf_xmaint: integer := 2;
constant xbuf_ibf_xval : integer := 8;
constant xbuf_ibf_rrdy : integer := 9;
constant xbuf_ibf_xval : integer := 15;
constant xbuf_ibf_xval8 : integer := 8;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
@@ -95,11 +99,8 @@ architecture syn of ibdr_dl11 is
rbuf : slv8; -- rbuf:
rval : slbit; -- rx rbuf valid
rintreq : slbit; -- rx interrupt request
rdlybsy : slbit; -- rx delay busy
rdlycnt : slv10; -- rx delay counter
xrdy : slbit; -- xcsr: transmitter ready
xie : slbit; -- xcsr: transmitter interrupt enable
xmaint : slbit; -- xcsr: maintenance mode
xbuf : slv8; -- xbuf:
xintreq : slbit; -- tx interrupt request
end record regs_type;
@@ -109,28 +110,40 @@ architecture syn of ibdr_dl11 is
(others=>'0'), -- rrlim
'0','0', -- rdone, rie
(others=>'0'), -- rbuf
'0','0','0', -- rval,rintreq,rdlybsy
(others=>'0'), -- rdlycnt
'0','0', -- rval,rintreq
'1', -- xrdy !! is set !!
'0','0', -- xie,xmaint
'0', -- xie
(others=>'0'), -- xbuf
'0' -- xintreq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal RRLIM_START : slbit := '0';
signal RRLIM_BUSY : slbit := '0';
begin
RRLIM : ib_rlim_slv
port map (
CLK => CLK,
RESET => RESET,
RLIM_CEV => RLIM_CEV,
SEL => R_REGS.rrlim,
START => RRLIM_START,
STOP => BRESET,
DONE => open,
BUSY => RRLIM_BUSY
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.rrlim <= N_REGS.rrlim; -- don't reset rx rate limit
R_REGS.rdlybsy <= N_REGS.rdlybsy; -- don't reset rx delay busy
R_REGS.rdlycnt <= N_REGS.rdlycnt; -- don't reset rx delay counter
R_REGS.rrlim <= N_REGS.rrlim; -- keep RLIM flag
end if;
else
R_REGS <= N_REGS;
@@ -138,7 +151,7 @@ begin
end if;
end process proc_regs;
proc_next : process (CE_USEC, R_REGS, IB_MREQ, EI_ACK_RX, EI_ACK_TX)
proc_next : process (R_REGS, IB_MREQ, EI_ACK_RX, EI_ACK_TX, RRLIM_BUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
@@ -147,8 +160,7 @@ begin
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
variable rdlystart : slbit := '0';
variable rdlyinit : slv10 := (others=>'0');
variable irrlimsta : slbit := '0';
begin
r := R_REGS;
@@ -160,7 +172,7 @@ begin
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
rdlystart := '0';
irrlimsta := '0';
-- ibus address decoder
n.ibsel := '0';
@@ -201,26 +213,17 @@ begin
idout(r.rbuf'range) := r.rbuf;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibrd = '1' then
n.rdone := '0'; -- clear DONE
if ibrd='1' and r.rdone='1' then
n.rval := '0'; -- clear rbuf valid
n.rintreq := '0'; -- clear pending interrupts
rdlystart := '1'; -- start rx delay counter
if r.xmaint = '0' then -- if not in loop-back
ilam := '1'; -- request rb attention
end if;
irrlimsta := '1'; -- start rx timer
ilam := '1'; -- request rb attention
end if;
else -- rri ---------------------
idout(rbuf_ibf_rrdy) := not r.rval;
if ibw0 = '1' then
n.rbuf := IB_MREQ.din(n.rbuf'range);
n.rval := '1'; -- set rbuf valid
if r.rdlybsy = '0' then -- if rdly timer not running
n.rdone := '1'; -- set DONE
if r.rie = '1' then -- if rx interrupt enabled
n.rintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
@@ -228,7 +231,6 @@ begin
idout(xcsr_ibf_xrdy) := r.xrdy;
idout(xcsr_ibf_xie) := r.xie;
idout(xcsr_ibf_xmaint):= r.xmaint;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
@@ -240,7 +242,6 @@ begin
else
n.xintreq := '0';
end if;
n.xmaint := IB_MREQ.din(xcsr_ibf_xmaint);
end if;
end if;
@@ -251,17 +252,13 @@ begin
n.xbuf := IB_MREQ.din(n.xbuf'range);
n.xrdy := '0';
n.xintreq := '0';
if r.xmaint = '0' then
ilam := '1';
end if;
ilam := '1';
end if;
else -- rri ---------------------
idout(r.xbuf'range) := r.xbuf;
if r.xmaint = '0' then -- if not in maintenace mode
idout(xbuf_ibf_xval) := not r.xrdy;
idout(xbuf_ibf_rrdy) := not r.rval;
end if;
idout(r.xbuf'range) := r.xbuf;
idout(xbuf_ibf_xval) := not r.xrdy;
idout(xbuf_ibf_xval8) := not r.xrdy;
if ibrd = '1' then
n.xrdy := '1';
if r.xie = '1' then
@@ -273,59 +270,10 @@ begin
when others => null;
end case;
else -- if unselected handle loop-back
if r.xmaint = '1' and -- if in maintenace mode
r.xrdy='0' and -- and transmit pending
r.rdone='0' and -- and receive buffer empty
r.rdlybsy='0' then -- and rdly timer not running
n.rbuf := r.xbuf; -- copy transmit to receive buffer
n.xrdy := '1'; -- mark transmit done
n.rdone := '1'; -- make receive done
if r.rie = '1' then -- if rx interrupt enabled
n.rintreq := '1'; -- request it
end if;
if r.xie = '1' then -- if tx interrupt enabled
n.xintreq := '1'; -- request it
end if;
end if;
end if;
-- other state changes
rdlyinit := (others=>'0');
case r.rrlim is
when "000" => rdlyinit := "0000000000"; -- rlim=0 -> disabled
when "001" => rdlyinit := "0000000011"; -- rlim=1 -> delay by 3+ usec
when "010" => rdlyinit := "0000001111"; -- rlim=2 -> delay by 15+ usec
when "011" => rdlyinit := "0000111111"; -- rlim=3 -> delay by 63+ usec
when "100" => rdlyinit := "0001111111"; -- rlim=4 -> delay by 127+ usec
when "101" => rdlyinit := "0011111111"; -- rlim=5 -> delay by 255+ usec
when "110" => rdlyinit := "0111111111"; -- rlim=6 -> delay by 511+ usec
when "111" => rdlyinit := "1111111111"; -- rlim=7 -> delay by 1023+ usec
when others => null;
end case;
if rdlystart = '1' then -- if rdly timer start requested
n.rdlycnt := rdlyinit; -- init counter
if r.rrlim /= "000" then -- rate limiter enabled ?
n.rdlybsy := '1'; -- set busy
end if;
elsif CE_USEC = '1' then -- if end-of-usec
n.rdlycnt := slv(unsigned(r.rdlycnt) - 1); -- decrement
if r.rdlybsy='1' and -- if delay busy
unsigned(r.rdlycnt) = 0 then -- and counter at zero
n.rdlybsy := '0'; -- clear busy
if n.rval = '1' then -- if rbuf is valid or is set
-- valid this cycle (use n.!!)
n.rdone := '1'; -- set DONE
if r.rie = '1' then -- if rx interrupt enabled
n.rintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
if EI_ACK_RX = '1' then
n.rintreq := '0';
end if;
@@ -333,7 +281,19 @@ begin
n.xintreq := '0';
end if;
if (RRLIM_BUSY or (not r.rval)) = '1' then -- busy or no data
n.rdone := '0'; -- clear done
n.rintreq := '0'; -- clear pending interrupts
else -- not busy and data valid
n.rdone := '1'; -- clear done
if r.rdone='0' and r.rie='1' then -- done going 0->1 and ie=1
n.rintreq := '1'; -- request rx interrupt
end if;
end if;
N_REGS <= n;
RRLIM_START <= irrlimsta;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;

7
rtl/ibus/ibdr_maxisys.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: ibdr_maxisys.vhd 1123 2019-03-17 17:55:12Z mueller $
-- $Id: ibdr_maxisys.vhd 1128 2019-04-07 13:12:47Z mueller $
--
-- Copyright 2009-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -51,6 +51,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-07 1127 1.6.3 ibdr_dl11: use RLIM_CEV, drop CE_USEC
-- 2019-03-17 1123 1.6.2 add ib_rlim_gen, use with ibdr_lp11_buf
-- 2019-03-09 1121 1.6.1 add ibdr_lp11_buf
-- 2019-02-10 1111 1.6 use typ for DL,PC,LP
@@ -380,9 +381,9 @@ begin
DL11_0 : ibdr_dl11
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
BRESET => BRESET,
RLIM_CEV => RLIM_CEV,
RB_LAM => RB_LAM_DL11_0,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DL11_0,
@@ -399,9 +400,9 @@ begin
IB_ADDR => slv(to_unsigned(8#176500#,16)))
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
BRESET => BRESET,
RLIM_CEV => RLIM_CEV,
RB_LAM => RB_LAM_DL11_1,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DL11_1,

1
rtl/ibus/ibdr_minisys.vbom
View File

@@ -3,6 +3,7 @@
iblib.vhd
ibdlib.vhd
# components
ib_rlim_gen.vbom
ibdr_sdreg.vbom
ibd_kw11l.vbom
ibdr_dl11.vbom

22
rtl/ibus/ibdr_minisys.vhd
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@@ -1,6 +1,6 @@
-- $Id: ibdr_minisys.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: ibdr_minisys.vhd 1129 2019-04-07 13:27:35Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -15,7 +15,8 @@
-- Module Name: ibdr_minisys - syn
-- Description: ibus(rem) devices for minimal system:SDR+KW+DL+RK
--
-- Dependencies: ibdr_sdreg
-- Dependencies: ib_rlim_gen
-- ibdr_sdreg
-- ibd_kw11l
-- ibdr_dl11
-- ibdr_rk11
@@ -23,7 +24,7 @@
-- ib_intmap
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
-- Tool versions: ise 8.2-14.7; viv 2014.4-2017.2; ghdl 0.18-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -32,6 +33,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-07 1129 1.1.3 ibdr_dl11: use RLIM_CEV, drop CE_USEC
-- 2011-11-18 427 1.1.2 now numeric_std clean
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
@@ -124,9 +126,19 @@ architecture syn of ibdr_minisys is
signal EI_ACK_DL11RX : slbit := '0';
signal EI_ACK_DL11TX : slbit := '0';
signal EI_ACK_RK11 : slbit := '0';
signal RLIM_CEV : slv7 := (others=>'0');
begin
RLIM : ib_rlim_gen
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => '0',
RLIM_CEV => RLIM_CEV
);
SDREG : ibdr_sdreg
port map (
CLK => CLK,
@@ -152,9 +164,9 @@ begin
DL11 : ibdr_dl11
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
BRESET => BRESET,
RLIM_CEV => RLIM_CEV,
RB_LAM => RB_LAM_DL11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DL11,

19
rtl/ibus/ibdr_pc11.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibdr_pc11.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: ibdr_pc11.vhd 1126 2019-04-06 17:37:40Z mueller $
--
-- Copyright 2009-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2009-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,7 +18,7 @@
-- Dependencies: -
-- Test bench: xxdp: zpcae0
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
-- Tool versions: ise 8.2-14.7; viv 2014.4-2017.2; ghdl 0.18-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -27,6 +27,8 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-06 1126 1.4 for pc11_buf compat: pbuf.pval in bit 15 and 8;
-- move rbusy reporting from pbuf to rbuf register
-- 2013-05-04 515 1.3 BUGFIX: r.rbuf was immediately cleared ! Was broken
-- since ibus V2 update, never tested afterwards...
-- 2011-11-18 427 1.2.2 now numeric_std clean
@@ -76,13 +78,15 @@ architecture syn of ibdr_pc11 is
constant rcsr_ibf_rdone : integer := 7;
constant rcsr_ibf_rie : integer := 6;
constant rcsr_ibf_renb : integer := 0;
constant rbuf_ibf_rbusy : integer := 15;
constant pcsr_ibf_perr : integer := 15;
constant pcsr_ibf_prdy : integer := 7;
constant pcsr_ibf_pie : integer := 6;
constant pbuf_ibf_pval : integer := 8;
constant pbuf_ibf_rbusy : integer := 9;
constant pbuf_ibf_pval : integer := 15;
constant pbuf_ibf_pval8 : integer := 8;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
@@ -224,6 +228,7 @@ begin
end if;
else -- rri ---------------------
idout(rbuf_ibf_rbusy) := r.rbusy;
if ibw0 = '1' then
n.rbuf := IB_MREQ.din(n.rbuf'range);
n.rbusy := '0';
@@ -285,7 +290,7 @@ begin
else -- rri ---------------------
idout(r.pbuf'range) := r.pbuf;
idout(pbuf_ibf_pval) := not r.prdy;
idout(pbuf_ibf_rbusy) := r.rbusy;
idout(pbuf_ibf_pval8) := not r.prdy;
if ibrd = '1' then
n.prdy := '1';
if r.pie = '1' then

14
rtl/w11a/tb/tb_rlink_tba_pdp11core_ibdr.dat
View File

@@ -1,9 +1,10 @@
# $Id: tb_rlink_tba_pdp11core_ibdr.dat 675 2015-05-08 21:05:08Z mueller $
# $Id: tb_rlink_tba_pdp11core_ibdr.dat 1126 2019-04-06 17:37:40Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2019-04-06 1126 1.6 adapt to new dl11 iface
# 2015-05-03 674 1.5 start/stop/suspend overhaul
# 2014-12-26 621 1.4 adopt wmembe,ribr,wibr testing to new 4k window
# 2014-12-26 621 1.4 adapt wmembe,ribr,wibr testing to new 4k window
# 2014-09-27 595 1.3 now for rlink v4 iface
# 2014-08-15 583 1.2 rb_mreq addr now 16 bit
# 2010-06-18 306 1.1 adapt to new rri<->cp implementation
@@ -44,11 +45,13 @@
# ibus -> ibr mapping: (addr-160000)/2 + 40000
# RKWC: 177406 -> ibr 047603
# RKBA: 177410 -> ibr 047604
# RBUF: 177562 -> ibr 047671
# XCSR: 177564 -> ibr 047672
# XBUF: 177566 -> ibr 047673
#
.amdef RKWC o"047603"
.amdef RKBA o"047604"
.amdef RBUF o"047671"
.amdef XCSR o"047672"
.amdef XBUF o"047673"
#
@@ -140,12 +143,13 @@ C -----------------------------------------------------------------------------
C test device attention (use DL11 XCSR/XBUF [177564/177566])
#
rreg .XCSR d=o"000200" -- read XCSR via RRI: XRDY=1
rreg .XBUF d=o"001000" -- read XBUF via RRI: RRDY=1,XDONE=0
rreg .RBUF d=o"100000" -- read RBUF via RRI: RRDY=1
rreg .XBUF d=o"000000" -- read XBUF via RRI: XDONE=0
wreg .al o"177566" -- #XBUF
wreg .mem o"000123" s=00001000 -- write XBUF via CPU
rreg .XCSR d=o"000000" s=00001000 -- read XCSR via RRI: XRDY=0
rreg .XBUF d=o"001523" s=00001000 -- read XBUF via RRI: RRDY=1,XDONE=1
rreg .XBUF d=o"001123" s=00001000 -- read2 XBUF via RRI: RRDY=1,XDONE=0
rreg .XBUF d=o"100523" s=00001000 -- read XBUF via RRI: VAL,VAL8=1
rreg .XBUF d=o"000123" s=00001000 -- read2 XBUF via RRI: VAL,VAL8=0
rreg .XCSR d=o"000200" s=00001000 -- read XCSR via RRI: XRDY=1
attn d=o"000002" s=00000000 -- read/clean LAM's: lam(1) used by DL11
#