diff --git a/Makefile b/Makefile index 8ca3a213..e1dd5830 100644 --- a/Makefile +++ b/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 745 2016-03-18 22:10:34Z mueller $ +# $Id: Makefile 772 2016-06-05 12:55:11Z mueller $ # # 'Meta Makefile' for whole retro project # allows to make all synthesis targets @@ -6,6 +6,8 @@ # # Revision History: # Date Rev Version Comment +# 2016-06-05 772 1.2.4 add vmfsum,imfsum targets +# 2016-03-19 748 1.2.3 comment out legacy designs and tests # 2016-02-19 732 1.2.1 remove dispunit syn and sim entries # 2015-02-01 640 1.2 add vivado targets, separate from ise targets # 2015-01-25 638 1.1 drop as type fx2 targets @@ -30,18 +32,18 @@ SYN_ise += rtl/sys_gen/tst_snhumanio/s3board SYN_ise += rtl/sys_gen/w11a/s3board # Nexys2 ------------------------------------- -SYN_ise += rtl/sys_gen/tst_fx2loop/nexys2/ic -SYN_ise += rtl/sys_gen/tst_fx2loop/nexys2/ic3 +#SYN_ise += rtl/sys_gen/tst_fx2loop/nexys2/ic +#SYN_ise += rtl/sys_gen/tst_fx2loop/nexys2/ic3 SYN_ise += rtl/sys_gen/tst_rlink/nexys2 SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic -SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic3 +#SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic3 SYN_ise += rtl/sys_gen/tst_serloop/nexys2 SYN_ise += rtl/sys_gen/tst_snhumanio/nexys2 SYN_ise += rtl/sys_gen/w11a/nexys2 # Nexys3 ------------------------------------- -SYN_ise += rtl/sys_gen/tst_fx2loop/nexys3/ic -SYN_ise += rtl/sys_gen/tst_fx2loop/nexys3/ic3 +#SYN_ise += rtl/sys_gen/tst_fx2loop/nexys3/ic +#SYN_ise += rtl/sys_gen/tst_fx2loop/nexys3/ic3 SYN_ise += rtl/sys_gen/tst_rlink/nexys3 SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys3/ic SYN_ise += rtl/sys_gen/tst_serloop/nexys3 @@ -111,6 +113,7 @@ SIM_viv += rtl/sys_gen/w11a/arty_bram/tb .PHONY : default .PHONY : all all_ise all_viv .PHONY : all_sim_ise all_syn_ise all_syn_viv +.PHONY : vmfsum imfsum .PHONY : clean .PHONY : clean_sim_ise clean_sim_ise_tmp .PHONY : clean_sym_ise clean_sim_viv clean_sym_ise_tmp clean_sym_viv_tmp @@ -129,6 +132,8 @@ default : @echo " make -j `nproc` all_syn_ise" @echo " make -j `nproc` all_sim_viv" @echo " make -j 1 all_syn_viv" + @echo " make vmfsum" + @echo " make imfsum" @echo " make clean" @echo " make clean_sim_ise" @echo " make clean_syn_ise" @@ -206,6 +211,11 @@ $(SIM_viv): $(SYN_viv): $(MAKE) -j 1 -C $@ # +vmfsum : + @xviv_msg_summary +imfsum : + @xise_msg_summary +# all_lib : $(MAKE) -C tools/src clean_lib : diff --git a/doc/README.txt b/doc/README.txt index bc4d6a87..b2f8d4d0 100644 --- a/doc/README.txt +++ b/doc/README.txt @@ -1,4 +1,4 @@ -$Id: README.txt 746 2016-03-19 13:08:36Z mueller $ +$Id: README.txt 779 2016-06-26 15:37:16Z mueller $ Release notes for w11a @@ -22,6 +22,213 @@ Release notes for w11a 2. Change Log ---------------------------------------------------------------- +- trunk (2016-06-26: svn rev 36(oc) 779(wfjm); untagged w11a_V0.73) +++++++++ + - Preface + - the 'basic vivado support' added with V0.64 was a minimal effort port of + the code base used under ISE, leading to sub-optimal results under vivado. + - the FSM inference under vivado is quirky and has several issues. The + most essential one prevented re-coding with 'one_hot' encoding, which + lead to high logic depth and low clock rates. Proper work-arounds were + applied to almost all FSMs, now vivado infers all (but one) properly + and re-codes them as 'one_hot'. That is especially important for the + pdp11_sequencer, which has 113 states. The sys_w11a_n4 system can now + run with up to 90 MHz (was 75-80 MHz before). + - due to a remaining synthesis issue the dmscnt and dmcmon debug units + are currently disabled for Artix based systems (see issue V0.73-3). + - memory inference is now used for all distributed and block rams under + vivado. The memory generators in memlib are still used under ISE + Note: they were initially setup to work around ISE synthesis issues. + - vivado synthesis and implementation use now 'explore' type flows for + optimal timing performance. + - the two clock dram based fifo was re-written (as fifo_2c_dram2) to allow + proper usage of vivado constraints (e.g. scoped xdc). + + - vivado is now the prime platform for all further development + - the component test benches run now by default under Vivado with an + Artix-7 as default target. The makefiles for ISE with a Spartan-6 target + are available as 'Makefile.ise' and via the 'makeise' command. + - a message filter (xviv_msg_filter) has been developed which lists only + the unexpected message of a synthesis or implementation run. Filter + rule sets (.vmfset files) are available for all designs. + - full support for the vivado simuator 'xsim' has been added, there are + make targets to build a behavioral simulation as well as post-synthesis, + post-optimize, and post-routing functional and timing models. All these + models are now created in separate sub-directories and can now co-exist. + However see issues V.073-1 and 0.73-2 for severe caveats on xsim. + - vivado write_vhdl generates code which violates a vhdl language rule. + Attributes of port signals are declared in the wrong place. xsim and + other simulators accept this, but ghdl doesn't. As a work-around the + generated code is cleaned up by a filter (see xviv_sim_vhdl_cleanup). + + - additional rlink devices + - the XADC block, available on all 7Series FPGAs, is now accessible via + rlink on all Arty, Basys3 and Nexys4 designs. Especially useful on the + Arty board because on this board also the currents are monitored. + - the USR_ACCESS register, available on all 7Series FPGAs, is now readable + via rlink on all Arty, Basys3 and Nexys4 designs. The vivado build flow + initializes this register with the build timestamp. This allows to + verify the build time of a design at run time. + + - the cache used by the w11a (pdp11_cache) was initialy developed with the + tight block ram resources of the early Spartan-3 systems in mind. It had + 8 kByte and used 5 BRAMs of size 18 kBit. With very little changes the + implenenation is now parametrized, and can generate also 16,32, 64 and + even 128 kByte caches which also use the 36 kBit BRAMs on the Artix. + There is a trade-off between cache sizes and clock rate due to routing + delays to the BRAM blocks. The w11a on the nexys4 runs with 16 kByte + cache and 90 MHz clock or with 64 kByte cache and 80 MHz. For practical + work loads, like a kernel compile, the 64 kByte configuration is better + and thus the default. + + - resolved known issue V0.64-7: was caused by a combination of issues + and is now resolved by a combination of measures: add portsel logic for + arty tb, proper portsel setup, configurable timeout, and finally proper + timeout setting. + - resolved known issue V0.64-3: So far the arty, basys3 and nexys4 serial + port, based on a FTDI FT2232, was often operated at 10 MBaud. This rate + is in fact not supported by FTDI, the chip will use 8 instead of 10 MBaud. + Due to auto-bauding, which simly adapts to the actual baud rate, this went + undetected for some time. Now all designs use a serport block clocked with + 120 MHz and can be operated with 12 MBaud. + + - Summary + - new reference system: switched to Vivado 2016.2 (from 2015.4) + - code base cleaned-up for vivado, fsm now inferred + - xsim support complete (but many issues to be resolved yet) + - added configurable w11a cache + - removed some never documented and now strategically obsolete designs: + - sys_tst_fx2loop (for nexys2 and nexys3) + - sys_tst_rlink_cuff_ic3 (a three channel variant of the fx2 interface) + + - New features + - new modules + - rtl/vlib + - generic_clk_100mhz.xdc - generic 100 MHz on CLK constraint (for tbs) + - rtl/vlib/cdclib - new directory for clock domain crossing + - cdc_pulse.vhd - cdc for a pulse (moved in from genlib) + - cdc_signal_s1.vhd - cdc for a signal, 2 stage + - cdc_vector_s0.vhd - cdc for a vector, 1 stage + - rtl/vlib/memlib + - fifo_2c_dram2.vhd - re-write of fifo_2c_dram to allow + proper usage of vivado constraints + - rtl/vlib/rbus + - rb_sres_or_6.vhd - rbus result or, 6 input + - rbd_usracc.vhd - return usr_access register + - rtl/vlib/rlink + - rlink_sp2c.vhd - rlink_core8 + serport_2clock2 combo + - rtl/vlib/serport + - serport_2clock2.vhd - like serport_2clock, use fifo_2c_dram2 + - rtl/vlib/xlib + - usr_access_unisim.vhd - Wrapper for USR_ACCESS* entities + - new files + - tools/bin + - xise_msg_summary - list all filtered ISE messages + - xviv_msg_filter - message filter for vivado + - xviv_msg_summary - list all filtered vivado messages + - xviv_sim_vhdl_cleanup - cleanup vivado generated vhdl for ghdl + - makeise - wrapper for make -f Makefile.ise + - tools/tcl/rbtest + - test_flow.tcl - test back pressure and flow control + + - Changes + - rtl/bplib/*/*_pins.xdc - add BITSTREAM.CONFIG.USR_ACCESS setup + - rtl/bplib/*/tb/tb_*.vbom - use -UUT attribute + - rtl/sys_gen/*/*/tb/tb_*.vbom - use -UUT attribute + - rtl/make_ise + - generic_ghdl.mk - use ghdl.?sim as workdir for ghdl + - generic_xflow.mk - use .imfset for ISE message rules + - rtl/make_viv + - generic_ghdl.mk - use ghdl.?sim as workdir for ghdl + - generic_vivado.mk - add [sorep]sim.v and %.vivado targets + - vmfset support, use xviv_sim_vhdl_cleanup + - generic_xsim.mk - [rep]sim models; use xsim.?sim as workdir + - viv_tools_build.tcl - use explore flows; prj,opt,pla modes + - viv_tools_config.tcl - add USR_ACCESS readback + - viv_tools_model.tcl - add [sor]sim_vhdl [sorepd]sim_veri modes + - rtl/sys_gen/*/* (all rlink based designs) + - sys_*.vhd - define rlink SYSID + - rtl/sys_gen/*/* (all rlink and 7series based designs) + - sys_*.vhd - add rbd_usracc, use serport_2clock2 + - sys_conf.vhd - use PLL for clkser_gentype + - rtl/sys_gen/w11a/* + - sys_conf.vhd - add sys_conf_cache_twidth + - rtl/sys_gen/tst_serloop/nexys4 + - sys_tst_serloop1_n4.vhd - clock now from cmt and configurable + - rtl/sys_gen/tst_serloop/tb + - tb_tst_serloop.vhd - use serport_(uart_rxtx|xontx)_tb + - rtl/vlib/*/tb/tb_*.vbom - use -UUT attribute + - rtl/vlib/*/tb/tbd_*.vbom - use generic_clk_100mhz.xdc + - rtl/vlib/comlib/comlib.vhd - leave return type unconstraint + - rtl/vlib/simlib/simlib.vhd - add writetimens() + - rtl/w11a + - pdp11_bram_memctl.vhd - use memory inference now + - pdp11_cache.vhd - now configurable size (8,16,32,64,128 kB) + - pdp11_sequencer.vhd - proc_snum conditional (vivado fsm fix) + - rtl/*/*.vbom - use memory inference for vivado + - rtl/*/*.vhd - workarounds and fixes to many FSMs + - tools/bin + - tbrun_tbw - use _bsim.log for behavioral sim log + - tbrun_tbwrri - use _bsim.log for behavioral sim log + use 120 sec timeout for simulation + - tbw - add '-norun', -run now default + - ti_rri - add --tout option + use 120 sec timeout for simulation + - vbomconv - add file properties (-UUT,-SCOPE_REF) + full xsim support now in -vsim_prj + - tools/src/librlink + - RlinkConnect - add USR_ACCESS register support + - tools/src/librlinktpp + - RtclRlinkConnect - add USR_ACCESS, timeout access + - tools/tcl/rbtest + - test_data.tcl - add dinc register tests + - tools/tcl/rlink + - util.tcl - add USR_ACCESS register support + + - removed designs + - rtl/sys_gen/tst_fx2loop/nexys*/*/sys_tst_fx2loop_*_n* + - rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2 + - renames + - *.mfset -> *.imfset - to be complementary to new .vmfset + - Makefile -> Makefile.ise - old ISE makefiles in component areas + + - Bug fixes + - rtl/bplib/arty/tb + - tb_arty.vhd: - add portsel logic + - rtl/bplib/sysmon + - sysmon_rbus_core.vhd - use s_init (and not s_idle) after RESET + - rtl/vlib/xlib + - s7_cmt_sfs_*.vhd - correct mmcm range check boundaries + - tools/bin + - ti_w11: - proper portsel oob for -fx + - tbrun_tbwrri: - proper portsel oob for -hxon + + - Known issues + - all issues: see README_known_issues.txt + - resolved issues: + - V0.72-1: since vivado 2016.1 xelab builds models which use DPI in a + mixed vhdl-verilog language environment. + - V0.72-2: now full support to build behavioral as well as functional and + timing simulations with xsim. See V.073-1 and 0.73-2 for caveats. + - V0.64-7: flow control issues with simulation models resolved + - V0.64-3: basys3, nexys4 and arty designs support now 12 MBaud. + + - new issues: + - V0.73-1: as of vivado 2016.2 xelab shows sometimes extremely long build + times, especially for generated post-synthesis vhdl models. But also + building a behavioral simulation for a w11a design can take 25 min. + Even though post-synthesis or post-routing models are now generated + in verilog working with xsim is cumbersome and time consuming. + - V0.73-2: Many post-synthesis functional and especially post-routing + timing simulations currently fail due to startup and initialization + problems. Cause is MMCM/PLL startup, which is not properly reflected + in the test bench. Will be resolved in an upcoming release. + - V0.73-3: The 'state number generator' code in pdp11_sequencer causes + in vivado 2016.1 (and .2) that the main FSM isn't re-coded anymore, + which has high impact on achievable clock rate. The two optional + debug units depending on the state number, dmscnt and dmcmon, are + therefore currently deactivated in all Artix based systems (but are + available on all Spartan based systems). + - trunk (2016-03-19: svn rev 35(oc) 746(wfjm); untagged w11a_V0.72) +++++++++ - Preface - The new low-cost Digilent Arty board is a very attractive platform. @@ -70,7 +277,7 @@ Release notes for w11a - serport_uart_*_tb - added copies for tb usage - rtl/vlib/xlib/tb - s7_cmt_sfs_tb - added copy for tb usage - - + - new files - doc/man/man1 - tbrun_tbw.1 - man file for tbrun_tbw diff --git a/doc/README_buildsystem_ISE.txt b/doc/README_buildsystem_ISE.txt index fe728f3f..6ef13ffe 100644 --- a/doc/README_buildsystem_ISE.txt +++ b/doc/README_buildsystem_ISE.txt @@ -1,4 +1,4 @@ -# $Id: README_buildsystem_ISE.txt 651 2015-02-26 21:32:15Z mueller $ +# $Id: README_buildsystem_ISE.txt 779 2016-06-26 15:37:16Z mueller $ Guide to the Build System (Xilinx ISE Version) @@ -114,13 +114,17 @@ Guide to the Build System (Xilinx ISE Version) In many cases the test benches can also be compiled against the gate level models derived after the xst, map or par step. To compile them - make ghdl_tmp_clean - make _ssim # for post-xst - make _fsim # for post-map - make _tsim # for post-par + make _ssim # for post-xst (using UNISIM) + make _fsim # for post-map (using SIMPRIM) + make _tsim # for post-par (using SIMPRIM) - The 'make ghdl_tmp_clean' is needed to flush the ghdl work area from - the compilation remains of earlier functional model compiles. + Individual working directories are used for the different models + ghdl.bsim for bahavioral model + ghdl.ssim for post-xst + ghdl.fsim for post-map + ghdl.tsim for post-par + and can co-exist. The 'make ghdl_tmp_clean' can be used to flush the ghdl + work areas, but in general this is not needed (since V0.73). Notes: - the post-xst simulation (_ssim targets) proved to be a valuable tool. diff --git a/doc/README_buildsystem_Vivado.txt b/doc/README_buildsystem_Vivado.txt index 63f48bfa..b58f2bef 100644 --- a/doc/README_buildsystem_Vivado.txt +++ b/doc/README_buildsystem_Vivado.txt @@ -1,4 +1,4 @@ -# $Id: README_buildsystem_Vivado.txt 745 2016-03-18 22:10:34Z mueller $ +# $Id: README_buildsystem_Vivado.txt 779 2016-06-26 15:37:16Z mueller $ Guide to the Build System (Xilinx Vivado Version) @@ -12,8 +12,9 @@ Guide to the Build System (Xilinx Vivado Version) a. With ghdl b. With Vivado xsim 4. Building systems - 5. Configuring FPGAs (via make flow) - 6. Note on ISE + 5. Building vivado projects, creating gate level models + 6. Configuring FPGAs (via make flow) + 7. Note on ISE 1. Concept ---------------------------------------------------------------- @@ -102,8 +103,7 @@ Guide to the Build System (Xilinx Vivado Version) 3. Building test benches -------------------------------------------------- - The build flows currently supports only ghdl. - Support for the Vivado simulator XSim will be added in a future release. + The build flows currently supports ghdl and the vivado simulator xsim. 3a. With ghdl -------------------------------------------------------- @@ -115,18 +115,29 @@ Guide to the Build System (Xilinx Vivado Version) and generate the needed ghdl commands. In some cases the test benches can also be compiled against the gate - level models derived after the synthesis or optimize step. To compile them + level models derived after the synthesis or optimize step. + Vivado only generated functional (UNISIM based) models in vhdl. Timing + (SIMPRIM based) models are only available on verilog. The combination + vivado + ghdl is therefore limited to functional model simulation. + + To compile them make ghdl_tmp_clean - make _ssim # for post synthesis {see Notes} - make _osim # for post optimize {see Notes} + make _ssim # for post synthesis functional + make _osim # for post optimize functional + make _rsim # for post routing functional - The 'make ghdl_tmp_clean' is needed to flush the ghdl work area from - the compilation remains of earlier functional model compiles. + Individual working directories are used for the different models + ghdl.bsim for bahavioral model + ghdl.ssim for post synthesis + ghdl.osim for post optimize + ghdl.rsim for post routing + and can co-exist. The 'make ghdl_tmp_clean' can be used to flush the ghdl + work areas, but in general this is not needed (since V0.73). Notes: - - post synthesis or optimize models currently very often fail to compile - in ghdl due to a bug in the ghdl code generator. + - Many post-synthesis functional currently fail due to startup and + initialization problems (see issue V0.73-2). 3b. With Vivado xsim ------------------------------------------------- @@ -139,16 +150,25 @@ Guide to the Build System (Xilinx Vivado Version) In many cases the test benches can also be compiled against the gate level models derived after the synthesis, optimize or routing step. + Vivado supports functional (UNISIM based) models in vhdl and in verilog, + and timing (SIMPRIM based) models only in verilog. Since practice showed + that verilog models compile and execute faster, verilog is used for both + functional and timing models. - make _XSim_ssim # for post-synthesis - make _XSim_osim # for post-optimize - make _XSim_tsim # for post-routing + make _XSim_ssim # for post-synthesis functional + make _XSim_osim # for post-optimize functional + make _XSim_rsim # for post-routing functional + + make _XSim_esim # for post-synthesis timing + make _XSim_psim # for post-optimize timing + make _XSim_tsim # for post-routing timing Notes: - - xsim currently (as of Vivado 2015.4) crashes when DPI is used in a mixed - vhdl verilog context. - Since DPI is used in the rlink simulation all system test benches with - an rlink interface, thus most, will only run with ghdl and not with XSim. + - as of vivado 2016.2 xelab shows sometimes extremely long build times, + especially for generated post-synthesis vhdl models (see issue V0.73-1). + - Many post-synthesis functional and especially post-routing timing + simulations currently fail due to startup and initialization problems + (see issue V0.73-2). 4. Building systems ------------------------------------------------------- @@ -191,16 +211,48 @@ Guide to the Build System (Xilinx Vivado Version) make _opt.dcp make _rou.dcp -5. Configuring FPGAs ------------------------------------------------------ +5. Building vivado projects, creating gate level models ------------------- + + Vivado is used in 'project mode', whenever one of the targets mentioned + above is build a vivado project is freshly created in the directory + project_mflow + with the project file + project_mflow/project_mflow.xpr + + There are many make targets which + - just create the project + - start vivado in gui mode to inspect the most recent project + - create gate level models + + Specifically + + make .vivado # create vivado project from .vbom + make vivado # open project in project_mflow + + make _ssim.vhd # post-synthesis functional model (vhdl) + make _osim.vhd # post-optimize functional model (vhdl) + make _rsim.vhd # post-routing functional model (vhdl) + + make _ssim.v # post-synthesis functional model (verilog) + make _osim.v # post-optimize functional model (verilog) + make _rsim.v # post-routing functional model (verilog) + + make _esim.v # post-synthesis timing model (verilog) + make _psim.v # post-optimize timing model (verilog) + make _tsim.v # post-routing timing model (verilog) + + For timing model verilog file an associated sdf file is also generated. + +6. Configuring FPGAs ------------------------------------------------------ The make flow supports also loading the bitstream into FPGAs via the Vivado hardware server. Simply use make .vconfig - Note: works with Basys3 and Nexys4, only one board must connected. + Note: works with Arty, Basys3, and Nexys4, only one board must connected. -6. Note on ISE ------------------------------------------------------------ +7. Note on ISE ------------------------------------------------------------ The development for Nexys4 started with ISE, but has now fully moved to Vivado. The make files for the ISE build flows have been kept for comparison @@ -208,6 +260,8 @@ Guide to the Build System (Xilinx Vivado Version) one can still start with a make -f Makefile.ise + or + makeise an ISE based build. To be used for tool comparisons, the ISE generated bit files were never tested in an FPGA. diff --git a/doc/README_known_issues.txt b/doc/README_known_issues.txt index df3d0a02..3dc969b7 100644 --- a/doc/README_known_issues.txt +++ b/doc/README_known_issues.txt @@ -1,12 +1,22 @@ -$Id: README_known_issues.txt 746 2016-03-19 13:08:36Z mueller $ +$Id: README_known_issues.txt 779 2016-06-26 15:37:16Z mueller $ Known issues for this release. The case id indicates the release when the issue was first recognized. -- V0.72-2: xsim simulations with timing annotation not yet available. -- V0.72-1: Vivado 2015.4 xelab crashes when DPI is used in a mxied vhdl-verilog - language environment. This prevents currently to build a xsim simulation - model for rlink based test benches. +- V0.73-1: as of vivado 2016.2 xelab shows sometimes extremely long build times, + especially for generated post-synthesis vhdl models. But also building a + behavioral simulation for a w11a design can take 25 min. Even though + post-synthesis or post-routing models are now generated in verilog working + with xsim is cumbersome and time consuming. +- V0.73-2: Many post-synthesis functional and especially post-routing timing + simulations currently fail due to startup and initialization problems. + Cause is MMCM/PLL startup, which is not properly reflected in the test + bench. Will be resolved in an upcoming release. +- V0.73-3: The 'state number generator' code in pdp11_sequencer causes in vivado + 2016.1 (and .2) that the main FSM isn't re-coded anymore, which has high + impact on achievable clock rate. The two optional debug units depending on + the state number, dmscnt and dmcmon, are therefore currently deactivated in + all Artix based systems (but are available on all Spartan based systems). - V0.66-1: the TM11 controller transfers data byte wise (all disk do it 16bit word wise) and allows for odd byte length transfers. Odd length transfers @@ -25,12 +35,8 @@ The case id indicates the release when the issue was first recognized. - read or write 'with header' gives currently ILF All this isn't used by any OS, so in practice not relevant. -- V0.64-7: ghdl simulated OS boots via ti_w11 (-n4 ect options) fail due to a - flow control issue (likely since V0.63). - V0.64-6: IO delays still unconstraint in vivado. All critical IOs use explicitly IOB flops, thus timing well defined. -- V0.64-3: Highest baud rate with basys3 and nexys4 is 10 MBaud. 10 MBaud is - not supported according to FTDI, but works. 12 MBaud in an upcoming release. - V0.64-2: rlink throughput on basys3/nexys4 limited by serial port stack round trip times. Will be overcome by libusb based custom driver. - V0.64-1: The large default transfer size for disk accesses leads to bad diff --git a/doc/man/man1/tbrun_tbw.1 b/doc/man/man1/tbrun_tbw.1 index 469f1f97..0c692931 100644 --- a/doc/man/man1/tbrun_tbw.1 +++ b/doc/man/man1/tbrun_tbw.1 @@ -1,5 +1,5 @@ .\" -*- nroff -*- -.\" $Id: tbrun_tbw.1 745 2016-03-18 22:10:34Z mueller $ +.\" $Id: tbrun_tbw.1 774 2016-06-12 17:08:47Z mueller $ .\" .\" Copyright 2016- by Walter F.J. Mueller .\" @@ -55,7 +55,7 @@ dry run, prints the commands but doesn't execute . .\" -- --lsuf ------------------------------------ .IP \fB\-\-lsuf\ \fIsuff\fR -use '_\fIsuff\fR.log' as suffix for log file. Default is '_dsim.log' +use '_\fIsuff\fR.log' as suffix for log file. Default is '_bsim.log' . .\" -- --stack ----------------------------------- .IP \fB\-\-stack\ \fInnn\fR @@ -77,7 +77,7 @@ Simplest default case, will execute make tb_serport_uart_rx time tbw tb_serport_uart_rx 2>&1 |\\ ghdl_assert_filter |\\ - tee tb_serport_uart_rx_dsim.log |\\ + tee tb_serport_uart_rx_bsim.log |\\ egrep "(-[EFW]:|ERROR|FAIL|PASS|DONE)" .EE diff --git a/doc/man/man1/tbrun_tbwrri.1 b/doc/man/man1/tbrun_tbwrri.1 index cc51e45e..c4833011 100644 --- a/doc/man/man1/tbrun_tbwrri.1 +++ b/doc/man/man1/tbrun_tbwrri.1 @@ -1,5 +1,5 @@ .\" -*- nroff -*- -.\" $Id: tbrun_tbwrri.1 745 2016-03-18 22:10:34Z mueller $ +.\" $Id: tbrun_tbwrri.1 774 2016-06-12 17:08:47Z mueller $ .\" .\" Copyright 2016- by Walter F.J. Mueller .\" @@ -63,7 +63,7 @@ dry run, prints the commands but doesn't execute . .\" -- --lsuf ------------------------------------ .IP \fB\-\-lsuf\ \fIsuff\fR -use '_\fIsuff\fR.log' as suffix for log file. Default is '_dsim.log' +use '_\fIsuff\fR.log' as suffix for log file. Default is '_bsim.log' . .\" -- --stack ----------------------------------- .IP \fB\-\-stack\ \fInnn\fR @@ -97,8 +97,8 @@ For s3board, nexys2, and nexys3 designs. . .\" -- --sxon ------------------------------------ .IP \fB\-\-sxon\fR -switched\ XON: enable XON flow control with SWI(1), will generate appropriate -'rlc oob' commands and ti_rri \-\-fifo options. +switched\ XON: enable XON flow control with SWI(1), will generate +appropriate 'rlc oob' commands and ti_rri \-\-fifo options. For nexys4 designs. . .\" -- --hxon ------------------------------------ diff --git a/doc/man/man1/tbw.1 b/doc/man/man1/tbw.1 index 9f6e1ce9..0d6a2eac 100644 --- a/doc/man/man1/tbw.1 +++ b/doc/man/man1/tbw.1 @@ -1,11 +1,11 @@ .\" -*- nroff -*- -.\" $Id: tbw.1 727 2016-02-07 13:58:47Z mueller $ +.\" $Id: tbw.1 774 2016-06-12 17:08:47Z mueller $ .\" .\" Copyright 2013-2016 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ . -.TH TBW 1 2016-02-06 "Retro Project" "Retro Project Manual" +.TH TBW 1 2016-04-17 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME tbw \- wrapper script to start ghdl based VHDL test benches @@ -52,9 +52,10 @@ or if defined to \fIFILEDEF\fP, and execute \fITBPROG\fP. In essence .SS Using a \fItbw.dat\fP configuration file When the generic file name or the stimulus file name does not follow the simple default pattern or more than one input file is required a -configuration file can be used to define the setup. It has the fixed -name \fItbw.dat\fP and is searched the current working directory. The -format is described in section FILES. +configuration file can be used to define the setup. It has the fixed name +\fItbw.dat\fP and is searched the directory of the test bench program +\fITBPROG\fP. +The format is described in section FILES. In this case the \fIFILEDEF\fP argument can be specified as 'tag=value' pairs where tag refers to a generic name and value gives the concrete @@ -68,15 +69,18 @@ defined via the \fItbw.dat\fP file, for details see section FILES. . .\" ------------------------------------------------------------------ .SH OPTIONS -The options \fB\-run\fP, \fB\-fifo\fP and \fB\-verbose\fP are processed -by tbw itself. If more than one is given they must be in this order. -.IP \fB\-run\fR -Used for _ISim or _XSim tb's, ensures that simulation runs till end. Will -issue a 'run all' command for ISim and a '-R' option for XSim. +The options \fB\-fifo\fP, \fB\-verbose\fP and \fB\-norun\fP are processed +by tbw itself. They must be the first options after \fITBPROG\fP. .IP \fB\-fifo\fR -Forces usage of rlink_cext fifo, will ignore tbw.dat +Forces usage of rlink_cext fifo in case no \fItbw.dat\fP is found or no section +matching \fITBPROG\fP is found in tbw.dat. .IP \fB\-verbose\fR -show the used tag,value settings before execution +Show the used tag,value settings before execution +.IP \fB\-norun\fR +Start simulator in interactive mode. +Default for _XSim or _ISim tb's is to ensure that the simulation runs till +the end, as for ghdl. Therefore a '-R' option for XSim or a 'run all' command +for ISim is generated. The -norun option suppresses this. .\" ------------------------------------------------------------------ .SH GHDL OPTIONS @@ -111,9 +115,10 @@ display process name before each cycle. .\" ------------------------------------------------------------------ .SH FILES .IP "\fI./tbw.dat\fR" 4 -This configuration file is searched for in the current working directory -and holds associations between generic file names and concrete file names -for one or more test bench executables. It contains sections of the format +This configuration file is searched for in the directory of the test bench +program \fITBPROG\fP and holds associations between generic file names and +concrete file names for one or more test bench executables. It contains +sections of the format .EX [\fITBPROG\fP] @@ -179,6 +184,9 @@ produce a single \fIDONE\fP line .PD .RE +The convenience script \fBtbrun_tbw\fP(1) can be used in many cases to create +such a pipeline. + .SS Test benches controlled with \fBti_rri\fP In these cases the test bench is started via \fBti_rri\fP using the \fB\-\-run\fP and \fB\-\-fifo\fP options. Also here usually a pipe with @@ -188,14 +196,19 @@ In these cases the test bench is started via \fBti_rri\fP using the ti_rri \-\-run="tbw tb_tst_rlink_n3" \-\-fifo \-\-logl=3 \-\- \\ "package require tst_rlink" \\ "tst_rlink::setup" "tst_rlink::test_all" |\\ - tee tb_tst_rlink_n3_dsim.log |\\ + tee tb_tst_rlink_n3_bsim.log |\\ egrep "(\-[EFW]:|FAIL|PEND|DONE)" .EE +The convenience script \fBtbrun_tbwrri\fP(1) can be used in many cases to +create these sometimes rather lengthy constructs. + . .\" ------------------------------------------------------------------ .SH "SEE ALSO" .BR ti_rri (1), +.BR tbrun_tbw (1), +.BR tbrun_tbwrri (1), .BR gtkwave (1), .BR symlink (7), .BR fifo (7) diff --git a/doc/man/man1/ti_rri.1 b/doc/man/man1/ti_rri.1 index 89fa507a..a11040c9 100644 --- a/doc/man/man1/ti_rri.1 +++ b/doc/man/man1/ti_rri.1 @@ -1,11 +1,11 @@ .\" -*- nroff -*- -.\" $Id: ti_rri.1 742 2016-03-13 14:40:19Z mueller $ +.\" $Id: ti_rri.1 776 2016-06-18 17:22:51Z mueller $ .\" .\" Copyright 2013-2016 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ . -.TH TI_RRI 1 2016-03-13 "Retro Project" "Retro Project Manual" +.TH TI_RRI 1 2016-06-18 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME ti_rri \- \fBRlink\fP Backend Server @@ -34,6 +34,8 @@ loads additional tcl packages when requested with \fB\-\-pack\fP sets up logging and debug according to \fB\-\-log\fP, \fB\-\-logl\fP, \fB\-\-dmpl\fP, and \fB\-\-tiol\fP .IP "-" +sets up connection timeout according to \fB\-\-tout\fP +.IP "-" starts an additional process if requested with \fB\-\-run\fP .IP "-" opens a connection when requested with \fB\-\-fifo\fP, @@ -191,6 +193,12 @@ trace character activities .PD .RE . +.\" -- --tout ----------------------------------- +.IP \fB\-\-tout=\fIdt\fR +set connection timeout. Default is '1.'. Must be >0. . Should be set to a +larger value when slow simulators are connected, e.g. post-implentation +timing models. +. .\" -- --int ------------------------------------ .IP \fB\-\-int\fP enter interactive mode even when further tcl commands are given on the diff --git a/doc/man/man1/ti_w11.1 b/doc/man/man1/ti_w11.1 index 7c113459..925abc06 100644 --- a/doc/man/man1/ti_w11.1 +++ b/doc/man/man1/ti_w11.1 @@ -1,5 +1,5 @@ .\" -*- nroff -*- -.\" $Id: ti_w11.1 745 2016-03-18 22:10:34Z mueller $ +.\" $Id: ti_w11.1 748 2016-03-20 15:18:50Z mueller $ .\" .\" Copyright 2013-2015 by Walter F.J. Mueller .\" @@ -87,12 +87,21 @@ use 2nd serport with switched xon .RE .IP \fB-tmu\fP activate trace and monitoring unit -.PD 0 .IP \fB-ghw\fP -activate ghw wave file writing +activate ghdl wave dump, will write a dump file with the name +\f.ghw\fR where is the filename of the test bench +.PD 0 .PD . .SS "common options" +.IP \fB-ll\fIn\fR +set rlink logging level to \fIn\fR (will issue a --logl=\fIn\fR). +.IP \fB-dl\fIn\fR +set rlink dump level to \fIn\fR (will issue a --dmpl=\fIn\fR). +.IP \fB-tl\fIn\fR +set rlink I/O trace level to \fIn\fR (will issue a --tiol=\fIn\fR). +.IP \fB-b\fR +batch mode .IP \fB-e "\fR=\fIfile"\fR load and execute \fIfile\fP. If the file type is '.mac' the file will be on the fly compiled with \fBasm-11\fP(1), for all other file types diff --git a/doc/man/man1/vbomconv.1 b/doc/man/man1/vbomconv.1 index e89c3a19..2f83a9dd 100644 --- a/doc/man/man1/vbomconv.1 +++ b/doc/man/man1/vbomconv.1 @@ -1,5 +1,5 @@ .\" -*- nroff -*- -.\" $Id: vbomconv.1 746 2016-03-19 13:08:36Z mueller $ +.\" $Id: vbomconv.1 779 2016-06-26 15:37:16Z mueller $ .\" .\" Copyright 2010-2016 by Walter F.J. Mueller .\" @@ -208,7 +208,7 @@ The first definition seen in the \fIvbom\fP traversal is taken, all others are ignored. The filename in the usage clause is the default used in case the logical name wasn't defined. -Last but not least are 5 directives defined in the \fBvbom\fP +Last but not least are 4 directives defined in the \fBvbom\fP file format: . .IP "\fB@top\fP:\fIname\fP" @@ -220,13 +220,6 @@ allows to specify additional system libraries. Currently used to indicate that the \fIunisim\fP, \fIunimacro\fP or \fIsimprim\fP libraries are needed by \fBghdl\fP. . -.IP "\fB@uut\fP:\fIfile\fP" -signals that the \fIvbom\fP descibes a test bench and that \fIfile\fP is -the 'unit under test'. This allows to split the sources into a simulation -only test bench part and a synthesizable 'unit under test' part. \fIfile\fP -is typically a \fIvbom\fP in case of a functional simulation or the file -name of a generated post synthesis model. -. .IP "\fB@xdc\fP:\fIfile\fP" specifies that \fIfile\fP is a constraint file for Vivado synthesis and should be included in the constraints fileset. @@ -452,6 +445,15 @@ actions use \fBexec\fP(3) to execute the \fBghdl\fP command. In these cases the caller will see the exit status of \fBghdl\fP. . .\" ------------------------------------------------------------------ +.SH ENVIRONMENT +.IP \fBVBOMCONV_XSIM_LANG\fP +Controls the language for the generated models used by xsim. Can be set to +\fIverilog\fP or to \fIvhdl\fP. If not defined \fIverilog\fP is used. +It affects \fB\-\-vsim_prj\fP but also \fB\-\-dep_vsim\fP. +Use \fBrm_dep\fP(1) to force regeneration of dependency files when this +environment variable is set, unset or changed. +. +.\" ------------------------------------------------------------------ .SH BUGS .IP \(bu 2 Duplicate file elimination fails when one source file is refered to by @@ -550,7 +552,6 @@ output like in vbomconv --ghdl_a_cmd tb_w11a_n2.vbom | wc vbomconv --isim_prj tb_w11a_n2.vbom | wc .EP -. .\" ------------------------------------------------------------------ .SH "SEE ALSO" .BR vbom (5), diff --git a/doc/man/man1/xise_ghdl_simprim.1 b/doc/man/man1/xise_ghdl_simprim.1 index 2d81e46f..73fae3c4 100644 --- a/doc/man/man1/xise_ghdl_simprim.1 +++ b/doc/man/man1/xise_ghdl_simprim.1 @@ -1,5 +1,5 @@ .\" -*- nroff -*- -.\" $Id: xise_ghdl_simprim.1 639 2015-01-30 18:12:19Z mueller $ +.\" $Id: xise_ghdl_simprim.1 779 2016-06-26 15:37:16Z mueller $ .\" .\" Copyright 2010-2015 by Walter F.J. Mueller .\" @@ -47,7 +47,7 @@ The \fBxilinx_vhdl_memcolltype_fix\fP helper script simply removes them, no further problems seen so far. .\" ------------------------------------------------------------------ -.SH ENVIRONMENT VARIABLES +.SH ENVIRONMENT .IP \fBXTWI_PATH\fP points to the root of the currently active ISE/WebPack installation. . diff --git a/doc/man/man1/xise_ghdl_unisim.1 b/doc/man/man1/xise_ghdl_unisim.1 index 60599628..69f751e2 100644 --- a/doc/man/man1/xise_ghdl_unisim.1 +++ b/doc/man/man1/xise_ghdl_unisim.1 @@ -1,5 +1,5 @@ .\" -*- nroff -*- -.\" $Id: xise_ghdl_unisim.1 642 2015-02-06 18:53:12Z mueller $ +.\" $Id: xise_ghdl_unisim.1 779 2016-06-26 15:37:16Z mueller $ .\" .\" Copyright 2010-2015 by Walter F.J. Mueller .\" @@ -41,7 +41,7 @@ The \fBxilinx_vhdl_memcolltype_fix\fP helper script simply removes them, no further problems seen so far. .\" ------------------------------------------------------------------ -.SH ENVIRONMENT VARIABLES +.SH ENVIRONMENT .IP \fBXTWI_PATH\fP points to the root of the currently active ISE installation. . diff --git a/doc/man/man1/xise_msg_filter.1 b/doc/man/man1/xise_msg_filter.1 index 1c1a8840..c25eb413 100644 --- a/doc/man/man1/xise_msg_filter.1 +++ b/doc/man/man1/xise_msg_filter.1 @@ -1,10 +1,10 @@ .\" -*- nroff -*- -.\" $Id: xise_msg_filter.1 640 2015-02-01 09:56:53Z mueller $ +.\" $Id: xise_msg_filter.1 779 2016-06-26 15:37:16Z mueller $ .\" .\" Copyright 2014-2015 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ -.TH ISEMSG_FILTER 1 2015-01-30 "Retro Project" "Retro Project Manual" +.TH XISE_MSG_FILTER 1 2015-01-30 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME xise_msg_filter \- message filter for Xilinx ISE tool chain log files @@ -14,7 +14,7 @@ xise_msg_filter \- message filter for Xilinx ISE tool chain log files .SY xise_msg_filter .OP \-\-pack .I TYPE -.I MFSET +.I IMFSET .I LOGFILE . .SY xise_msg_filter @@ -27,7 +27,7 @@ xise_msg_filter \- message filter for Xilinx ISE tool chain log files Scans the log file \fILOGFILE\fP generated by Xilinx ISE tool specified by \fITYPE\fP for informational, warning and error messages and compares these messages against a set of message filter rules defined in the -\fIMFSET\fP file. +\fIIMFSET\fP file. xise_msg_filter will print all no-matching messages. All filter rules which do not match a message are also listed, these messages are considered missing. @@ -69,7 +69,7 @@ print full help. .\" ------------------------------------------------------------------ .SH MESSAGE FILTER FILE FORMAT .\" ---------------------------------------------- -Simply a list of regular expression patters structured by section headers +Simply a list of regular expression patterns structured by section headers of the form "[TYPE]". Blank lines and lines starting with '#' will be ignored. xise_msg_filter will extract the patters of the section matching the @@ -86,22 +86,23 @@ xise_msg_filter will extract the patters of the section matching the .EE .\" ------------------------------------------------------------------ .SH EXIT STATUS -If \fITYPE\fP is invalid or the \fIMFSET\fP or \fILOGFILE\fP files -can't be opend an exit status 1 is returned. +If \fITYPE\fP is invalid or the \fIIMFSET\fP or \fILOGFILE\fP files +can't be opened an exit status 1 is returned. .\" ------------------------------------------------------------------ .SH EXAMPLES -.IP "\fBxise_msg_filter xst proj.mfset proj_xst.log\fR" 4 +.IP "\fBxise_msg_filter xst proj.imfset proj_xst.log\fR" 4 Generate a short summary of a ISE xst log file. . .\" ------------------------------------------------------------------ .SH "BUGS" -The \fIMFSET\fP file is flat, no structuring possible, e.g. with includes. +The \fIIMFSET\fP file is flat, no structuring possible, e.g. with includes. It be great to have for example default rules for each target device. Since ISE is 'end-of-life' no further work on xise_msg_filter will be done. . .\" ------------------------------------------------------------------ .SH "SEE ALSO" +.BR xise_msg_summary (1) . .\" ------------------------------------------------------------------ .SH AUTHOR diff --git a/doc/man/man1/xise_msg_summary.1 b/doc/man/man1/xise_msg_summary.1 new file mode 100644 index 00000000..da942bb2 --- /dev/null +++ b/doc/man/man1/xise_msg_summary.1 @@ -0,0 +1,34 @@ +.\" -*- nroff -*- +.\" $Id: xise_msg_summary.1 779 2016-06-26 15:37:16Z mueller $ +.\" +.\" Copyright 2016- by Walter F.J. Mueller +.\" +.\" ------------------------------------------------------------------ +.TH XISE_MSG_SUMMARY 1 2016-06-05 "Retro Project" "Retro Project Manual" +.\" ------------------------------------------------------------------ +.SH NAME +xise_msg_summary \- summarize all ISE tool chain log files +.\" ------------------------------------------------------------------ +.SH SYNOPSIS +. +.SY xise_msg_summary +.YS +. +.\" ------------------------------------------------------------------ +.SH DESCRIPTION +.\" ---------------------------------------------- +Scans the current and all sub-directories for .imfset files and calls for +each message filter set +.EX + make \fIbasename\fP.mfsum +.EE +which in turn will use \fBxise_msg_filter\fP(1) to show unexpected messages +from all relevant log files and reports. +. +.\" ------------------------------------------------------------------ +.SH "SEE ALSO" +.BR xise_msg_filter (1) +. +.\" ------------------------------------------------------------------ +.SH AUTHOR +Walter F.J. Mueller diff --git a/doc/man/man1/xviv_ghdl_unisim.1 b/doc/man/man1/xviv_ghdl_unisim.1 index 766290ea..64f6194e 100644 --- a/doc/man/man1/xviv_ghdl_unisim.1 +++ b/doc/man/man1/xviv_ghdl_unisim.1 @@ -1,5 +1,5 @@ .\" -*- nroff -*- -.\" $Id: xviv_ghdl_unisim.1 642 2015-02-06 18:53:12Z mueller $ +.\" $Id: xviv_ghdl_unisim.1 779 2016-06-26 15:37:16Z mueller $ .\" .\" Copyright 2015- by Walter F.J. Mueller .\" @@ -42,7 +42,7 @@ The \fBxilinx_vhdl_memcolltype_fix\fP helper script simply removes them, no further problems seen so far. .\" ------------------------------------------------------------------ -.SH ENVIRONMENT VARIABLES +.SH ENVIRONMENT .IP \fBXTWV_PATH\fP points to the root of the currently active Vivado installation. . diff --git a/doc/man/man1/xviv_msg_filter.1 b/doc/man/man1/xviv_msg_filter.1 new file mode 100644 index 00000000..02198d53 --- /dev/null +++ b/doc/man/man1/xviv_msg_filter.1 @@ -0,0 +1,128 @@ +.\" -*- nroff -*- +.\" $Id: xviv_msg_filter.1 779 2016-06-26 15:37:16Z mueller $ +.\" +.\" Copyright 2016- by Walter F.J. Mueller +.\" +.\" ------------------------------------------------------------------ +.TH XVIV_MSG_FILTER 1 2016-05-27 "Retro Project" "Retro Project Manual" +.\" ------------------------------------------------------------------ +.SH NAME +xviv_msg_filter \- message filter for Xilinx Vivado tool chain log files +.\" ------------------------------------------------------------------ +.SH SYNOPSIS +. +.SY xviv_msg_filter +.OP \-\-pack +.I TYPE +.I VMFSET +.I LOGFILE +. +.SY xviv_msg_filter +.B \-\-help +.YS +. +.\" ------------------------------------------------------------------ +.SH DESCRIPTION +.\" ---------------------------------------------- +Scans the log file \fILOGFILE\fP generated by Xilinx Vivado for messages and +compares these messages against a set of message filter rules defined in the +\fIVMFSET\fP file and selected by \fITYPE\fP. +xviv_msg_filter will print all no-matching messages. +All filter rules which do not match a message are also listed, these +messages are considered missing. +Matched messages are considered accepted. +In normal operation they will not create output. +xviv_msg_filter is useful for example in \fBmake\fP(1) based flows to +create a short summary from the log files. + +The accepted values for \fITYPE\fP are: + +.RS 3 +.PD 0 +.IP \fBsyn\fP 6 +Vivado synthesis flow +.IP \fBimp\fP +Vivado implementation flow +.PD +.RE +. +.\" ------------------------------------------------------------------ +.SH OPTIONS +.\" ---------------------------------------------- +.IP \fB\-\-pacc\fP +Print a summary of all accepted messages. The match count for each rule is +listed. +. +.\" ---------------------------------------------- +.IP \fB\-\-help\fP +print full help. +. +.\" ------------------------------------------------------------------ +.SH MESSAGE FILTER FILE FORMAT +.\" ---------------------------------------------- +Simply a list of match rules structured by section headers +of the form "[TYPE]". '#' is interpreted as comment delimiter, everything +after a '#' in a line will be ignored. +xviv_msg_filter will extract the rules of the section matching the +\fITYPE\fP argument. + +A line starting with '@' specifies a nested mfset file. This allows to +store the message filter sets in a structured way and factor out common +rule sets in separate files. + +Each rule line has the format +.EX + [] +.EE +with +.IP \fBmode\fP 10 +determines how the rule is applied +.RS +.PD 0 +.IP \fBI\fP 4 +matching messages are ignored +.IP \fBi\fP 4 +matching messages are not printed, if no matching message is found a +notifivation is printed. +.IP \fBr\fP 4 +signals that at least one matching message is required, if none seen, a +notifivation is printed. +.PD +.RE +.IP \fBname\fP +vivado message name, enclosed in [] brackets +.IP \fBpattern\fP +regular expression to match the message text. This field is optional, if +omitted all messages with th given name will match. '[' and ']' characters +are escaped to '\\[' and '\\]', because [] is very often part of signal +names. Character set matches are therefore not possible. + +.SS Example message filter file +.EX + # ----------- + [syn] + i [Designutils 20-1567] # false_path -hold and synth + # unused sequential element + i [Synth 8-3332] R_LREGS_reg[attn][\\d*] + i [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\\d*] + # ----------- + [imp] + I [Vivado 12-2489] # multiple of 1 ps +.EE +.\" ------------------------------------------------------------------ +.SH EXIT STATUS +If \fITYPE\fP is invalid or the \fIVMFSET\fP or \fILOGFILE\fP files +can't be opened an exit status 1 is returned. + +.\" ------------------------------------------------------------------ +.SH EXAMPLES +.IP "\fBxviv_msg_filter syn proj.vmfset proj_syn.log\fR" 4 +Generate a short summary of the vivado synthesis log file. +. +.\" ------------------------------------------------------------------ +.SH "SEE ALSO" +.BR xviv_msg_summary (1) +. +.\" ------------------------------------------------------------------ +.SH AUTHOR +Walter F.J. Mueller diff --git a/doc/man/man1/xviv_msg_summary.1 b/doc/man/man1/xviv_msg_summary.1 new file mode 100644 index 00000000..c1f28dff --- /dev/null +++ b/doc/man/man1/xviv_msg_summary.1 @@ -0,0 +1,34 @@ +.\" -*- nroff -*- +.\" $Id: xviv_msg_summary.1 779 2016-06-26 15:37:16Z mueller $ +.\" +.\" Copyright 2016- by Walter F.J. Mueller +.\" +.\" ------------------------------------------------------------------ +.TH XVIV_MSG_SUMMARY 1 2016-06-05 "Retro Project" "Retro Project Manual" +.\" ------------------------------------------------------------------ +.SH NAME +xviv_msg_summary \- summarize all Vivado tool chain log files +.\" ------------------------------------------------------------------ +.SH SYNOPSIS +. +.SY xviv_msg_summary +.YS +. +.\" ------------------------------------------------------------------ +.SH DESCRIPTION +.\" ---------------------------------------------- +Scans the current and all sub-directories for .vmfset files and calls for +each message filter set +.EX + make \fIbasename\fP.mfsum +.EE +which in turn will use \fBxviv_msg_filter\fP(1) to show unexpected messages +from all relevant log files and reports. +. +.\" ------------------------------------------------------------------ +.SH "SEE ALSO" +.BR xviv_msg_filter (1) +. +.\" ------------------------------------------------------------------ +.SH AUTHOR +Walter F.J. Mueller diff --git a/doc/man/man1/xviv_sim_vhdl_cleanup.1 b/doc/man/man1/xviv_sim_vhdl_cleanup.1 new file mode 100644 index 00000000..0498f980 --- /dev/null +++ b/doc/man/man1/xviv_sim_vhdl_cleanup.1 @@ -0,0 +1,37 @@ +.\" -*- nroff -*- +.\" $Id: xviv_sim_vhdl_cleanup.1 779 2016-06-26 15:37:16Z mueller $ +.\" +.\" Copyright 2016- by Walter F.J. Mueller +.\" +.\" ------------------------------------------------------------------ +.TH XVIV_SIM_VHDL_CLEANUP 1 2016-06-05 "Retro Project" "Retro Project Manual" +.\" ------------------------------------------------------------------ +.SH NAME +xviv_sim_vhdl_cleanup \- cleanup vivado generated vhdl for ghdl +.\" ------------------------------------------------------------------ +.SH SYNOPSIS +. +.SY xviv_sim_vhdl_cleanup +.I file +.YS +. +.\" ------------------------------------------------------------------ +.SH DESCRIPTION +.\" ---------------------------------------------- +The vivado write_vhdl command generates code which violates a vhdl language +rule. Attributes of port signals are declared in the architecture, but should +be in the entiry declaration. xsim and other simulators accept this, but +\fBghdl\fP(1) doesn't. This script simply filters out lines like +.EX + attribute .... RTL_KEEP +.EE +Since attributes are ignored by \fBghdl\fP(1) anyway this avoids the +problem without any other side effects. +. +.\" ------------------------------------------------------------------ +.SH "SEE ALSO" +.BR ghdl (1) +. +.\" ------------------------------------------------------------------ +.SH AUTHOR +Walter F.J. Mueller diff --git a/doc/man/man5/vbom.5 b/doc/man/man5/vbom.5 index e105ad60..529d7c27 100644 --- a/doc/man/man5/vbom.5 +++ b/doc/man/man5/vbom.5 @@ -1,5 +1,5 @@ .\" -*- nroff -*- -.\" $Id: vbom.5 746 2016-03-19 13:08:36Z mueller $ +.\" $Id: vbom.5 779 2016-06-26 15:37:16Z mueller $ .\" .\" Copyright 2010-2016 by Walter F.J. Mueller .\" @@ -34,7 +34,7 @@ Either source files or nested \fBvbom\fP's. The file names must be given as relative path name from the directory the \fBvbom\fP file is located in. Absolute path names are not allowed, nor is expansion of environment variables. -Currently three file types are accepted: +Currently the following file types are accepted: .RS .IP "\fB.vbom\fP" 6 refers to a nested \fBvbom\fP. Usually used for instantiated components. @@ -58,6 +58,27 @@ via the \fIvhpi\fP mechanism. Supported only in conjunction with \fBghdl\fP. . .RE . +.\" ---------------------------------------------- +.IP "\fBFile attributes\fP" +File names can be followed by a list of attributes of the form +.EX + -\fIname\fP[:\fIvalue\fP] ... +.EE +Currently the following attributes are recognized +.RS +.IP "\fB-UUT\fP" 6 +Signals that the \fIvbom\fP descibes a test bench and that file is +the 'unit under test'. This allows to split the sources into a simulation +only test bench part and a synthesizable 'unit under test' part. The file +is typically a \fIvbom\fP in case of a behavioural simulation or the file +name of a generated model for a functional or timing simulation. +. +.IP "\fB-SCOPE_REF[:\fIentity\fP]\fP" 6 +Signals that the xdc file should be 'scoped to reference' to \fIentity\fP. +If \fIentity\fP is omitted the filename is taken as entity name. +In general used together with the \fB@xdc:\fP directive. +. +.RE . .\" ---------------------------------------------- .IP "\fBConditional file names\fP" @@ -104,21 +125,22 @@ included in conjunction with simulation (ghdl,isim,vsim) .IP "\fBLogical names\fP" A logical name can be defined with .EX - = + \fIlname\fP = \fIfilename\fP .EE The first definition of a logical name encountered in the traversal of the \fBvbom\fP's by \fBvbomconv\fP(1) is taken, all later definitions are ignored. A logical name can be used with .EX - : + ${\fIlname\fP} + ${\fIlname\fP := \fIdefault\fP} .EE -The filename in the usage clause is the default used in case the -logical name wasn't defined before it is used. +In the first form \fIlname\fP must have been defined before. +The second form allows to specify a \fIdefault\fP which is used when +\fIlname\fP hasn't been defined so far. -Again, the filenames, either of type \fI.vhd\fP or \fI.vbom\fP , -must be given as relative path name from the directory the \fBvbom\fP -file is located in. +Again, the filenames must be given as relative path name from the directory +the \fBvbom\fP file is located in. .\" ---------------------------------------------- .IP \fBDirectives\fP @@ -134,13 +156,6 @@ Specifies an additional system library. Allowed values for \fIname\fP are Currently used to generate the appropriate -L options for \fBghdl\fP commands, e.g. generated by the \fBvbomconv\fP action \fB\-\-ghdl_m\fP. . -.IP "\fB@uut\fP:\fIfile\fP" -Signals that the \fIvbom\fP descibes a test bench and that \fIfile\fP is -the 'unit under test'. This allows to split the sources into a simulation -only test bench part and a synthesizable 'unit under test' part. \fIfile\fP -is typically a \fIvbom\fP in case of a functional simulation or the file -name of a generated post synthesis model. -. .IP "\fB@xdc\fP:\fIfile\fP" Specifies that \fIfile\fP is a constraint file for Vivado synthesis and should be included in the constraints fileset. diff --git a/doc/w11a_os_guide.txt b/doc/w11a_os_guide.txt index b5f0895b..2f05768c 100644 --- a/doc/w11a_os_guide.txt +++ b/doc/w11a_os_guide.txt @@ -1,4 +1,4 @@ -# $Id: w11a_os_guide.txt 745 2016-03-18 22:10:34Z mueller $ +# $Id: w11a_os_guide.txt 779 2016-06-26 15:37:16Z mueller $ Guide to run operating system images on w11a systems @@ -107,7 +107,7 @@ Guide to run operating system images on w11a systems - for arty over serial SWI = 0110 (gives console light emulation...) - ti_w11 -tu,10M,break,xon @_boot.tcl + ti_w11 -tu,12M,break,xon @_boot.tcl NOTE: the arty w11a has currently only 176 kB memory (all from BRAMS!) unix-v5 works fine. XXDP, RT11 and RSX-11M should work. @@ -123,7 +123,7 @@ Guide to run operating system images on w11a systems - for n4 over serial SWI = 00000000 00101000 (gives console light display on LEDS) - ti_w11 -tu,10M,break,cts @_boot.tcl + ti_w11 -tu,12M,break,cts @_boot.tcl - for n2,n3 over fx2 SWI = 00101100 @@ -164,7 +164,7 @@ Guide to run operating system images on w11a systems 4. simh simulator setup --------------------------------------------------- - Sometimes it is good to compare the w11a behaviour with the PDP-11 software + Sometimes it is good to compare the w11a behavior with the PDP-11 software emulator from the simh project (see http://simh.trailing-edge.com/). Under $RETROBASE/tools/simh two setup files are provided with configure diff --git a/doc/w11a_tb_guide.txt b/doc/w11a_tb_guide.txt index cba088ca..9c844d68 100644 --- a/doc/w11a_tb_guide.txt +++ b/doc/w11a_tb_guide.txt @@ -1,9 +1,10 @@ -# $Id: w11a_tb_guide.txt 745 2016-03-18 22:10:34Z mueller $ +# $Id: w11a_tb_guide.txt 779 2016-06-26 15:37:16Z mueller $ -Note: - Ghdl is used to all functional simulations - - Optionally Vivado xsim can be used (with some limitations) - - For post synthesis or post implementation simulations either - Ghdl or Vivado xsim (with some limitations) can be used. +Note: - Ghdl is used for all behavioral simulations + - Optionally Vivado xsim can be used + - For post synthesis or post implementation functionnal simulations + either Ghdl or Vivado xsim can be used. + - For timing simulations only Vivado xsim can be used. - ISE isim is also available, but considered legacy support Guide to running w11a test benches @@ -47,27 +48,18 @@ Guide to running w11a test benches produce a single DONE line - Most tests can be run against - - the functional model + - the behavioral model + - post-synthesis functional + - post-optimization functional + - post-routing functional + - post-synthesis timing + - post-optimization timing + - post-routing timing - - gate level models at three stages (vivado flow) - - the post synthesis model (from *_syn.dcp) - - the post optimization model (from *_opt.dcp) - - the post routing model (from *_rou.dcp) - This is simply done using - make _ssim for post-synthesis - make _osim for post-optimization - make _tsim for post-routing + Building the simulation models is handled by the build environment. See + README_buildsystem_Vivado.txt for details of the vivado flow and + README_buildsystem_ISE.txt for the ISE flow. - - gate level models at three stages (ISE flow) - - the post-xst model (produced by netgen from ngc xst output) - - the post-map model (produced by netgen from ncd ngdbuild output) - - the post-par model (produced by netgen from ncd par output) - This is simply done using - make _ssim for post-xst - make _fsim for post-map - make _tsim for post-par - - All the rest is handled by the build environment. An example of a post-synthesis model is given for the w11a core test. - for convenience a wrapper script 'tbrun_tbw' is used to generate the @@ -85,69 +77,76 @@ Guide to running w11a test benches cd $RETROBASE/rtl/vlib/serport/tb tbrun_tbw tb_serport_uart_rx -> 1269955.0 ns 63488: DONE - -> real 0m0.444s user 0m0.453s sys 0m0.007s + -> real 0m0.531s user 0m0.392s sys 0m0.014s - serport receiver/transmitter test tbrun_tbw tb_serport_uart_rxtx -> 52335.0 ns 2607: DONE - -> real 0m0.074s user 0m0.077s sys 0m0.010s + -> real 0m0.120s user 0m0.065s sys 0m0.013s - serport autobauder test tbrun_tbw tb_serport_autobaud -> 367475.0 ns 18364: DONE - -> real 0m0.247s user 0m0.258s sys 0m0.007s + -> real 0m0.343s user 0m0.316s sys 0m0.003s - 9 bit comma,data to Byte stream converter test cd $RETROBASE/rtl/vlib/comlib/tb tbrun_tbw tb_cdata2byte -> 7261.0 ns 354: DONE - -> real 0m0.042s user 0m0.042s sys 0m0.019s + -> real 0m0.088s user 0m0.057s sys 0m0.013s - rlink core test cd $RETROBASE/rtl/vlib/rlink/tb tbrun_tbw tb_rlink_direct -> 78975.0 ns 3939: DONE - -> real 0m0.225s user 0m0.226s sys 0m0.025s + -> real 0m0.270s user 0m0.222s sys 0m0.026s - rlink core test via serial port interface cd $RETROBASE/rtl/vlib/rlink/tb - tbrun_tbw --lsuf stim2_dsim tb_rlink_sp1c tb_rlink_sp1c_stim.dat + tbrun_tbw --lsuf stim2_bsim tb_rlink_sp1c tb_rlink_sp1c_stim.dat -> 27595.0 ns 1370: DONE - -> real 0m0.098s user 0m0.111s sys 0m0.007s + -> real 0m0.184s user 0m0.145s sys 0m0.011s - tbrun_tbw --lsuf stim1_dsim tb_rlink_sp1c tb_rlink_stim.dat + tbrun_tbw --lsuf stim1_bsim tb_rlink_sp1c tb_rlink_stim.dat -> 420295.0 ns 21005: DONE - -> real 0m0.942s user 0m0.947s sys 0m0.012s + -> real 0m0.939s user 0m0.945s sys 0m0.026s - - w11a core test (using behavioural model) + - w11a core test + - using behavioral model - cd $RETROBASE/rtl/w11a/tb - tbrun_tbw tb_pdp11core - -> 225355.0 ns 61258: DONE - -> real 0m6.280s user 0m6.284s sys 0m0.018s + cd $RETROBASE/rtl/w11a/tb + tbrun_tbw tb_pdp11core + -> 225355.0 ns 61258: DONE + -> real 0m6.446s user 0m6.387s sys 0m0.024s - - w11a core test (using Vivado post-synthesis model) + - using Vivado post-synthesis vhdl model and ghdl - tbrun_tbw tb_pdp11core_ssim - -> 225355.0 ns 61258: DONE - -> real 2m4.138s user 2m4.063s sys 0m0.050s + tbrun_tbw tb_pdp11core_ssim + -> 1225355.0 ns 61258: DONE + -> real 1m40.446s user 1m40.344s sys 0m0.075s + + - using Vivado post-synthesis verilog model and xsim + + tbrun_tbw tb_pdp11core_XSim_ssim + -> 1225355.0 ns 61258: DONE + -> real 1m14.835s user 1m13.997s sys 0m1.011s - s3board sram controller test cd $RETROBASE/rtl/bplib/s3board/tb tbrun_tbw tb_s3_sram_memctl -> 5015.0 ns 241: DONE - -> real 0m0.107s user 0m0.055s sys 0m0.020s + -> real 0m0.075s user 0m0.045s sys 0m0.022s - nexys2/nexys3 cram controller test cd $RETROBASE/rtl/bplib/nxcramlib/tb tbrun_tbw tb_nx_cram_memctl_as -> 24272.5 ns 1204: DONE - -> real 0m0.189s user 0m0.149s sys 0m0.055s + -> real 0m0.337s user 0m0.147s sys 0m0.146s 3. System tests benches --------------------------------------------------- @@ -177,25 +176,25 @@ Guide to running w11a test benches cd $RETROBASE/rtl/sys_gen/tst_serloop/s3board/tb tbrun_tbw tb_tst_serloop_s3 -> 301353.3 ns 18068: DONE - -> real 0m0.765s user 0m0.781s sys 0m0.013s + -> real 0m0.832s user 0m0.765s sys 0m0.036s - sys_tst_serloop_n2 test bench cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys2/tb tbrun_tbw tb_tst_serloop1_n2 -> 361560.0 ns 18068: DONE - -> real 0m0.994s user 0m0.991s sys 0m0.022s + -> real 0m0.799s user 0m0.758s sys 0m0.021s tbrun_tbw tb_tst_serloop2_n2 -> 304353.3 ns 18248: DONE - -> real 0m1.543s user 0m1.561s sys 0m0.007s + -> real 0m1.274s user 0m1.236s sys 0m0.017s - sys_tst_serloop_n3 test bench cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys3/tb tbrun_tbw tb_tst_serloop1_n3 -> 361560.0 ns 18068: DONE - -> real 0m0.740s user 0m0.755s sys 0m0.012s + -> real 0m0.841s user 0m0.820s sys 0m0.014s 4b. rlink tester ----------------------------------------------------- @@ -209,24 +208,24 @@ Guide to running w11a test benches cd $RETROBASE/rtl/sys_gen/tst_rlink/arty/tb tbrun_tbwrri --hxon --pack tst_rlink tb_tst_rlink_arty \ "tst_rlink::setup" "tst_rlink::test_all" - -> 764400.0 ns 76419: DONE - -> real 0m9.323s user 0m9.233s sys 0m0.080s + -> 1028590.0 ns 102838: DONE + -> real 0m14.163s user 0m12.637s sys 0m0.152s - sys_tst_rlink_b3 test bench cd $RETROBASE/rtl/sys_gen/tst_rlink/basys3/tb tbrun_tbwrri --hxon --pack tst_rlink tb_tst_rlink_b3 \ "tst_rlink::setup" "tst_rlink::test_all" - -> 763900.0 ns 76369: DONE - -> real 0m6.804s user 0m6.696s sys 0m0.085s - + -> 1028820.0 ns 102861: DONE + -> real 0m9.275s user 0m9.041s sys 0m0.094s + - sys_tst_rlink_n4 test bench cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys4/tb tbrun_tbwrri --pack tst_rlink tb_tst_rlink_n4 \ "tst_rlink::setup" "tst_rlink::test_all" - -> 758010.0 ns 75780: DONE - -> real 0m10.198s user 0m10.081s sys 0m0.104s + -> 1020240.0 ns 102003: DONE + -> real 0m9.751s user 0m9.544s sys 0m0.081s - Spartan based systems @@ -236,24 +235,24 @@ Guide to running w11a test benches cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3/tb tbrun_tbwrri --fusp --pack tst_rlink tb_tst_rlink_n3 \ "tst_rlink::setup" "tst_rlink::test_all" - -> 763770.0 ns 76356: DONE - -> real 0m5.955s user 0m5.834s sys 0m0.094s + -> 1024980.0 ns 102477: DONE + -> real 0m8.081s user 0m7.904s sys 0m0.106s - sys_tst_rlink_n2 test bench cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb tbrun_tbwrri --fusp --pack tst_rlink tb_tst_rlink_n2 \ "tst_rlink::setup" "tst_rlink::test_all" - -> 1526860.0 ns 76332: DONE - -> real 0m8.607s user 0m8.448s sys 0m0.150s - + -> 2049320.0 ns 102455: DONE + -> real 0m7.934s user 0m7.748s sys 0m0.114s + - sys_tst_rlink_s3 test bench cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board/tb tbrun_tbwrri --fusp --pack tst_rlink tb_tst_rlink_s3 \ "tst_rlink::setup" "tst_rlink::test_all" - -> 1526540.0 ns 76317: DONE - -> real 0m5.650s user 0m5.571s sys 0m0.052s + -> 2049720.0 ns 102476: DONE + -> real 0m7.612s user 0m7.437s sys 0m0.075s 4c. rlink tester, Cypress FX2 based version -------------------------- @@ -266,16 +265,16 @@ Guide to running w11a test benches cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb tbrun_tbwrri --cuff --pack tst_rlink tb_tst_rlink_cuff_ic_n3 \ "tst_rlink::setup" "tst_rlink::test_all" - -> 440440.0 ns 44023: DONE - -> real 0m4.062s user 0m3.922s sys 0m0.111s + -> 558770.0 ns 55856: DONE + -> real 0m7.679s user 0m7.433s sys 0m0.185s - sys_tst_rlink_cuff_ic_n2 test bench cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb tbrun_tbwrri --cuff --pack tst_rlink tb_tst_rlink_cuff_ic_n2 \ "tst_rlink::setup" "tst_rlink::test_all" - -> 466940.0 ns 23336: DONE - -> real 0m2.831s user 0m2.696s sys 0m0.101s + -> 596300.0 ns 29804: DONE + -> real 0m3.741s user 0m3.542s sys 0m0.127s 4d. w11a systems ----------------------------------------------------- @@ -296,8 +295,8 @@ Guide to running w11a test benches tbrun_tbwrri --pack rw11 tb_w11a_n4 \ "rw11::setup_cpu" \ "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" - -> 6681310.0 ns 534488: DONE - -> real 1m26.253s user 1m26.139s sys 0m0.430s + -> 4812818.3 ns 577513: DONE + -> real 1m11.139s user 1m10.726s sys 0m0.545s - Spartan based systems - sys_w11a_n3 test bench @@ -306,8 +305,8 @@ Guide to running w11a test benches tbrun_tbwrri --cuff --pack rw11 tb_w11a_n3 \ "rw11::setup_cpu" \ "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" - -> 3614866.2 ns 231338: DONE - -> real 0m47.290s user 0m46.975s sys 0m0.537s + -> 3612428.7 ns 231182: DONE + -> real 0m47.454s user 0m47.241s sys 0m0.456s - sys_w11a_n2 test bench @@ -315,18 +314,18 @@ Guide to running w11a test benches tbrun_tbwrri --cuff --pack rw11 tb_w11a_n2 \ "rw11::setup_cpu" \ "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" - -> 4007500.0 ns 200364: DONE - -> real 0m43.803s user 0m43.698s sys 0m0.400s - + -> 4009900.0 ns 200484: DONE + -> real 0m45.429s user 0m45.215s sys 0m0.480s + - sys_w11a_s3 test bench cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb tbrun_tbwrri --fusp --pack rw11 tb_w11a_s3 \ "rw11::setup_cpu" \ "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" - -> 10526060.0 ns 526293: DONE - -> real 1m13.659s user 1m13.467s sys 0m0.431s - + -> 10528880.0 ns 526434: DONE + -> real 1m13.706s user 1m13.483s sys 0m0.470s + A new, modular w11a test bench is under construction. So far it is very incomplete. This very preliminary version can be executed with @@ -334,13 +333,13 @@ Guide to running w11a test benches - sys_w11a_n2 test bench cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb - tbrun_tbwrri --cuff --lsuf tbench_dsim --pack rw11 tb_w11a_n2 \ + tbrun_tbwrri --cuff --lsuf tbench_bsim --pack rw11 tb_w11a_n2 \ "rw11::setup_cpu" "rw11::tbench @cpu_all.dat" - -> 3280220.0 ns 164000: DONE - -> real 0m30.190s user 0m30.843s sys 0m0.577s + -> 3268940.0 ns 163436: DONE + -> real 0m30.761s user 0m31.576s sys 0m0.502s - tbrun_tbwrri --cuff --lsuf tbench_dsim --pack rw11 tb_w11a_n2 \ + tbrun_tbwrri --cuff --lsuf tbench_bsim --pack rw11 tb_w11a_n2 \ "rw11::setup_cpu" "rw11::tbench @dev_all.dat" - -> 1387300.0 ns 69354: DONE - -> real 0m14.298s user 0m14.314s sys 0m0.240s + -> 1376360.0 ns 68807: DONE + -> real 0m16.991s user 0m17.049s sys 0m0.235s diff --git a/rtl/bplib/arty/arty_pins.xdc b/rtl/bplib/arty/arty_pins.xdc index e47a6cc9..22d3a29c 100644 --- a/rtl/bplib/arty/arty_pins.xdc +++ b/rtl/bplib/arty/arty_pins.xdc @@ -1,15 +1,20 @@ # -*- tcl -*- -# $Id: arty_pins.xdc 740 2016-03-06 20:56:56Z mueller $ +# $Id: arty_pins.xdc 758 2016-04-02 18:01:39Z mueller $ # # Copyright 2016- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # -# Pin locks for Digilent Arty core functionality -# - USB UART -# - human I/O (switches, buttons, leds) +# Digilent Arty core functionality +# - Configuration setup +# - config voltage +# - enable bitstream timestamp +# - Pin Locks for +# - USB UART +# - human I/O (switches, buttons, leds) # # Revision History: # Date Rev Version Comment +# 2016-04-02 758 1.2 add BITSTREAM.CONFIG.USR_ACCESS setup # 2016-03-06 740 1.1 add A_VPWRP/N to baseline config # 2016-01-31 726 1.0 Initial version # @@ -17,6 +22,7 @@ # config setup -------------------------------------------------------------- set_property CFGBVS VCCO [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] # clocks -- in bank 35 ------------------------------------------------------ set_property PACKAGE_PIN e3 [get_ports {I_CLK100}] diff --git a/rtl/bplib/arty/tb/Makefile b/rtl/bplib/arty/tb/Makefile index 1f091bcb..bff119a9 100644 --- a/rtl/bplib/arty/tb/Makefile +++ b/rtl/bplib/arty/tb/Makefile @@ -1,30 +1,41 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $ # # Revision History: # Date Rev Version Comment +# 2016-06-18 776 1.1.1 add xsim_clean +# 2016-04-22 763 1.1 add include dep_vsim # 2016-01-31 726 1.0 Initial version # EXE_all = tb_arty_dummy # include ${RETROBASE}/rtl/make_viv/viv_default_arty.mk # -.PHONY : all all_ssim clean +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim # all : $(EXE_all) all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) # -clean : viv_clean ghdl_clean +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean # #----- # -include ${RETROBASE}/rtl/make_viv/generic_vivado.mk include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # VBOM_all = $(wildcard *.vbom) # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_vsyn) include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) include $(wildcard *.o.dep_ghdl) endif # diff --git a/rtl/bplib/arty/tb/tb_arty.vbom b/rtl/bplib/arty/tb/tb_arty.vbom index d10c6c8e..a3ad0bd5 100644 --- a/rtl/bplib/arty/tb/tb_arty.vbom +++ b/rtl/bplib/arty/tb/tb_arty.vbom @@ -17,7 +17,7 @@ ${sys_conf := sys_conf_sim.vhd} ../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom tb_arty_core.vbom ../../../vlib/serport/tb/serport_master_tb.vbom -@uut: ${arty_aif := arty_dummy.vbom} +${arty_aif := arty_dummy.vbom} -UUT # design tb_arty.vhd @top:tb_arty diff --git a/rtl/bplib/arty/tb/tb_arty.vhd b/rtl/bplib/arty/tb/tb_arty.vhd index 54f5a1d6..508b250c 100644 --- a/rtl/bplib/arty/tb/tb_arty.vhd +++ b/rtl/bplib/arty/tb/tb_arty.vhd @@ -1,4 +1,4 @@ --- $Id: tb_arty.vhd 740 2016-03-06 20:56:56Z mueller $ +-- $Id: tb_arty.vhd 748 2016-03-20 15:18:50Z mueller $ -- -- Copyright 2016- by Walter F.J. Mueller -- @@ -30,6 +30,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-03-20 748 1.2 BUGFIX: add PORTSEL_XON logic -- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config -- 2016-02-20 734 1.0.2 use s7_cmt_sfs_tb to avoid xsim conflict -- 2016-02-13 730 1.0.1 direct instantiation of tbcore_rlink @@ -81,6 +82,10 @@ architecture sim of tb_arty is signal O_RGBLED2 : slv3 := (others=>'0'); signal O_RGBLED3 : slv3 := (others=>'0'); + signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff + + constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); + constant clock_period : time := 10 ns; constant clock_offset : time := 200 ns; @@ -152,7 +157,7 @@ begin CLK => CLKCOM, RESET => RESET, CLKDIV => CLKDIV, - ENAXON => '0', -- FIXME: or 1 ??? + ENAXON => R_PORTSEL_XON, ENAESC => '0', RXDATA => RXDATA, RXVAL => RXVAL, @@ -183,4 +188,19 @@ begin end process proc_moni; + -- + -- Notes on portsel and XON control: + -- - most arty designs will use hardwired XON=1 + -- - but some (especially basis tests) might not use flow control + -- - that's why XON flow control must be optional and configurable ! + -- + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_portsel then + R_PORTSEL_XON <= to_x01(SB_DATA(1)); + end if; + end if; + end process proc_simbus; + end sim; diff --git a/rtl/bplib/basys3/basys3_pins.xdc b/rtl/bplib/basys3/basys3_pins.xdc index a5f9de88..ef25f6b7 100644 --- a/rtl/bplib/basys3/basys3_pins.xdc +++ b/rtl/bplib/basys3/basys3_pins.xdc @@ -1,21 +1,27 @@ # -*- tcl -*- -# $Id: basys3_pins.xdc 726 2016-01-31 23:02:31Z mueller $ +# $Id: basys3_pins.xdc 758 2016-04-02 18:01:39Z mueller $ # -# Copyright 2015- by Walter F.J. Mueller +# Copyright 2015-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # -# Pin locks for Digilent Basys 3 core functionality -# - USB UART -# - human I/O (switches, buttons, leds, display) +# Digilent Basys 3 core functionality +# - Configuration setup +# - config voltage +# - enable bitstream timestamp +# - Pin Locks for +# - USB UART +# - human I/O (switches, buttons, leds, display) # # Revision History: # Date Rev Version Comment +# 2016-04-02 758 1.1 add BITSTREAM.CONFIG.USR_ACCESS setup # 2015-01-30 640 1.0 Initial version # # config setup -------------------------------------------------------------- set_property CFGBVS VCCO [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] # clocks -- in bank 34 ------------------------------------------------------ set_property PACKAGE_PIN w5 [get_ports {I_CLK100}] diff --git a/rtl/bplib/basys3/tb/tb_basys3.vbom b/rtl/bplib/basys3/tb/tb_basys3.vbom index d2a55abb..8f06f9c9 100644 --- a/rtl/bplib/basys3/tb/tb_basys3.vbom +++ b/rtl/bplib/basys3/tb/tb_basys3.vbom @@ -17,7 +17,7 @@ ${sys_conf := sys_conf_sim.vhd} ../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom tb_basys3_core.vbom ../../../vlib/serport/tb/serport_master_tb.vbom -@uut: ${basys3_aif := basys3_dummy.vbom} +${basys3_aif := basys3_dummy.vbom} -UUT # design tb_basys3.vhd @top:tb_basys3 diff --git a/rtl/bplib/basys3/tb/tb_basys3.vhd b/rtl/bplib/basys3/tb/tb_basys3.vhd index 1bbbd21e..e5733618 100644 --- a/rtl/bplib/basys3/tb/tb_basys3.vhd +++ b/rtl/bplib/basys3/tb/tb_basys3.vhd @@ -1,4 +1,4 @@ --- $Id: tb_basys3.vhd 734 2016-02-20 22:43:20Z mueller $ +-- $Id: tb_basys3.vhd 748 2016-03-20 15:18:50Z mueller $ -- -- Copyright 2015-2016 by Walter F.J. Mueller -- @@ -26,7 +26,7 @@ -- To test: generic, any basys3_aif target -- -- Target Devices: generic --- Tool versions: viv 2014.4-2015.4; ghdl 0.31 +-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 -- -- Revision History: -- Date Rev Version Comment @@ -182,6 +182,12 @@ begin end process proc_moni; + -- + -- Notes on portsel and XON control: + -- - most basys3 designs will use hardwired XON=1 + -- - but some (especially basis tests) might not use flow control + -- - that's why XON flow control must be optional and configurable ! + -- proc_simbus: process (SB_VAL) begin if SB_VAL'event and to_x01(SB_VAL)='1' then diff --git a/rtl/bplib/bpgen/Makefile b/rtl/bplib/bpgen/Makefile.ise similarity index 89% rename from rtl/bplib/bpgen/Makefile rename to rtl/bplib/bpgen/Makefile.ise index f8e67068..5f8b5a6d 100644 --- a/rtl/bplib/bpgen/Makefile +++ b/rtl/bplib/bpgen/Makefile.ise @@ -1,4 +1,5 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ # # Revision History: # Date Rev Version Comment diff --git a/rtl/bplib/bpgen/bp_swibtnled.vhd b/rtl/bplib/bpgen/bp_swibtnled.vhd index 33971cd8..0a202db6 100644 --- a/rtl/bplib/bpgen/bp_swibtnled.vhd +++ b/rtl/bplib/bpgen/bp_swibtnled.vhd @@ -1,4 +1,4 @@ --- $Id: bp_swibtnled.vhd 637 2015-01-25 18:36:40Z mueller $ +-- $Id: bp_swibtnled.vhd 756 2016-03-29 21:49:46Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -22,7 +22,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31 +-- Tool versions: ise 11.4-14.7; viv 2014.4-2015.4; ghdl 0.26-0.33 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/bplib/bpgen/sn_7segctl.vhd b/rtl/bplib/bpgen/sn_7segctl.vhd index 71698900..9e3dcfd1 100644 --- a/rtl/bplib/bpgen/sn_7segctl.vhd +++ b/rtl/bplib/bpgen/sn_7segctl.vhd @@ -1,4 +1,4 @@ --- $Id: sn_7segctl.vhd 637 2015-01-25 18:36:40Z mueller $ +-- $Id: sn_7segctl.vhd 750 2016-03-24 23:11:51Z mueller $ -- -- Copyright 2007-2015 by Walter F.J. Mueller -- @@ -100,11 +100,11 @@ begin assert DCWIDTH=2 or DCWIDTH=3 report "assert(DCWIDTH=2 or DCWIDTH=3): unsupported DCWIDTH" - severity FAILURE; + severity failure; assert CDWIDTH >= 5 report "assert(CDWIDTH >= 5): CDWIDTH too small" - severity FAILURE; + severity failure; proc_regs: process (CLK) begin diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom b/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom index ebc62f73..76708d85 100644 --- a/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom +++ b/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom @@ -17,7 +17,7 @@ ${sys_conf := sys_conf_sim.vhd} ../../../vlib/xlib/dcm_sfs_gsim.vbom tb_nexys2_core.vbom ../../../vlib/serport/tb/serport_master_tb.vbom -@uut: ${nexys2_fusp_aif := nexys2_fusp_dummy.vbom} +${nexys2_fusp_aif := nexys2_fusp_dummy.vbom} -UUT # design tb_nexys2_fusp.vhd @top:tb_nexys2_fusp diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom b/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom index 14c839aa..b99b1519 100644 --- a/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom +++ b/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom @@ -18,7 +18,7 @@ ${sys_conf := sys_conf_sim.vhd} tb_nexys2_core.vbom ../../../vlib/serport/tb/serport_master_tb.vbom ../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom -@uut: ${nexys2_fusp_cuff_aif := nexys2_fusp_cuff_dummy.vbom} +${nexys2_fusp_cuff_aif := nexys2_fusp_cuff_dummy.vbom} -UUT # design tb_nexys2_fusp_cuff.vhd @top:tb_nexys2_fusp_cuff diff --git a/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom b/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom index 814c610d..9d6d6542 100644 --- a/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom +++ b/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom @@ -17,7 +17,7 @@ ${sys_conf := sys_conf_sim.vhd} ../../../vlib/xlib/s6_cmt_sfs_gsim.vbom tb_nexys3_core.vbom ../../../vlib/serport/tb/serport_master_tb.vbom -@uut: ${nexys3_fusp_aif := nexys3_fusp_dummy.vbom} +${nexys3_fusp_aif := nexys3_fusp_dummy.vbom} -UUT # design tb_nexys3_fusp.vhd @top:tb_nexys3_fusp diff --git a/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom b/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom index fe8704a1..ccc05be8 100644 --- a/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom +++ b/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom @@ -18,7 +18,7 @@ ${sys_conf := sys_conf_sim.vhd} tb_nexys3_core.vbom ../../../vlib/serport/tb/serport_master_tb.vbom ../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom -@uut: ${nexys3_fusp_cuff_aif := nexys3_fusp_cuff_dummy.vbom} +${nexys3_fusp_cuff_aif := nexys3_fusp_cuff_dummy.vbom} -UUT # design tb_nexys3_fusp_cuff.vhd @top:tb_nexys3_fusp_cuff diff --git a/rtl/bplib/nexys4/nexys4_pins.xdc b/rtl/bplib/nexys4/nexys4_pins.xdc index c5288103..05df96cb 100644 --- a/rtl/bplib/nexys4/nexys4_pins.xdc +++ b/rtl/bplib/nexys4/nexys4_pins.xdc @@ -1,12 +1,20 @@ # -*- tcl -*- -# $Id: nexys4_pins.xdc 726 2016-01-31 23:02:31Z mueller $ +# $Id: nexys4_pins.xdc 758 2016-04-02 18:01:39Z mueller $ # -# Pin locks for Nexys 4 core functionality -# - USB UART -# - human I/O (switches, buttons, leds, display) +# Copyright 2015-2016 by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Nexys 4 core functionality +# - Configuration setup +# - config voltage +# - enable bitstream timestamp +# - Pin Locks for +# - USB UART +# - human I/O (switches, buttons, leds, display) # # Revision History: # Date Rev Version Comment +# 2016-04-02 758 1.4 add BITSTREAM.CONFIG.USR_ACCESS setup # 2015-02-06 643 1.3 factor out cram # 2015-02-01 641 1.2 separate I_BTNRST_N # 2015-01-31 640 1.1 fix RTS/CTS @@ -16,6 +24,7 @@ # config setup -------------------------------------------------------------- set_property CFGBVS VCCO [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] # clocks -- in bank 35 ------------------------------------------------------ set_property PACKAGE_PIN e3 [get_ports {I_CLK100}] diff --git a/rtl/bplib/nexys4/tb/Makefile b/rtl/bplib/nexys4/tb/Makefile index de3a39d7..18375d92 100644 --- a/rtl/bplib/nexys4/tb/Makefile +++ b/rtl/bplib/nexys4/tb/Makefile @@ -1,30 +1,41 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $ # # Revision History: # Date Rev Version Comment +# 2016-06-18 776 1.1.1 add xsim_clean +# 2016-04-22 763 1.1 add include dep_vsim # 2016-01-03 724 1.0 Initial version # EXE_all = tb_nexys4_dummy tb_nexys4_cram_dummy # include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk # -.PHONY : all all_ssim clean +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim # all : $(EXE_all) all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) # -clean : viv_clean ghdl_clean +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean # #----- # -include ${RETROBASE}/rtl/make_viv/generic_vivado.mk include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # VBOM_all = $(wildcard *.vbom) # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_vsyn) include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) include $(wildcard *.o.dep_ghdl) endif # diff --git a/rtl/bplib/nexys4/tb/tb_nexys4.vbom b/rtl/bplib/nexys4/tb/tb_nexys4.vbom index 039933b6..359b9f50 100644 --- a/rtl/bplib/nexys4/tb/tb_nexys4.vbom +++ b/rtl/bplib/nexys4/tb/tb_nexys4.vbom @@ -17,7 +17,7 @@ ${sys_conf := sys_conf_sim.vhd} ../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom tb_nexys4_core.vbom ../../../vlib/serport/tb/serport_master_tb.vbom -@uut: ${nexys4_aif := nexys4_dummy.vbom} +${nexys4_aif := nexys4_dummy.vbom} -UUT # design tb_nexys4.vhd @top:tb_nexys4 diff --git a/rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom b/rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom index 6daca7b2..1d7caf34 100644 --- a/rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom +++ b/rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom @@ -18,7 +18,7 @@ ${sys_conf := sys_conf_sim.vhd} tb_nexys4_core.vbom ../../micron/mt45w8mw16b.vbom ../../../vlib/serport/tb/serport_master_tb.vbom -@uut: ${nexys4_cram_aif := nexys4_cram_dummy.vbom} +${nexys4_cram_aif := nexys4_cram_dummy.vbom} -UUT # design tb_nexys4_cram.vhd @top:tb_nexys4_cram diff --git a/rtl/bplib/nxcramlib/Makefile b/rtl/bplib/nxcramlib/Makefile.ise similarity index 91% rename from rtl/bplib/nxcramlib/Makefile rename to rtl/bplib/nxcramlib/Makefile.ise index 46045e37..4b503f0c 100644 --- a/rtl/bplib/nxcramlib/Makefile +++ b/rtl/bplib/nxcramlib/Makefile.ise @@ -1,4 +1,4 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# $Id: Makefile.ise 761 2016-04-17 08:53:48Z mueller $ # # Revision History: # Date Rev Version Comment diff --git a/rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd b/rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd index 18273e7b..4a6df1bf 100644 --- a/rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd +++ b/rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd @@ -1,6 +1,6 @@ --- $Id: nx_cram_memctl_as.vhd 718 2015-12-26 15:59:48Z mueller $ +-- $Id: nx_cram_memctl_as.vhd 767 2016-05-26 07:47:51Z mueller $ -- --- Copyright 2010-2015 by Walter F.J. Mueller +-- Copyright 2010-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -13,7 +13,7 @@ -- ------------------------------------------------------------------------------ -- Module Name: nx_cram_memctl_as - syn --- Description: nexys2/3: CRAM driver - async and page mode +-- Description: nexys2/3/4: CRAM driver - async and page mode -- -- Dependencies: vlib/xlib/iob_reg_o -- vlib/xlib/iob_reg_o_gen @@ -21,7 +21,7 @@ -- Test bench: tb/tb_nx_cram_memctl_as -- sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2 -- Target Devices: generic --- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31 +-- Tool versions: ise 11.4-14.7; viv 2014.4-2016.1; ghdl 0.26-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -31,6 +31,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-05-22 787 1.2.2 don't init N_REGS (vivado fix for fsm inference) -- 2015-12-26 718 1.2.1 BUGFIX: do_dispatch(): always define imem_oe -- 2011-11-26 433 1.2 renamed from n2_cram_memctl_as -- 2011-11-19 432 1.1 remove O_FLA_CE_N port @@ -197,8 +198,8 @@ architecture syn of nx_cram_memctl_as is (others=>'0') -- memdi ); - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs + signal R_REGS : regs_type := regs_init; + signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) signal CLK_180 : slbit := '0'; signal MEM_CE_N : slbit := '1'; diff --git a/rtl/bplib/nxcramlib/tb/Makefile b/rtl/bplib/nxcramlib/tb/Makefile.ise similarity index 94% rename from rtl/bplib/nxcramlib/tb/Makefile rename to rtl/bplib/nxcramlib/tb/Makefile.ise index fabed81e..a56f76e9 100644 --- a/rtl/bplib/nxcramlib/tb/Makefile +++ b/rtl/bplib/nxcramlib/tb/Makefile.ise @@ -1,4 +1,4 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# $Id: Makefile.ise 761 2016-04-17 08:53:48Z mueller $ # # Revision History: # Date Rev Version Comment diff --git a/rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vbom b/rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vbom index 4054920f..28b94c13 100644 --- a/rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vbom +++ b/rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vbom @@ -9,7 +9,7 @@ ../../../vlib/simlib/simclk.vbom ../../../vlib/simlib/simclkcnt.vbom ../../micron/mt45w8mw16b.vbom -@uut: ${uut := tbd_nx_cram_memctl_as.vbom} +${uut := tbd_nx_cram_memctl_as.vbom} -UUT # design tb_nx_cram_memctl.vhd @top:tb_nx_cram_memctl diff --git a/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom b/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom index cc6f377c..0b5f058b 100644 --- a/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom +++ b/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom @@ -14,7 +14,7 @@ ../../../vlib/rlink/tbcore/tbcore_rlink.vbom tb_s3board_core.vbom ../../../vlib/serport/tb/serport_master_tb.vbom -@uut: ${s3board_fusp_aif := s3board_fusp_dummy.vbom} +${s3board_fusp_aif := s3board_fusp_dummy.vbom} -UUT # design tb_s3board_fusp.vhd @top:tb_s3board_fusp diff --git a/rtl/bplib/sysmon/Makefile b/rtl/bplib/sysmon/Makefile new file mode 100644 index 00000000..8a3f16c1 --- /dev/null +++ b/rtl/bplib/sysmon/Makefile @@ -0,0 +1,37 @@ +# $Id: Makefile 761 2016-04-17 08:53:48Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-04-15 761 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +DCP_all = $(VBOM_all:.vbom=_syn.dcp) +# +# reference board for test synthesis is Artix-7 based Nexys4 +ifndef XTW_BOARD + XTW_BOARD=nexys4 +endif +include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk +# +.PHONY : catch all +# +catch : + @echo "no default target defined, use" + @echo " make all" + @echo " make _syn.dcp" + @exit 1 +# +all : $(DCP_all) +# +clean : viv_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/bplib/sysmon/sysmon_rbus_core.vbom b/rtl/bplib/sysmon/sysmon_rbus_core.vbom index 12e72177..81410de1 100644 --- a/rtl/bplib/sysmon/sysmon_rbus_core.vbom +++ b/rtl/bplib/sysmon/sysmon_rbus_core.vbom @@ -1,6 +1,7 @@ # libs ../../vlib/slvtypes.vhd ../../vlib/rbus/rblib.vhd +sysmonrbuslib.vbom # components # design sysmon_rbus_core.vhd diff --git a/rtl/bplib/sysmon/sysmon_rbus_core.vhd b/rtl/bplib/sysmon/sysmon_rbus_core.vhd index aaab1c26..b8acf341 100644 --- a/rtl/bplib/sysmon/sysmon_rbus_core.vhd +++ b/rtl/bplib/sysmon/sysmon_rbus_core.vhd @@ -1,4 +1,4 @@ --- $Id: sysmon_rbus_core.vhd 741 2016-03-12 23:49:03Z mueller $ +-- $Id: sysmon_rbus_core.vhd 767 2016-05-26 07:47:51Z mueller $ -- -- Copyright 2016- by Walter F.J. Mueller -- @@ -20,10 +20,12 @@ -- Test bench: - -- -- Target Devices: generic (all with SYSMON or XADC) --- Tool versions: viv 2015.4; ghdl 0.33 +-- Tool versions: viv 2015.4-2016.1; ghdl 0.33 -- -- Revision History: -- Date Rev Version Comment +-- 2016-05-25 787 1.0.1 don't init N_REGS (vivado fix for fsm inference) +-- BUGFIX: use s_init in regs_init (was s_idle) -- 2016-03-12 741 1.0 Initial version -- 2016-03-06 738 0.1 First draft ------------------------------------------------------------------------------ @@ -115,7 +117,7 @@ architecture syn of sysmon_rbus_core is constant regs_init : regs_type := ( '0', -- rbsel - s_idle, -- state + s_init, -- state (others=>'0'), -- eoscnt '0','0','0','0', -- stat_ot, stat_j* slv(to_unsigned(0,ALWIDTH)), -- almh @@ -124,7 +126,7 @@ architecture syn of sysmon_rbus_core is ); signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs + signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) -- only internal regs have names, only 3 LSB in constant constant rbaddr_cntl: slv3 := "000"; -- 0 -/-/f diff --git a/rtl/bplib/sysmon/sysmonrbuslib.vhd b/rtl/bplib/sysmon/sysmonrbuslib.vhd index 0f1b6ba3..4cdc86bc 100644 --- a/rtl/bplib/sysmon/sysmonrbuslib.vhd +++ b/rtl/bplib/sysmon/sysmonrbuslib.vhd @@ -1,4 +1,4 @@ --- $Id: sysmonrbuslib.vhd 742 2016-03-13 14:40:19Z mueller $ +-- $Id: sysmonrbuslib.vhd 770 2016-05-28 14:15:00Z mueller $ -- -- Copyright 2016- by Walter F.J. Mueller -- @@ -19,6 +19,7 @@ -- Tool versions: viv2015.4; ghdl 0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-05-28 770 1.0.1 ensure to_unsigned() has a type natural argument -- 2016-03-13 742 1.0 Initial version -- 2016-03-06 738 0.1 First draft ------------------------------------------------------------------------------ @@ -195,17 +196,17 @@ package body sysmonrbuslib is -- ------------------------------------- pure function xadc_temp2alim(temp : real) return bv16 is - variable ival : integer := 0; + variable ival : natural := 0; begin - ival := integer(((temp + 273.14) * 16.0 * 4096.0) / 503.975); + ival := natural(((temp + 273.14) * 16.0 * 4096.0) / 503.975); return to_bitvector(slv(to_unsigned(ival,16))); end function xadc_temp2alim; -- ------------------------------------- pure function xadc_svolt2alim (volt : real) return bv16 is - variable ival : integer := 0; + variable ival : natural := 0; begin - ival := integer((volt * 16.0 * 4096.0) / 3.0); + ival := natural((volt * 16.0 * 4096.0) / 3.0); return to_bitvector(slv(to_unsigned(ival,16))); end function xadc_svolt2alim; diff --git a/rtl/ibus/Makefile b/rtl/ibus/Makefile.ise similarity index 89% rename from rtl/ibus/Makefile rename to rtl/ibus/Makefile.ise index ed92a827..2ce605a6 100644 --- a/rtl/ibus/Makefile +++ b/rtl/ibus/Makefile.ise @@ -1,4 +1,5 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ # # Revision History: # Date Rev Version Comment diff --git a/rtl/ibus/ibd_ibmon.vbom b/rtl/ibus/ibd_ibmon.vbom index 28957c68..a441cecd 100644 --- a/rtl/ibus/ibd_ibmon.vbom +++ b/rtl/ibus/ibd_ibmon.vbom @@ -4,6 +4,7 @@ iblib.vhd # components [sim]../vlib/memlib/ram_1swsr_wfirst_gen.vbom -[xst,vsyn]../vlib/memlib/ram_1swsr_wfirst_gen_unisim.vbom +[xst]../vlib/memlib/ram_1swsr_wfirst_gen_unisim.vbom +[vsyn]../vlib/memlib/ram_1swsr_wfirst_gen.vbom # design ibd_ibmon.vhd diff --git a/rtl/ibus/ibd_iist.vhd b/rtl/ibus/ibd_iist.vhd index 751ac9d1..02143bd0 100644 --- a/rtl/ibus/ibd_iist.vhd +++ b/rtl/ibus/ibd_iist.vhd @@ -1,6 +1,6 @@ --- $Id: ibd_iist.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: ibd_iist.vhd 767 2016-05-26 07:47:51Z mueller $ -- --- Copyright 2009-2011 by Walter F.J. Mueller +-- Copyright 2009-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -29,6 +29,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-05-22 787 0.8.2 don't init N_REGS (vivado fix for fsm inference) -- 2011-11-18 427 0.8.1 now numeric_std clean -- 2010-10-17 333 0.8 use ibus V2 interface -- 2009-06-07 224 0.7 send inverted stc_stp; remove pgc_err; honor msk_im @@ -218,7 +219,7 @@ architecture syn of ibd_iist is ); signal R_REGS : regs_type := regs_init; - signal N_REGS : regs_type := regs_init; + signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) begin diff --git a/rtl/ibus/ibdr_rhrp.vbom b/rtl/ibus/ibdr_rhrp.vbom index 84a968cb..b227038d 100644 --- a/rtl/ibus/ibdr_rhrp.vbom +++ b/rtl/ibus/ibdr_rhrp.vbom @@ -4,6 +4,7 @@ iblib.vhd # components [sim]../vlib/memlib/ram_1swar_gen.vbom -[xst,vsyn]../vlib/memlib/ram_1swar_gen_unisim.vbom +[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom +[vsyn]../vlib/memlib/ram_1swar_gen.vbom # design ibdr_rhrp.vhd diff --git a/rtl/ibus/ibdr_rhrp.vhd b/rtl/ibus/ibdr_rhrp.vhd index ceacf642..e9f91c52 100644 --- a/rtl/ibus/ibdr_rhrp.vhd +++ b/rtl/ibus/ibdr_rhrp.vhd @@ -1,6 +1,6 @@ --- $Id: ibdr_rhrp.vhd 692 2015-06-21 11:53:24Z mueller $ +-- $Id: ibdr_rhrp.vhd 767 2016-05-26 07:47:51Z mueller $ -- --- Copyright 2015- by Walter F.J. Mueller +-- Copyright 2015-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,7 +18,7 @@ -- Dependencies: ram_1swar_gen -- Test bench: - -- Target Devices: generic --- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 +-- Tool versions: ise 14.7; viv 2014.4-2016.1; ghdl 0.31-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -28,6 +28,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-05-22 787 1.0.4 don't init N_REGS (vivado fix for fsm inference) -- 2015-06-20 692 1.0.3 BUGFIX: fix func-go when drive/init busy checks -- 2015-06-05 690 1.0.2 use 'not unit' for lsb of rpsn to avoid SI detect -- BUGFIX: set rmr only for write to busy unit @@ -401,7 +402,7 @@ architecture syn of ibdr_rhrp is ); signal R_REGS : regs_type := regs_init; - signal N_REGS : regs_type := regs_init; + signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) signal MEM_1_WE : slbit := '0'; signal MEM_0_WE : slbit := '0'; diff --git a/rtl/ibus/ibdr_rk11.vbom b/rtl/ibus/ibdr_rk11.vbom index aff5865c..45900725 100644 --- a/rtl/ibus/ibdr_rk11.vbom +++ b/rtl/ibus/ibdr_rk11.vbom @@ -4,6 +4,7 @@ iblib.vhd # components [sim]../vlib/memlib/ram_1swar_gen.vbom -[xst,vsyn]../vlib/memlib/ram_1swar_gen_unisim.vbom +[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom +[vsyn]../vlib/memlib/ram_1swar_gen.vbom # design ibdr_rk11.vhd diff --git a/rtl/ibus/ibdr_rk11.vhd b/rtl/ibus/ibdr_rk11.vhd index 38ff51c2..c8050293 100644 --- a/rtl/ibus/ibdr_rk11.vhd +++ b/rtl/ibus/ibdr_rk11.vhd @@ -1,6 +1,6 @@ --- $Id: ibdr_rk11.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: ibdr_rk11.vhd 767 2016-05-26 07:47:51Z mueller $ -- --- Copyright 2008-2015 by Walter F.J. Mueller +-- Copyright 2008-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,7 +18,7 @@ -- Dependencies: ram_1swar_gen -- Test bench: - -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -29,6 +29,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-05-22 787 1.3.1 don't init N_REGS (vivado fix for fsm inference) -- 2015-05-01 672 1.3 BUGFIX: interrupt after dreset,seek command start -- 2011-11-18 427 1.2.2 now numeric_std clean -- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM; @@ -168,7 +169,7 @@ architecture syn of ibdr_rk11 is ); signal R_REGS : regs_type := regs_init; - signal N_REGS : regs_type := regs_init; + signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) signal MEM_1_WE : slbit := '0'; signal MEM_0_WE : slbit := '0'; diff --git a/rtl/ibus/ibdr_rl11.vbom b/rtl/ibus/ibdr_rl11.vbom index 98bb21fc..9024e312 100644 --- a/rtl/ibus/ibdr_rl11.vbom +++ b/rtl/ibus/ibdr_rl11.vbom @@ -4,6 +4,7 @@ iblib.vhd # components [sim]../vlib/memlib/ram_1swar_gen.vbom -[xst,vsyn]../vlib/memlib/ram_1swar_gen_unisim.vbom +[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom +[vsyn]../vlib/memlib/ram_1swar_gen.vbom # design ibdr_rl11.vhd diff --git a/rtl/ibus/ibdr_rl11.vhd b/rtl/ibus/ibdr_rl11.vhd index 6036379f..63d4d27d 100644 --- a/rtl/ibus/ibdr_rl11.vhd +++ b/rtl/ibus/ibdr_rl11.vhd @@ -1,6 +1,6 @@ --- $Id: ibdr_rl11.vhd 655 2015-03-04 20:35:21Z mueller $ +-- $Id: ibdr_rl11.vhd 767 2016-05-26 07:47:51Z mueller $ -- --- Copyright 2014-2015 by Walter F.J. Mueller +-- Copyright 2014-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,7 +18,7 @@ -- Dependencies: ram_1swar_gen -- Test bench: - -- Target Devices: generic --- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 +-- Tool versions: ise 14.7; viv 2014.4-2016.1; ghdl 0.31-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -27,6 +27,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-05-22 787 1.0.2 don't init N_REGS (vivado fix for fsm inference) -- 2015-03-04 655 1.0.1 seek: ignore da(6:5), don't check for 0 anymore -- 2015-02-28 653 1.0 Initial verison -- 2014-06-09 561 0.1 First draft @@ -238,7 +239,7 @@ architecture syn of ibdr_rl11 is ); signal R_REGS : regs_type := regs_init; - signal N_REGS : regs_type := regs_init; + signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) signal MEM_1_WE : slbit := '0'; signal MEM_0_WE : slbit := '0'; diff --git a/rtl/ibus/iblib.vhd b/rtl/ibus/iblib.vhd index 243ca30d..3544be8c 100644 --- a/rtl/ibus/iblib.vhd +++ b/rtl/ibus/iblib.vhd @@ -1,6 +1,6 @@ --- $Id: iblib.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: iblib.vhd 770 2016-05-28 14:15:00Z mueller $ -- --- Copyright 2008-2015 by Walter F.J. Mueller +-- Copyright 2008-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Definitions for ibus interface and bus entities -- -- Dependencies: - --- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.1-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-05-28 770 2.1.1 use type natural for vec,pri fields of intmap_type -- 2015-04-24 668 2.1 add ibd_ibmon -- 2010-10-23 335 2.0.1 add ib_sel; add ib_sres_or_mon -- 2010-10-17 333 2.0 ibus V2 interface: use aval,re,we,rmw @@ -115,8 +116,8 @@ component ib_sres_or_gen is -- ibus result or, generic end component; type intmap_type is record -- interrupt map entry type - vec : integer; -- vector address - pri : integer; -- priority + vec : natural; -- vector address + pri : natural; -- priority end record intmap_type; constant intmap_init : intmap_type := (0,0); diff --git a/rtl/make_ise/generic_ghdl.mk b/rtl/make_ise/generic_ghdl.mk index 9cb1c822..b0b3d4f1 100644 --- a/rtl/make_ise/generic_ghdl.mk +++ b/rtl/make_ise/generic_ghdl.mk @@ -1,10 +1,11 @@ -# $Id: generic_ghdl.mk 733 2016-02-20 12:24:13Z mueller $ +# $Id: generic_ghdl.mk 778 2016-06-25 15:18:01Z mueller $ # -# Copyright 2007-2015 by Walter F.J. Mueller +# Copyright 2007-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2016-06-24 778 1.1 use ghdl.?sim as workdir # 2015-02-14 646 1.4 use --xlpath for vbomconv; drop cygwin support; # 2014-07-26 575 1.3.2 use XTWI_PATH now (ise/vivado switch done later) # 2013-01-27 477 1.3.1 use dontincdep.mk to suppress .dep include on clean @@ -42,9 +43,8 @@ include ${RETROBASE}/rtl/make_ise/dontincdep.mk ghdl_clean: ghdl_tmp_clean rm -f $(EXE_all) rm -f $(EXE_all:%=%_[sft]sim) - rm -f cext_*.o # ghdl_tmp_clean: - find -maxdepth 1 -name "*.o" | grep -v "^\./cext_" | xargs rm -f - rm -f work-obj93.cf + rm -rf ghdl.[bsft]sim + rm -f cext_*.o e~*.o # diff --git a/rtl/make_ise/generic_xflow.mk b/rtl/make_ise/generic_xflow.mk index e9d76e88..cfa9f95e 100644 --- a/rtl/make_ise/generic_xflow.mk +++ b/rtl/make_ise/generic_xflow.mk @@ -1,10 +1,12 @@ -# $Id: generic_xflow.mk 733 2016-02-20 12:24:13Z mueller $ +# $Id: generic_xflow.mk 778 2016-06-25 15:18:01Z mueller $ # -# Copyright 2007-2015 by Walter F.J. Mueller +# Copyright 2007-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2016-06-25 778 1.11.2 mfset rule: add message if log not found +# 2016-05-27 769 1.11.1 rename mfset to imfset # 2015-05-02 672 1.11 ucf_cpp handling: remove -C (gcc 4.8 stdc-predef.h) # 2015-02-06 643 1.10 use make_ise; rename xise_msg_filter <- isemsg_filter # drop --ise_path from vbomconv; @@ -100,8 +102,8 @@ XFLOW = xflow -p ${ISE_PATH} @ echo "===============================================================" @ echo "* XST Diagnostic Summary *" @ echo "===============================================================" - @ if [ -r $*.mfset ]; then xise_msg_filter xst $*.mfset $*_xst.log; fi - @ if [ ! -r $*.mfset ]; then grep -i -A 1 ":.*:" $*_xst.log || true; fi + @ if [ -r $*.imfset ]; then xise_msg_filter xst $*.imfset $*_xst.log; fi + @ if [ ! -r $*.imfset ]; then grep -i -A 1 ":.*:" $*_xst.log || true; fi @ echo "===============================================================" # # the following rule needed to generate an %_*sim.vhd in a ./tb sub-directory @@ -122,8 +124,8 @@ XFLOW = xflow -p ${ISE_PATH} @ echo "===============================================================" @ echo "* XST Diagnostic Summary *" @ echo "===============================================================" - @ if [ -r $*.mfset ]; then xise_msg_filter xst $*.mfset $*_xst.log; fi - @ if [ ! -r $*.mfset ]; then grep -i -A 1 ":.*:" $*_xst.log || true; fi + @ if [ -r $*.imfset ]; then xise_msg_filter xst $*.imfset $*_xst.log; fi + @ if [ ! -r $*.imfset ]; then grep -i -A 1 ":.*:" $*_xst.log || true; fi @ echo "===============================================================" # # Implement 1 (map+par) @@ -155,19 +157,19 @@ XFLOW = xflow -p ${ISE_PATH} if [ -r ./ise/$*_pad.txt ]; then cp -p ./ise/$*_pad.txt ./$*_pad.log; fi if [ -r ./ise/$*.twr ]; then cp -p ./ise/$*.twr ./$*_twr.log; fi if [ -r ./ise/$*.tsi ]; then cp -p ./ise/$*.tsi ./$*_tsi.log; fi - @ if [ -r $*.mfset ]; then \ + @ if [ -r $*.imfset ]; then \ echo "=============================================================";\ echo "* Translate Diagnostic Summary *";\ echo "=============================================================";\ - xise_msg_filter tra $*.mfset $*_tra.log;\ + xise_msg_filter tra $*.imfset $*_tra.log;\ echo "=============================================================";\ echo "* MAP Diagnostic Summary *";\ echo "=============================================================";\ - xise_msg_filter map $*.mfset $*_map.log;\ + xise_msg_filter map $*.imfset $*_map.log;\ echo "=============================================================";\ echo "* PAR Diagnostic Summary *";\ echo "=============================================================";\ - xise_msg_filter par $*.mfset $*_par.log;\ + xise_msg_filter par $*.imfset $*_par.log;\ echo "=============================================================";\ fi # @@ -185,11 +187,11 @@ XFLOW = xflow -p ${ISE_PATH} if [ -r ./ise/$*.bit ]; then cp -p ./ise/$*.bit .; fi if [ -r ./ise/$*.msk ]; then cp -p ./ise/$*.msk .; fi if [ -r ./ise/$*.bgn ]; then cp -p ./ise/$*.bgn ./$*_bgn.log; fi - @ if [ -r $*.mfset ]; then \ + @ if [ -r $*.imfset ]; then \ echo "=============================================================";\ echo "* Bitgen Diagnostic Summary *";\ echo "=============================================================";\ - xise_msg_filter bgn $*.mfset $*_bgn.log;\ + xise_msg_filter bgn $*.imfset $*_bgn.log;\ echo "=============================================================";\ fi # @@ -225,18 +227,27 @@ endif # Print log file summary # input: %_*.log (not depended) # output: .PHONY -%.mfsum: %.mfset +%.mfsum: %.imfset @ echo "=== XST summary =============================================" - @ if [ -r $*_xst.log ]; then xise_msg_filter xst $*.mfset $*_xst.log; fi + @ if [ -r $*_xst.log ]; \ + then xise_msg_filter xst $*.imfset $*_xst.log; \ + else echo " !!! no $*_xst.log found"; fi @ echo "=== Translate summary =======================================" - @ if [ -r $*_tra.log ]; then xise_msg_filter tra $*.mfset $*_tra.log; fi + @ if [ -r $*_tra.log ]; \ + then xise_msg_filter tra $*.imfset $*_tra.log; \ + else echo " !!! no $*_tra.log found"; fi @ echo "=== MAP summary =============================================" - @ if [ -r $*_map.log ]; then xise_msg_filter map $*.mfset $*_map.log; fi + @ if [ -r $*_map.log ]; \ + then xise_msg_filter map $*.imfset $*_map.log; \ + else echo " !!! no $*_map.log found"; fi @ echo "=== PAR summary =============================================" - @ if [ -r $*_par.log ]; then xise_msg_filter par $*.mfset $*_par.log; fi + @ if [ -r $*_par.log ]; \ + then xise_msg_filter par $*.imfset $*_par.log; \ + else echo " !!! no $*_par.log found"; fi @ echo "=== Bitgen summary ==========================================" - @ if [ -r $*_bgn.log ]; then xise_msg_filter bgn $*.mfset $*_bgn.log; fi - + @ if [ -r $*_bgn.log ]; \ + then xise_msg_filter bgn $*.imfset $*_bgn.log; \ + else echo " !!! no $*_bgn.log found"; fi # # # diff --git a/rtl/make_viv/generic_ghdl.mk b/rtl/make_viv/generic_ghdl.mk index a4bd1688..c1ca9414 100644 --- a/rtl/make_viv/generic_ghdl.mk +++ b/rtl/make_viv/generic_ghdl.mk @@ -1,10 +1,11 @@ -# $Id: generic_ghdl.mk 733 2016-02-20 12:24:13Z mueller $ +# $Id: generic_ghdl.mk 778 2016-06-25 15:18:01Z mueller $ # -# Copyright 2015- by Walter F.J. Mueller +# Copyright 2015-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2016-06-24 778 1.1 add rsim model; use ghdl.?sim as workdir # 2015-02-14 646 1.0 Initial version (cloned from make_ise) # GHDLIEEE = --ieee=synopsys @@ -14,12 +15,16 @@ GHDLXLPATH = ${XTWV_PATH}/ghdl vbomconv --ghdl_i $< vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $< # -# rules for _[o]sim to use 'virtual' [o]sim vbom's (derived from _ssim) +# rules for _[or]sim to use 'virtual' [or]sim vbom's (derived from _ssim) # %_osim : %_ssim.vbom vbomconv --ghdl_i $*_osim.vbom vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $*_osim.vbom # +%_rsim : %_ssim.vbom + vbomconv --ghdl_i $*_rsim.vbom + vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $*_rsim.vbom +# %.dep_ghdl: %.vbom vbomconv --dep_ghdl $< > $@ # @@ -29,10 +34,9 @@ include ${RETROBASE}/rtl/make_ise/dontincdep.mk # ghdl_clean: ghdl_tmp_clean rm -f $(EXE_all) - rm -f $(EXE_all:%=%_[so]sim) - rm -f cext_*.o + rm -f $(EXE_all:%=%_[sor]sim) # ghdl_tmp_clean: - find -maxdepth 1 -name "*.o" | grep -v "^\./cext_" | xargs rm -f - rm -f work-obj93.cf + rm -rf ghdl.[bsor]sim + rm -f cext_*.o e~*.o # diff --git a/rtl/make_viv/generic_vivado.mk b/rtl/make_viv/generic_vivado.mk index 0aa755c2..0f7aad62 100644 --- a/rtl/make_viv/generic_vivado.mk +++ b/rtl/make_viv/generic_vivado.mk @@ -1,10 +1,14 @@ -# $Id: generic_vivado.mk 733 2016-02-20 12:24:13Z mueller $ +# $Id: generic_vivado.mk 778 2016-06-25 15:18:01Z mueller $ # -# Copyright 2015- by Walter F.J. Mueller +# Copyright 2015-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2016-06-24 778 1.3 add rsim.vhd and [sorep]sim.v targets +# 2016-06-11 774 1.2.1 call xviv_sim_vhdl_cleanup for %_[so]sim rules +# 2016-05-27 769 1.2 add xviv_msg_filter support +# 2016-03-26 752 1.1 new %.vivado; separate %_opt.dcp,%_pla.dcp,%_rou.dcp # 2015-02-15 646 1.0 Initial version # 2015-01-25 637 0.1 First draft #--- @@ -37,6 +41,18 @@ endif # when chaining, don't delete 'expensive' intermediate files: .SECONDARY : # +# Setup vivado project +# input: %.vbom vbom project description +# output: .PHONY +# +%.vivado : %.vbom + rm -rf project_mflow + xtwv vivado -mode batch \ + -source ${VIV_INIT} \ + -source ${VIV_BOARD_SETUP} \ + -source ${VIV_BUILD_FLOW} \ + -tclargs $* prj +# # Synthesize + Implement -> generate bit file # input: %.vbom vbom project description # output: %.bit @@ -48,6 +64,20 @@ endif -source ${VIV_BOARD_SETUP} \ -source ${VIV_BUILD_FLOW} \ -tclargs $* bit + @ if [ -r $*.vmfset ]; then make $*.mfsum; fi +# +# Print log file summary +# input: %_*.log (not depended) +# output: .PHONY +%.mfsum: %.vmfset + @ echo "=== Synthesis flow summary ==================================" + @ if [ -r $*_syn.log ]; \ + then xviv_msg_filter syn $*.vmfset $*_syn.log; \ + else echo " !!! no $*_syn.log found"; fi + @ echo "=== Implementation flow summary==============================" + @ if [ -r $*_imp.log ]; \ + then xviv_msg_filter imp $*.vmfset $*_imp.log; \ + else echo " !!! no $*_imp.log found"; fi # # Configure FPGA with vivado hardware server # input: %.bit @@ -62,6 +92,7 @@ endif # # Partial Synthesize + Implement -> generate dcp for model generation # +# run synthesis only %_syn.dcp : %.vbom rm -rf project_mflow xtwv vivado -mode batch \ @@ -69,7 +100,27 @@ endif -source ${VIV_BOARD_SETUP} \ -source ${VIV_BUILD_FLOW} \ -tclargs $* syn -%_opt.dcp %_rou.dcp : %.vbom +# +# run synthesis + implementation up to step opt_design +%_opt.dcp : %.vbom + rm -rf project_mflow + xtwv vivado -mode batch \ + -source ${VIV_INIT} \ + -source ${VIV_BOARD_SETUP} \ + -source ${VIV_BUILD_FLOW} \ + -tclargs $* opt +# +# run synthesis + implementation up to step place_design +%_pla.dcp : %.vbom + rm -rf project_mflow + xtwv vivado -mode batch \ + -source ${VIV_INIT} \ + -source ${VIV_BOARD_SETUP} \ + -source ${VIV_BUILD_FLOW} \ + -tclargs $* pla +# +# run synthesis + implementation (but not bit file generation) +%_rou.dcp : %.vbom rm -rf project_mflow xtwv vivado -mode batch \ -source ${VIV_INIT} \ @@ -85,7 +136,8 @@ endif xtwv vivado -mode batch \ -source ${VIV_INIT} \ -source ${VIV_MODEL_FLOW} \ - -tclargs $* ssim + -tclargs $* ssim_vhd + xviv_sim_vhdl_cleanup $@ # # Post-optimization functional simulation model (Vhdl/Unisim) # input: %_opt.dcp @@ -95,7 +147,71 @@ endif xtwv vivado -mode batch \ -source ${VIV_INIT} \ -source ${VIV_MODEL_FLOW} \ - -tclargs $* osim + -tclargs $* osim_vhd + xviv_sim_vhdl_cleanup $@ +# +# Post-routing functional simulation model (Vhdl/Unisim) +# input: %_rou.dcp +# output: %_rsim.vhd +# +%_rsim.vhd : %_rou.dcp + xtwv vivado -mode batch \ + -source ${VIV_INIT} \ + -source ${VIV_MODEL_FLOW} \ + -tclargs $* rsim_vhd + xviv_sim_vhdl_cleanup $@ +# +# Post-synthesis functional simulation model (Verilog/Unisim) +# input: %_syn.dcp +# output: %_ssim.v +# +%_ssim.v : %_syn.dcp + xtwv vivado -mode batch \ + -source ${VIV_INIT} \ + -source ${VIV_MODEL_FLOW} \ + -tclargs $* ssim_v +# +# Post-optimization functional simulation model (Verilog/Unisim) +# input: %_opt.dcp +# output: %_osim.v +# +%_osim.v : %_opt.dcp + xtwv vivado -mode batch \ + -source ${VIV_INIT} \ + -source ${VIV_MODEL_FLOW} \ + -tclargs $* osim_v +# +# Post-routing functional simulation model (Verilog/Unisim) +# input: %_rou.dcp +# output: %_rsim.v +# +%_rsim.v : %_rou.dcp + xtwv vivado -mode batch \ + -source ${VIV_INIT} \ + -source ${VIV_MODEL_FLOW} \ + -tclargs $* rsim_v +# +# Post-synthesis timing simulation model (Verilog/Simprim) +# input: %_syn.dcp +# output: %_esim.v +# %_esim.sdf +# +%_esim.v %_esim.sdf : %_syn.dcp + xtwv vivado -mode batch \ + -source ${VIV_INIT} \ + -source ${VIV_MODEL_FLOW} \ + -tclargs $* esim_v +# +# Post-optimization timing simulation model (Verilog/Simprim) +# input: %_opt.dcp +# output: %_psim.v +# %_psim.sdf +# +%_psim.v %_psim.sdf : %_opt.dcp + xtwv vivado -mode batch \ + -source ${VIV_INIT} \ + -source ${VIV_MODEL_FLOW} \ + -tclargs $* psim_v # # Post-routing timing simulation model (Verilog/Simprim) # input: %_rou.dcp @@ -106,7 +222,7 @@ endif xtwv vivado -mode batch \ -source ${VIV_INIT} \ -source ${VIV_MODEL_FLOW} \ - -tclargs $* tsim + -tclargs $* tsim_v # # vivado project quick starter # @@ -133,9 +249,9 @@ viv_clean: viv_tmp_clean rm -f *.jou rm -f *.log rm -f *.rpt - rm -f *_[so]sim.vhd - rm -f *_tsim.v - rm -f *_tsim.sdf + rm -f *_[sor]sim.vhd + rm -f *_[sorept]sim.v + rm -f *_[ept]sim.sdf # viv_tmp_clean: rm -rf ./project_mflow diff --git a/rtl/make_viv/generic_xsim.mk b/rtl/make_viv/generic_xsim.mk index 02f5c228..b0e3e984 100644 --- a/rtl/make_viv/generic_xsim.mk +++ b/rtl/make_viv/generic_xsim.mk @@ -1,10 +1,11 @@ -# $Id: generic_xsim.mk 733 2016-02-20 12:24:13Z mueller $ +# $Id: generic_xsim.mk 778 2016-06-25 15:18:01Z mueller $ # # Copyright 2016- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2016-06-24 778 1.1 add [rep]sim models; use xsim.?sim as workdir # 2016-02-06 727 1.0 Initial version # %_XSim : %.vbom @@ -13,7 +14,7 @@ $*_vsim.sh rm -rf $*_vsim.sh # -# rule to build XSim ssim model from _ssim vbom +# rule to build XSim ssim model from _ssim vbom (post synth, functional) # %_XSim_ssim : %_ssim.vbom vbomconv -vsim_prj $< > $*_vsim.sh @@ -21,7 +22,7 @@ $*_vsim.sh rm -rf $*_vsim.sh # -# rule to build XSim osim model from _ssim vbom +# rule to build XSim osim model from _ssim vbom (post opt, functional) # %_XSim_osim : %_ssim.vbom vbomconv -vsim_prj $*_osim.vbom > $*_vsim.sh @@ -29,7 +30,31 @@ $*_vsim.sh rm -rf $*_vsim.sh # -# rule to build XSim tsim model from _ssim vbom +# rule to build XSim rsim model from _ssim vbom (post route, functional) +# +%_XSim_rsim : %_ssim.vbom + vbomconv -vsim_prj $*_rsim.vbom > $*_vsim.sh + chmod +x $*_vsim.sh + $*_vsim.sh + rm -rf $*_vsim.sh +# +# rule to build XSim esim model from _ssim vbom (post synth, timing) +# +%_XSim_esim : %_ssim.vbom + vbomconv -vsim_prj $*_esim.vbom > $*_vsim.sh + chmod +x $*_vsim.sh + $*_vsim.sh + rm -rf $*_vsim.sh +# +# rule to build XSim psim model from _ssim vbom (post opt, timing) +# +%_XSim_psim : %_ssim.vbom + vbomconv -vsim_prj $*_psim.vbom > $*_vsim.sh + chmod +x $*_vsim.sh + $*_vsim.sh + rm -rf $*_vsim.sh +# +# rule to build XSim tsim model from _ssim vbom (post rou, timing) # %_XSim_tsim : %_ssim.vbom vbomconv -vsim_prj $*_tsim.vbom > $*_vsim.sh @@ -48,13 +73,18 @@ xsim_clean: xsim_tmp_clean rm -f $(EXE_all:%=%_XSim) rm -f $(EXE_all:%=%_XSim_ssim) rm -f $(EXE_all:%=%_XSim_osim) + rm -f $(EXE_all:%=%_XSim_rsim) + rm -f $(EXE_all:%=%_XSim_esim) + rm -f $(EXE_all:%=%_XSim_psim) rm -f $(EXE_all:%=%_XSim_tsim) + rm -rf xsim.[bsorept]sim # xsim_tmp_clean: - rm -f isim.log isim.wdb - rm -f xsim.jou xsim.log - rm -f xsim_*.backup.jou xsim_*.backup.log - rm -f webtalk.jou webtalk.log - rm -f webtalk_*.backup.jou webtalk_*.backup.log - rm -rf xsim.dir + rm -f *.wdb + rm -f xsim.jou xsim_*.backup.jou + rm -f xsim.log xsim_*.backup.log + rm -f webtalk.jou webtalk_*.backup.jou + rm -f webtalk.log webtalk_*.backup.log + rm -rf xsim.[bsorept]sim/xsim.dir/xil_defaultlib + rm -f xsim.dir # diff --git a/rtl/make_viv/viv_tools_build.tcl b/rtl/make_viv/viv_tools_build.tcl index cfe6a015..366f851e 100644 --- a/rtl/make_viv/viv_tools_build.tcl +++ b/rtl/make_viv/viv_tools_build.tcl @@ -1,11 +1,17 @@ -# $Id: viv_tools_build.tcl 738 2016-03-06 13:02:53Z mueller $ +# $Id: viv_tools_build.tcl 767 2016-05-26 07:47:51Z mueller $ # -# Copyright 2015- by Walter F.J. Mueller +# Copyright 2015-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment -# 2016-02-28 649 1.1.1 add 2015.4 specific setups +# 2016-05-22 767 1.2 cleaner setup handling; use explore flows +# add 2016.1 specific setups +# 2016-04-02 758 1.1.5 remove USR_ACCESS setup, must be done in xdc +# 2016-03-26 752 1.1.4 more steps supported: prj,opt,pla +# 2016-03-25 751 1.1.3 suppress some messages +# 2016-03-19 748 1.1.2 set bitstream USR_ACCESS to TIMESTAMP +# 2016-02-28 738 1.1.1 add 2015.4 specific setups # 2015-02-21 649 1.1 add 2014.4 specific setups # 2015-02-14 646 1.0 Initial version # @@ -42,6 +48,13 @@ proc rvtb_mv_file {src dst} { return "" } +# +# -------------------------------------------------------------------- +# +proc rvtb_rm_file {src} { + exec rm -f $src +} + # # -------------------------------------------------------------------- # @@ -58,50 +71,125 @@ proc rvtb_cp_file {src dst} { # -------------------------------------------------------------------- # proc rvtb_build_check {step} { - get_msg_config -rules return "" } +# +# -------------------------------------------------------------------- +# +proc rvtb_version_is {val} { + set vers [version -short] + return [expr {$vers eq $val}] +} +# +# -------------------------------------------------------------------- +# +proc rvtb_version_min {val} { + set vers [version -short] + return [expr {[string compare $vers $val] >= 0}] +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_version_max {val} { + set vers [version -short] + return [expr {[string compare $vers $val] <= 0}] +} + +# +# -------------------------------------------------------------------- +# +proc rvtb_version_in {min max} { + set vers [version -short] + return [expr {[string compare $vers $min] >= 0 && \ + [string compare $vers $max] <= 0}] +} + # # -------------------------------------------------------------------- # proc rvtb_default_build {stem step} { - - # general setups - switch [version -short] { - "2014.4" { - # suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages - # set here to avoid messages during create_project - set_msg_config -suppress -id {Board 49-26} - } - "2015.4" { - # enable vhdl asserts, see http://www.xilinx.com/support/answers/65415.html - set_param synth.elaboration.rodinMoreOptions \ - {rt::set_parameter ignoreVhdlAssertStmts false} - } + # supported step values + # prj setup project + # syn run synthesis + # opt run synthesis + implementation up to step opt_design + # pla run synthesis + implementation up to step place_design + # imp run synthesis + implementation (but not bit file generation) + # bit Synthesize + Implement + generate bit file + + if {![regexp -- {^(prj|syn|opt|pla|imp|bit)$} $step]} { + error "bad step name $step" + } + + # general setups (prior to project creation) ------------------ + # version dependent setups + if {[rvtb_version_is "2014.4"]} { + # suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages + # set here to avoid messages during create_project + set_msg_config -suppress -id {Board 49-26} } # read setup set setup_file [rvtb_locate_setup_file $stem] if {$setup_file ne ""} {source -notrace $setup_file} - # Create project + # Create project ---------------------------------------------- rvtb_trace_cmd "create_project project_mflow ./project_mflow" - # Setup project properties + # Setup project properties ------------------------------- set obj [get_projects project_mflow] set_property "default_lib" "xil_defaultlib" $obj set_property "part" $::rvtb_part $obj set_property "simulator_language" "Mixed" $obj set_property "target_language" "VHDL" $obj - # version dependent setups - switch [version -short] { - "2014.4" { - # suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages - # repeated here because create_project apparently clears msg_config - set_msg_config -suppress -id {Board 49-26} - } + # general setups ----------------------------------------- + # suppress message which don't convey useful information + set_msg_config -suppress -id {DRC 23-20}; # DSP48 output pilelining + set_msg_config -suppress -id {Project 1-120}; # WebTalk mandatory + set_msg_config -suppress -id {Common 17-186}; # WebTalk info send + + # Setup list of extra synthesis options (for later rodinMoreOptions) + set synth_more_opts {} + + # version independent setups ----------------------------- + + # setup synthesis and implementation strategies + set_property strategy Flow_PerfOptimized_high [get_runs synth_1] + set_property strategy Performance_Explore [get_runs impl_1] + + # FSM recognition threshold (default is 5) + # see http://www.xilinx.com/support/answers/58574.html + lappend synth_more_opts {rt::set_parameter minFsmStates 3} + + # version dependent setups ------------------------------- + if {[rvtb_version_is "2014.4"]} { + # suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages + # repeated here because create_project apparently clears msg_config + set_msg_config -suppress -id {Board 49-26} + } + + if {[rvtb_version_is "2015.4"]} { + # enable vhdl asserts, see http://www.xilinx.com/support/answers/65415.html + lappend synth_more_opts {rt::set_parameter ignoreVhdlAssertStmts false} + } + + if {[rvtb_version_min "2016.1"]} { + # enable vhdl asserts via global option (after 2016.1) + set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1] + } + + # now setup extra synthesis options + # see http://www.xilinx.com/support/answers/58248.html + # -> since used via 'set_param' it's a parameter + # -> only last definition counts + # -> use ';' separated list + # -> these options are **NOT** preserved in project file !! + if {[llength $synth_more_opts]} { + puts "# extra synthesis options:" + foreach opt $synth_more_opts { puts "# $opt"} + set_param synth.elaboration.rodinMoreOptions [join $synth_more_opts "; "] } # Setup filesets @@ -109,61 +197,102 @@ proc rvtb_default_build {stem step} { eval $vbom_prj update_compile_order -fileset sources_1 + if {$step eq "prj"} { + puts "rvtb_default_build-I: new project setup for ${stem}" + return "" + } + # some handy variables set path_runs "project_mflow/project_mflow.runs" set path_syn1 "${path_runs}/synth_1" set path_imp1 "${path_runs}/impl_1" - # build: synthesize + # build: synthesize ------------------------------------------------ + puts "# current rodinMoreOptions:" + puts [get_param synth.elaboration.rodinMoreOptions] + rvtb_trace_cmd "launch_runs synth_1" rvtb_trace_cmd "wait_on_run synth_1" rvtb_mv_file "$path_syn1/runme.log" "${stem}_syn.log" rvtb_cp_file "$path_syn1/${stem}_utilization_synth.rpt" "${stem}_syn_util.rpt" - rvtb_cp_file "$path_syn1/${stem}.dcp" "${stem}_syn.dcp" + rvtb_cp_file "$path_syn1/${stem}.dcp" "${stem}_syn.dcp" if {$step eq "syn"} {return [rvtb_build_check $step]} - # build: implement - rvtb_trace_cmd "launch_runs impl_1" + # build: implement ------------------------------------------------- + set launch_opt "" + if {$step eq "opt"} {set launch_opt "-to_step opt_design"} + if {$step eq "pla"} {set launch_opt "-to_step place_design"} + + rvtb_trace_cmd "launch_runs ${launch_opt} impl_1" rvtb_trace_cmd "wait_on_run impl_1" rvtb_cp_file "$path_imp1/runme.log" "${stem}_imp.log" - rvtb_cp_file "$path_imp1/${stem}_route_status.rpt" "${stem}_rou_sta.rpt" - rvtb_cp_file "$path_imp1/${stem}_drc_routed.rpt" "${stem}_rou_drc.rpt" + rvtb_cp_file "$path_imp1/${stem}_opt.dcp" "${stem}_opt.dcp" + rvtb_cp_file "$path_imp1/${stem}_drc_opted.rpt" "${stem}_opt_drc.rpt" + + if {$step eq "opt"} { + rvtb_trace_cmd "open_checkpoint $path_imp1/${stem}_opt.dcp" + report_utilization -file "${stem}_opt_util.rpt" + report_utilization -hierarchical -file "${stem}_opt_util_h.rpt" + return [rvtb_build_check $step] + } + + rvtb_cp_file "$path_imp1/${stem}_placed.dcp" "${stem}_pla.dcp" rvtb_cp_file "$path_imp1/${stem}_io_placed.rpt" "${stem}_pla_io.rpt" - rvtb_cp_file "$path_imp1/${stem}_clock_utilization_placed.rpt" \ - "${stem}_pla_clk.rpt" - rvtb_cp_file "$path_imp1/${stem}_timing_summary_routed.rpt" \ - "${stem}_rou_tim.rpt" rvtb_cp_file "$path_imp1/${stem}_utilization_placed.rpt" \ "${stem}_pla_util.rpt" - rvtb_cp_file "$path_imp1/${stem}_drc_opted.rpt" "${stem}_opt_drc.rpt" rvtb_cp_file "$path_imp1/${stem}_control_sets_placed.rpt" \ - "${stem}_pla_cset.rpt" - rvtb_cp_file "$path_imp1/${stem}_power_routed.rpt" "${stem}_rou_pwr.rpt" + "${stem}_pla_clk_set.rpt" - rvtb_cp_file "$path_imp1/${stem}_opt.dcp" "${stem}_opt.dcp" - rvtb_cp_file "$path_imp1/${stem}_placed.dcp" "${stem}_pla.dcp" - rvtb_cp_file "$path_imp1/${stem}_routed.dcp" "${stem}_rou.dcp" + if {$step eq "pla"} { + return [rvtb_build_check $step] + } + + rvtb_cp_file "$path_imp1/${stem}_routed.dcp" "${stem}_rou.dcp" + rvtb_cp_file "$path_imp1/${stem}_route_status.rpt" "${stem}_rou_sta.rpt" + rvtb_cp_file "$path_imp1/${stem}_drc_routed.rpt" "${stem}_rou_drc.rpt" + rvtb_cp_file "$path_imp1/${stem}_timing_summary_routed.rpt" \ + "${stem}_rou_tim.rpt" + rvtb_cp_file "$path_imp1/${stem}_power_routed.rpt" "${stem}_rou_pwr.rpt" + rvtb_cp_file "$path_imp1/${stem}_clock_utilization_routed.rpt" \ + "${stem}_rou_clk_util.rpt" # additional reports rvtb_trace_cmd "open_run impl_1" - report_utilization -file "${stem}_rou_util.rpt" + report_utilization -file "${stem}_rou_util.rpt" report_utilization -hierarchical -file "${stem}_rou_util_h.rpt" - report_datasheet -file "${stem}_rou_ds.rpt" + report_datasheet -file "${stem}_rou_ds.rpt" + report_cdc -file "${stem}_rou_cdc.rpt" + report_clock_interaction -delay_type min_max -significant_digits 3 \ + -file "${stem}_rou_clk_int.rpt" + if {[get_property SSN_REPORT [get_property PART [current_project]]]} { + report_ssn -format TXT -file "${stem}_rou_ssn.rpt" + } if {$step eq "imp"} {return [rvtb_build_check $step]} - # build: bitstream + # build: bitstream ------------------------------------------------- + # check for critical warnings, e.g. + # [Timing 38-282] The design failed to meet the timing requirements. + # in that case abort build + + rvtb_rm_file "./${stem}.bit" + + if {[get_msg_config -severity {critical warning} -count]} { + puts "rvtb_default_build-E: abort due to critical warnings seen before" + puts "rvtb_default_build-E: no bitfile generated" + return [rvtb_build_check $step] + } + rvtb_trace_cmd "launch_runs impl_1 -to_step write_bitstream" rvtb_trace_cmd "wait_on_run impl_1" - rvtb_mv_file "$path_imp1/${stem}.bit" "." - rvtb_mv_file "$path_imp1/runme.log" "${stem}_bit.log" + rvtb_mv_file "$path_imp1/runme.log" "${stem}_bit.log" + rvtb_mv_file "$path_imp1/${stem}.bit" "." return [rvtb_build_check $step] } - diff --git a/rtl/make_viv/viv_tools_config.tcl b/rtl/make_viv/viv_tools_config.tcl index 22a36a6a..96c413d8 100644 --- a/rtl/make_viv/viv_tools_config.tcl +++ b/rtl/make_viv/viv_tools_config.tcl @@ -1,13 +1,27 @@ -# $Id: viv_tools_config.tcl 646 2015-02-15 12:04:55Z mueller $ +# $Id: viv_tools_config.tcl 758 2016-04-02 18:01:39Z mueller $ # -# Copyright 2015- by Walter F.J. Mueller +# Copyright 2015-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2016-04-02 758 1.1 add USR_ACCESS readback # 2015-02-14 646 1.0 Initial version # +# +# -------------------------------------------------------------------- +# +proc rvtb_format_usracc {usracc} { + set sec [expr { ($usracc >> 0) & 0x3f } ]; # 6 bit 05:00 + set min [expr { ($usracc >> 6) & 0x3f } ]; # 6 bit 11:06 + set hr [expr { ($usracc >> 12) & 0x1f } ]; # 5 bit 16:12 + set yr [expr {(($usracc >> 17) & 0x3f)+2000} ]; # 6 bit 22:17 + set mo [expr { ($usracc >> 23) & 0x0f } ]; # 4 bit 26:23 + set day [expr { ($usracc >> 27) & 0x1f } ]; # 5 bit 31:27 + return [format "%04d-%02d-%02d %02d:%02d:%02d" $yr $mo $day $hr $min $sec] +} + # # -------------------------------------------------------------------- # @@ -25,5 +39,13 @@ proc rvtb_default_config {stem} { # and configure FPGA program_hw_devices [lindex [get_hw_devices] 0] + # and check USR_ACCESS setting + set usracc_raw [get_property REGISTER.USR_ACCESS [lindex [get_hw_devices] 0] ] + set usracc_num "0x$usracc_raw" + set usracc_fmt [rvtb_format_usracc $usracc_num] + puts "" + puts "USR_ACCESS: 0x$usracc_raw $usracc_fmt" + puts "" + return ""; } diff --git a/rtl/make_viv/viv_tools_model.tcl b/rtl/make_viv/viv_tools_model.tcl index 9d284428..4fce77cc 100644 --- a/rtl/make_viv/viv_tools_model.tcl +++ b/rtl/make_viv/viv_tools_model.tcl @@ -1,38 +1,59 @@ -# $Id: viv_tools_model.tcl 646 2015-02-15 12:04:55Z mueller $ +# $Id: viv_tools_model.tcl 778 2016-06-25 15:18:01Z mueller $ # -# Copyright 2015- by Walter F.J. Mueller +# Copyright 2015-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2016-06-24 778 1.1 support mode [sor]sim_vhdl [sorepd]sim_veri +# 2016-06-19 777 1.0.1 use full absolute path name for sdf annotate # 2015-02-14 646 1.0 Initial version -# - # # -------------------------------------------------------------------- -# +# supported modes +# base ----- func ----- timing +# vhdl veri veri +# post synth _syn.dcp ssim_vhd ssim_v esim_v +# post phys_opt _opt.dcp osim_vhd osim_v psim_v +# post route _rou.dcp rsim_vhd rsim_v tsim_v +# proc rvtb_default_model {stem mode} { - switch $mode { - ssim { - open_checkpoint "${stem}_syn.dcp" - write_vhdl -mode funcsim -force "${stem}_ssim.vhd" + if {[regexp -- {^([sor])sim_(vhd|v)$} $mode matched type lang] || + [regexp -- {^([ept])sim_(v)$} $mode matched type lang]} { + + switch $type { + s - + e {open_checkpoint "${stem}_syn.dcp"} + o - + p {open_checkpoint "${stem}_opt.dcp"} + r - + t {open_checkpoint "${stem}_rou.dcp"} } - osim { - open_checkpoint "${stem}_opt.dcp" - write_vhdl -mode funcsim -force "${stem}_osim.vhd" + if {$lang eq "vhd"} { + write_vhdl -mode funcsim -force "${stem}_${type}sim.vhd" + } else { + if {$type eq "s" || $type eq "o" || $type eq "r"} { + write_verilog -mode funcsim -force "${stem}_${type}sim.v" + } else { + # use full absolute path name for sdf annotate + # reason: the _tsim.v is sometimes generated in system path and + # used from the tb path. xelab doesn't find the sdf in that case + # Solution are absolute path (ugly) or symlink (ugly, who does setup..) + write_verilog -mode timesim -force \ + -sdf_anno true \ + -sdf_file "[pwd]/${stem}_${type}sim.sdf" \ + "${stem}_${type}sim.v" + write_sdf -mode timesim -force \ + -process_corner slow \ + "${stem}_${type}sim.sdf" + } } - tsim { - open_checkpoint "${stem}_rou.dcp" - write_verilog -mode timesim -force -sdf_anno true "${stem}_tsim.v" - write_sdf -mode timesim -force "${stem}_tsim.sdf" - } - - default { - error "-E: bad mode: $mode"; - } + } else { + error "rvtb_default_model-E: bad mode: $mode"; } + return ""; } diff --git a/rtl/sys_gen/tst_fx2loop/.cvsignore b/rtl/sys_gen/tst_fx2loop/.cvsignore deleted file mode 100644 index d277b2fa..00000000 --- a/rtl/sys_gen/tst_fx2loop/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -tst_fx2loop -tst_fx2loop_si diff --git a/rtl/sys_gen/tst_fx2loop/Makefile b/rtl/sys_gen/tst_fx2loop/Makefile deleted file mode 100644 index 1f6f9e1b..00000000 --- a/rtl/sys_gen/tst_fx2loop/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ -# -# Revision History: -# Date Rev Version Comment -# 2014-11-08 602 1.3 rename realclean->distclean -# 2013-01-05 470 1.2 fix LDLIBS (must come after objs) -# 2012-02-26 458 1.1 add tst_fx2loop_si -# 2011-12-26 445 1.0 Initial version -# -VBOM_all = $(wildcard *.vbom) -NGC_all = $(VBOM_all:.vbom=.ngc) -# -include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk -# -.PHONY : all clean distclean -# -all : tst_fx2loop tst_fx2loop_si -# -clean : ise_clean - rm -f tst_fx2loop - rm -f tst_fx2loop_si -# -distclean : - rm -f tst_fx2loop tst_fx2loop_si -# -CFLAGS = -Wall -O2 -g -LDLIBS = -lusb-1.0 -# -tst_fx2loop : tst_fx2loop.c - ${CC} ${CFLAGS} -o tst_fx2loop tst_fx2loop.c ${LDLIBS} -tst_fx2loop_si : tst_fx2loop_si.c - ${CC} ${CFLAGS} -o tst_fx2loop_si tst_fx2loop_si.c ${LDLIBS} -# -#---- -# -include ${RETROBASE}/rtl/make_ise/generic_xflow.mk -# -ifndef DONTINCDEP -include $(VBOM_all:.vbom=.dep_xst) -endif -# diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic/.cvsignore b/rtl/sys_gen/tst_fx2loop/nexys2/ic/.cvsignore deleted file mode 100644 index 0445c0c1..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic/.cvsignore +++ /dev/null @@ -1 +0,0 @@ -sys_tst_fx2loop_ic_n2.ucf diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic/Makefile b/rtl/sys_gen/tst_fx2loop/nexys2/ic/Makefile deleted file mode 100644 index 02d5983c..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ -# -# Revision History: -# Date Rev Version Comment -# 2012-01-15 453 1.0 Initial version -# -# -VBOM_all = $(wildcard *.vbom) -BIT_all = $(VBOM_all:.vbom=.bit) -# -include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk -FX2_FILE = nexys2_jtag_2fifo_ic.ihx -# -.PHONY : all clean -# -all : $(BIT_all) -# -clean : ise_clean - rm -f $(VBOM_all:.vbom=.ucf) -# -#---- -# -include ${RETROBASE}/rtl/make_ise/generic_xflow.mk -include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk -# -ifndef DONTINCDEP -include $(VBOM_all:.vbom=.dep_xst) -include $(VBOM_all:.vbom=.dep_ghdl) -endif -# diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_conf.vhd b/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_conf.vhd deleted file mode 100644 index fe7e16a9..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_conf.vhd +++ /dev/null @@ -1,58 +0,0 @@ --- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2012- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Package Name: sys_conf --- Description: Definitions for sys_tst_fx2loop_ic_n2 (for synthesis) --- --- Dependencies: - --- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 --- Revision History: --- Date Rev Version Comment --- 2012-01-15 453 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.slvtypes.all; - -package sys_conf is - - constant sys_conf_clkfx_divide : positive := 1; - constant sys_conf_clkfx_multiply : positive := 2; - - constant sys_conf_fx2_type : string := "ic2"; - - -- dummy values defs for generic parameters of as controller - constant sys_conf_fx2_rdpwldelay : positive := 1; - constant sys_conf_fx2_rdpwhdelay : positive := 1; - constant sys_conf_fx2_wrpwldelay : positive := 1; - constant sys_conf_fx2_wrpwhdelay : positive := 1; - constant sys_conf_fx2_flagdelay : positive := 1; - - -- pktend timer setting - -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) - constant sys_conf_fx2_petowidth : positive := 10; - - constant sys_conf_fx2_ccwidth : positive := 5; - - constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers - - -- derived constants - - constant sys_conf_clksys : integer := - (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; - constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; - -end package sys_conf; diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.mfset b/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.mfset deleted file mode 100644 index a6c6a4f4..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.mfset +++ /dev/null @@ -1,63 +0,0 @@ -# $Id: sys_tst_fx2loop_ic_n2.mfset 453 2012-01-15 17:51:18Z mueller $ -# -# ---------------------------------------------------------------------------- -[xst] -INFO:.*Mux is complete : default of case is discarded - -Unconnected output port 'LOCKED' of component 'dcm_sfs' -Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' - -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected - -Signal is assigned but never used - -Input is never used -Input > is never used -Input is never used -Input is never used -Input is never used -Input is never used - -Signal is assigned but never used -Signal is assigned but never used -Signal is assigned but never used - -# -# ---------------------------------------------------------------------------- -[tra] -INFO:.* - TNM 'I_CLK50', used in period specification.*was traced into DCM_SP -The Offset constraint .*, is specified without a duration - -# -# ---------------------------------------------------------------------------- -[map] -The signal is incomplete -The signal _IBUF> is incomplete -The signal _IBUF> is incomplete -The signal _IBUF> is incomplete -INFO:.* - -# -# ---------------------------------------------------------------------------- -[par] -A clock IOB / clock component pair have been found that are not placed at -The Offset constraint .*, is specified without a duration -The signal I_MEM_WAIT_IBUF has no load -The signal I_BTN<1>_IBUF has no load -The signal I_BTN<2>_IBUF has no load -The signal I_BTN<3>_IBUF has no load -There are 4 loadless signals in this design - -# -# ---------------------------------------------------------------------------- -[bgn] -Spartan-3 1200E and 1600E devices do not support bitstream -To achieve optimal frequency synthesis performance .* consult -The signal is incomplete -The signal _IBUF> is incomplete -The signal _IBUF> is incomplete -The signal _IBUF> is incomplete diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.ucf_cpp b/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.ucf_cpp deleted file mode 100644 index 8705a89a..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.ucf_cpp +++ /dev/null @@ -1,15 +0,0 @@ -## $Id: sys_tst_fx2loop_ic_n2.ucf_cpp 453 2012-01-15 17:51:18Z mueller $ -## -## Revision History: -## Date Rev Version Comment -## 2011-12-26 445 1.0 Initial version -## - -NET "I_CLK50" TNM_NET = "I_CLK50"; -TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; -OFFSET = IN 10 ns BEFORE "I_CLK50"; -OFFSET = OUT 20 ns AFTER "I_CLK50"; - -#include "bplib/nexys2/nexys2_pins.ucf" -#include "bplib/nexys2/nexys2_pins_fx2.ucf" -#include "bplib/nexys2/nexys2_time_fx2_ic.ucf" diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.vbom b/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.vbom deleted file mode 100644 index 5e80e277..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.vbom +++ /dev/null @@ -1,8 +0,0 @@ -# conf -sys_conf = sys_conf.vhd -# libs -# components -# design -../sys_tst_fx2loop_n2.vbom -@ucf_cpp: sys_tst_fx2loop_ic_n2.ucf -@top: sys_tst_fx2loop_n2 diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/.cvsignore b/rtl/sys_gen/tst_fx2loop/nexys2/ic3/.cvsignore deleted file mode 100644 index 58ee46ff..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/.cvsignore +++ /dev/null @@ -1 +0,0 @@ -sys_tst_fx2loop_ic3_n2.ucf diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile b/rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile deleted file mode 100644 index 24aef271..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ -# -# Revision History: -# Date Rev Version Comment -# 2012-01-15 453 1.0 Initial version -# -# -VBOM_all = $(wildcard *.vbom) -BIT_all = $(VBOM_all:.vbom=.bit) -# -include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk -FX2_FILE = nexys2_jtag_3fifo_ic.ihx -# -.PHONY : all clean -# -all : $(BIT_all) -# -clean : ise_clean - rm -f $(VBOM_all:.vbom=.ucf) -# -#---- -# -include ${RETROBASE}/rtl/make_ise/generic_xflow.mk -include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk -# -ifndef DONTINCDEP -include $(VBOM_all:.vbom=.dep_xst) -include $(VBOM_all:.vbom=.dep_ghdl) -endif -# diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd b/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd deleted file mode 100644 index 0df1ffe9..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd +++ /dev/null @@ -1,58 +0,0 @@ --- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2012- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Package Name: sys_conf --- Description: Definitions for sys_tst_fx2loop_ic3_n2 (for synthesis) --- --- Dependencies: - --- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 --- Revision History: --- Date Rev Version Comment --- 2012-01-15 453 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.slvtypes.all; - -package sys_conf is - - constant sys_conf_clkfx_divide : positive := 1; - constant sys_conf_clkfx_multiply : positive := 2; - - constant sys_conf_fx2_type : string := "ic3"; - - -- dummy values defs for generic parameters of as controller - constant sys_conf_fx2_rdpwldelay : positive := 1; - constant sys_conf_fx2_rdpwhdelay : positive := 1; - constant sys_conf_fx2_wrpwldelay : positive := 1; - constant sys_conf_fx2_wrpwhdelay : positive := 1; - constant sys_conf_fx2_flagdelay : positive := 1; - - -- pktend timer setting - -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) - constant sys_conf_fx2_petowidth : positive := 10; - - constant sys_conf_fx2_ccwidth : positive := 5; - - constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers - - -- derived constants - - constant sys_conf_clksys : integer := - (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; - constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; - -end package sys_conf; diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset b/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset deleted file mode 100644 index b3184ef3..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset +++ /dev/null @@ -1,58 +0,0 @@ -# $Id: sys_tst_fx2loop_ic3_n2.mfset 453 2012-01-15 17:51:18Z mueller $ -# -# ---------------------------------------------------------------------------- -[xst] -INFO:.*Mux is complete : default of case is discarded - -Unconnected output port 'LOCKED' of component 'dcm_sfs' -Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' - -Node of sequential type is unconnected -Node of sequential type is unconnected - -Input is never used -Input > is never used -Input is never used -Input is never used -Input is never used -Input is never used - -Signal is assigned but never used -Signal is assigned but never used -Signal is assigned but never used - -# -# ---------------------------------------------------------------------------- -[tra] -INFO:.* - TNM 'I_CLK50', used in period specification.*was traced into DCM_SP -The Offset constraint .*, is specified without a duration - -# -# ---------------------------------------------------------------------------- -[map] -The signal is incomplete -The signal _IBUF> is incomplete -The signal _IBUF> is incomplete -The signal _IBUF> is incomplete -INFO:.* - -# -# ---------------------------------------------------------------------------- -[par] -A clock IOB / clock component pair have been found that are not placed at -The Offset constraint .*, is specified without a duration -The signal I_MEM_WAIT_IBUF has no load -The signal I_BTN<1>_IBUF has no load -The signal I_BTN<2>_IBUF has no load -The signal I_BTN<3>_IBUF has no load -There are 4 loadless signals in this design - -# -# ---------------------------------------------------------------------------- -[bgn] -Spartan-3 1200E and 1600E devices do not support bitstream -To achieve optimal frequency synthesis performance .* consult -The signal is incomplete -The signal _IBUF> is incomplete -The signal _IBUF> is incomplete -The signal _IBUF> is incomplete diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp b/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp deleted file mode 100644 index f6440b5a..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp +++ /dev/null @@ -1,15 +0,0 @@ -## $Id: sys_tst_fx2loop_ic3_n2.ucf_cpp 453 2012-01-15 17:51:18Z mueller $ -## -## Revision History: -## Date Rev Version Comment -## 2011-12-26 445 1.0 Initial version -## - -NET "I_CLK50" TNM_NET = "I_CLK50"; -TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; -OFFSET = IN 10 ns BEFORE "I_CLK50"; -OFFSET = OUT 20 ns AFTER "I_CLK50"; - -#include "bplib/nexys2/nexys2_pins.ucf" -#include "bplib/nexys2/nexys2_pins_fx2.ucf" -#include "bplib/nexys2/nexys2_time_fx2_ic.ucf" diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom b/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom deleted file mode 100644 index 143b9299..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom +++ /dev/null @@ -1,8 +0,0 @@ -# conf -sys_conf = sys_conf.vhd -# libs -# components -# design -../sys_tst_fx2loop_n2.vbom -@ucf_cpp: sys_tst_fx2loop_ic3_n2.ucf -@top: sys_tst_fx2loop_n2 diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom b/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom deleted file mode 100644 index ba88e02f..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom +++ /dev/null @@ -1,28 +0,0 @@ -# this is the vbom for the 'generic' top level entity -# to be referenced in the vbom's of the specific systems -# ./ic/sys_tst_fx2loop_ic_n2 -# ./ic3/sys_tst_fx2loop_ic3_n2 -# -# libs -../../../vlib/slvtypes.vhd -../../../vlib/xlib/xlib.vhd -../../../vlib/genlib/genlib.vhd -../../../bplib/bpgen/bpgenlib.vbom -../tst_fx2looplib.vbom -../../../bplib/fx2lib/fx2lib.vhd -../../../bplib/nxcramlib/nxcramlib.vhd -${sys_conf} -# components -[xst,vsyn]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom -[ghdl,isim,vsim]../../../vlib/xlib/dcm_sfs_gsim.vbom -../../../vlib/genlib/clkdivce.vbom -../../../bplib/bpgen/sn_humanio.vbom -../tst_fx2loop_hiomap.vbom -../tst_fx2loop.vbom -../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom -../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom -../../../bplib/nxcramlib/nx_cram_dummy.vbom -# design -sys_tst_fx2loop_n2.vhd -## no @ucf_cpp - diff --git a/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd b/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd deleted file mode 100644 index b07af9db..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd +++ /dev/null @@ -1,316 +0,0 @@ --- $Id: sys_tst_fx2loop_n2.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2011-2015 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: sys_tst_fx2loop_n2 - syn --- Description: test of Cypress EZ-USB FX2 controller --- --- Dependencies: vlib/xlib/dcm_sfs --- vlib/genlib/clkdivce --- bpgen/sn_humanio --- tst_fx2loop_hiomap --- tst_fx2loop --- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"] --- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"] --- bplib/nxcramlib/nx_cram_dummy --- --- Test bench: - --- --- Target Devices: generic --- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 --- --- Synthesized (xst): --- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz --- 2012-04-09 461 13.3 O76d xc3s1200e-4 307 390 64 325 p 9.9 as2/100 --- 2012-04-09 461 13.3 O76d xc3s1200e-4 358 419 64 369 p 9.4 ic2/100 --- 2012-04-09 461 13.3 O76c xc3s1200e-4 436 537 96 476 p 8.9 ic3/100 --- --- Revision History: --- Date Rev Version Comment --- 2015-01-25 638 1.1.1 retire fx2_2fifoctl_as --- 2012-01-15 453 1.1 now generic for as,ic,ic3 controllers --- 2011-12-26 445 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; -use work.xlib.all; -use work.genlib.all; -use work.bpgenlib.all; -use work.tst_fx2looplib.all; -use work.fx2lib.all; -use work.nxcramlib.all; -use work.sys_conf.all; - --- ---------------------------------------------------------------------------- - -entity sys_tst_fx2loop_n2 is -- top level - -- implements nexys2_aif + fx2 pins - port ( - I_CLK50 : in slbit; -- 50 MHz board clock - I_RXD : in slbit; -- receive data (board view) - O_TXD : out slbit; -- transmit data (board view) - I_SWI : in slv8; -- n2 switches - I_BTN : in slv4; -- n2 buttons - O_LED : out slv8; -- n2 leds - O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) - O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) - O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) - O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) - O_MEM_WE_N : out slbit; -- cram: write enable (act.low) - O_MEM_OE_N : out slbit; -- cram: output enable (act.low) - O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) - O_MEM_CLK : out slbit; -- cram: clock - O_MEM_CRE : out slbit; -- cram: command register enable - I_MEM_WAIT : in slbit; -- cram: mem wait - O_MEM_ADDR : out slv23; -- cram: address lines - IO_MEM_DATA : inout slv16; -- cram: data lines - O_FLA_CE_N : out slbit; -- flash ce.. (act.low) - I_FX2_IFCLK : in slbit; -- fx2: interface clock - O_FX2_FIFO : out slv2; -- fx2: fifo address - I_FX2_FLAG : in slv4; -- fx2: fifo flags - O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) - O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) - O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) - O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) - IO_FX2_DATA : inout slv8 -- fx2: data lines - ); -end sys_tst_fx2loop_n2; - -architecture syn of sys_tst_fx2loop_n2 is - - signal CLK : slbit := '0'; - signal RESET : slbit := '0'; - - signal CE_USEC : slbit := '0'; - signal CE_MSEC : slbit := '0'; - - signal SWI : slv8 := (others=>'0'); - signal BTN : slv4 := (others=>'0'); - signal LED : slv8 := (others=>'0'); - signal DSP_DAT : slv16 := (others=>'0'); - signal DSP_DP : slv4 := (others=>'0'); - - signal LED_MAP : slv8 := (others=>'0'); - - signal HIO_CNTL : hio_cntl_type := hio_cntl_init; - signal HIO_STAT : hio_stat_type := hio_stat_init; - - signal FX2_RXDATA : slv8 := (others=>'0'); - signal FX2_RXVAL : slbit := '0'; - signal FX2_RXHOLD : slbit := '0'; - signal FX2_RXAEMPTY : slbit := '0'; - signal FX2_TXDATA : slv8 := (others=>'0'); - signal FX2_TXENA : slbit := '0'; - signal FX2_TXBUSY : slbit := '0'; - signal FX2_TXAFULL : slbit := '0'; - signal FX2_TX2DATA : slv8 := (others=>'0'); - signal FX2_TX2ENA : slbit := '0'; - signal FX2_TX2BUSY : slbit := '1'; - signal FX2_TX2AFULL : slbit := '0'; - signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; - -begin - - assert (sys_conf_clksys mod 1000000) = 0 - report "assert sys_conf_clksys on MHz grid" - severity failure; - - DCM : dcm_sfs - generic map ( - CLKFX_DIVIDE => sys_conf_clkfx_divide, - CLKFX_MULTIPLY => sys_conf_clkfx_multiply, - CLKIN_PERIOD => 20.0) - port map ( - CLKIN => I_CLK50, - CLKFX => CLK, - LOCKED => open - ); - - CLKDIV : clkdivce - generic map ( - CDUWIDTH => 7, -- good for up to 127 MHz ! - USECDIV => sys_conf_clksys_mhz, - MSECDIV => 1000) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC - ); - - HIO : sn_humanio - generic map ( - DEBOUNCE => sys_conf_hio_debounce) - port map ( - CLK => CLK, - RESET => '0', - CE_MSEC => CE_MSEC, - SWI => SWI, - BTN => BTN, - LED => LED, - DSP_DAT => DSP_DAT, - DSP_DP => DSP_DP, - I_SWI => I_SWI, - I_BTN => I_BTN, - O_LED => O_LED, - O_ANO_N => O_ANO_N, - O_SEG_N => O_SEG_N - ); - - RESET <= BTN(0); -- BTN(0) will reset tester !! - - HIOMAP : tst_fx2loop_hiomap - port map ( - CLK => CLK, - RESET => RESET, - HIO_CNTL => HIO_CNTL, - HIO_STAT => HIO_STAT, - FX2_MONI => FX2_MONI, - SWI => SWI, - BTN => BTN, - LED => LED_MAP, - DSP_DAT => DSP_DAT, - DSP_DP => DSP_DP - ); - - proc_led: process (SWI, LED_MAP, FX2_TX2BUSY, FX2_TX2ENA, - FX2_TXBUSY, FX2_TXENA, FX2_RXHOLD, FX2_RXVAL) - begin - - if SWI(4) = '1' then - LED(7) <= '0'; - LED(6) <= '0'; - LED(5) <= FX2_TX2BUSY; - LED(4) <= FX2_TX2ENA; - LED(3) <= FX2_TXBUSY; - LED(2) <= FX2_TXENA; - LED(1) <= FX2_RXHOLD; - LED(0) <= FX2_RXVAL; - else - LED <= LED_MAP; - end if; - - end process proc_led; - - - TST : tst_fx2loop - port map ( - CLK => CLK, - RESET => RESET, - CE_MSEC => CE_MSEC, - HIO_CNTL => HIO_CNTL, - HIO_STAT => HIO_STAT, - FX2_MONI => FX2_MONI, - RXDATA => FX2_RXDATA, - RXVAL => FX2_RXVAL, - RXHOLD => FX2_RXHOLD, - TXDATA => FX2_TXDATA, - TXENA => FX2_TXENA, - TXBUSY => FX2_TXBUSY, - TX2DATA => FX2_TX2DATA, - TX2ENA => FX2_TX2ENA, - TX2BUSY => FX2_TX2BUSY - ); - - FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate - CNTL : fx2_2fifoctl_ic - generic map ( - RXFAWIDTH => 5, - TXFAWIDTH => 5, - PETOWIDTH => sys_conf_fx2_petowidth, - CCWIDTH => sys_conf_fx2_ccwidth, - RXAEMPTY_THRES => 1, - TXAFULL_THRES => 1) - port map ( - CLK => CLK, - RESET => RESET, - RXDATA => FX2_RXDATA, - RXVAL => FX2_RXVAL, - RXHOLD => FX2_RXHOLD, - RXAEMPTY => FX2_RXAEMPTY, - TXDATA => FX2_TXDATA, - TXENA => FX2_TXENA, - TXBUSY => FX2_TXBUSY, - TXAFULL => FX2_TXAFULL, - MONI => FX2_MONI, - I_FX2_IFCLK => I_FX2_IFCLK, - O_FX2_FIFO => O_FX2_FIFO, - I_FX2_FLAG => I_FX2_FLAG, - O_FX2_SLRD_N => O_FX2_SLRD_N, - O_FX2_SLWR_N => O_FX2_SLWR_N, - O_FX2_SLOE_N => O_FX2_SLOE_N, - O_FX2_PKTEND_N => O_FX2_PKTEND_N, - IO_FX2_DATA => IO_FX2_DATA - ); - end generate FX2_CNTL_IC; - - FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate - CNTL : fx2_3fifoctl_ic - generic map ( - RXFAWIDTH => 5, - TXFAWIDTH => 5, - PETOWIDTH => sys_conf_fx2_petowidth, - CCWIDTH => sys_conf_fx2_ccwidth, - RXAEMPTY_THRES => 1, - TXAFULL_THRES => 1, - TX2AFULL_THRES => 1) - port map ( - CLK => CLK, - RESET => RESET, - RXDATA => FX2_RXDATA, - RXVAL => FX2_RXVAL, - RXHOLD => FX2_RXHOLD, - RXAEMPTY => FX2_RXAEMPTY, - TXDATA => FX2_TXDATA, - TXENA => FX2_TXENA, - TXBUSY => FX2_TXBUSY, - TXAFULL => FX2_TXAFULL, - TX2DATA => FX2_TX2DATA, - TX2ENA => FX2_TX2ENA, - TX2BUSY => FX2_TX2BUSY, - TX2AFULL => FX2_TX2AFULL, - MONI => FX2_MONI, - I_FX2_IFCLK => I_FX2_IFCLK, - O_FX2_FIFO => O_FX2_FIFO, - I_FX2_FLAG => I_FX2_FLAG, - O_FX2_SLRD_N => O_FX2_SLRD_N, - O_FX2_SLWR_N => O_FX2_SLWR_N, - O_FX2_SLOE_N => O_FX2_SLOE_N, - O_FX2_PKTEND_N => O_FX2_PKTEND_N, - IO_FX2_DATA => IO_FX2_DATA - ); - end generate FX2_CNTL_IC3; - - SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy - port map ( - O_MEM_CE_N => O_MEM_CE_N, - O_MEM_BE_N => O_MEM_BE_N, - O_MEM_WE_N => O_MEM_WE_N, - O_MEM_OE_N => O_MEM_OE_N, - O_MEM_ADV_N => O_MEM_ADV_N, - O_MEM_CLK => O_MEM_CLK, - O_MEM_CRE => O_MEM_CRE, - I_MEM_WAIT => I_MEM_WAIT, - O_MEM_ADDR => O_MEM_ADDR, - IO_MEM_DATA => IO_MEM_DATA - ); - - O_FLA_CE_N <= '1'; -- keep Flash memory disabled - - O_TXD <= I_RXD; -- loop-back in serial port... - -end syn; - diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/ic/.cvsignore b/rtl/sys_gen/tst_fx2loop/nexys3/ic/.cvsignore deleted file mode 100644 index 06082257..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys3/ic/.cvsignore +++ /dev/null @@ -1 +0,0 @@ -sys_tst_fx2loop_ic_n3.ucf diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile b/rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile deleted file mode 100644 index 4635374e..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ -# -# Revision History: -# Date Rev Version Comment -# 2012-04-09 461 1.0 Initial version -# -# -VBOM_all = $(wildcard *.vbom) -BIT_all = $(VBOM_all:.vbom=.bit) -# -include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk -FX2_FILE = nexys3_jtag_2fifo_ic.ihx -# -.PHONY : all clean -# -all : $(BIT_all) -# -clean : ise_clean - rm -f $(VBOM_all:.vbom=.ucf) -# -#---- -# -include ${RETROBASE}/rtl/make_ise/generic_xflow.mk -include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk -# -ifndef DONTINCDEP -include $(VBOM_all:.vbom=.dep_xst) -include $(VBOM_all:.vbom=.dep_ghdl) -endif -# diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_conf.vhd b/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_conf.vhd deleted file mode 100644 index 1ea1f4d4..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_conf.vhd +++ /dev/null @@ -1,63 +0,0 @@ --- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2012-2013 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Package Name: sys_conf --- Description: Definitions for sys_tst_fx2loop_ic_n3 (for synthesis) --- --- Dependencies: - --- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 --- Revision History: --- Date Rev Version Comment --- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect --- 2012-04-24 510 1.1 use 3/2 clock-> 150 MHz sysclk --- 2012-04-09 461 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.slvtypes.all; - -package sys_conf is - - constant sys_conf_clksys_vcodivide : positive := 2; - constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 150 MHz - constant sys_conf_clksys_outdivide : positive := 1; -- sys 150 MHz - constant sys_conf_clksys_gentype : string := "DCM"; - - constant sys_conf_fx2_type : string := "ic2"; - - -- dummy values defs for generic parameters of as controller - constant sys_conf_fx2_rdpwldelay : positive := 1; - constant sys_conf_fx2_rdpwhdelay : positive := 1; - constant sys_conf_fx2_wrpwldelay : positive := 1; - constant sys_conf_fx2_wrpwhdelay : positive := 1; - constant sys_conf_fx2_flagdelay : positive := 1; - - -- pktend timer setting - -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) - constant sys_conf_fx2_petowidth : positive := 10; - - constant sys_conf_fx2_ccwidth : positive := 5; - - constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers - - -- derived constants - - constant sys_conf_clksys : integer := - ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / - sys_conf_clksys_outdivide; - constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; - -end package sys_conf; diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.ucf_cpp b/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.ucf_cpp deleted file mode 100644 index 90de95f4..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.ucf_cpp +++ /dev/null @@ -1,48 +0,0 @@ -## $Id: sys_tst_fx2loop_ic_n3.ucf_cpp 556 2014-05-29 19:01:39Z mueller $ -## -## Revision History: -## Date Rev Version Comment -## 2013-10-13 540 1.1 add pad->clk and fx2 cdc constraints -## 2012-04-09 461 1.0 Initial version -## - -NET "I_CLK100" TNM_NET = "I_CLK100"; -TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; -OFFSET = IN 10 ns BEFORE "I_CLK100"; -OFFSET = OUT 20 ns AFTER "I_CLK100"; - -## constrain pad->net clock delay -NET CLK TNM = TNM_CLK; -TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK100) TO TNM_CLK 10 ns; -NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK; -TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns; - -## constrain async pad->pad delays -TIMEGRP TG_SLOW_INS = PADS(I_RXD); -TIMEGRP TG_SLOW_OUTS = PADS(O_TXD); -TIMESPEC TS_ASYNC_PADS=FROM TG_SLOW_INS TO TG_SLOW_OUTS 10 ns; - -## FX2 controller specific constraints -## constrain cdc path in fifos and reset -TIMESPEC TS_CDC_FIFO = - FROM FFS(*FIFO/GC?/GRAY_*.CNT/R_DATA* - *FIFO/R_REG?_rst? - *FIFO/R_REG?_rst?_s) - TO FFS(*FIFO/R_REG?_?addr_c* - *FIFO/R_REG?_rst?_c - *FIFO/R_REG?_rst?_sc) - 5 ns DATAPATHONLY; - -## constrain cdc path in monitor -TIMESPEC TS_CDC_FX2MONI = FROM FFS - TO FFS(FX2_CNTL*/R_MONI_C*) 5 ns DATAPATHONLY; - -## -## std board -## -#include "bplib/nexys3/nexys3_pins.ucf" -## -## FX2 interface -## -#include "bplib/nexys3/nexys3_pins_fx2.ucf" -#include "bplib/nexys3/nexys3_time_fx2_ic.ucf" diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.vbom b/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.vbom deleted file mode 100644 index 49e749ba..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.vbom +++ /dev/null @@ -1,8 +0,0 @@ -# conf -sys_conf = sys_conf.vhd -# libs -# components -# design -../sys_tst_fx2loop_n3.vbom -@ucf_cpp: sys_tst_fx2loop_ic_n3.ucf -@top: sys_tst_fx2loop_n3 diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/ic3/.cvsignore b/rtl/sys_gen/tst_fx2loop/nexys3/ic3/.cvsignore deleted file mode 100644 index ebe1a6e1..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys3/ic3/.cvsignore +++ /dev/null @@ -1 +0,0 @@ -sys_tst_fx2loop_ic3_n3.ucf diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile b/rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile deleted file mode 100644 index 24fae27a..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ -# -# Revision History: -# Date Rev Version Comment -# 2012-04-09 461 1.0 Initial version -# -# -VBOM_all = $(wildcard *.vbom) -BIT_all = $(VBOM_all:.vbom=.bit) -# -include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk -FX2_FILE = nexys3_jtag_3fifo_ic.ihx -# -.PHONY : all clean -# -all : $(BIT_all) -# -clean : ise_clean - rm -f $(VBOM_all:.vbom=.ucf) -# -#---- -# -include ${RETROBASE}/rtl/make_ise/generic_xflow.mk -include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk -# -ifndef DONTINCDEP -include $(VBOM_all:.vbom=.dep_xst) -include $(VBOM_all:.vbom=.dep_ghdl) -endif -# diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_conf.vhd b/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_conf.vhd deleted file mode 100644 index 56de9076..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_conf.vhd +++ /dev/null @@ -1,63 +0,0 @@ --- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2012-2013 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Package Name: sys_conf --- Description: Definitions for sys_tst_fx2loop_ic3_n3 (for synthesis) --- --- Dependencies: - --- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 --- Revision History: --- Date Rev Version Comment --- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect --- 2012-04-25 510 1.1 use 3/2 clock-> 150 MHz sysclk --- 2012-04-09 461 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.slvtypes.all; - -package sys_conf is - - constant sys_conf_clksys_vcodivide : positive := 2; - constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 150 MHz - constant sys_conf_clksys_outdivide : positive := 1; -- sys 150 MHz - constant sys_conf_clksys_gentype : string := "DCM"; - - constant sys_conf_fx2_type : string := "ic3"; - - -- dummy values defs for generic parameters of as controller - constant sys_conf_fx2_rdpwldelay : positive := 1; - constant sys_conf_fx2_rdpwhdelay : positive := 1; - constant sys_conf_fx2_wrpwldelay : positive := 1; - constant sys_conf_fx2_wrpwhdelay : positive := 1; - constant sys_conf_fx2_flagdelay : positive := 1; - - -- pktend timer setting - -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) - constant sys_conf_fx2_petowidth : positive := 10; - - constant sys_conf_fx2_ccwidth : positive := 5; - - constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers - - -- derived constants - - constant sys_conf_clksys : integer := - ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / - sys_conf_clksys_outdivide; - constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; - -end package sys_conf; diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.ucf_cpp b/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.ucf_cpp deleted file mode 100644 index 14535ffd..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.ucf_cpp +++ /dev/null @@ -1,20 +0,0 @@ -## $Id: sys_tst_fx2loop_ic3_n3.ucf_cpp 461 2012-04-09 21:17:54Z mueller $ -## -## Revision History: -## Date Rev Version Comment -## 2012-04-09 461 1.0 Initial version -## - -NET "I_CLK100" TNM_NET = "I_CLK100"; -TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; -OFFSET = IN 10 ns BEFORE "I_CLK100"; -OFFSET = OUT 20 ns AFTER "I_CLK100"; - -## std board -## -#include "bplib/nexys3/nexys3_pins.ucf" -## -## FX2 interface -## -#include "bplib/nexys3/nexys3_pins_fx2.ucf" -#include "bplib/nexys3/nexys3_time_fx2_ic.ucf" diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.vbom b/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.vbom deleted file mode 100644 index bed54e92..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.vbom +++ /dev/null @@ -1,8 +0,0 @@ -# conf -sys_conf = sys_conf.vhd -# libs -# components -# design -../sys_tst_fx2loop_n3.vbom -@ucf_cpp: sys_tst_fx2loop_ic3_n3.ucf -@top: sys_tst_fx2loop_n3 diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom b/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom deleted file mode 100644 index 8bc82ddc..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom +++ /dev/null @@ -1,28 +0,0 @@ -# this is the vbom for the 'generic' top level entity -# to be referenced in the vbom's of the specific systems -# ./ic/sys_tst_fx2loop_ic_n3 -# ./ic3/sys_tst_fx2loop_ic3_n3 -# -# libs -../../../vlib/slvtypes.vhd -../../../vlib/xlib/xlib.vhd -../../../vlib/genlib/genlib.vhd -../../../bplib/bpgen/bpgenlib.vbom -../tst_fx2looplib.vbom -../../../bplib/fx2lib/fx2lib.vhd -../../../bplib/nxcramlib/nxcramlib.vhd -${sys_conf} -# components -[xst,vsyn]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom -[ghdl,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom -../../../vlib/genlib/clkdivce.vbom -../../../bplib/bpgen/sn_humanio.vbom -../tst_fx2loop_hiomap.vbom -../tst_fx2loop.vbom -../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom -../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom -../../../bplib/nxcramlib/nx_cram_dummy.vbom -# design -sys_tst_fx2loop_n3.vhd -## no @ucf_cpp - diff --git a/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd b/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd deleted file mode 100644 index f26e6006..00000000 --- a/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd +++ /dev/null @@ -1,330 +0,0 @@ --- $Id: sys_tst_fx2loop_n3.vhd 638 2015-01-25 22:01:38Z mueller $ --- --- Copyright 2012-2015 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: sys_tst_fx2loop_n3 - syn --- Description: test of Cypress EZ-USB FX2 controller --- --- Dependencies: vlib/xlib/s6_cmt_sfs --- vlib/genlib/clkdivce --- bpgen/sn_humanio --- tst_fx2loop_hiomap --- tst_fx2loop --- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"] --- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"] --- bplib/nxcramlib/nx_cram_dummy --- --- Test bench: - --- --- Target Devices: generic --- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 --- --- Synthesized (xst): --- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz --- 2013-04-25 510 14.5 P58f xc6slx16-2 416 516 68 199 p 5.3 ic3/150 --- 2013-04-24 510 13.3 O76d xc6slx16-2 417 674 68 228 p 5.3 ic3/175 --- 2012-04-09 461 13.3 O76d xc6slx16-2 429 620 48 232 p 7.2 ic3/100 --- --- 2013-04-25 510 14.5 P58f xc6slx16-2 349 427 48 163 p 5.4 ic2/150 --- 2013-04-24 510 13.3 O76d xc6slx16-2 355 569 48 208 p 5.4 ic2/175 --- 2012-04-09 461 13.3 O76d xc6slx16-2 347 499 32 175 p 7.9 ic2/100 --- --- 2013-04-24 510 13.3 O76d xc6slx16-2 299 486 32 175 p FAIL as2/100 --- 2012-04-09 461 13.3 O76d xc6slx16-2 299 460 32 164 p FAIL as2/100 --- --- Revision History: --- Date Rev Version Comment --- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect --- 2013-04-24 510 1.0.1 CLKDIV.CDUWIDTH now 8, support >127 sysclk --- 2012-04-09 461 1.0 Initial version (derived from sys_tst_fx2loop_n2) ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; -use work.xlib.all; -use work.genlib.all; -use work.bpgenlib.all; -use work.tst_fx2looplib.all; -use work.fx2lib.all; -use work.nxcramlib.all; -use work.sys_conf.all; - --- ---------------------------------------------------------------------------- - -entity sys_tst_fx2loop_n3 is -- top level - -- implements nexys3_aif + fx2 pins - port ( - I_CLK100 : in slbit; -- 100 MHz clock - I_RXD : in slbit; -- receive data (board view) - O_TXD : out slbit; -- transmit data (board view) - I_SWI : in slv8; -- n3 switches - I_BTN : in slv5; -- n3 buttons - O_LED : out slv8; -- n3 leds - O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) - O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) - O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) - O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) - O_MEM_WE_N : out slbit; -- cram: write enable (act.low) - O_MEM_OE_N : out slbit; -- cram: output enable (act.low) - O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) - O_MEM_CLK : out slbit; -- cram: clock - O_MEM_CRE : out slbit; -- cram: command register enable - I_MEM_WAIT : in slbit; -- cram: mem wait - O_MEM_ADDR : out slv23; -- cram: address lines - IO_MEM_DATA : inout slv16; -- cram: data lines - O_PPCM_CE_N : out slbit; -- ppcm: ... - O_PPCM_RST_N : out slbit; -- ppcm: ... - I_FX2_IFCLK : in slbit; -- fx2: interface clock - O_FX2_FIFO : out slv2; -- fx2: fifo address - I_FX2_FLAG : in slv4; -- fx2: fifo flags - O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) - O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) - O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) - O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) - IO_FX2_DATA : inout slv8 -- fx2: data lines - ); -end sys_tst_fx2loop_n3; - -architecture syn of sys_tst_fx2loop_n3 is - - signal CLK : slbit := '0'; - signal RESET : slbit := '0'; - - signal CE_USEC : slbit := '0'; - signal CE_MSEC : slbit := '0'; - - signal SWI : slv8 := (others=>'0'); - signal BTN : slv5 := (others=>'0'); - signal LED : slv8 := (others=>'0'); - signal DSP_DAT : slv16 := (others=>'0'); - signal DSP_DP : slv4 := (others=>'0'); - - signal LED_MAP : slv8 := (others=>'0'); - - signal HIO_CNTL : hio_cntl_type := hio_cntl_init; - signal HIO_STAT : hio_stat_type := hio_stat_init; - - signal FX2_RXDATA : slv8 := (others=>'0'); - signal FX2_RXVAL : slbit := '0'; - signal FX2_RXHOLD : slbit := '0'; - signal FX2_RXAEMPTY : slbit := '0'; - signal FX2_TXDATA : slv8 := (others=>'0'); - signal FX2_TXENA : slbit := '0'; - signal FX2_TXBUSY : slbit := '0'; - signal FX2_TXAFULL : slbit := '0'; - signal FX2_TX2DATA : slv8 := (others=>'0'); - signal FX2_TX2ENA : slbit := '0'; - signal FX2_TX2BUSY : slbit := '1'; - signal FX2_TX2AFULL : slbit := '0'; - signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; - -begin - - assert (sys_conf_clksys mod 1000000) = 0 - report "assert sys_conf_clksys on MHz grid" - severity failure; - - GEN_CLKSYS : s6_cmt_sfs - generic map ( - VCO_DIVIDE => sys_conf_clksys_vcodivide, - VCO_MULTIPLY => sys_conf_clksys_vcomultiply, - OUT_DIVIDE => sys_conf_clksys_outdivide, - CLKIN_PERIOD => 10.0, - CLKIN_JITTER => 0.01, - STARTUP_WAIT => false, - GEN_TYPE => sys_conf_clksys_gentype) - port map ( - CLKIN => I_CLK100, - CLKFX => CLK, - LOCKED => open - ); - - CLKDIV : clkdivce - generic map ( - CDUWIDTH => 8, -- good for up to 255 MHz ! - USECDIV => sys_conf_clksys_mhz, - MSECDIV => 1000) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC - ); - - HIO : sn_humanio - generic map ( - BWIDTH => 5, - DEBOUNCE => sys_conf_hio_debounce) - port map ( - CLK => CLK, - RESET => '0', - CE_MSEC => CE_MSEC, - SWI => SWI, - BTN => BTN, - LED => LED, - DSP_DAT => DSP_DAT, - DSP_DP => DSP_DP, - I_SWI => I_SWI, - I_BTN => I_BTN, - O_LED => O_LED, - O_ANO_N => O_ANO_N, - O_SEG_N => O_SEG_N - ); - - RESET <= BTN(0); -- BTN(0) will reset tester !! - - HIOMAP : tst_fx2loop_hiomap - port map ( - CLK => CLK, - RESET => RESET, - HIO_CNTL => HIO_CNTL, - HIO_STAT => HIO_STAT, - FX2_MONI => FX2_MONI, - SWI => SWI, - BTN => BTN(3 downto 0), - LED => LED_MAP, - DSP_DAT => DSP_DAT, - DSP_DP => DSP_DP - ); - - proc_led: process (SWI, LED_MAP, FX2_TX2BUSY, FX2_TX2ENA, - FX2_TXBUSY, FX2_TXENA, FX2_RXHOLD, FX2_RXVAL) - begin - - if SWI(4) = '1' then - LED(7) <= '0'; - LED(6) <= '0'; - LED(5) <= FX2_TX2BUSY; - LED(4) <= FX2_TX2ENA; - LED(3) <= FX2_TXBUSY; - LED(2) <= FX2_TXENA; - LED(1) <= FX2_RXHOLD; - LED(0) <= FX2_RXVAL; - else - LED <= LED_MAP; - end if; - - end process proc_led; - - - TST : tst_fx2loop - port map ( - CLK => CLK, - RESET => RESET, - CE_MSEC => CE_MSEC, - HIO_CNTL => HIO_CNTL, - HIO_STAT => HIO_STAT, - FX2_MONI => FX2_MONI, - RXDATA => FX2_RXDATA, - RXVAL => FX2_RXVAL, - RXHOLD => FX2_RXHOLD, - TXDATA => FX2_TXDATA, - TXENA => FX2_TXENA, - TXBUSY => FX2_TXBUSY, - TX2DATA => FX2_TX2DATA, - TX2ENA => FX2_TX2ENA, - TX2BUSY => FX2_TX2BUSY - ); - - FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate - CNTL : fx2_2fifoctl_ic - generic map ( - RXFAWIDTH => 5, - TXFAWIDTH => 5, - PETOWIDTH => sys_conf_fx2_petowidth, - CCWIDTH => sys_conf_fx2_ccwidth, - RXAEMPTY_THRES => 1, - TXAFULL_THRES => 1) - port map ( - CLK => CLK, - RESET => RESET, - RXDATA => FX2_RXDATA, - RXVAL => FX2_RXVAL, - RXHOLD => FX2_RXHOLD, - RXAEMPTY => FX2_RXAEMPTY, - TXDATA => FX2_TXDATA, - TXENA => FX2_TXENA, - TXBUSY => FX2_TXBUSY, - TXAFULL => FX2_TXAFULL, - MONI => FX2_MONI, - I_FX2_IFCLK => I_FX2_IFCLK, - O_FX2_FIFO => O_FX2_FIFO, - I_FX2_FLAG => I_FX2_FLAG, - O_FX2_SLRD_N => O_FX2_SLRD_N, - O_FX2_SLWR_N => O_FX2_SLWR_N, - O_FX2_SLOE_N => O_FX2_SLOE_N, - O_FX2_PKTEND_N => O_FX2_PKTEND_N, - IO_FX2_DATA => IO_FX2_DATA - ); - end generate FX2_CNTL_IC; - - FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate - CNTL : fx2_3fifoctl_ic - generic map ( - RXFAWIDTH => 5, - TXFAWIDTH => 5, - PETOWIDTH => sys_conf_fx2_petowidth, - CCWIDTH => sys_conf_fx2_ccwidth, - RXAEMPTY_THRES => 1, - TXAFULL_THRES => 1, - TX2AFULL_THRES => 1) - port map ( - CLK => CLK, - RESET => RESET, - RXDATA => FX2_RXDATA, - RXVAL => FX2_RXVAL, - RXHOLD => FX2_RXHOLD, - RXAEMPTY => FX2_RXAEMPTY, - TXDATA => FX2_TXDATA, - TXENA => FX2_TXENA, - TXBUSY => FX2_TXBUSY, - TXAFULL => FX2_TXAFULL, - TX2DATA => FX2_TX2DATA, - TX2ENA => FX2_TX2ENA, - TX2BUSY => FX2_TX2BUSY, - TX2AFULL => FX2_TX2AFULL, - MONI => FX2_MONI, - I_FX2_IFCLK => I_FX2_IFCLK, - O_FX2_FIFO => O_FX2_FIFO, - I_FX2_FLAG => I_FX2_FLAG, - O_FX2_SLRD_N => O_FX2_SLRD_N, - O_FX2_SLWR_N => O_FX2_SLWR_N, - O_FX2_SLOE_N => O_FX2_SLOE_N, - O_FX2_PKTEND_N => O_FX2_PKTEND_N, - IO_FX2_DATA => IO_FX2_DATA - ); - end generate FX2_CNTL_IC3; - - SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy - port map ( - O_MEM_CE_N => O_MEM_CE_N, - O_MEM_BE_N => O_MEM_BE_N, - O_MEM_WE_N => O_MEM_WE_N, - O_MEM_OE_N => O_MEM_OE_N, - O_MEM_ADV_N => O_MEM_ADV_N, - O_MEM_CLK => O_MEM_CLK, - O_MEM_CRE => O_MEM_CRE, - I_MEM_WAIT => I_MEM_WAIT, - O_MEM_ADDR => O_MEM_ADDR, - IO_MEM_DATA => IO_MEM_DATA - ); - - O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled - O_PPCM_RST_N <= '1'; -- - - O_TXD <= I_RXD; -- loop-back in serial port... - -end syn; - diff --git a/rtl/sys_gen/tst_fx2loop/tst_fx2loop.c b/rtl/sys_gen/tst_fx2loop/tst_fx2loop.c deleted file mode 100644 index 65d3577a..00000000 --- a/rtl/sys_gen/tst_fx2loop/tst_fx2loop.c +++ /dev/null @@ -1,1045 +0,0 @@ -/* $Id: tst_fx2loop.c 530 2013-08-09 21:25:04Z mueller $ */ -/* - * Copyright 2011-2013 by Walter F.J. Mueller - * - * This program is free software; you may redistribute and/or modify it under - * the terms of the GNU General Public License as published by the Free - * Software Foundation, either version 2, or at your option any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for complete details. - * - * - * Revision History: - * Date Rev Version Comment - * 2013-08-09 530 2.1.2 -read: write up to 9 nstead of 7 words - * 2012-04-09 461 2.1.1 fix loop back code: fix run-down, add pipe drain - * 2012-03-24 460 2.1 add message loop back code (preliminary) - * 2012-03-10 459 2.0 re-write for asynchronous libusb interface - * 2012-02-12 457 1.1 redo argument handling; add -stat and -rndm - * 2012-01-15 453 1.0.1 add -tx2blast; fix bug in loop read loop - * 2011-12-29 446 1.0 Initial version (only -read/write/loop) -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -static int nsigint = 0; -static int endpoll = 0; -static libusb_context* pUsbContext = 0; -static libusb_device** pUsbDevList = 0; -static int UsbDevCount = 0; -static libusb_device_handle* pUsbDevHdl = 0; - -static struct pollfd pollfd_fds[16]; -static int pollfd_nfds = 0; - -struct dsc_queue { - int par_nfrm; - int par_nque; - double stat_nbuf; - double stat_nbyt; - double stat_npt; - uint16_t cval; -}; - -static struct dsc_queue dsc_rx; -static struct dsc_queue dsc_tx1; -static struct dsc_queue dsc_tx2; - -static int par_nwmsg = 0; -static int par_nwrndm = 0; -static int par_stat = 0; -static int par_trace = 0; -static int par_nsec = 0; - -static int cur_nwmsg = 0; -static double stat_nmsg = 0.; - -static double t_start; -static int nreq = 0; - -static char** argv; -static int argc; -static int argi; - - -void usage(FILE* of); -int get_pint(char* p); -double get_double(char* p); -int get_arg_pint(int min, int max, const char* text); - -void do_write(uint16_t* buf, int nw); -void do_read(int ep); -void do_run(); -void do_stat(); -void usb_claim(); -void usb_release(); -char* usb_strerror(int rc); -void prt_time(void); -double get_time(void); -void bad_syscall_exit(const char* text, int rc); -void bad_usbcall_exit(const char* text, int rc); -void bad_transfer_exit(struct libusb_transfer *t, const char* text); - -void sigint_handler(int signum) -{ - printf("\n"); - nsigint += 1; - if (nsigint > 3) { - fprintf(stderr, "tst_fx2loop-F: 3rd ^C, aborting\n"); - exit(EXIT_FAILURE); - } - return; -} - -int main(int main_argc, char *main_argv[]) -{ - argc = main_argc; - argv = main_argv; - argi = 1; - - int i; - - /* setup ^C handler */ - struct sigaction new_action; - - new_action.sa_handler = sigint_handler; - sigemptyset (&new_action.sa_mask); - new_action.sa_flags = 0; - sigaction (SIGINT, &new_action, NULL); - - /* capture -help case here */ - for (i = 1; i < argc; i++) { - if (strcmp(argv[i], "-help") == 0) { - usage(stdout); - return EXIT_SUCCESS; - } - } - - /* determine usb device path (first arg or from RETRO_FX2_VID/PID */ - char devbuf[10]; - char* path = 0; - - if (argc > argi && argv[argi][0] != '-') { - path = argv[argi]; - argi += 1; - } else { - char* env_vid = getenv("RETRO_FX2_VID"); - char* env_pid = getenv("RETRO_FX2_PID"); - if (env_vid && strlen(env_vid) == 4 && - env_pid && strlen(env_pid) == 4) { - strncpy(devbuf , env_vid,4); - devbuf[4] = ':'; - strncpy(devbuf+5, env_pid,4); - devbuf[9] = 0; - path = devbuf; - } else { - fprintf(stderr, - "tst_fx2loop-F: RETRO_FX2_VID/PID not or ill defined\n"); - return EXIT_FAILURE; - } - } - - /* init libusb, connect to device */ - libusb_init(&pUsbContext); - libusb_set_debug(pUsbContext, 3); - UsbDevCount = libusb_get_device_list(pUsbContext, &pUsbDevList); - - libusb_device* mydev = 0; - - if (strlen(path)==8 && path[0]=='/' && path[4]=='/') { - char busnam[4]; - char devnam[4]; - strncpy(busnam, path+1, 3); - strncpy(devnam, path+5, 3); - busnam[3] = 0; - devnam[3] = 0; - - char* endptr; - uint8_t busnum = strtol(busnam, &endptr, 10); - uint8_t devnum = strtol(devnam, &endptr, 10); - - int idev; - for (idev=0; idev 0xffff) { - nw = 0; - break; - } - argi += 1; - buf[nw++] = (uint16_t)val; - } - if (nw == 0) { - fprintf(stderr, "tst_fx2loop-E: bad word list\n"); - break; - } - do_write(buf, nw); - - } else if (strcmp(argv[argi],"-read") == 0) { - argi += 1; - int ep = 6; - if (argi < argc) ep = get_pint(argv[argi++]); - if (ep != 6 && ep != 8) { - fprintf(stderr, "tst_fx2loop-F: bad read endpoint (must be 6 or 8)\n"); - return EXIT_FAILURE; - } - do_read(ep); - - } else if (strcmp(argv[argi],"-run") == 0) { - argi += 1; - if (argi < argc) par_nsec = get_pint(argv[argi++]); - if (par_nsec < 0) { - fprintf(stderr, "tst_fx2loop-E: bad args for -run\n"); - break; - } - do_run(); - do_stat(); - - } else { - fprintf(stderr, "tst_fx2loop-F: unknown option %s\n", argv[argi]); - usage(stderr); - return EXIT_FAILURE; - } - } - - return EXIT_SUCCESS; -} - -/*--------------------------------------------------------------------------*/ -void usage(FILE* of) -{ - fprintf(of, "Usage: tst_fx2loop [dev] [setup-opts...] [action-opts...]\n"); - fprintf(of, " arguments:\n"); - fprintf(of, " dev path usb device, either bus/dev or vend:prod\n"); - fprintf(of, " default is $RETRO_FX2_VID:$RETRO_FX2_VID\n"); - fprintf(of, " setup options:\n"); - fprintf(of, " -nbrx nb buffer size (in 512B) for rxblast\n"); - fprintf(of, " -nqrx nb number of buffers for rxblast\n"); - fprintf(of, " -nbtx nb buffer size (in 512B) for txblast or loop\n"); - fprintf(of, " -nqtx nb number of buffers for txblast or loop\n"); - fprintf(of, " -nbtx2 nb buffer size (in 512B) for tx2blast\n"); - fprintf(of, " -nqtx2 nb number of buffers for tx2blast\n"); - fprintf(of, " -nwmsg nw number words for loop test\n"); - fprintf(of, " -rndm use random length for loop test\n"); - fprintf(of, " -stat print live stats\n"); - fprintf(of, " -trace trace usb calls\n"); - fprintf(of, " action options:\n"); - fprintf(of, " -write w0 w1 ... write list of words to endpoint 4\n"); - fprintf(of, " -read ep read from endpoint ep\n"); - fprintf(of, " -run ns run tests for nw seconds\n"); -} - -/*--------------------------------------------------------------------------*/ - -int get_pint(char* p) -{ - char *endptr; - long num = 0; - - num = strtol(p, &endptr, 0); - if ((endptr && *endptr) || num < 0 || num > INT_MAX) { - fprintf(stderr, "tst_fx2loop-E: \"%s\" not a non-negative integer\n", p); - return -1; - } - return num; -} - -/*--------------------------------------------------------------------------*/ - -double get_double(char* p) -{ - char *endptr; - double num = 0.; - - num = strtod(p, &endptr); - if ((endptr && *endptr) || num < 0.) { - fprintf(stderr, "tst_fx2loop-E: \"%s\" not a valid positive float\n", p); - return -1.; - } - return num; -} - -/*--------------------------------------------------------------------------*/ - -int get_arg_pint(int min, int max, const char* text) -{ - int tmp = -1; - if (argi < argc) tmp = get_pint(argv[argi++]); - if (tmp < min || tmp > max) { - fprintf(stderr, "tst_fx2loop-F: %s\n", text); - exit(EXIT_FAILURE); - } - return tmp; -} - -/*--------------------------------------------------------------------------*/ - -void do_write(uint16_t* buf, int nw) -{ - int rc; - int i; - int ntrans; - int tout = 1000; - int ep = 4; - - usb_claim(); - rc = libusb_bulk_transfer(pUsbDevHdl, ep, - (unsigned char *)buf, nw*2, &ntrans, tout); - if (rc!=0 || ntrans != nw*2) { - fprintf(stderr, "tst_fx2loop-E: bulk write failed ntrans=%d rc=%d: %s \n", - ntrans, rc, usb_strerror(rc)); - } else { - prt_time(); - printf("write %4d word:", nw); - for (i = 0; i < nw; i++) printf(" %4.4x", buf[i]); - printf("\n"); - } - usb_release(); - - return; -} - -/*--------------------------------------------------------------------------*/ - -void do_read(int ep) -{ - int rc; - int i; - int ntrans; - uint16_t buf[4096]; - int tout = 1000; - int nloop; - - usb_claim(); - for (nloop=0;;nloop++) { - rc = libusb_bulk_transfer(pUsbDevHdl, ep|0x80, - (unsigned char *)buf, 2*4096, &ntrans, tout); - - if (ntrans==0 && rc) { - if (rc==LIBUSB_ERROR_TIMEOUT && ntrans==0 && nloop>0) break; - fprintf(stderr, "tst_fx2loop-E: bulk read failed ntrans=%d rc=%d: %s \n", - ntrans, rc, usb_strerror(rc)); - break; - } - prt_time(); - printf("read %4d word:", ntrans/2); - int nprt = ntrans/2; - if (nprt > 9) nprt = 9; - for (i = 0; i < nprt; i++) printf(" %4.4x", (uint16_t)buf[i]); - printf("\n"); - if (nsigint>0) break; - } - usb_release(); - return; -} - -/*----------------------------------------------------------*/ -void pollfd_add(int fd, short events, void *user_data) -{ - if (pollfd_nfds >= 16) { - fprintf(stderr, "tst_fx2loop-F: pollfd list overflow\n"); - exit(EXIT_FAILURE); - } - if (par_trace) { - prt_time(); - printf("pollfd_add: fd=%3d evt=%4.4x\n", fd, events); - } - pollfd_fds[pollfd_nfds].fd = fd; - pollfd_fds[pollfd_nfds].events = events; - pollfd_fds[pollfd_nfds].revents = 0; - pollfd_nfds += 1; - return; -} - -/*----------------------------------------------------------*/ -void pollfd_remove(int fd, void *user_data) -{ - int iw = 0; - int ir = 0; - if (par_trace) { - prt_time(); - printf("pollfd_remove: fd=%3d\n", fd); - } - for (ir = 0; ir < pollfd_nfds; ir++) { - if (pollfd_fds[ir].fd != fd) { - pollfd_fds[iw].fd = pollfd_fds[ir].fd; - pollfd_fds[iw].events = pollfd_fds[ir].events; - pollfd_fds[iw].revents = pollfd_fds[ir].revents; - iw += 1; - } - } - pollfd_nfds = iw; - return; -} - -/*----------------------------------------------------------*/ -void pollfd_init() -{ - const struct libusb_pollfd** plist = libusb_get_pollfds(pUsbContext); - const struct libusb_pollfd** p; - - for (p = plist; *p !=0; p++) { - pollfd_add((*p)->fd, (*p)->events, NULL); - } - - free(plist); - - libusb_set_pollfd_notifiers(pUsbContext, pollfd_add, pollfd_remove,NULL); - - return; -} - -/*----------------------------------------------------------*/ -int keep_running() -{ - if (nsigint > 0) return 0; - if (par_nsec > 0 && (get_time()-t_start) > par_nsec) return 0; - return 1; - -} - -/* forward declaration needed... */ -void cb_rxblast(struct libusb_transfer *t); - -/*----------------------------------------------------------*/ -void que_write() -{ - int rc; - int i; - int nw = 512*dsc_rx.par_nfrm/2; - int length = 2*nw; - uint16_t* pdat; - - struct libusb_transfer* t = libusb_alloc_transfer(0); - - t->dev_handle = pUsbDevHdl; - t->flags = LIBUSB_TRANSFER_FREE_TRANSFER | LIBUSB_TRANSFER_FREE_BUFFER; - t->endpoint = 4; - t->type = LIBUSB_TRANSFER_TYPE_BULK; - t->timeout = 1000; - t->status = 0; - t->buffer = malloc(length); - t->length = length; - t->actual_length = 0; - t->callback = cb_rxblast; - t->user_data = 0; - - pdat = (uint16_t*)(t->buffer); - for (i = 0; i < nw; i++) *pdat++ = dsc_rx.cval++; - - rc = libusb_submit_transfer(t); - if (rc) bad_usbcall_exit("libusb_submit_transfer()", rc); - - nreq += 1; - - if (par_trace) { - prt_time(); - printf("que_write: ep=%1d l=%5d\n", t->endpoint&(~0x80), t->length); - } - - return; -} - -/*----------------------------------------------------------*/ -void que_read(int ep, int nb, libusb_transfer_cb_fn cb) -{ - int rc; - int length = 512*nb; - - struct libusb_transfer* t = libusb_alloc_transfer(0); - - t->dev_handle = pUsbDevHdl; - t->flags = LIBUSB_TRANSFER_FREE_TRANSFER | LIBUSB_TRANSFER_FREE_BUFFER; - t->endpoint = (unsigned char) (ep|0x80); - t->type = LIBUSB_TRANSFER_TYPE_BULK; - t->timeout = 1000; - t->status = 0; - t->buffer = malloc(length); - t->length = length; - t->actual_length = 0; - t->callback = cb; - t->user_data = 0; - - rc = libusb_submit_transfer(t); - if (rc) bad_usbcall_exit("libusb_submit_transfer()", rc); - - nreq += 1; - - if (par_trace) { - prt_time(); - printf("que_read: ep=%1d l=%5d\n", t->endpoint&(~0x80), t->length); - } - - return; -} - -/*----------------------------------------------------------*/ -void send_msg() -{ - int rc; - int i; - int nw = par_nwmsg; - int length; - uint16_t* pdat; - - if (par_nwrndm) nw = 1 + (random() % par_nwmsg); - length = 2 * nw; - cur_nwmsg = nw; - - struct libusb_transfer* t = libusb_alloc_transfer(0); - - t->dev_handle = pUsbDevHdl; - t->flags = LIBUSB_TRANSFER_FREE_TRANSFER | LIBUSB_TRANSFER_FREE_BUFFER; - t->endpoint = 4; - t->type = LIBUSB_TRANSFER_TYPE_BULK; - t->timeout = 1000; - t->status = 0; - t->buffer = malloc(length); - t->length = length; - t->actual_length = 0; - t->callback = cb_rxblast; - t->user_data = 0; - - pdat = (uint16_t*)(t->buffer); - for (i = 0; i < nw-1; i++) *pdat++ = dsc_rx.cval++; - *pdat++ = 0xdead; - - rc = libusb_submit_transfer(t); - if (rc) bad_usbcall_exit("libusb_submit_transfer()", rc); - - nreq += 1; - - if (par_trace) { - prt_time(); - printf("send_msg: ep=%1d l=%5d", t->endpoint&(~0x80), t->length); - printf(" buf=%4.4x,..", ((uint16_t*)(t->buffer))[0]); - for (i = nw-2; i < nw; i++) { - printf(",%4.4x", ((uint16_t*)(t->buffer))[i]); - } - printf("\n"); - } - - return; -} - -/*----------------------------------------------------------*/ -void cb_rxblast(struct libusb_transfer *t) -{ - nreq -= 1; - - if (par_trace) { - prt_time(); - printf("cb_rx : ep=%d l=%5d al=%5d\n", - t->endpoint&(~0x80), t->length, t->actual_length); - } - - bad_transfer_exit(t, "cb_rxblast"); - dsc_rx.stat_nbuf += 1; - dsc_rx.stat_nbyt += t->actual_length; - - if (par_nwmsg==0 && keep_running()) que_write(); - - return; -} - -/*----------------------------------------------------------*/ -void cb_txblast(struct libusb_transfer *t, int ep, libusb_transfer_cb_fn cb, - struct dsc_queue* pdsc) -{ - nreq -= 1; - - if (par_trace) { - prt_time(); - printf("cb_txx: ep=%d l=%5d al=%5d\n", - t->endpoint&(~0x80), t->length, t->actual_length); - } - - bad_transfer_exit(t, "cb_txblast"); - if (t->actual_length > 0) { - uint16_t* pdat = (uint16_t*)(t->buffer); - int nw = t->actual_length/2; - int i; - if (pdsc->stat_nbuf == 0) pdsc->cval = pdat[0]; - for (i = 0; i < nw; i++) { - uint16_t dat = *pdat++; - if (pdsc->cval != dat) { - prt_time(); - printf("FAIL: on ep=%d seen %4.4x expect %4.4x after %10.0f char\n", - ep&(~0x80), dat, pdsc->cval, pdsc->stat_nbyt+2*i); - pdsc->cval = dat; - } - pdsc->cval += 1; - } - } - - pdsc->stat_nbuf += 1; - pdsc->stat_nbyt += t->actual_length; - if (t->actual_length < t->length) pdsc->stat_npt += 1; - - if (keep_running()) que_read(ep, pdsc->par_nfrm, cb); -} - -/*----------------------------------------------------------*/ -void cb_tx1blast(struct libusb_transfer *t) -{ - cb_txblast(t, 6, cb_tx1blast, &dsc_tx1); - return; -} - -/*----------------------------------------------------------*/ -void cb_tx2blast(struct libusb_transfer *t) -{ - cb_txblast(t, 8, cb_tx2blast, &dsc_tx2); - return; -} - -/*----------------------------------------------------------*/ -void cb_txloop(struct libusb_transfer *t) -{ - nreq -= 1; - - if (par_trace) { - prt_time(); - printf("cb_txl: ep=%d l=%5d al=%5d\n", - t->endpoint&(~0x80), t->length, t->actual_length); - } - - bad_transfer_exit(t, "cb_txloop"); - if (t->actual_length > 0) { - uint16_t* pdat = (uint16_t*)(t->buffer); - int nw = t->actual_length/2; - int i; - - for (i = 0; i < nw; i++) { - uint16_t dat = *pdat++; - - if (cur_nwmsg > 0) { - uint16_t dat_exp = (cur_nwmsg>1) ? dsc_tx1.cval++ : 0xdead; - if (dat_exp != dat) { - prt_time(); - printf("FAIL: on ep=6 seen %4.4x expect %4.4x after %10.0f char\n", - dat, dat_exp, dsc_tx1.stat_nbyt+2*i); - if (cur_nwmsg>1) dsc_tx1.cval = dat + 1; - } - cur_nwmsg -= 1; - if (cur_nwmsg==0 && dat==0xdead) stat_nmsg += 1; - } else { - prt_time(); - printf("FAIL: on ep=6 seen %4.4x unexpected after %10.0f char\n", - dat, dsc_tx1.stat_nbyt+2*i); - } - } - } - - dsc_tx1.stat_nbuf += 1; - dsc_tx1.stat_nbyt += t->actual_length; - if (t->actual_length < t->length) dsc_tx1.stat_npt += 1; - - if (cur_nwmsg==0) { /* end of message seen */ - if (keep_running()) { - send_msg(); - } else { - if (par_trace) { prt_time(); printf("set endpoll = 1\n"); } - endpoll = 1; - } - } - - que_read(6, dsc_tx1.par_nfrm, cb_txloop); - - return; -} - -/*----------------------------------------------------------*/ -void tx_pipe_drain(int ep) -{ - unsigned char buf[16384]; - int ntrans; - int rc = libusb_bulk_transfer(pUsbDevHdl, ep|0x80, - buf, sizeof(buf), &ntrans, 10); - if (rc == LIBUSB_ERROR_TIMEOUT) return; - if (rc) bad_usbcall_exit("pipe drain: libusb_bulk_transfer()", rc); - - fprintf(stderr, "tst_fx2loop-I: pipe drain for ep=%d: ntrans=%d\n", - ep&(~0x80), ntrans); - - return; -} - -/*--------------------------------------------------------------------------*/ -void do_run() -{ - int rc; - int fd_timer = -1; - int i; - - struct itimerspec tspec; - struct dsc_queue dsc_rx_last = dsc_rx; - struct dsc_queue dsc_tx1_last = dsc_tx1; - struct dsc_queue dsc_tx2_last = dsc_tx2; - - if (par_trace) { - prt_time(); - printf("rx:nf=%d,nq=%d; tx1:nf=%d,nq=%d; tx2:nf=%d,nq=%d\n", - dsc_rx.par_nfrm, dsc_rx.par_nque, - dsc_tx1.par_nfrm, dsc_tx2.par_nque, - dsc_tx2.par_nfrm, dsc_tx2.par_nque); - } - - /* setup pollfd list */ - fd_timer = timerfd_create(CLOCK_MONOTONIC, TFD_NONBLOCK); - if (fd_timer < 0) bad_syscall_exit("timerfd_create() failed", fd_timer); - tspec.it_interval.tv_sec = 1; - tspec.it_interval.tv_nsec = 0; - tspec.it_value.tv_sec = 1; - tspec.it_value.tv_nsec = 0; - rc = timerfd_settime(fd_timer, 0, &tspec, NULL); - if (rc<0) bad_syscall_exit("timerfd_settime() failed", rc); - pollfd_fds[0].fd = fd_timer; - pollfd_fds[0].events = POLLIN; - pollfd_fds[0].revents = 0; - pollfd_nfds = 1; - - pollfd_init(); - - /* setup loop */ - if (par_nwmsg > 0) { - dsc_rx.par_nfrm = 0; - dsc_rx.par_nque = 0; - if (dsc_tx1.par_nfrm == 0) dsc_tx1.par_nfrm = 1; - if (dsc_tx1.par_nque == 0) dsc_tx1.par_nque = 1; - - tx_pipe_drain(6); /* drain tx1 */ - for (i = 0; i < dsc_tx1.par_nque; i++) /* prime tx1 */ - que_read(6, dsc_tx1.par_nfrm, cb_txloop); - send_msg(); - } - - /* setup rxblast */ - if (dsc_rx.par_nfrm > 0) { - int i; - if (dsc_rx.par_nque == 0) dsc_rx.par_nque = 1; - for (i = 0; i < dsc_rx.par_nque; i++) que_write(); - } - - /* setup txblast */ - if (par_nwmsg==0 && dsc_tx1.par_nfrm>0) { - int i; - if (dsc_tx1.par_nque == 0) dsc_tx1.par_nque = 1; - for (i = 0; i < dsc_tx1.par_nque; i++) - que_read(6, dsc_tx1.par_nfrm, cb_tx1blast); - } - - /* setup tx2blast */ - if (dsc_tx2.par_nfrm > 0) { - int i; - if (dsc_tx2.par_nque == 0) dsc_tx2.par_nque = 1; - for (i = 0; i < dsc_tx2.par_nque; i++) - que_read(8, dsc_tx2.par_nfrm, cb_tx2blast); - } - - t_start = get_time(); - - while(nreq>0 && endpoll==0) { - uint64_t tbuf; - rc = poll(pollfd_fds, pollfd_nfds, 2000); - if (rc==-1 && errno==EINTR) continue; - if (rc < 0) bad_syscall_exit("poll() failed", rc); - if (rc == 0) fprintf(stderr, "tst_fx2loop-I: poll() timeout\n"); - - if (par_trace) { - int i; - prt_time(); - printf("poll: rc=%d:", rc); - for (i = 0; i < pollfd_nfds; i++) { - printf(" %d,%2.2x", pollfd_fds[i].fd, pollfd_fds[i].revents); - } - printf("\n"); - } - - if (pollfd_fds[0].revents == POLLIN) { - errno = EBADMSG; /* to be reported on short read */ - rc = read(fd_timer, &tbuf, sizeof(tbuf)); - if (rc != sizeof(tbuf)) bad_syscall_exit("read(fd_timer,...) failed", rc); - if (par_stat) { - prt_time(); - if (par_nwmsg>0 || dsc_rx.par_nque>0) { - double nbuf = dsc_rx.stat_nbuf - dsc_rx_last.stat_nbuf; - double nbyt = dsc_rx.stat_nbyt - dsc_rx_last.stat_nbyt; - printf("rx: %5.0f,%7.1f ", nbuf, nbyt/1000.); - } - if (dsc_tx1.par_nque > 0 ) { - double nbuf = dsc_tx1.stat_nbuf - dsc_tx1_last.stat_nbuf; - double nbyt = dsc_tx1.stat_nbyt - dsc_tx1_last.stat_nbyt; - printf("tx1: %5.0f,%7.1f ", nbuf, nbyt/1000.); - } - if (dsc_tx2.par_nque > 0 ) { - double nbuf = dsc_tx2.stat_nbuf - dsc_tx2_last.stat_nbuf; - double nbyt = dsc_tx2.stat_nbyt - dsc_tx2_last.stat_nbyt; - printf("tx2: %5.0f,%7.1f ", nbuf, nbyt/1000.); - } - printf("\n"); - dsc_rx_last = dsc_rx; - dsc_tx1_last = dsc_tx1; - dsc_tx2_last = dsc_tx2; - } - } else { - struct timeval tv; - tv.tv_sec = 0; - tv.tv_usec = 0; - rc = libusb_handle_events_timeout(pUsbContext, &tv); - //setting the timeval pointer to NULL should work, but doesn't (in 1.0.6) - //rc = libusb_handle_events_timeout(pUsbContext, 0); - if (rc) bad_usbcall_exit("libusb_handle_events_timeout()", rc); - } - } - - return; -} - -/*--------------------------------------------------------------------------*/ - -void do_stat() -{ - printf("run statistics:\n"); - printf("runtime : %13.3f\n", get_time()-t_start); - printf("nbuf_rx : %13.0f\n", dsc_rx.stat_nbuf); - printf("nbyt_rx : %13.0f\n", dsc_rx.stat_nbyt); - printf("nbuf_tx1 : %13.0f\n", dsc_tx1.stat_nbuf); - printf("nbyt_tx1 : %13.0f\n", dsc_tx1.stat_nbyt); - printf("npt_tx1 : %13.0f\n", dsc_tx1.stat_npt); - printf("nbuf_tx2 : %13.0f\n", dsc_tx2.stat_nbuf); - printf("nbyt_tx2 : %13.0f\n", dsc_tx2.stat_nbyt); - printf("npt_tx2 : %13.0f\n", dsc_tx2.stat_npt); - printf("nmsg : %13.0f\n", stat_nmsg); - return; -} - -/*--------------------------------------------------------------------------*/ - -void usb_claim() -{ - int rc = libusb_claim_interface(pUsbDevHdl, 0); - if (rc) bad_usbcall_exit("libusb_claim_interface()", rc); - return; -} - -/*--------------------------------------------------------------------------*/ - -void usb_release() -{ - int rc = libusb_release_interface(pUsbDevHdl, 0); - if (rc) bad_usbcall_exit("libusb_release_interface()", rc); - return; -} - -/*--------------------------------------------------------------------------*/ - -char* usb_strerror(int rc) -{ - switch(rc) { - case LIBUSB_SUCCESS: - return ""; - case LIBUSB_ERROR_IO: - return "Input/output error"; - case LIBUSB_ERROR_INVALID_PARAM: - return "Invalid parameter"; - case LIBUSB_ERROR_ACCESS: - return "Access denied"; - case LIBUSB_ERROR_NO_DEVICE: - return "No such device"; - case LIBUSB_ERROR_NOT_FOUND: - return "Entity not found"; - case LIBUSB_ERROR_BUSY: - return "Resource busy"; - case LIBUSB_ERROR_TIMEOUT: - return "Operation timed out"; - case LIBUSB_ERROR_OVERFLOW: - return "Overflow"; - case LIBUSB_ERROR_PIPE: - return "Pipe error"; - case LIBUSB_ERROR_INTERRUPTED: - return "System call interrupted"; - case LIBUSB_ERROR_NO_MEM: - return "Insufficient memory"; - case LIBUSB_ERROR_NOT_SUPPORTED: - return "Operation not supported"; - case LIBUSB_ERROR_OTHER: - return "Other error"; - default: - return "Unknown libusb error code"; - } -} - -/*--------------------------------------------------------------------------*/ - -void prt_time(void) -{ - struct timeval tv; - struct timezone tz; - struct tm tmval; - - gettimeofday(&tv, &tz); - localtime_r(&tv.tv_sec, &tmval); - printf("%02d:%02d:%02d.%06d: ", tmval.tm_hour, tmval.tm_min, tmval.tm_sec, - (int) tv.tv_usec); -} - -/*--------------------------------------------------------------------------*/ - -double get_time(void) -{ - struct timeval tv; - struct timezone tz; - gettimeofday(&tv, &tz); - return (double)tv.tv_sec + 1.e-6 * (double)tv.tv_usec; -} - -/*--------------------------------------------------------------------------*/ - -void bad_syscall_exit(const char* text, int rc) -{ - fprintf(stderr, "tst_fx2loop-F: %s failed with rc=%d errno=%d : %s\n", - text, rc, errno, strerror(errno)); - exit(EXIT_FAILURE); -} - -/*--------------------------------------------------------------------------*/ - -void bad_usbcall_exit(const char* text, int rc) -{ - fprintf(stderr, "tst_fx2loop-F: %s failed with rc=%d: %s\n", - text, rc, usb_strerror(rc)); - exit(EXIT_FAILURE); -} - -/*--------------------------------------------------------------------------*/ - -void bad_transfer_exit(struct libusb_transfer *t, const char* text) -{ - const char* etext = 0; - - if (t->status == LIBUSB_TRANSFER_ERROR) etext = "ERROR"; - if (t->status == LIBUSB_TRANSFER_STALL) etext = "STALL"; - if (t->status == LIBUSB_TRANSFER_NO_DEVICE) etext = "NO_DEVICE"; - if (t->status == LIBUSB_TRANSFER_OVERFLOW) etext = "OVERFLOW"; - - if (etext == 0) return; - - fprintf(stderr, "tst_fx2loop-F: transfer failure in %s on ep=%d: %s\n", - text, (int)(t->endpoint&(~0x80)), etext); - exit(EXIT_FAILURE); -} - diff --git a/rtl/sys_gen/tst_fx2loop/tst_fx2loop.vbom b/rtl/sys_gen/tst_fx2loop/tst_fx2loop.vbom deleted file mode 100644 index c1d7afa4..00000000 --- a/rtl/sys_gen/tst_fx2loop/tst_fx2loop.vbom +++ /dev/null @@ -1,10 +0,0 @@ -# libs -../../vlib/slvtypes.vhd -../../vlib/comlib/comlib.vhd -../../bplib/fx2lib/fx2lib.vhd -tst_fx2looplib.vhd -# components -../../vlib/comlib/byte2word.vbom -../../vlib/comlib/word2byte.vbom -# design -tst_fx2loop.vhd diff --git a/rtl/sys_gen/tst_fx2loop/tst_fx2loop.vhd b/rtl/sys_gen/tst_fx2loop/tst_fx2loop.vhd deleted file mode 100644 index e6aaaba6..00000000 --- a/rtl/sys_gen/tst_fx2loop/tst_fx2loop.vhd +++ /dev/null @@ -1,267 +0,0 @@ --- $Id: tst_fx2loop.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2011-2013 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: tst_fx2loop - syn --- Description: simple stand-alone tester for fx2lib components --- --- Dependencies: comlib/byte2word --- comlib/word2byte --- Test bench: - --- --- Target Devices: generic --- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 --- --- Revision History: --- Date Rev Version Comment --- 2013-04-24 510 1.0.1 fix sensitivity list of proc_next --- 2012-01-15 453 1.0 Initial version --- 2011-12-26 445 0.5 First draft ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; -use work.comlib.all; -use work.fx2lib.all; -use work.tst_fx2looplib.all; - --- ---------------------------------------------------------------------------- - -entity tst_fx2loop is -- tester for fx2lib components - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - CE_MSEC : in slbit; -- msec pulse - HIO_CNTL : in hio_cntl_type; -- humanio controls - HIO_STAT : out hio_stat_type; -- humanio status - FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor - RXDATA : in slv8; -- receiver data out - RXVAL : in slbit; -- receiver data valid - RXHOLD : out slbit; -- receiver data hold - TXDATA : out slv8; -- transmit data in - TXENA : out slbit; -- transmit data enable - TXBUSY : in slbit; -- transmit busy - TX2DATA : out slv8; -- transmit 2 data in - TX2ENA : out slbit; -- transmit 2 data enable - TX2BUSY : in slbit -- transmit 2 busy - ); -end tst_fx2loop; - -architecture syn of tst_fx2loop is - - type regs_type is record - rxdata : slv16; -- next rx word - txdata : slv16; -- next tx word - tx2data : slv16; -- next tx2 word - rxsecnt : slv16; -- rx sequence error counter - rxcnt : slv32; -- rx word counter - txcnt : slv32; -- tx word counter - tx2cnt : slv32; -- tx2 word counter - rxthrottle : slbit; -- rx throttle flag - end record regs_type; - - constant regs_init : regs_type := ( - (others=>'0'), -- rxdata - (others=>'0'), -- txdata - (others=>'0'), -- tx2data - (others=>'0'), -- rxsecnt - (others=>'0'), -- rxcnt - (others=>'0'), -- txcnt - (others=>'0'), -- tx2cnt - '0' -- rxthrottle - ); - - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs - - signal RXWDATA : slv16 := (others=>'0'); - signal RXWVAL : slbit := '0'; - signal RXWHOLD : slbit := '0'; - signal RXODD : slbit := '0'; - - signal TXWDATA : slv16 := (others=>'0'); - signal TXWENA : slbit := '0'; - signal TXWBUSY : slbit := '0'; - signal TXODD : slbit := '0'; - signal TX2WDATA : slv16 := (others=>'0'); - signal TX2WENA : slbit := '0'; - signal TX2WBUSY : slbit := '0'; - signal TX2ODD : slbit := '0'; - - signal RXHOLD_L : slbit := '0'; -- local copy of out port signal - signal TXENA_L : slbit := '0'; -- local copy of out port signal - signal TX2ENA_L : slbit := '0'; -- local copy of out port signal - signal CNTL_RESET_L : slbit := '0'; -- local copy of out port signal - -begin - - CNTL_RESET_L <= '0'; -- so far unused - - RXB2W : byte2word - port map ( - CLK => CLK, - RESET => CNTL_RESET_L, - DI => RXDATA, - ENA => RXVAL, - BUSY => RXHOLD_L, - DO => RXWDATA, - VAL => RXWVAL, - HOLD => RXWHOLD, - ODD => RXODD - ); - - TX1W2B : word2byte - port map ( - CLK => CLK, - RESET => CNTL_RESET_L, - DI => TXWDATA, - ENA => TXWENA, - BUSY => TXWBUSY, - DO => TXDATA, - VAL => TXENA_L, - HOLD => TXBUSY, - ODD => TXODD - ); - - TX2W2B : word2byte - port map ( - CLK => CLK, - RESET => CNTL_RESET_L, - DI => TX2WDATA, - ENA => TX2WENA, - BUSY => TX2WBUSY, - DO => TX2DATA, - VAL => TX2ENA_L, - HOLD => TX2BUSY, - ODD => TX2ODD - ); - - proc_regs: process (CLK) - begin - - if rising_edge(CLK) then - if RESET = '1' then - R_REGS <= regs_init; - else - R_REGS <= N_REGS; - end if; - end if; - - end process proc_regs; - - proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, FX2_MONI, - RXWDATA, RXWVAL, TXWBUSY, TX2WBUSY, - RXHOLD_L, TXBUSY, TX2BUSY) - - variable r : regs_type := regs_init; - variable n : regs_type := regs_init; - - variable irxwhold : slbit := '1'; - variable itxwena : slbit := '0'; - variable itxwdata : slv16 := (others=>'0'); - variable itx2wena : slbit := '0'; - - begin - r := R_REGS; - n := R_REGS; - - irxwhold := '1'; - itxwena := '0'; - itxwdata := RXWDATA; - itx2wena := '0'; - - if HIO_CNTL.throttle = '1' then - if CE_MSEC = '1' then - n.rxthrottle := not r.rxthrottle; - end if; - else - n.rxthrottle := '0'; - end if; - - - case HIO_CNTL.mode is - when c_mode_idle => - null; - - when c_mode_rxblast => - if RXWVAL='1' and r.rxthrottle='0' then - irxwhold := '0'; - if RXWDATA /= r.rxdata then - n.rxsecnt := slv(unsigned(r.rxsecnt) + 1); - end if; - n.rxdata := slv(unsigned(RXWDATA) + 1); - end if; - - when c_mode_txblast => - itxwdata := r.txdata; - if TXWBUSY = '0' then - itxwena := '1'; - n.txdata := slv(unsigned(r.txdata) + 1); - end if; - irxwhold := '0'; - - when c_mode_loop => - itxwdata := RXWDATA; - if RXWVAL='1' and r.rxthrottle='0' and TXWBUSY = '0' then - irxwhold := '0'; - itxwena := '1'; - end if; - - when others => null; - end case; - - if HIO_CNTL.tx2blast = '1' then - if TX2WBUSY = '0' then - itx2wena := '1'; - n.tx2data := slv(unsigned(r.tx2data) + 1); - end if; - end if; - - if RXWVAL='1' and irxwhold='0' then - n.rxcnt := slv(unsigned(r.rxcnt) + 1); - end if; - - if itxwena = '1' then - n.txcnt := slv(unsigned(r.txcnt) + 1); - end if; - - if itx2wena = '1' then - n.tx2cnt := slv(unsigned(r.tx2cnt) + 1); - end if; - - N_REGS <= n; - - RXWHOLD <= irxwhold; - TXWENA <= itxwena; - TXWDATA <= itxwdata; - TX2WENA <= itx2wena; - TX2WDATA <= r.tx2data; - - HIO_STAT.rxhold <= RXHOLD_L; - HIO_STAT.txbusy <= TXBUSY; - HIO_STAT.tx2busy <= TX2BUSY; - HIO_STAT.rxsecnt <= r.rxsecnt; - HIO_STAT.rxcnt <= r.rxcnt; - HIO_STAT.txcnt <= r.txcnt; - HIO_STAT.tx2cnt <= r.tx2cnt; - - end process proc_next; - - RXHOLD <= RXHOLD_L; - TXENA <= TXENA_L; - TX2ENA <= TX2ENA_L; - -end syn; diff --git a/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vbom b/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vbom deleted file mode 100644 index 91378a2a..00000000 --- a/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vbom +++ /dev/null @@ -1,7 +0,0 @@ -# libs -../../vlib/slvtypes.vhd -../../bplib/fx2lib/fx2lib.vhd -tst_fx2looplib.vbom -# components -# design -tst_fx2loop_hiomap.vhd diff --git a/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vhd b/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vhd deleted file mode 100644 index a8f496db..00000000 --- a/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vhd +++ /dev/null @@ -1,194 +0,0 @@ --- $Id: tst_fx2loop_hiomap.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2011-2012 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: tst_fx2loop_hiomap - syn --- Description: default human I/O mapper --- --- Dependencies: - --- Test bench: - --- --- Target Devices: generic --- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 --- --- Revision History: --- Date Rev Version Comment --- 2012-01-15 453 1.0.2 re-arrange DP,DSP usage --- 2012-01-03 449 1.0.1 use new fx2ctl_moni layout --- 2011-12-26 445 1.0 Initial version ------------------------------------------------------------------------------- --- --- Usage of Switches, Buttons, LEDs: --- --- BTN(3) -- unused -- --- (2) -- unused -- --- (1) -- unused -- --- (0) reset state [!! decoded by top level design !!] --- --- SWI(7:5) select display --- (4) -- unused -- --- (3) throttle --- (2) tx2blast --- (1:0) mode 00 idle --- 01 rxblast --- 10 txblast --- 11 loop --- --- LED(7) MONI.fifo_ep4 --- (6) MONI.fifo_ep6 --- (5) MONI.fifo_ep8 --- (4) MONI.flag_ep4_empty --- (3) MONI.flag_ep4_almost --- (2) MONI.flag_ep6_full --- (1) MONI.flag_ep6_almost --- (0) rxsecnt > 0 (sequence error) --- --- DSP data as selected by SWI(7:5) --- 000 -> rxsecnt --- 001 -> -- unused -- (display ffff) --- 010 -> rxcnt.l --- 011 -> rxcnt.h --- 100 -> txcnt.l --- 101 -> txcnt.h --- 110 -> tx2cnt.l --- 111 -> tx2cnt.h --- --- DP(3) FX2_TXBUSY (shows tx back preasure) --- (2) FX2_MONI.slwr (shows tx activity) --- (1) FX2_RXHOLD (shows rx back preasure) --- (0) FX2_MONI.slrd (shows rx activity) --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; -use work.fx2lib.all; -use work.tst_fx2looplib.all; - --- ---------------------------------------------------------------------------- - -entity tst_fx2loop_hiomap is -- default human I/O mapper - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - HIO_CNTL : out hio_cntl_type; -- tester controls from hio - HIO_STAT : in hio_stat_type; -- tester status to diaplay by hio - FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor to display by hio - SWI : in slv8; -- switch settings - BTN : in slv4; -- button settings - LED : out slv8; -- led data - DSP_DAT : out slv16; -- display data - DSP_DP : out slv4 -- display decimal points - ); -end tst_fx2loop_hiomap; - -architecture syn of tst_fx2loop_hiomap is - - type regs_type is record - dspdat : slv16; -- display data - dummy : slbit; -- - end record regs_type; - - constant regs_init : regs_type := ( - (others=>'0'), -- dspdat - '0' - ); - - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs - -begin - - proc_regs: process (CLK) - begin - - if rising_edge(CLK) then - if RESET = '1' then - R_REGS <= regs_init; - else - R_REGS <= N_REGS; - end if; - end if; - - end process proc_regs; - - proc_next: process (R_REGS, HIO_STAT, FX2_MONI, SWI, BTN) - - variable r : regs_type := regs_init; - variable n : regs_type := regs_init; - - variable icntl : hio_cntl_type := hio_cntl_init; - variable iled : slv8 := (others=>'0'); - variable idat : slv16 := (others=>'0'); - variable idp : slv4 := (others=>'0'); - - begin - - r := R_REGS; - n := R_REGS; - - icntl := hio_cntl_init; - iled := (others=>'0'); - idat := (others=>'0'); - idp := (others=>'0'); - - -- setup tester controls - - icntl.mode := SWI(1 downto 0); - icntl.tx2blast := SWI(2); - icntl.throttle := SWI(3); - - -- setup leds - iled(7) := FX2_MONI.fifo_ep4; - iled(6) := FX2_MONI.fifo_ep6; - iled(5) := FX2_MONI.fifo_ep8; - iled(4) := FX2_MONI.flag_ep4_empty; - iled(3) := FX2_MONI.flag_ep4_almost; - iled(2) := FX2_MONI.flag_ep6_full; - iled(1) := FX2_MONI.flag_ep6_almost; - if unsigned(HIO_STAT.rxsecnt) > 0 then iled(0) := '1'; end if; - - -- setup display data - - case SWI(7 downto 5) is - when "000" => idat := HIO_STAT.rxsecnt; - when "001" => idat := (others=>'1'); - when "010" => idat := HIO_STAT.rxcnt(15 downto 0); - when "011" => idat := HIO_STAT.rxcnt(31 downto 16); - when "100" => idat := HIO_STAT.txcnt(15 downto 0); - when "101" => idat := HIO_STAT.txcnt(31 downto 16); - when "110" => idat := HIO_STAT.tx2cnt(15 downto 0); - when "111" => idat := HIO_STAT.tx2cnt(31 downto 16); - when others => null; - end case; - n.dspdat := idat; - - -- setup display decimal points - - idp(3) := HIO_STAT.txbusy; -- tx back preasure - idp(2) := FX2_MONI.slwr; -- tx activity - idp(1) := HIO_STAT.rxhold; -- rx back preasure - idp(0) := FX2_MONI.slrd; -- rx activity - - N_REGS <= n; - - HIO_CNTL <= icntl; - LED <= iled; - DSP_DAT <= r.dspdat; - DSP_DP <= idp; - - end process proc_next; - -end syn; diff --git a/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vbom b/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vbom deleted file mode 100644 index 98f758ce..00000000 --- a/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vbom +++ /dev/null @@ -1,4 +0,0 @@ -# libs -../../vlib/slvtypes.vhd -../../bplib/fx2lib/fx2lib.vhd -tst_fx2looplib.vhd diff --git a/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd b/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd deleted file mode 100644 index 5dd81142..00000000 --- a/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd +++ /dev/null @@ -1,109 +0,0 @@ --- $Id: tst_fx2looplib.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2011-2012 by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Package Name: tst_fx2looplib --- Description: Definitions for tst_fx2loop records and helpers --- --- Dependencies: - --- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 --- Revision History: --- Date Rev Version Comment --- 2012-01-15 453 1.1 drop pecnt, add rxhold,(tx|tx2)busy in hio_stat --- 2011-12-26 445 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.slvtypes.all; -use work.fx2lib.all; - -package tst_fx2looplib is - - constant c_ctltyp_2fifo_as : integer := 0; -- fx2ctl type: 2fifo_as - constant c_ctltyp_2fifo_ic : integer := 1; -- fx2ctl type: 2fifo_ic - constant c_ctltyp_3fifo_ic : integer := 2; -- fx2ctl type: 3fifo_ic - - constant c_mode_idle : slv2 := "00"; -- mode: idle (no tx activity) - constant c_mode_rxblast : slv2 := "01"; -- mode: rxblast (check rx activity) - constant c_mode_txblast : slv2 := "10"; -- mode: txblast (saturate tx) - constant c_mode_loop : slv2 := "11"; -- mode: loop (rx->tx loop-back) - - type hio_cntl_type is record -- humanio controls - mode : slv2; -- mode (idle,(tx|tx)blast,loop) - tx2blast : slbit; -- enable tx2 blast - throttle : slbit; -- enable 1 msec tx throttling - end record hio_cntl_type; - - constant hio_cntl_init : hio_cntl_type := ( - c_mode_idle, -- mode - '0','0' -- tx2blast,throttle - ); - - type hio_stat_type is record -- humanio status - rxhold : slbit; -- rx hold - txbusy : slbit; -- tx busy - tx2busy : slbit; -- tx2 busy - rxsecnt : slv16; -- rx sequence error counter - rxcnt : slv32; -- rx word counter - txcnt : slv32; -- tx word counter - tx2cnt : slv32; -- tx2 word counter - end record hio_stat_type; - - constant hio_stat_init : hio_stat_type := ( - '0','0','0', -- rxhold,txbusy,tx2busy - (others=>'0'), -- rxsecnt - (others=>'0'), -- rxcnt - (others=>'0'), -- txcnt - (others=>'0') -- tx2cnt - ); - --- ------------------------------------- - -component tst_fx2loop is -- tester for serport components - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - CE_MSEC : in slbit; -- msec pulse - HIO_CNTL : in hio_cntl_type; -- humanio controls - HIO_STAT : out hio_stat_type; -- humanio status - FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor - RXDATA : in slv8; -- receiver data out - RXVAL : in slbit; -- receiver data valid - RXHOLD : out slbit; -- receiver data hold - TXDATA : out slv8; -- transmit data in - TXENA : out slbit; -- transmit data enable - TXBUSY : in slbit; -- transmit busy - TX2DATA : out slv8; -- transmit 2 data in - TX2ENA : out slbit; -- transmit 2 data enable - TX2BUSY : in slbit -- transmit 2 busy - ); -end component; - -component tst_fx2loop_hiomap is -- default human I/O mapper - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - HIO_CNTL : out hio_cntl_type; -- tester controls from hio - HIO_STAT : in hio_stat_type; -- tester status to display by hio - FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor to display by hio - SWI : in slv8; -- switch settings - BTN : in slv4; -- button settings - LED : out slv8; -- led data - DSP_DAT : out slv16; -- display data - DSP_DP : out slv4 -- display decimal points - ); -end component; - -end package tst_fx2looplib; diff --git a/rtl/sys_gen/tst_rlink/Makefile b/rtl/sys_gen/tst_rlink/Makefile.ise similarity index 83% rename from rtl/sys_gen/tst_rlink/Makefile rename to rtl/sys_gen/tst_rlink/Makefile.ise index 99bcff32..a7a6609f 100644 --- a/rtl/sys_gen/tst_rlink/Makefile +++ b/rtl/sys_gen/tst_rlink/Makefile.ise @@ -1,4 +1,5 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ # # Revision History: # Date Rev Version Comment diff --git a/rtl/sys_gen/tst_rlink/arty/sys_conf.vhd b/rtl/sys_gen/tst_rlink/arty/sys_conf.vhd index 6c1b2a08..d74cd2f0 100644 --- a/rtl/sys_gen/tst_rlink/arty/sys_conf.vhd +++ b/rtl/sys_gen/tst_rlink/arty/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 743 2016-03-13 16:42:31Z mueller $ +-- $Id: sys_conf.vhd 754 2016-03-28 12:26:13Z mueller $ -- -- Copyright 2016- by Walter F.J. Mueller -- @@ -19,6 +19,7 @@ -- Tool versions: viv 2015.4; ghdl 0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-03-28 754 1.2 run at 120 MHz -- 2016-03-12 741 1.1 add sysmon_rbus -- 2016-02-16 731 1.0 Initial version ------------------------------------------------------------------------------ @@ -32,8 +33,8 @@ package sys_conf is -- configure clocks -------------------------------------------------------- constant sys_conf_clksys_vcodivide : positive := 1; - constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz - constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz constant sys_conf_clksys_gentype : string := "MMCM"; -- configure rlink and hio interfaces -------------------------------------- diff --git a/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vbom b/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vbom index 61f1f118..5e2e204e 100644 --- a/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vbom +++ b/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vbom @@ -4,6 +4,7 @@ ../../../vlib/genlib/genlib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd +../../../vlib/rbus/rbdlib.vhd ../../../vlib/rlink/rlinklib.vbom ../../../bplib/bpgen/bpgenlib.vbom ../../../bplib/bpgen/bpgenrbuslib.vbom @@ -20,8 +21,8 @@ ${sys_conf := sys_conf.vhd} ../../../bplib/bpgen/rgbdrv_master.vbom ../../../bplib/bpgen/rgbdrv_analog_rbus.vbom ../../../bplib/sysmon/sysmonx_rbus_arty.vbom +../../../vlib/rbus/rbd_usracc.vbom ../../../vlib/rbus/rb_sres_or_4.vbom -../../../vlib/rbus/rb_sres_or_3.vbom # design sys_tst_rlink_arty.vhd @xdc:../../../bplib/arty/arty_pclk.xdc diff --git a/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vhd b/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vhd index b4df25bd..c070e44b 100644 --- a/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vhd +++ b/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_rlink_arty.vhd 743 2016-03-13 16:42:31Z mueller $ +-- $Id: sys_tst_rlink_arty.vhd 758 2016-04-02 18:01:39Z mueller $ -- -- Copyright 2016- by Walter F.J. Mueller -- @@ -24,8 +24,8 @@ -- bplib/bpgen/rgbdrv_master -- bplib/bpgen/rgbdrv_analog_rbus -- bplib/sysmon/sysmonx_rbus_arty +-- vlib/rbus/rbd_usracc -- vlib/rbus/rb_sres_or_4 --- vlib/rbus/rb_sres_or_3 -- -- Test bench: tb/tb_tst_rlink_arty -- @@ -34,12 +34,15 @@ -- -- Synthesized (xst): -- Date Rev viv Target flop lutl lutm bram slic +-- 2016-03-27 753 2015.4 xc7a35t-1L 980 1396 36 3.0 494 meminf -- 2016-03-13 743 2015.4 xc7a35t-1L 980 1390 64 4.5 514 +XADC -- 2016-02-20 734 2015.4 xc7a35t-1L 941 1352 64 4.5 478 -- 2016-02-14 731 2015.4 xc7a35t-1L 777 1313 64 4.5 399 -- -- Revision History: -- Date Rev Version Comment +-- 2016-04-02 758 1.1.5 add rbd_usracc (bitfile+jtag timestamp access) +-- 2016-03-19 748 1.1.4 define rlink SYSID -- 2016-03-13 743 1.1.3 hardwire XON=1, all SWI now unused -- 2016-03-12 741 1.1.2 use sysmonx_rbus_arty now -- 2016-03-06 740 1.1.1 add A_VPWRN/P to baseline config @@ -67,6 +70,7 @@ use work.xlib.all; use work.genlib.all; use work.serportlib.all; use work.rblib.all; +use work.rbdlib.all; use work.rlinklib.all; use work.bpgenlib.all; use work.bpgenrbuslib.all; @@ -117,6 +121,7 @@ architecture syn of sys_tst_rlink_arty is signal RB_SRES_RGB2 : rb_sres_type := rb_sres_init; signal RB_SRES_RGB3 : rb_sres_type := rb_sres_init; signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; + signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); @@ -133,6 +138,10 @@ architecture syn of sys_tst_rlink_arty is constant rbaddr_rgb3 : slv16 := x"fc0c"; -- fe0c/0004: 1111 1100 0000 11xx constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx + constant sysid_proj : slv16 := x"0101"; -- tst_rlink + constant sysid_board : slv8 := x"07"; -- arty + constant sysid_vers : slv8 := x"00"; + begin assert (sys_conf_clksys mod 1000000) = 0 @@ -198,12 +207,12 @@ begin generic map ( BTOWIDTH => 6, RTAWIDTH => 12, - SYSID => (others=>'0'), + SYSID => sysid_proj & sysid_board & sysid_vers, IFAWIDTH => 5, OFAWIDTH => 5, ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, - CDWIDTH => 15, + CDWIDTH => 12, CDINIT => sys_conf_ser2rri_cdinit, RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink RBMON_RBADDR => (others=>'0')) @@ -336,11 +345,19 @@ begin RB_SRES_OR => RB_SRES_RGB ); - RB_SRES_OR1 : rb_sres_or_3 + UARB : rbd_usracc + port map ( + CLK => CLK, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_USRACC + ); + + RB_SRES_OR1 : rb_sres_or_4 port map ( RB_SRES_1 => RB_SRES_TST, RB_SRES_2 => RB_SRES_RGB, RB_SRES_3 => RB_SRES_SYSMON, + RB_SRES_4 => RB_SRES_USRACC, RB_SRES_OR => RB_SRES ); diff --git a/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vmfset b/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vmfset new file mode 100644 index 00000000..1a1b0574 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vmfset @@ -0,0 +1,27 @@ +# $Id: sys_tst_rlink_arty.vmfset 773 2016-06-05 20:03:15Z mueller $ +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# unconnected ports -------------------------------------------- +I [Synth 8-3331] RB_MREQ # generic +# --> rlink_sp1c doesn't use CE_USEC # OK 2016-06-05 +i [Synth 8-3331] rlink_sp1c.*CE_USEC + +# unused sequential element ------------------------------------ +# --> many HIO pins not used # OK 2016-06-05 +i [Synth 8-3332] IOB_(SWI|BTN)/R_DI_reg[\d*] +i [Synth 8-3332] DEB.DEB_(SWI|BTN)/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*] + +# --> monitor outputs moneop,monattn currently not used # OK 2016-06-05 +i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop] +i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn] +# ENAESC=0, therefore esc logic inactive # OK 2016-06-05 +i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[escseen] +i [Synth 8-3332] SERPORT/XONTX/R_REGS_reg[escpend] +# --> SER_MONI.rxovr indeed unused # OK 2016-06-05 +i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[rxovr] + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization diff --git a/rtl/sys_gen/tst_rlink/arty/tb/Makefile b/rtl/sys_gen/tst_rlink/arty/tb/Makefile index 7684277a..b523e95a 100644 --- a/rtl/sys_gen/tst_rlink/arty/tb/Makefile +++ b/rtl/sys_gen/tst_rlink/arty/tb/Makefile @@ -1,30 +1,41 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $ # # Revision History: # Date Rev Version Comment +# 2016-06-18 776 1.1.1 add xsim_clean +# 2016-04-22 763 1.1 add include dep_vsim # 2016-02-14 731 1.0 Initial version # EXE_all = tb_tst_rlink_arty # include ${RETROBASE}/rtl/make_viv/viv_default_arty.mk # -.PHONY : all all_ssim clean +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim # all : $(EXE_all) all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) # -clean : viv_clean ghdl_clean +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean # #----- # -include ${RETROBASE}/rtl/make_viv/generic_vivado.mk include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # VBOM_all = $(wildcard *.vbom) # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_vsyn) include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) include $(wildcard *.o.dep_ghdl) endif # diff --git a/rtl/sys_gen/tst_rlink/arty/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_rlink/arty/tb/sys_conf_sim.vhd index 7ed15fda..767ae27f 100644 --- a/rtl/sys_gen/tst_rlink/arty/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/tst_rlink/arty/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 743 2016-03-13 16:42:31Z mueller $ +-- $Id: sys_conf_sim.vhd 775 2016-06-18 13:42:00Z mueller $ -- -- Copyright 2016- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_arty (for simulation) -- -- Dependencies: - --- Tool versions: viv 2015.4; ghdl 0.33 +-- Tool versions: viv 2015.4-2016.2; ghdl 0.33 -- Revision History: -- Date Rev Version Comment -- 2016-03-12 741 1.1 add sysmon_rbus diff --git a/rtl/sys_gen/tst_rlink/basys3/sys_conf.vhd b/rtl/sys_gen/tst_rlink/basys3/sys_conf.vhd index 0321ae47..d9aff63c 100644 --- a/rtl/sys_gen/tst_rlink/basys3/sys_conf.vhd +++ b/rtl/sys_gen/tst_rlink/basys3/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 743 2016-03-13 16:42:31Z mueller $ +-- $Id: sys_conf.vhd 754 2016-03-28 12:26:13Z mueller $ -- -- Copyright 2015-2016 by Walter F.J. Mueller -- @@ -19,6 +19,7 @@ -- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-03-28 754 1.2 run at 120 MHz -- 2016-03-12 741 1.1 add sysmon_rbus -- 2016-02-26 735 1.0.2 use s7_cmt_sfs -- 2015-01-16 636 1.0 Initial version @@ -33,8 +34,8 @@ package sys_conf is -- configure clocks -------------------------------------------------------- constant sys_conf_clksys_vcodivide : positive := 1; - constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz - constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz constant sys_conf_clksys_gentype : string := "MMCM"; -- configure rlink and hio interfaces -------------------------------------- diff --git a/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vbom b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vbom index 4d3054f6..49da8c3a 100644 --- a/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vbom +++ b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vbom @@ -4,6 +4,7 @@ ../../../vlib/genlib/genlib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd +../../../vlib/rbus/rbdlib.vhd ../../../vlib/rlink/rlinklib.vbom ../../../bplib/bpgen/bpgenlib.vbom ../../../bplib/bpgen/bpgenrbuslib.vbom @@ -18,7 +19,8 @@ ${sys_conf := sys_conf.vhd} ../../../vlib/rlink/rlink_sp1c.vbom ../rbd_tst_rlink.vbom ../../../bplib/sysmon/sysmonx_rbus_base.vbom -../../../vlib/rbus/rb_sres_or_3.vbom +../../../vlib/rbus/rbd_usracc.vbom +../../../vlib/rbus/rb_sres_or_4.vbom # design sys_tst_rlink_b3.vhd @xdc:../../../bplib/basys3/basys3_pclk.xdc diff --git a/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd index 2fad1792..0c4a36cc 100644 --- a/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd +++ b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_rlink_b3.vhd 745 2016-03-18 22:10:34Z mueller $ +-- $Id: sys_tst_rlink_b3.vhd 758 2016-04-02 18:01:39Z mueller $ -- -- Copyright 2015-2016 by Walter F.J. Mueller -- @@ -22,7 +22,8 @@ -- vlib/rlink/rlink_sp1c -- rbd_tst_rlink -- bplib/sysmon/sysmonx_rbus_base --- vlib/rbus/rb_sres_or_3 +-- vlib/rbus/rbd_usracc +-- vlib/rbus/rb_sres_or_4 -- -- Test bench: tb/tb_tst_rlink_b3 -- @@ -31,11 +32,14 @@ -- -- Synthesized (xst): -- Date Rev viv Target flop lutl lutm bram slic +-- 2016-03-27 753 2015.4 xc7a35t-1 986 1352 36 3.0 473 meminf -- 2016-03-13 743 2015.4 xc7a35t-1 988 1372 64 4.5 503 +XADC -- 2015-01-30 636 2014.4 xc7a35t-1 946 1319 64 4.5 476 -- -- Revision History: -- Date Rev Version Comment +-- 2016-04-02 758 1.1.3 add rbd_usracc (bitfile+jtag timestamp access) +-- 2016-03-19 748 1.1.2 define rlink SYSID -- 2016-03-18 745 1.1.1 hardwire XON=1 -- 2016-03-12 741 1.1 add sysmon_rbus -- 2016-02-26 735 1.0.2 use s7_cmt_sfs @@ -68,6 +72,7 @@ use work.xlib.all; use work.genlib.all; use work.serportlib.all; use work.rblib.all; +use work.rbdlib.all; use work.rlinklib.all; use work.bpgenlib.all; use work.bpgenrbuslib.all; @@ -112,6 +117,7 @@ architecture syn of sys_tst_rlink_b3 is signal RB_SRES_HIO : rb_sres_type := rb_sres_init; signal RB_SRES_TST : rb_sres_type := rb_sres_init; signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; + signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); @@ -122,6 +128,10 @@ architecture syn of sys_tst_rlink_b3 is constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx + constant sysid_proj : slv16 := x"0101"; -- tst_rlink + constant sysid_board : slv8 := x"06"; -- basys3 + constant sysid_vers : slv8 := x"00"; + begin assert (sys_conf_clksys mod 1000000) = 0 @@ -194,12 +204,12 @@ begin generic map ( BTOWIDTH => 6, RTAWIDTH => 12, - SYSID => (others=>'0'), + SYSID => sysid_proj & sysid_board & sysid_vers, IFAWIDTH => 5, OFAWIDTH => 5, ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, - CDWIDTH => 15, + CDWIDTH => 12, CDINIT => sys_conf_ser2rri_cdinit, RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink RBMON_RBADDR => (others=>'0')) @@ -254,11 +264,19 @@ begin ); end generate SMRB; - RB_SRES_OR1 : rb_sres_or_3 + UARB : rbd_usracc + port map ( + CLK => CLK, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_USRACC + ); + + RB_SRES_OR1 : rb_sres_or_4 port map ( RB_SRES_1 => RB_SRES_HIO, RB_SRES_2 => RB_SRES_TST, RB_SRES_3 => RB_SRES_SYSMON, + RB_SRES_4 => RB_SRES_USRACC, RB_SRES_OR => RB_SRES ); diff --git a/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vmfset b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vmfset new file mode 100644 index 00000000..71c226da --- /dev/null +++ b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vmfset @@ -0,0 +1,26 @@ +# $Id: sys_tst_rlink_b3.vmfset 773 2016-06-05 20:03:15Z mueller $ +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# unconnected ports -------------------------------------------- +I [Synth 8-3331] RB_MREQ # generic +# --> rlink_sp1c doesn't use CE_USEC # OK 2016-06-05 +i [Synth 8-3331] rlink_sp1c.*CE_USEC + +# unused sequential element ------------------------------------ +I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic +# --> monitor outputs moneop,monattn currently not used # OK 2016-06-05 +i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop] +i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn] +# --> LED(6:2) currently not driven # OK 2016-06-05 +i [Synth 8-3332] R_REGS_reg[ledin][\d] +# ENAESC=0, therefore esc logic inactive # OK 2016-06-05 +i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[escseen] +i [Synth 8-3332] SERPORT/XONTX/R_REGS_reg[escpend] +# --> SER_MONI.rxovr indeed unused # OK 2016-06-05 +i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[rxovr] + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization diff --git a/rtl/sys_gen/tst_rlink/basys3/tb/Makefile b/rtl/sys_gen/tst_rlink/basys3/tb/Makefile index 20ad50e3..c2b705ca 100644 --- a/rtl/sys_gen/tst_rlink/basys3/tb/Makefile +++ b/rtl/sys_gen/tst_rlink/basys3/tb/Makefile @@ -1,30 +1,41 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $ # # Revision History: # Date Rev Version Comment +# 2016-06-18 776 1.1.1 add xsim_clean +# 2016-04-22 763 1.1 add include dep_vsim # 2015-02-18 648 1.0 Initial version # EXE_all = tb_tst_rlink_b3 # include ${RETROBASE}/rtl/make_viv/viv_default_basys3.mk # -.PHONY : all all_ssim clean +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim # all : $(EXE_all) all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) # -clean : viv_clean ghdl_clean +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean # #----- # -include ${RETROBASE}/rtl/make_viv/generic_vivado.mk include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # VBOM_all = $(wildcard *.vbom) # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_vsyn) include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) include $(wildcard *.o.dep_ghdl) endif # diff --git a/rtl/sys_gen/tst_rlink/basys3/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_rlink/basys3/tb/sys_conf_sim.vhd index ec64eed0..f14e63c4 100644 --- a/rtl/sys_gen/tst_rlink/basys3/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/tst_rlink/basys3/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 743 2016-03-13 16:42:31Z mueller $ +-- $Id: sys_conf_sim.vhd 775 2016-06-18 13:42:00Z mueller $ -- -- Copyright 2015-2016 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_b3 (for simulation) -- -- Dependencies: - --- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 +-- Tool versions: viv 2014.4-2016.2; ghdl 0.31-0.33 -- Revision History: -- Date Rev Version Comment -- 2016-03-12 741 1.1 add sysmon_rbus diff --git a/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.mfset b/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.imfset similarity index 95% rename from rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.mfset rename to rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.imfset index a8b1fe6b..181d581a 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.mfset +++ b/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.imfset @@ -1,4 +1,4 @@ -# $Id: sys_tst_rlink_n2.mfset 440 2011-12-18 20:08:09Z mueller $ +# $Id: sys_tst_rlink_n2.imfset 779 2016-06-26 15:37:16Z mueller $ # # ---------------------------------------------------------------------------- [xst] @@ -57,4 +57,4 @@ There are 1 loadless signals in this design # ---------------------------------------------------------------------------- [bgn] Spartan-3 1200E and 1600E devices do not support bitstream -The signal is incomplete \ No newline at end of file +The signal is incomplete diff --git a/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd b/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd index 4ac65eb9..07111f8c 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd +++ b/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_rlink_n2.vhd 743 2016-03-13 16:42:31Z mueller $ +-- $Id: sys_tst_rlink_n2.vhd 748 2016-03-20 15:18:50Z mueller $ -- -- Copyright 2010-2016 by Walter F.J. Mueller -- @@ -41,6 +41,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-03-19 748 1.4.2 define rlink SYSID -- 2015-04-11 666 1.4.1 rearrange XON handling -- 2014-11-09 603 1.4 use new rlink v4 iface and 4 bit STAT -- 2014-08-15 583 1.3 rb_mreq addr now 16 bit @@ -150,6 +151,10 @@ architecture syn of sys_tst_rlink_n2 is constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx + constant sysid_proj : slv16 := x"0101"; -- tst_rlink + constant sysid_board : slv8 := x"02"; -- nexys2 + constant sysid_vers : slv8 := x"00"; + begin assert (sys_conf_clksys mod 1000000) = 0 @@ -223,7 +228,7 @@ begin generic map ( BTOWIDTH => 6, RTAWIDTH => 12, - SYSID => (others=>'0'), + SYSID => sysid_proj & sysid_board & sysid_vers, IFAWIDTH => 5, OFAWIDTH => 5, ENAPIN_RLMON => sbcntl_sbf_rlmon, diff --git a/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd b/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd index 19dec502..4d3f4cd7 100644 --- a/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd +++ b/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_rlink_n3.vhd 743 2016-03-13 16:42:31Z mueller $ +-- $Id: sys_tst_rlink_n3.vhd 748 2016-03-20 15:18:50Z mueller $ -- -- Copyright 2011-2016 by Walter F.J. Mueller -- @@ -38,6 +38,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-03-19 748 1.4.2 define rlink SYSID -- 2015-04-11 666 1.4.1 rearrange XON handling -- 2014-11-09 603 1.4 use new rlink v4 iface and 4 bit STAT -- 2014-08-15 583 1.3 rb_mreq addr now 16 bit @@ -143,6 +144,10 @@ architecture syn of sys_tst_rlink_n3 is constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx + constant sysid_proj : slv16 := x"0101"; -- tst_rlink + constant sysid_board : slv8 := x"03"; -- nexys3 + constant sysid_vers : slv8 := x"00"; + begin assert (sys_conf_clksys mod 1000000) = 0 @@ -221,7 +226,7 @@ begin generic map ( BTOWIDTH => 6, RTAWIDTH => 12, - SYSID => (others=>'0'), + SYSID => sysid_proj & sysid_board & sysid_vers, IFAWIDTH => 5, OFAWIDTH => 5, ENAPIN_RLMON => sbcntl_sbf_rlmon, diff --git a/rtl/sys_gen/tst_rlink/nexys4/Makefile b/rtl/sys_gen/tst_rlink/nexys4/Makefile index 31f766a3..f138e977 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/Makefile +++ b/rtl/sys_gen/tst_rlink/nexys4/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# $Id: Makefile 763 2016-04-22 17:48:24Z mueller $ # # Revision History: # Date Rev Version Comment @@ -21,6 +21,5 @@ include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_vsyn) -##include $(VBOM_all:.vbom=.dep_ghdl) endif # diff --git a/rtl/sys_gen/tst_rlink/nexys4/sys_conf.vhd b/rtl/sys_gen/tst_rlink/nexys4/sys_conf.vhd index 90a40b07..b39561a6 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/sys_conf.vhd +++ b/rtl/sys_gen/tst_rlink/nexys4/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 743 2016-03-13 16:42:31Z mueller $ +-- $Id: sys_conf.vhd 775 2016-06-18 13:42:00Z mueller $ -- -- Copyright 2013-2016 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_n4 (for synthesis) -- -- Dependencies: - --- Tool versions: ise 14.5-14.7; viv 2014.42015.4; ghdl 0.29-0.33 +-- Tool versions: ise 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33 -- Revision History: -- Date Rev Version Comment -- 2016-03-12 741 1.1 add sysmon_rbus diff --git a/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vbom b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vbom index b2df0549..13088b7c 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vbom +++ b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vbom @@ -4,6 +4,7 @@ ../../../vlib/genlib/genlib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd +../../../vlib/rbus/rbdlib.vhd ../../../vlib/rlink/rlinklib.vbom ../../../bplib/bpgen/bpgenlib.vbom ../../../bplib/bpgen/bpgenrbuslib.vbom @@ -20,8 +21,9 @@ ${sys_conf := sys_conf.vhd} ../../../bplib/bpgen/rgbdrv_master.vbom ../../../bplib/bpgen/rgbdrv_analog_rbus.vbom ../../../bplib/sysmon/sysmonx_rbus_base.vbom +../../../vlib/rbus/rbd_usracc.vbom ../../../vlib/rbus/rb_sres_or_2.vbom -../../../vlib/rbus/rb_sres_or_4.vbom +../../../vlib/rbus/rb_sres_or_6.vbom # design sys_tst_rlink_n4.vhd @ucf_cpp: sys_tst_rlink_n4.ucf diff --git a/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd index 6afac52e..2d839267 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd +++ b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_rlink_n4.vhd 743 2016-03-13 16:42:31Z mueller $ +-- $Id: sys_tst_rlink_n4.vhd 772 2016-06-05 12:55:11Z mueller $ -- -- Copyright 2013-2016 by Walter F.J. Mueller -- @@ -24,8 +24,9 @@ -- bplib/bpgen/rgbdrv_master -- bplib/bpgen/rgbdrv_analog_rbus -- bplib/sysmon/sysmonx_rbus_base +-- vlib/rbus/rbd_usracc -- vlib/rbus/rb_sres_or_2 --- vlib/rbus/rb_sres_or_4 +-- vlib/rbus/rb_sres_or_6 -- -- Test bench: tb/tb_tst_rlink_n4 -- @@ -34,12 +35,17 @@ -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic +-- 2016-04-02 758 2015.4 xc7a100t-1 1113 1461 36 3.0 528 usracc +-- 2016-03-27 753 2015.4 xc7a100t-1 1124 1461 36 3.0 522 meminf -- 2016-03-13 743 2015.4 xc7a100t-1 1124 1463 64 4.5 567 +XADC -- 2016-02-20 734 2015.4 xc7a100t-1 1080 1424 64 4.5 502 +RGB -- 2015-01-31 640 2014.4 xc7a100t-1 990 1360 64 4.5 495 -- -- Revision History: -- Date Rev Version Comment +-- 2016-06-05 772 1.5.3 use CDUWIDTH=7, 120 MHz clock is natural choice +-- 2016-04-02 758 1.5.2 add rbd_usracc_e2 (bitfile+jtag timestamp access) +-- 2016-03-19 748 1.5.1 define rlink SYSID -- 2016-03-12 741 1.5 add sysmon_rbus -- 2016-02-20 734 1.4.2 add rgbdrv_analog_rbus for two rgb leds -- 2015-04-11 666 1.4.1 rearrange XON handling @@ -76,6 +82,7 @@ use work.xlib.all; use work.genlib.all; use work.serportlib.all; use work.rblib.all; +use work.rbdlib.all; use work.rlinklib.all; use work.bpgenlib.all; use work.bpgenrbuslib.all; @@ -130,6 +137,7 @@ architecture syn of sys_tst_rlink_n4 is signal RB_SRES_RGB1 : rb_sres_type := rb_sres_init; signal RB_SRES_RGB : rb_sres_type := rb_sres_init; signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; + signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); @@ -145,6 +153,10 @@ architecture syn of sys_tst_rlink_n4 is constant rbaddr_rgb1 : slv16 := x"fc04"; -- fe04/0004: 1111 1100 0000 01xx constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx + constant sysid_proj : slv16 := x"0101"; -- tst_rlink + constant sysid_board : slv8 := x"05"; -- nexys4 + constant sysid_vers : slv8 := x"00"; + begin assert (sys_conf_clksys mod 1000000) = 0 @@ -170,7 +182,7 @@ begin CLKDIV : clkdivce generic map ( - CDUWIDTH => 8, -- good up to 254 MHz + CDUWIDTH => 7, -- good up to 127 MHz USECDIV => sys_conf_clksys_mhz, MSECDIV => 1000) port map ( @@ -222,12 +234,12 @@ begin generic map ( BTOWIDTH => 6, RTAWIDTH => 12, - SYSID => (others=>'0'), + SYSID => sysid_proj & sysid_board & sysid_vers, IFAWIDTH => 5, OFAWIDTH => 5, ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, - CDWIDTH => 15, + CDWIDTH => 12, CDINIT => sys_conf_ser2rri_cdinit, RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink RBMON_RBADDR => (others=>'0')) @@ -322,6 +334,13 @@ begin ); end generate SMRB; + UARB : rbd_usracc + port map ( + CLK => CLK, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_USRACC + ); + RB_SRES_ORRGB : rb_sres_or_2 port map ( RB_SRES_1 => RB_SRES_RGB0, @@ -329,12 +348,13 @@ begin RB_SRES_OR => RB_SRES_RGB ); - RB_SRES_OR1 : rb_sres_or_4 + RB_SRES_OR1 : rb_sres_or_6 port map ( RB_SRES_1 => RB_SRES_HIO, RB_SRES_2 => RB_SRES_TST, RB_SRES_3 => RB_SRES_RGB, RB_SRES_4 => RB_SRES_SYSMON, + RB_SRES_5 => RB_SRES_USRACC, RB_SRES_OR => RB_SRES ); diff --git a/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vmfset b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vmfset new file mode 100644 index 00000000..5bdbc8e5 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vmfset @@ -0,0 +1,28 @@ +# $Id: sys_tst_rlink_n4.vmfset 773 2016-06-05 20:03:15Z mueller $ +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# unconnected ports -------------------------------------------- +I [Synth 8-3331] RB_MREQ # generic +# --> I_BTNRST_N unused in design # OK 2016-06-05 +I [Synth 8-3331] I_BTNRST_N +# --> rlink_sp1c doesn't use CE_USEC # OK 2016-06-05 +i [Synth 8-3331] rlink_sp1c.*CE_USEC + +# unused sequential element ------------------------------------ +I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic +# --> monitor outputs moneop,monattn currently not used # OK 2016-06-05 +i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop] +i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn] +# --> LED(6:2) currently not driven # OK 2016-06-05 +i [Synth 8-3332] R_REGS_reg[ledin][\d].*sn_humanio_rbus +# ENAESC=0, therefore esc logic inactive # OK 2016-06-05 +i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[escseen] +i [Synth 8-3332] SERPORT/XONTX/R_REGS_reg[escpend] +# --> SER_MONI.rxovr indeed unused # OK 2016-06-05 +i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[rxovr] + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization diff --git a/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile b/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile index 130aa9da..6ffe2bfb 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile +++ b/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile @@ -1,7 +1,9 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $ # # Revision History: # Date Rev Version Comment +# 2016-06-18 776 1.1.1 add xsim_clean +# 2016-04-22 763 1.1 add include dep_vsim # 2016-02-07 729 1.0.1 add generic_xsim.mk # 2015-02-18 648 1.0 Initial version # @@ -9,7 +11,8 @@ EXE_all = tb_tst_rlink_n4 # include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk # -.PHONY : all all_ssim clean +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim # all : $(EXE_all) all_ssim : $(EXE_all:=_ssim) @@ -20,19 +23,20 @@ all_XSim_ssim : $(EXE_all:=_XSim_ssim) all_XSim_osim : $(EXE_all:=_XSim_osim) all_XSim_tsim : $(EXE_all:=_XSim_tsim) # -clean : viv_clean ghdl_clean +clean : viv_clean ghdl_clean xsim_clean # #----- # -include ${RETROBASE}/rtl/make_viv/generic_vivado.mk include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # VBOM_all = $(wildcard *.vbom) # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_vsyn) include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) include $(wildcard *.o.dep_ghdl) endif # diff --git a/rtl/sys_gen/tst_rlink/nexys4/tb/sys_conf_sim.vhd b/rtl/sys_gen/tst_rlink/nexys4/tb/sys_conf_sim.vhd index 41c52ff8..ea68a4b9 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/tst_rlink/nexys4/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 743 2016-03-13 16:42:31Z mueller $ +-- $Id: sys_conf_sim.vhd 775 2016-06-18 13:42:00Z mueller $ -- -- Copyright 2013-2016 by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for sys_tst_rlink_n4 (for simulation) -- -- Dependencies: - --- Tool versions: xst 14.5-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 +-- Tool versions: xst 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33 -- Revision History: -- Date Rev Version Comment -- 2016-03-12 741 1.1 add sysmon_rbus diff --git a/rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd b/rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd index 09a6d9d8..8d5ca067 100644 --- a/rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd +++ b/rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_rlink_s3.vhd 743 2016-03-13 16:42:31Z mueller $ +-- $Id: sys_tst_rlink_s3.vhd 748 2016-03-20 15:18:50Z mueller $ -- -- Copyright 2011-2016 by Walter F.J. Mueller -- @@ -36,6 +36,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-03-19 748 1.2.2 define rlink SYSID -- 2015-04-11 666 1.2.1 rearrange XON handling -- 2014-11-09 603 1.2 use new rlink v4 iface and 4 bit STAT -- 2014-08-15 583 1.1 rb_mreq addr now 16 bit @@ -131,6 +132,10 @@ architecture syn of sys_tst_rlink_s3 is constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx + constant sysid_proj : slv16 := x"0101"; -- tst_rlink + constant sysid_board : slv8 := x"01"; -- s3board + constant sysid_vers : slv8 := x"00"; + begin assert (sys_conf_clksys mod 1000000) = 0 @@ -194,7 +199,7 @@ begin generic map ( BTOWIDTH => 6, RTAWIDTH => 12, - SYSID => (others=>'0'), + SYSID => sysid_proj & sysid_board & sysid_vers, IFAWIDTH => 5, OFAWIDTH => 5, ENAPIN_RLMON => sbcntl_sbf_rlmon, diff --git a/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.mfset b/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.imfset similarity index 98% rename from rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.mfset rename to rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.imfset index 75f29b0a..15643e63 100644 --- a/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.mfset +++ b/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.imfset @@ -1,4 +1,4 @@ -# $Id: sys_tst_rlink_cuff_ic_atlys.mfset 472 2013-01-06 14:39:10Z mueller $ +# $Id: sys_tst_rlink_cuff_ic_atlys.imfset 769 2016-05-28 11:36:22Z mueller $ # # ---------------------------------------------------------------------------- [xst] diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.mfset b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.imfset similarity index 98% rename from rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.mfset rename to rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.imfset index 2e785517..6b004649 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.mfset +++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.imfset @@ -1,4 +1,4 @@ -# $Id: sys_tst_rlink_cuff_ic_n2.mfset 466 2012-12-30 13:26:55Z mueller $ +# $Id: sys_tst_rlink_cuff_ic_n2.imfset 769 2016-05-28 11:36:22Z mueller $ # # ---------------------------------------------------------------------------- [xst] diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/.cvsignore b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/.cvsignore deleted file mode 100644 index b988e8c2..00000000 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/.cvsignore +++ /dev/null @@ -1 +0,0 @@ -sys_tst_rlink_cuff_ic3_n2.ucf diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/Makefile b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/Makefile deleted file mode 100644 index 3e0833f5..00000000 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ -# -# Revision History: -# Date Rev Version Comment -# 2012-12-29 466 1.0 Initial version -# -# -VBOM_all = $(wildcard *.vbom) -BIT_all = $(VBOM_all:.vbom=.bit) -# -include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk -FX2_FILE = nexys2_jtag_3fifo_ic.ihx -# -.PHONY : all clean -# -all : $(BIT_all) -# -clean : ise_clean - rm -f $(VBOM_all:.vbom=.ucf) -# -#---- -# -include ${RETROBASE}/rtl/make_ise/generic_xflow.mk -include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk -# -ifndef DONTINCDEP -include $(VBOM_all:.vbom=.dep_xst) -include $(VBOM_all:.vbom=.dep_ghdl) -endif -# diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_conf.vhd b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_conf.vhd deleted file mode 100644 index 056d440c..00000000 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_conf.vhd +++ /dev/null @@ -1,62 +0,0 @@ --- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2012- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Package Name: sys_conf --- Description: Definitions for sys_tst_rlink_cuff_ic3_n2 (for synthesis) --- --- Dependencies: - --- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 --- Revision History: --- Date Rev Version Comment --- 2012-12-29 466 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.slvtypes.all; - -package sys_conf is - - constant sys_conf_clkfx_divide : positive := 1; - constant sys_conf_clkfx_multiply : positive := 1; - - constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud - constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers - - constant sys_conf_fx2_type : string := "ic3"; - - -- dummy values defs for generic parameters of as controller - constant sys_conf_fx2_rdpwldelay : positive := 1; - constant sys_conf_fx2_rdpwhdelay : positive := 1; - constant sys_conf_fx2_wrpwldelay : positive := 1; - constant sys_conf_fx2_wrpwhdelay : positive := 1; - constant sys_conf_fx2_flagdelay : positive := 1; - - -- pktend timer setting - -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) - constant sys_conf_fx2_petowidth : positive := 10; - - constant sys_conf_fx2_ccwidth : positive := 5; - - -- derived constants - - constant sys_conf_clksys : integer := - (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; - constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; - - constant sys_conf_ser2rri_cdinit : integer := - (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; - -end package sys_conf; diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.mfset b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.mfset deleted file mode 100644 index 2cd6389f..00000000 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.mfset +++ /dev/null @@ -1,97 +0,0 @@ -# $Id: sys_tst_rlink_cuff_ic3_n2.mfset 469 2013-01-05 12:29:44Z mueller $ -# -# ---------------------------------------------------------------------------- -[xst] -INFO:.*Mux is complete : default of case is discarded - -Unconnected output port 'SIZE' of component 'fifo_1c_dram' -Unconnected output port 'LOCKED' of component 'dcm_sfs' -Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' -Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen' -Unconnected output port 'RL_MONI' of component 'rlink_core8' - -Input is never used -Input > is never used -Input is never used -Input is never used -Input > is never used -Input > is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used -Input is never used - -Output is never assigned - -Signal > is assigned but never used -Signal is assigned but never used -Signal > is assigned but never used -Signal > is assigned but never used -Signal is assigned but never used -Signal is assigned but never used -Signal is assigned but never used -Signal > is assigned but never used -Signal is assigned but never used -Signal is assigned but never used -Signal is assigned but never used -Signal is assigned but never used -Signal is assigned but never used - -Signal is used but never assigned -Signal is used but never assigned - -FF/Latch in Unit is equivalent - -FF/Latch has a constant value of 0 -FF/Latch has a constant value of 0 -FF/Latch has a constant value of 0 -FF/Latch has a constant value of 0 -FF/Latch has a constant value -FF/Latch has a constant value - -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected -Node of sequential type is unconnected - -Node of sequential type is unconnected - -RAMs , are equivalent -RAMs , are equivalent - -# -# ---------------------------------------------------------------------------- -[tra] - -# -# ---------------------------------------------------------------------------- -[map] -The signal is incomplete -INFO:.* - -# -# ---------------------------------------------------------------------------- -[par] -The signal I_MEM_WAIT_IBUF has no load -There are 1 loadless signals in this design -This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied -# -# ---------------------------------------------------------------------------- -[bgn] -Spartan-3 1200E and 1600E devices do not support bitstream -The signal is incomplete diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.ucf_cpp b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.ucf_cpp deleted file mode 100644 index 52b3f5ac..00000000 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.ucf_cpp +++ /dev/null @@ -1,22 +0,0 @@ -## $Id: sys_tst_rlink_cuff_ic3_n2.ucf_cpp 466 2012-12-30 13:26:55Z mueller $ -## -## Revision History: -## Date Rev Version Comment -## 2012-12-29 466 1.0 Initial version -## - -NET "I_CLK50" TNM_NET = "I_CLK50"; -TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; -OFFSET = IN 10 ns BEFORE "I_CLK50"; -OFFSET = OUT 20 ns AFTER "I_CLK50"; - -#include "bplib/nexys2/nexys2_pins.ucf" -## -## Pmod B0 - RS232 -## -#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf" -## -## Cypress FX2 -## -#include "bplib/nexys2/nexys2_pins_fx2.ucf" -#include "bplib/nexys2/nexys2_time_fx2_ic.ucf" diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.vbom b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.vbom deleted file mode 100644 index 5e0cb787..00000000 --- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.vbom +++ /dev/null @@ -1,8 +0,0 @@ -# conf -sys_conf = sys_conf.vhd -# libs -# components -# design -../sys_tst_rlink_cuff_n2.vbom -@ucf_cpp: sys_tst_rlink_cuff_ic3_n2.ucf -@top: sys_tst_rlink_cuff_n2 diff --git a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.mfset b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.imfset similarity index 98% rename from rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.mfset rename to rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.imfset index 161d4794..8b957c94 100644 --- a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.mfset +++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.imfset @@ -1,4 +1,4 @@ -# $Id: sys_tst_rlink_cuff_ic_n3.mfset 472 2013-01-06 14:39:10Z mueller $ +# $Id: sys_tst_rlink_cuff_ic_n3.imfset 769 2016-05-28 11:36:22Z mueller $ # # ---------------------------------------------------------------------------- [xst] diff --git a/rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vhd b/rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vhd index 888a3e25..c408f410 100644 --- a/rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vhd +++ b/rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vhd @@ -1,6 +1,6 @@ --- $Id: tst_rlink_cuff.vhd 666 2015-04-12 21:17:54Z mueller $ +-- $Id: tst_rlink_cuff.vhd 748 2016-03-20 15:18:50Z mueller $ -- --- Copyright 2012-2015 by Walter F.J. Mueller +-- Copyright 2012-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -25,10 +25,11 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.33 -- -- Revision History: -- Date Rev Version Comment +-- 2016-03-19 748 1.2.1 define rlink SYSID -- 2015-04-11 666 1.2 rearrange XON handling -- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT -- 2013-01-02 467 1.0.1 use 64 usec led pulse width @@ -114,14 +115,18 @@ architecture syn of tst_rlink_cuff is signal R_LEDDIV : slv6 := (others=>'0'); -- clock divider for LED pulses signal R_LEDCE : slbit := '0'; -- ce every 64 usec - + + constant sysid_proj : slv16 := x"0103"; -- tst_rlink_cuff + constant sysid_board : slv8 := x"00"; -- generic + constant sysid_vers : slv8 := x"00"; + begin RLCORE : rlink_core8 generic map ( BTOWIDTH => 6, RTAWIDTH => 12, - SYSID => (others=>'0'), + SYSID => sysid_proj & sysid_board & sysid_vers, ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon) port map ( diff --git a/rtl/sys_gen/tst_serloop/Makefile b/rtl/sys_gen/tst_serloop/Makefile.ise similarity index 86% rename from rtl/sys_gen/tst_serloop/Makefile rename to rtl/sys_gen/tst_serloop/Makefile.ise index 230ada60..76cfa0f2 100644 --- a/rtl/sys_gen/tst_serloop/Makefile +++ b/rtl/sys_gen/tst_serloop/Makefile.ise @@ -1,4 +1,5 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ # # Revision History: # Date Rev Version Comment diff --git a/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vbom b/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vbom index ee6a2f7f..bce2f015 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vbom +++ b/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vbom @@ -5,7 +5,7 @@ sys_conf = sys_conf1_sim.vhd ../../../../vlib/simlib/simlib.vhd # components ../../../../vlib/simlib/simclk.vbom -@uut: ../sys_tst_serloop1_n2.vbom +../sys_tst_serloop1_n2.vbom -UUT ../../tb/tb_tst_serloop.vbom # design tb_tst_serloop1_n2.vhd diff --git a/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vbom b/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vbom index 22e18d0d..d1c1233b 100644 --- a/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vbom +++ b/rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vbom @@ -7,7 +7,7 @@ sys_conf = sys_conf2_sim.vhd # components ../../../../vlib/simlib/simclk.vbom ../../../../vlib/xlib/dcm_sfs_gsim.vbom -@uut: ../sys_tst_serloop2_n2.vbom +../sys_tst_serloop2_n2.vbom -UUT ../../tb/tb_tst_serloop.vbom # design tb_tst_serloop2_n2.vhd diff --git a/rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vbom b/rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vbom index bd9d4d16..9917dced 100644 --- a/rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vbom +++ b/rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vbom @@ -5,7 +5,7 @@ sys_conf = sys_conf1_sim.vhd ../../../../vlib/simlib/simlib.vhd # components ../../../../vlib/simlib/simclk.vbom -@uut: ../sys_tst_serloop1_n3.vbom +../sys_tst_serloop1_n3.vbom -UUT ../../tb/tb_tst_serloop.vbom # design tb_tst_serloop1_n3.vhd diff --git a/rtl/sys_gen/tst_serloop/nexys4/sys_conf1.vhd b/rtl/sys_gen/tst_serloop/nexys4/sys_conf1.vhd index da2ff81f..25613cdc 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/sys_conf1.vhd +++ b/rtl/sys_gen/tst_serloop/nexys4/sys_conf1.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf1.vhd 646 2015-02-15 12:04:55Z mueller $ +-- $Id: sys_conf1.vhd 751 2016-03-25 19:46:11Z mueller $ -- --- Copyright 2015- by Walter F.J. Mueller +-- Copyright 2015-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Definitions for sys_tst_serloop1_n4 (for synthesis) -- -- Dependencies: - --- Tool versions: viv 2014.4; ghdl 0.31 +-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-03-25 751 1.1 clock now from cmt and configurable -- 2015-02-01 641 1.0 Initial version ------------------------------------------------------------------------------ @@ -29,9 +30,28 @@ use work.slvtypes.all; package sys_conf is + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + constant sys_conf_clkdiv_usecdiv : integer := 100; -- default usec constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec + + -- configure hio interfaces ----------------------------------------------- constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers - constant sys_conf_uart_cdinit : integer := 868-1; -- 100000000/115200 + + -- configure serport ------------------------------------------------------ + constant sys_conf_uart_defbaud : integer := 115200; -- default 115k baud + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_uart_cdinit : integer := + (sys_conf_clksys/sys_conf_uart_defbaud)-1; end package sys_conf; diff --git a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vbom b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vbom index 9fa849f9..4d9323f8 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vbom +++ b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vbom @@ -7,6 +7,8 @@ ../../../vlib/serport/serportlib.vbom ${sys_conf := sys_conf1.vhd} # components +[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_4line_iob.vbom ../../../bplib/bpgen/sn_humanio.vbom diff --git a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vhd b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vhd index 946f6bfc..96cec9eb 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vhd +++ b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_serloop1_n4.vhd 646 2015-02-15 12:04:55Z mueller $ +-- $Id: sys_tst_serloop1_n4.vhd 772 2016-06-05 12:55:11Z mueller $ -- --- Copyright 2015- by Walter F.J. Mueller +-- Copyright 2015-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -13,9 +13,10 @@ -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_serloop1_n4 - syn --- Description: Tester serial link for nexys3 (serport_1clock case) +-- Description: Tester serial link for nexys4 (serport_1clock case) -- --- Dependencies: genlib/clkdivce +-- Dependencies: vlib/xlib/s7_cmt_sfs +-- vlib/genlib/clkdivce -- bpgen/bp_rs232_4line_iob -- bpgen/sn_humanio -- tst_serloop_hiomap @@ -25,14 +26,16 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: viv 2014.4; ghdl 0.31 +-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic --- 2015-02-01 641 2014.4 xc7a100t-1 xxx xxxx xx x xxx +-- 2016-03-25 751 2015.4 xc7a100t-1 415 402x 32 0 185 -- -- Revision History: -- Date Rev Version Comment +-- 2016-06-05 772 1.1.1 use CDUWIDTH=7, 120 MHz clock is natural choice +-- 2016-03-27 753 1.1 clock now from cmt and configurable -- 2015-02-06 643 1.1 factor out memory -- 2015-02-01 641 1.0 Initial version (derived from sys_tst_serloop1_n3) ------------------------------------------------------------------------------ @@ -104,13 +107,26 @@ architecture syn of sys_tst_serloop1_n4 is begin - CLK <= I_CLK100; - + GEN_CLKSYS : s7_cmt_sfs -- clock generator ------------------- + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + CLKDIV : clkdivce generic map ( - CDUWIDTH => 8, - USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20 - MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5 + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => sys_conf_clkdiv_msecdiv) port map ( CLK => CLK, CE_USEC => open, @@ -171,7 +187,7 @@ begin SERPORT : serport_1clock generic map ( - CDWIDTH => 15, + CDWIDTH => 12, CDINIT => sys_conf_uart_cdinit, RXFAWIDTH => 5, TXFAWIDTH => 5) diff --git a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vmfset b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vmfset new file mode 100644 index 00000000..87fc00ea --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vmfset @@ -0,0 +1,35 @@ +# $Id: sys_tst_serloop1_n4.vmfset 773 2016-06-05 20:03:15Z mueller $ +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] + +# +++# port driven by constant -------------------------------------- +# --> RGBLED0 unused # OK 2016-06-05 +i [Synth 8-3917] O_RGBLED0[\d] +# --> upper 8 LEDs unused +i [Synth 8-3917] O_LED[(8|9)] +i [Synth 8-3917] O_LED[1\d] + +# tying undriven pin to constant ------------------------------- +# upper 8 LEDs unused # OK 2016-06-05 +i [Synth 8-3295] HIO:LED[\d*] + +# unconnected ports -------------------------------------------- +# --> unused SWI and BTN # OK 2016-06-05 +i [Synth 8-3331] tst_serloop_hiomap.*SWI[\d] +i [Synth 8-3331] tst_serloop_hiomap.*BTN[\d] +# --> clkdiv isn't displayed # OK 2016-06-05 +i [Synth 8-3331] SER_MONI[abclkdiv.*][\d*] +# --> other unused fields which aren't visualized # OK 2016-06-05 +i [Synth 8-3331] SER_MONI[(rxact|txact|abdone|rxerr|rxovr)] +i [Synth 8-3331] HIO_CNTL[enaftdi] + +# unused sequential element ------------------------------------ +# --> many HIO pins not used # OK 2016-06-05 +i [Synth 8-3332] HIO/IOB_(SWI|BTN)/R_DI_reg[\d*] +i [Synth 8-3332] HIO/DEB.DEB_(SWI|BTN)/R_REGS_reg[(dref|dout|dchange)][\d*] + +# ++==+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization diff --git a/rtl/sys_gen/tst_serloop/nexys4/tb/.cvsignore b/rtl/sys_gen/tst_serloop/nexys4/tb/.cvsignore index e89da9a6..78932086 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/tb/.cvsignore +++ b/rtl/sys_gen/tst_serloop/nexys4/tb/.cvsignore @@ -1,2 +1,3 @@ tb_tst_serloop1_n4 +tb_tst_serloop2_n4 tb_tst_serloop_stim diff --git a/rtl/sys_gen/tst_serloop/nexys4/tb/Makefile b/rtl/sys_gen/tst_serloop/nexys4/tb/Makefile index ca75862a..766d4bd1 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/tb/Makefile +++ b/rtl/sys_gen/tst_serloop/nexys4/tb/Makefile @@ -1,15 +1,19 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $ # # Revision History: # Date Rev Version Comment +# 2016-06-18 776 1.1.1 add xsim_clean +# 2016-04-22 763 1.1 add include dep_vsim # 2016-02-07 729 1.0.1 add generic_xsim.mk # 2015-02-21 649 1.0 Initial version # -EXE_all = tb_tst_serloop1_n4 +EXE_all = tb_tst_serloop1_n4 +EXE_all += tb_tst_serloop2_n4 # include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk # -.PHONY : all all_ssim clean +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim # all : $(EXE_all) all_ssim : $(EXE_all:=_ssim) @@ -20,19 +24,20 @@ all_XSim_ssim : $(EXE_all:=_XSim_ssim) all_XSim_osim : $(EXE_all:=_XSim_osim) all_XSim_tsim : $(EXE_all:=_XSim_tsim) # -clean : viv_clean ghdl_clean +clean : viv_clean ghdl_clean xsim_clean # #----- # -include ${RETROBASE}/rtl/make_viv/generic_vivado.mk include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # VBOM_all = $(wildcard *.vbom) # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_vsyn) include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) include $(wildcard *.o.dep_ghdl) endif # diff --git a/rtl/sys_gen/tst_serloop/nexys4/tb/sys_conf1_sim.vhd b/rtl/sys_gen/tst_serloop/nexys4/tb/sys_conf1_sim.vhd index 5b4f1b88..84e98699 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/tb/sys_conf1_sim.vhd +++ b/rtl/sys_gen/tst_serloop/nexys4/tb/sys_conf1_sim.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf1_sim.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: sys_conf1_sim.vhd 753 2016-03-28 08:57:31Z mueller $ -- --- Copyright 2015- by Walter F.J. Mueller +-- Copyright 2015-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Definitions for sys_tst_serloop1_n4 (for test bench) -- -- Dependencies: - --- Tool versions: viv 2014.4; ghdl 0.31 +-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-033 -- Revision History: -- Date Rev Version Comment +-- 2016-03-27 753 1.1 clock now from cmt and configurable -- 2015-02-21 649 1.0 Initial version (cloned from sys_tst_serloop1_n3) ------------------------------------------------------------------------------ @@ -29,15 +30,30 @@ use work.slvtypes.all; package sys_conf is - -- in simulation a usec is shortened to 20 cycles (0.2 usec) and a msec - -- to 100 cycles (1 usec). This affects the pulse generators (usec) and - -- mainly the autobauder. A break will be detected after 128 msec periods, - -- this in simulation after 128 usec or 6400 cycles. This is compatible with - -- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles) + -- in simulation a usec stays to 120 cycles (1.0 usec) and a msec to + -- 240 cycles (2 usec). This affects mainly the autobauder. A break will be + -- detected after 128 msec periods, this in simulation after 256 usec or + -- 30720 cycles. This is compatible with bitrates of 115200 baud or higher + -- (115200 <-> 8.68 usec <-> 1040 cycles) - constant sys_conf_clkdiv_usecdiv : integer := 20; -- default usec - constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened ! - constant sys_conf_hio_debounce : boolean := false; -- no debouncers + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + + constant sys_conf_clkdiv_msecdiv : integer := 2; -- shortened !! + + -- configure hio interfaces ----------------------------------------------- + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- configure serport ------------------------------------------------------ constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; end package sys_conf; diff --git a/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vbom b/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vbom index 7ebf92bd..6bdf3349 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vbom +++ b/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vbom @@ -1,11 +1,11 @@ -# conf -sys_conf = sys_conf1_sim.vhd # libs ../../../../vlib/slvtypes.vhd ../../../../vlib/simlib/simlib.vhd +${sys_conf := sys_conf1_sim.vhd} # components ../../../../vlib/simlib/simclk.vbom -@uut: ../sys_tst_serloop1_n4.vbom +../../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom +../sys_tst_serloop1_n4.vbom -UUT ../../tb/tb_tst_serloop.vbom # design tb_tst_serloop1_n4.vhd diff --git a/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vhd b/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vhd index 74a8fd9e..15b1c632 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vhd +++ b/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vhd @@ -1,4 +1,4 @@ --- $Id: tb_tst_serloop1_n4.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: tb_tst_serloop1_n4.vhd 760 2016-04-09 16:17:13Z mueller $ -- -- Copyright 2015- by Walter F.J. Mueller -- @@ -16,6 +16,7 @@ -- Description: Test bench for sys_tst_serloop1_n4 -- -- Dependencies: simlib/simclk +-- vlib/xlib/tb/s7_cmt_sfs_tb -- sys_tst_serloop1_n4 [UUT] -- tb/tb_tst_serloop -- @@ -25,6 +26,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-04-09 760 1.1 clock now from cmt and configurable -- 2015-02-21 438 1.0 Initial version (cloned from tb_tst_serloop1_n3) ------------------------------------------------------------------------------ @@ -36,6 +38,7 @@ use std.textio.all; use work.slvtypes.all; use work.simlib.all; +use work.sys_conf.all; entity tb_tst_serloop1_n4 is end tb_tst_serloop1_n4; @@ -44,6 +47,8 @@ architecture sim of tb_tst_serloop1_n4 is signal CLK100 : slbit := '0'; signal CLK_STOP : slbit := '0'; + + signal CLK : slbit := '0'; signal I_RXD : slbit := '1'; signal O_TXD : slbit := '1'; @@ -74,6 +79,21 @@ begin CLK_STOP => CLK_STOP ); + GEN_CLKSYS : entity work.s7_cmt_sfs_tb + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => CLK100, + CLKFX => CLK, + LOCKED => open + ); + UUT : entity work.sys_tst_serloop1_n4 port map ( I_CLK100 => CLK100, @@ -93,17 +113,17 @@ begin GENTB : entity work.tb_tst_serloop port map ( - CLKS => CLK100, - CLKH => CLK100, + CLKS => CLK, + CLKH => CLK, CLK_STOP => CLK_STOP, P0_RXD => RXD, P0_TXD => TXD, P0_RTS_N => RTS_N, P0_CTS_N => CTS_N, - P1_RXD => RXD, - P1_TXD => TXD, - P1_RTS_N => RTS_N, - P1_CTS_N => CTS_N, + P1_RXD => open, -- port 1 unused for n4 ! + P1_TXD => '0', + P1_RTS_N => '0', + P1_CTS_N => open, SWI => SWI(7 downto 0), BTN => BTN(3 downto 0) ); diff --git a/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4_ssim.vbom b/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4_ssim.vbom new file mode 100644 index 00000000..3dd8c96e --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4_ssim.vbom @@ -0,0 +1,12 @@ +# libs +../../../../vlib/slvtypes.vhd +../../../../vlib/simlib/simlib.vhd +${sys_conf := sys_conf1_sim.vhd} +# components +../../../../vlib/simlib/simclk.vbom +../../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom +sys_tst_serloop1_n4_ssim.vhd -UUT +../../tb/tb_tst_serloop.vbom +# design +tb_tst_serloop1_n4.vhd +@top:tb_tst_serloop1_n4 diff --git a/rtl/sys_gen/tst_serloop/nexys4/tb/tbw.dat b/rtl/sys_gen/tst_serloop/nexys4/tb/tbw.dat index 94b47535..aaa46638 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/tb/tbw.dat +++ b/rtl/sys_gen/tst_serloop/nexys4/tb/tbw.dat @@ -1,6 +1,6 @@ -# $Id: tbw.dat 649 2015-02-21 21:10:16Z mueller $ +# $Id: tbw.dat 760 2016-04-09 16:17:13Z mueller $ # [tb_tst_serloop1_n4] -tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat +tb_tst_serloop_stim = ../../tb/tb_tst_serloop_p0_cts_stim.dat [tb_tst_serloop2_n4] -tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat +tb_tst_serloop_stim = ../../tb/tb_tst_serloop_p0_cts_stim.dat diff --git a/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.mfset b/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.imfset similarity index 92% rename from rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.mfset rename to rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.imfset index 4502f7d6..a7c7da39 100644 --- a/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.mfset +++ b/rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.imfset @@ -1,4 +1,4 @@ -# $Id: sys_tst_serloop_s3.mfset 441 2011-12-20 17:01:16Z mueller $ +# $Id: sys_tst_serloop_s3.imfset 769 2016-05-28 11:36:22Z mueller $ # # ---------------------------------------------------------------------------- [xst] diff --git a/rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vbom b/rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vbom index b8f8dea5..44bc6b67 100644 --- a/rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vbom +++ b/rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vbom @@ -7,7 +7,7 @@ sys_conf = sys_conf_sim.vhd # components ../../../../vlib/simlib/simclk.vbom ../../../../vlib/xlib/dcm_sfs_gsim.vbom -@uut: ../sys_tst_serloop_s3.vbom +../sys_tst_serloop_s3.vbom -UUT ../../tb/tb_tst_serloop.vbom # design tb_tst_serloop_s3.vhd diff --git a/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vbom b/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vbom index 85efd037..ed4cd539 100644 --- a/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vbom +++ b/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vbom @@ -1,10 +1,10 @@ # libs ../../../vlib/slvtypes.vhd ../../../vlib/simlib/simlib.vhd -../../../vlib/serport/serportlib.vbom +../../../vlib/serport/tb/serportlib_tb.vhd # components ../../../vlib/simlib/simclkcnt.vbom -../../../vlib/serport/serport_uart_rxtx.vbom -../../../vlib/serport/serport_xontx.vbom +../../../vlib/serport/tb/serport_uart_rxtx_tb.vbom +../../../vlib/serport/tb/serport_xontx_tb.vbom # design tb_tst_serloop.vhd diff --git a/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vhd b/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vhd index 7fb6ffe8..ee62feba 100644 --- a/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vhd +++ b/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop.vhd @@ -1,6 +1,6 @@ --- $Id: tb_tst_serloop.vhd 476 2013-01-26 22:23:53Z mueller $ +-- $Id: tb_tst_serloop.vhd 764 2016-04-23 18:21:44Z mueller $ -- --- Copyright 2011- by Walter F.J. Mueller +-- Copyright 2011-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,8 +16,8 @@ -- Description: Generic test bench for sys_tst_serloop_xx -- -- Dependencies: vlib/simlib/simclkcnt --- vlib/serport/serport_uart_rxtx --- vlib/serport/serport_xontx +-- vlib/serport/serport_uart_rxtx_tb +-- vlib/serport/serport_xontx_tb -- -- To test: sys_tst_serloop_xx -- @@ -25,6 +25,8 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-04-23 764 1.2 use serport/tb/serport_(uart_rxtx|xontx)_tb +-- use assert to halt simulation -- 2011-12-23 444 1.1 use new simclkcnt -- 2011-11-13 425 1.0 Initial version -- 2011-11-06 420 0.5 First draft @@ -38,7 +40,7 @@ use std.textio.all; use work.slvtypes.all; use work.simlib.all; -use work.serportlib.all; +use work.serportlib_tb.all; entity tb_tst_serloop is port ( @@ -105,7 +107,7 @@ begin CLKCNT : simclkcnt port map (CLK => CLKS, CLK_CYCLE => CLK_CYCLE); - UART : serport_uart_rxtx + UART : entity work.serport_uart_rxtx_tb generic map ( CDWIDTH => 13) port map ( @@ -123,7 +125,7 @@ begin TXBUSY => UART_TXBUSY ); - XONTX : serport_xontx + XONTX : entity work.serport_xontx_tb port map ( CLK => CLKS, RESET => UART_RESET, @@ -450,6 +452,8 @@ begin wait for 500 ns; -- allows dcm's to stop + assert false report "Simulation Finished" severity failure; + wait; -- suspend proc_stim forever -- clock is stopped, sim will end diff --git a/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop_p0_cts_stim.dat b/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop_p0_cts_stim.dat new file mode 100644 index 00000000..a51511d0 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/tb/tb_tst_serloop_p0_cts_stim.dat @@ -0,0 +1,92 @@ +# $Id: tb_tst_serloop_p0_cts_stim.dat 760 2016-04-09 16:17:13Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-04-09 760 1.0 Initial version (for port 0 cts) +# +C ------------------------------------------------ +C try SWI settings +# only the 4 LBS (disp and enable control) +# don't touch the 2 mode settings here !! +# +wait 10 +# +swi 10000000 2 +swi 01000000 2 +swi 00100000 2 +swi 00010000 2 +swi 00000000 2 +wait 2 +# +C ------------------------------------------------ +C loop-back message with 16 bytes on port 0 +# +port 0 +swi 00000000 2 +btn 0 10 +# +# mode=11(loop); +swi 00000110 2 +btn 1 10 +# +expect 16 0 0 +send 16 0 0 +wait 100 +expect 0 0 0 +# +C ------------------------------------------------ +C loop-back message with 32 bytes escaped on port 0 +# +port 0 +swi 00000000 2 +btn 0 10 +# +# enaesc=1; mode=11(loop) +swi 00100110 2 +btn 1 10 +# +expect 32 1 0 +send 32 1 0 +wait 100 +expect 0 0 0 +# +C ------------------------------------------------ +C loop-back message with 256 bytes raw on port 0; cts throttle +# +port 0 +swi 00000000 2 +btn 0 10 +# +# enaesc=0;enaxon=0; mode=11(loop); port=0 +swi 00000110 2 +btn 1 10 +# +cts 200 100 +expect 256 1 0 +send 256 1 0 +wait 1500 +expect 0 0 0 +cts 0 0 +# +C ------------------------------------------------ +C loop-back message with 256 bytes escaped on port 0; xon throttle +# +port 0 +swi 00000000 2 +btn 0 10 +# +# enaesc=1;enaxon=1; mode=11(loop); port=0 +swi 00110110 2 +btn 1 10 +# +xon 200 100 +expect 256 1 1 +send 256 1 1 +wait 1500 +expect 0 0 0 +xon 0 0 +# +C ------------------------------------------------ +C cool down +wait 200 + diff --git a/rtl/sys_gen/tst_serloop/tst_serloop.vhd b/rtl/sys_gen/tst_serloop/tst_serloop.vhd index 678cb590..f9432cb7 100644 --- a/rtl/sys_gen/tst_serloop/tst_serloop.vhd +++ b/rtl/sys_gen/tst_serloop/tst_serloop.vhd @@ -1,4 +1,4 @@ --- $Id: tst_serloop.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: tst_serloop.vhd 751 2016-03-25 19:46:11Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31 +-- Tool versions: ise 13.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 -- -- Revision History: -- Date Rev Version Comment @@ -189,7 +189,6 @@ begin when others => null; end case; - if SER_MONI.abact = '1' then -- if auto bauder active n.rxfecnt := (others=>'0'); -- reset frame error counter else -- otherwise @@ -235,7 +234,7 @@ begin HIO_STAT.rxuidat <= r.rxuidat; HIO_STAT.rxokcnt <= r.rxokcnt; HIO_STAT.txokcnt <= r.txokcnt; - + end process proc_next; end syn; diff --git a/rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vhd b/rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vhd index da101fb4..43a0506e 100644 --- a/rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vhd +++ b/rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vhd @@ -1,4 +1,4 @@ --- $Id: tst_serloop_hiomap.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: tst_serloop_hiomap.vhd 751 2016-03-25 19:46:11Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31 +-- Tool versions: ise 13.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/sys_gen/tst_serloop/tst_serlooplib.vhd b/rtl/sys_gen/tst_serloop/tst_serlooplib.vhd index 9e8543fd..37e53a0d 100644 --- a/rtl/sys_gen/tst_serloop/tst_serlooplib.vhd +++ b/rtl/sys_gen/tst_serloop/tst_serlooplib.vhd @@ -1,4 +1,4 @@ --- $Id: tst_serlooplib.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: tst_serlooplib.vhd 751 2016-03-25 19:46:11Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -16,7 +16,7 @@ -- Description: Definitions for tst_serloop records and helpers -- -- Dependencies: - --- Tool versions: ise 13.1-14.7; viv 2014.7; ghdl 0.29-0.31 +-- Tool versions: ise 13.1-14.7; viv 2014.7-2015.4; ghdl 0.29-0.33 -- Revision History: -- Date Rev Version Comment -- 2011-12-10 438 1.0.2 add rxui(cnt|dat) fields in hio_stat_type diff --git a/rtl/sys_gen/tst_snhumanio/Makefile b/rtl/sys_gen/tst_snhumanio/Makefile.ise similarity index 83% rename from rtl/sys_gen/tst_snhumanio/Makefile rename to rtl/sys_gen/tst_snhumanio/Makefile.ise index a91b61e9..027311dd 100644 --- a/rtl/sys_gen/tst_snhumanio/Makefile +++ b/rtl/sys_gen/tst_snhumanio/Makefile.ise @@ -1,4 +1,5 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ # # Revision History: # Date Rev Version Comment diff --git a/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.mfset b/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.imfset similarity index 91% rename from rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.mfset rename to rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.imfset index 4106309d..d3df242c 100644 --- a/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.mfset +++ b/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.imfset @@ -1,4 +1,4 @@ -# $Id: sys_tst_snhumanio_atlys.mfset 416 2011-10-15 13:32:57Z mueller $ +# $Id: sys_tst_snhumanio_atlys.imfset 769 2016-05-28 11:36:22Z mueller $ # # ---------------------------------------------------------------------------- [xst] diff --git a/rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vmfset b/rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vmfset new file mode 100644 index 00000000..0712447f --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vmfset @@ -0,0 +1,10 @@ +# $Id: sys_tst_snhumanio_b3.vmfset 772 2016-06-05 12:55:11Z mueller $ +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# --> really no messages ... ! + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization diff --git a/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.mfset b/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.imfset similarity index 93% rename from rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.mfset rename to rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.imfset index 11ad9657..e10c27dd 100644 --- a/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.mfset +++ b/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.imfset @@ -1,4 +1,4 @@ -# $Id: sys_tst_snhumanio_n2.mfset 412 2011-10-08 15:15:20Z mueller $ +# $Id: sys_tst_snhumanio_n2.imfset 769 2016-05-28 11:36:22Z mueller $ # # ---------------------------------------------------------------------------- [xst] diff --git a/rtl/sys_gen/tst_snhumanio/nexys4/sys_tst_snhumanio_n4.vmfset b/rtl/sys_gen/tst_snhumanio/nexys4/sys_tst_snhumanio_n4.vmfset new file mode 100644 index 00000000..0dc2f59b --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/nexys4/sys_tst_snhumanio_n4.vmfset @@ -0,0 +1,16 @@ +# $Id: sys_tst_snhumanio_n4.vmfset 772 2016-06-05 12:55:11Z mueller $ +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# port driven by constant -------------------------------------- +# --> RGBLED0 and upper 4 DSP digits unused # OK 2016-06-05 +i [Synth 8-3917] O_RGBLED0[\d] +i [Synth 8-3917] O_ANO_N[4] +i [Synth 8-3917] O_ANO_N[5] +i [Synth 8-3917] O_ANO_N[6] +i [Synth 8-3917] O_ANO_N[7] + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization diff --git a/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.mfset b/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.imfset similarity index 90% rename from rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.mfset rename to rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.imfset index f5179443..2577ec40 100644 --- a/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.mfset +++ b/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.imfset @@ -1,4 +1,4 @@ -# $Id: sys_tst_snhumanio_s3.mfset 417 2011-10-22 10:30:29Z mueller $ +# $Id: sys_tst_snhumanio_s3.imfset 769 2016-05-28 11:36:22Z mueller $ # # ---------------------------------------------------------------------------- [xst] diff --git a/rtl/sys_gen/w11a/arty_bram/sys_conf.vhd b/rtl/sys_gen/w11a/arty_bram/sys_conf.vhd index 573a3c46..f5a66953 100644 --- a/rtl/sys_gen/w11a/arty_bram/sys_conf.vhd +++ b/rtl/sys_gen/w11a/arty_bram/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 742 2016-03-13 14:40:19Z mueller $ +-- $Id: sys_conf.vhd 775 2016-06-18 13:42:00Z mueller $ -- -- Copyright 2016- by Walter F.J. Mueller -- @@ -16,9 +16,14 @@ -- Description: Definitions for sys_w11a_br_arty (for synthesis) -- -- Dependencies: - --- Tool versions: viv 2015.4; ghdl 0.33 +-- Tool versions: viv 2015.4-2016.2; ghdl 0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-06-18 775 1.3.3 use PLL for clkser_gentype +-- 2016-05-28 770 1.3.2 sys_conf_mem_losize now type natural +-- 2016-05-26 768 1.3.1 set dmscnt=0 (vivado fsm issue) (@ 80 MHz) +-- 2016-03-28 755 1.3 use serport_2clock2 -> define clkser (@75 MHz) +-- 2016-03-22 750 1.2 add sys_conf_cache_twidth -- 2016-03-13 742 1.1 add sysmon_bus -- 2016-02-27 736 1.0 Initial version (derived from _b3 version) ------------------------------------------------------------------------------ @@ -35,11 +40,11 @@ package sys_conf is constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz constant sys_conf_clksys_gentype : string := "MMCM"; - -- single clock design, clkser = clksys - constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; - constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; - constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; - constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud @@ -52,7 +57,7 @@ package sys_conf is -- configure debug and monitoring units ------------------------------------ constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs - constant sys_conf_dmscnt : boolean := true; + constant sys_conf_dmscnt : boolean := false; constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) @@ -60,9 +65,10 @@ package sys_conf is -- configure w11 cpu core -------------------------------------------------- -- sys_conf_mem_losize is highest 64 byte MMU block number -- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks - constant sys_conf_mem_losize : integer := 256*sys_conf_memctl_nblock-1; + constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1; constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + constant sys_conf_cache_twidth : integer := 9; -- 8kB cache -- configure w11 system devices -------------------------------------------- -- configure character and communication devices diff --git a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom index d3c7ea0a..80e3e119 100644 --- a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom +++ b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom @@ -4,6 +4,7 @@ ../../../vlib/genlib/genlib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd +../../../vlib/rbus/rbdlib.vhd ../../../vlib/rlink/rlinklib.vbom ../../../bplib/bpgen/bpgenlib.vbom ../../../bplib/sysmon/sysmonrbuslib.vbom @@ -16,7 +17,7 @@ sys_conf = sys_conf.vhd [ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2line_iob.vbom -../../../vlib/rlink/rlink_sp1c.vbom +../../../vlib/rlink/rlink_sp2c.vbom ../../../w11a/pdp11_sys70.vbom ../../../ibus/ibdr_maxisys.vbom ../../../w11a/pdp11_bram_memctl.vbom @@ -25,7 +26,8 @@ pdp11_hio70_arty.vbom ../../../bplib/bpgen/bp_swibtnled.vbom ../../../bplib/bpgen/rgbdrv_3x4mux.vbom ../../../bplib/sysmon/sysmonx_rbus_arty.vbom -../../../vlib/rbus/rb_sres_or_2.vbom +../../../vlib/rbus/rbd_usracc.vbom +../../../vlib/rbus/rb_sres_or_3.vbom # design sys_w11a_br_arty.vhd @xdc:../../../bplib/arty/arty_pclk.xdc diff --git a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd index add02693..cb729834 100644 --- a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd +++ b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_br_arty.vhd 742 2016-03-13 14:40:19Z mueller $ +-- $Id: sys_w11a_br_arty.vhd 768 2016-05-26 16:47:00Z mueller $ -- -- Copyright 2016- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: vlib/xlib/s7_cmt_sfs -- vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_2line_iob --- vlib/rlink/rlink_sp1c +-- vlib/rlink/rlink_sp2c -- w11a/pdp11_sys70 -- ibus/ibdr_maxisys -- w11a/pdp11_bram_memctl @@ -27,20 +27,27 @@ -- bplib/bpgen/bp_swibtnled -- bplib/bpgen/rgbdrv_3x4mux -- bplib/sysmon/sysmonx_rbus_arty --- vlib/rbus/rb_sres_or_2 +-- vlib/rbus/rbd_usracc +-- vlib/rbus/rb_sres_or_3 -- -- Test bench: tb/tb_sys_w11a_br_arty -- -- Target Devices: generic --- Tool versions: viv 2015.4; ghdl 0.33 +-- Tool versions: viv 2015.4-2016.1; ghdl 0.33 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic +-- 2016-05-26 768 2016.1 xc7a35t-1 2226 5080 138 47.5 1569 fsm+dsm=0 +-- 2016-03-29 756 2015.4 xc7a35t-1 2106 4428 138 48.5 1397 serport2 +-- 2016-03-27 753 2015.4 xc7a35t-1 1995 4298 138 48.5 1349 meminf -- 2016-03-13 742 2015.4 xc7a35t-1 1996 4309 162 48.5 1333 +XADC -- 2016-02-27 737 2015.4 xc7a35t-1 1952 4246 162 48.5 1316 -- -- Revision History: -- Date Rev Version Comment +-- 2016-04-02 758 1.2.1 add rbd_usracc (bitfile+jtag timestamp access) +-- 2016-03-28 755 1.2 use serport_2clock2 +-- 2016-03-19 748 1.1.2 define rlink SYSID -- 2016-03-13 742 1.1.1 add sysmon_rbus -- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config -- 2016-02-27 736 1.0 Initial version (derived from sys_w11a_b3) @@ -98,6 +105,7 @@ use work.xlib.all; use work.genlib.all; use work.serportlib.all; use work.rblib.all; +use work.rbdlib.all; use work.rlinklib.all; use work.bpgenlib.all; use work.sysmonrbuslib.all; @@ -134,6 +142,9 @@ architecture syn of sys_w11a_br_arty is signal CE_USEC : slbit := '0'; signal CE_MSEC : slbit := '0'; + signal CLKS : slbit := '0'; + signal CES_MSEC : slbit := '0'; + signal RXD : slbit := '1'; signal TXD : slbit := '0'; @@ -142,6 +153,7 @@ architecture syn of sys_w11a_br_arty is signal RB_SRES_CPU : rb_sres_type := rb_sres_init; signal RB_SRES_HIO : rb_sres_type := rb_sres_init; signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; + signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); @@ -187,13 +199,17 @@ architecture syn of sys_w11a_br_arty is constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx + constant sysid_proj : slv16 := x"0201"; -- w11a + constant sysid_board : slv8 := x"07"; -- arty + constant sysid_vers : slv8 := x"00"; + begin assert (sys_conf_clksys mod 1000000) = 0 report "assert sys_conf_clksys on MHz grid" severity failure; - GEN_CLKSYS : s7_cmt_sfs -- clock generator ------------------- + GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ generic map ( VCO_DIVIDE => sys_conf_clksys_vcodivide, VCO_MULTIPLY => sys_conf_clksys_vcomultiply, @@ -208,7 +224,7 @@ begin LOCKED => open ); - CLKDIV : clkdivce -- usec/msec clock divider ----------- + CLKDIV_CLK : clkdivce -- usec/msec clock divider system ---- generic map ( CDUWIDTH => 7, USECDIV => sys_conf_clksys_mhz, @@ -219,25 +235,51 @@ begin CE_MSEC => CE_MSEC ); + GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------ + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clkser_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLKS, + LOCKED => open + ); + + CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport --- + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clkser_mhz, + MSECDIV => 1000) + port map ( + CLK => CLKS, + CE_USEC => open, + CE_MSEC => CES_MSEC + ); + IOB_RS232 : bp_rs232_2line_iob -- serport iob ---------------------- port map ( - CLK => CLK, + CLK => CLKS, RXD => RXD, TXD => TXD, I_RXD => I_RXD, O_TXD => O_TXD ); - RLINK : rlink_sp1c -- rlink for serport ----------------- + RLINK : rlink_sp2c -- rlink for serport ----------------- generic map ( BTOWIDTH => 7, -- 128 cycles access timeout RTAWIDTH => 12, - SYSID => (others=>'0'), + SYSID => sysid_proj & sysid_board & sysid_vers, IFAWIDTH => 5, -- 32 word input fifo OFAWIDTH => 5, -- 32 word output fifo ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, - CDWIDTH => 13, + CDWIDTH => 12, CDINIT => sys_conf_ser2rri_cdinit, RBMON_AWIDTH => sys_conf_rbmon_awidth, RBMON_RBADDR => rbaddr_rbmon) @@ -247,6 +289,8 @@ begin CE_MSEC => CE_MSEC, CE_INT => CE_MSEC, RESET => RESET, + CLKS => CLKS, + CES_MSEC => CES_MSEC, ENAXON => '1', -- XON statically enabled ! ESCFILL => '0', RXSD => RXD, @@ -404,10 +448,18 @@ begin ); end generate SMRB; - RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- + UARB : rbd_usracc + port map ( + CLK => CLK, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_USRACC + ); + + RB_SRES_OR : rb_sres_or_3 -- rbus or --------------------------- port map ( RB_SRES_1 => RB_SRES_CPU, RB_SRES_2 => RB_SRES_SYSMON, + RB_SRES_3 => RB_SRES_USRACC, RB_SRES_OR => RB_SRES ); diff --git a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vmfset b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vmfset new file mode 100644 index 00000000..f6fce57f --- /dev/null +++ b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vmfset @@ -0,0 +1,50 @@ +# $Id: sys_w11a_br_arty.vmfset 773 2016-06-05 20:03:15Z mueller $ +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# false_path -hold ignored by synth ---------------------------- +I [Designutils 20-1567] # generic + +# net without driver ------------------------------------------- +i [Synth 8-3848] DM_STAT_SE[snum].*pdp11_sequencer # OK 2016-06-05 + +# unconnected ports -------------------------------------------- +I [Synth 8-3331] RB_MREQ # generic +I [Synth 8-3331] DM_STAT_DP # generic +# --> pdp11_hio70_arty uses only subset of CP_STAT info # OK 2016-06-05 +I [Synth 8-3331] pdp11_hio70_arty.*CP_STAT[.*] + +# unused sequential element ------------------------------------ +I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic +# --> many HIO pins not used # OK 2016-06-05 +I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*] +i [Synth 8-3332] HIO/IOB_BTN/R_DI_reg[\d*] +i [Synth 8-3332] HIO/DEB.DEB_BTN/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*] +# --> usec not used for serport clock domain # OK 2016-06-05 +i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec] +# --> inst_compl logic disabled in pdp11_mmu # OK 2016-06-05 +i [Synth 8-3332] VMBOX/MMU/R_SSR0_reg[inst_compl] +# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2016-06-05 +i [Synth 8-3332] VMBOX/R_REGS_reg[ibcacc] +# --> not yet used # OK 2016-06-05 +i [Synth 8-3332] SEQ/R_STATUS_reg[suspext] +# --> mawidth=4, nblock=11, so some cellen unused # OK 2016-06-05 +i [Synth 8-3332] BRAM_CTL/R_REGS_reg[cellen][1\d] +# --> indeed no types with [3] set # OK 2016-06-05 +i [Synth 8-3332] R_REGS_reg[dtyp][3].*ibdr_rhrp +# --> not yet used # OK 2016-06-05 +i [Synth 8-3332] R_REGS_reg[req_lock].*ibd_iist +i [Synth 8-3332] R_REGS_reg[req_boot].*ibd_iist +# --> [8] is for DZ11TX, not yet available # OK 2016-06-05 +# --> [9] is for DZ11RX, unclear why this one isn't removed too !! +i [Synth 8-3332] SEQ/R_STATUS_reg[intvect][8] +# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2016-06-05 +i [Synth 8-3332] SEQ/R_IDSTAT_reg[res_sel][2] +# --> monitor outputs moneop,monattn currently not used # OK 2016-06-05 +i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop] +i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn] + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization diff --git a/rtl/sys_gen/w11a/arty_bram/tb/Makefile b/rtl/sys_gen/w11a/arty_bram/tb/Makefile index 3ac5026a..2ea45e67 100644 --- a/rtl/sys_gen/w11a/arty_bram/tb/Makefile +++ b/rtl/sys_gen/w11a/arty_bram/tb/Makefile @@ -1,30 +1,41 @@ -# $Id: Makefile 736 2016-02-27 12:33:40Z mueller $ +# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $ # # Revision History: # Date Rev Version Comment +# 2016-06-18 776 1.1.1 add xsim_clean +# 2016-04-22 763 1.1 add include dep_vsim # 2016-02-27 736 1.0 Initial version # EXE_all = tb_w11a_br_arty # include ${RETROBASE}/rtl/make_viv/viv_default_arty.mk # -.PHONY : all all_ssim clean +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim # all : $(EXE_all) all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) # -clean : viv_clean ghdl_clean +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean # #----- # -include ${RETROBASE}/rtl/make_viv/generic_vivado.mk include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # VBOM_all = $(wildcard *.vbom) # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_vsyn) include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) include $(wildcard *.o.dep_ghdl) endif # diff --git a/rtl/sys_gen/w11a/arty_bram/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/arty_bram/tb/sys_conf_sim.vhd index 8864e5e6..3d97223e 100644 --- a/rtl/sys_gen/w11a/arty_bram/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/arty_bram/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 742 2016-03-13 14:40:19Z mueller $ +-- $Id: sys_conf_sim.vhd 775 2016-06-18 13:42:00Z mueller $ -- -- Copyright 2016- by Walter F.J. Mueller -- @@ -16,9 +16,14 @@ -- Description: Definitions for sys_w11a_br_arty (for simulation) -- -- Dependencies: - --- Tool versions: viv 2015.4; ghdl 0.33 +-- Tool versions: viv 2015.4-2016.2; ghdl 0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-06-18 775 1.3.3 use PLL for clkser_gentype +-- 2016-05-28 770 1.3.2 sys_conf_mem_losize now type natural +-- 2016-05-26 768 1.3.1 set dmscnt=0 (vivado fsm issue) +-- 2016-03-28 755 1.3 use serport_2clock2 -> define clkser +-- 2016-03-22 750 1.2 add sys_conf_cache_twidth -- 2016-03-13 742 1.1 add sysmon_bus -- 2016-02-27 736 1.0 Initial version ------------------------------------------------------------------------------ @@ -32,14 +37,14 @@ package sys_conf is -- configure clocks -------------------------------------------------------- constant sys_conf_clksys_vcodivide : positive := 1; - constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz - constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz constant sys_conf_clksys_gentype : string := "MMCM"; - -- single clock design, clkser = clksys - constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; - constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; - constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; - constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim @@ -52,7 +57,7 @@ package sys_conf is -- configure debug and monitoring units ------------------------------------ constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs - constant sys_conf_dmscnt : boolean := true; + constant sys_conf_dmscnt : boolean := false; constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) @@ -60,9 +65,10 @@ package sys_conf is -- configure w11 cpu core -------------------------------------------------- -- sys_conf_mem_losize is highest 64 byte MMU block number -- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks - constant sys_conf_mem_losize : integer := 256*sys_conf_memctl_nblock-1; + constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1; constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + constant sys_conf_cache_twidth : integer := 9; -- 8kB cache -- configure w11 system devices -------------------------------------------- -- configure character and communication devices diff --git a/rtl/sys_gen/w11a/basys3/sys_conf.vhd b/rtl/sys_gen/w11a/basys3/sys_conf.vhd index 6296413d..6be3de0d 100644 --- a/rtl/sys_gen/w11a/basys3/sys_conf.vhd +++ b/rtl/sys_gen/w11a/basys3/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 742 2016-03-13 14:40:19Z mueller $ +-- $Id: sys_conf.vhd 775 2016-06-18 13:42:00Z mueller $ -- -- Copyright 2015-2016 by Walter F.J. Mueller -- @@ -16,9 +16,14 @@ -- Description: Definitions for sys_w11a_b3 (for synthesis) -- -- Dependencies: - --- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 +-- Tool versions: viv 2014.4-2016.2; ghdl 0.31-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-06-18 775 1.3.3 use PLL for clkser_gentype +-- 2016-05-28 770 1.3.2 sys_conf_mem_losize now type natural +-- 2016-05-26 768 1.3.1 set dmscnt=0 (vivado fsm issue) (@80 MHz) +-- 2016-03-28 755 1.3 use serport_2clock2 -> define clkser (@75 MHz) +-- 2016-03-22 750 1.2 add sys_conf_cache_twidth -- 2016-03-13 742 1.1.2 add sysmon_bus; use 72 MHz, no tc otherwise -- 2015-06-26 695 1.1.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) -- 2015-03-14 658 1.1 add sys_conf_ibd_* definitions @@ -33,15 +38,15 @@ use work.slvtypes.all; package sys_conf is -- configure clocks -------------------------------------------------------- - constant sys_conf_clksys_vcodivide : positive := 5; -- f 20 Mhz - constant sys_conf_clksys_vcomultiply : positive := 36; -- vco 720 MHz - constant sys_conf_clksys_outdivide : positive := 10; -- sys 72 MHz + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz constant sys_conf_clksys_gentype : string := "MMCM"; - -- single clock design, clkser = clksys - constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; - constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; - constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; - constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud @@ -54,7 +59,7 @@ package sys_conf is -- configure debug and monitoring units ------------------------------------ constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs - constant sys_conf_dmscnt : boolean := true; + constant sys_conf_dmscnt : boolean := false; constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) @@ -62,9 +67,10 @@ package sys_conf is -- configure w11 cpu core -------------------------------------------------- -- sys_conf_mem_losize is highest 64 byte MMU block number -- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks - constant sys_conf_mem_losize : integer := 256*sys_conf_memctl_nblock-1; + constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1; constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + constant sys_conf_cache_twidth : integer := 9; -- 8kB cache -- configure w11 system devices -------------------------------------------- -- configure character and communication devices diff --git a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom index 3cf758fc..44b6ed6d 100644 --- a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom +++ b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom @@ -4,6 +4,7 @@ ../../../vlib/genlib/genlib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd +../../../vlib/rbus/rbdlib.vhd ../../../vlib/rlink/rlinklib.vbom ../../../bplib/bpgen/bpgenlib.vbom ../../../bplib/bpgen/bpgenrbuslib.vbom @@ -17,7 +18,7 @@ sys_conf = sys_conf.vhd [ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2line_iob.vbom -../../../vlib/rlink/rlink_sp1c.vbom +../../../vlib/rlink/rlink_sp2c.vbom ../../../w11a/pdp11_sys70.vbom ../../../ibus/ibdr_maxisys.vbom ../../../w11a/pdp11_bram_memctl.vbom @@ -25,7 +26,8 @@ sys_conf = sys_conf.vhd ../../../w11a/pdp11_hio70.vbom ../../../bplib/bpgen/sn_humanio_rbus.vbom ../../../bplib/sysmon/sysmonx_rbus_base.vbom -../../../vlib/rbus/rb_sres_or_3.vbom +../../../vlib/rbus/rbd_usracc.vbom +../../../vlib/rbus/rb_sres_or_4.vbom # design sys_w11a_b3.vhd @xdc:../../../bplib/basys3/basys3_pclk.xdc diff --git a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd index 943fb983..60e87198 100644 --- a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd +++ b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_b3.vhd 745 2016-03-18 22:10:34Z mueller $ +-- $Id: sys_w11a_b3.vhd 768 2016-05-26 16:47:00Z mueller $ -- -- Copyright 2015-2016 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: vlib/xlib/s7_cmt_sfs -- vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_2line_iob --- vlib/rlink/rlink_sp1c +-- vlib/rlink/rlink_sp2c -- w11a/pdp11_sys70 -- ibus/ibdr_maxisys -- w11a/pdp11_bram_memctl @@ -26,15 +26,20 @@ -- w11a/pdp11_hio70 -- bplib/bpgen/sn_humanio_rbus -- bplib/sysmon/sysmonx_rbus_base --- vlib/rbus/rb_sres_or_3 +-- vlib/rbus/rbd_usracc +-- vlib/rbus/rb_sres_or_4 -- -- Test bench: tb/tb_sys_w11a_b3 -- -- Target Devices: generic --- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 +-- Tool versions: viv 2014.4-2016.1; ghdl 0.31-0.33 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic +-- 2016-05-26 768 2016.1 xc7a35t-1 2361 5203 138 47.5 1600 fsm+dsm=0 +-- 2016-05-22 767 2016.1 xc7a35t-1 2362 5340 138 48.5 1660 fsm +-- 2016-03-29 756 2015.4 xc7a35t-1 2240 4518 138 48.5 1430 serport2 +-- 2016-03-27 753 2015.4 xc7a35t-1 2131 4398 138 48.5 1362 meminf -- 2016-03-13 742 2015.4 xc7a35t-1 2135 4420 162 48.5 1396 +XADC -- 2015-06-04 686 2014.4 xc7a35t-1 1919 4372 162 47.5 1408 +TM11 17% -- 2015-05-14 680 2014.4 xc7a35t-1 1837 4304 162 47.5 1354 +RHRP 17% @@ -42,6 +47,9 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-04-02 758 2.3.1 add rbd_usracc (bitfile+jtag timestamp access) +-- 2016-03-28 755 2.3 use serport_2clock2 +-- 2016-03-19 748 2.2.2 define rlink SYSID -- 2016-03-18 745 2.2.1 hardwire XON=1 -- 2016-03-13 742 2.2 add sysmon_rbus -- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul @@ -104,6 +112,7 @@ use work.xlib.all; use work.genlib.all; use work.serportlib.all; use work.rblib.all; +use work.rbdlib.all; use work.rlinklib.all; use work.bpgenlib.all; use work.bpgenrbuslib.all; @@ -137,6 +146,9 @@ architecture syn of sys_w11a_b3 is signal CE_USEC : slbit := '0'; signal CE_MSEC : slbit := '0'; + signal CLKS : slbit := '0'; + signal CES_MSEC : slbit := '0'; + signal RXD : slbit := '1'; signal TXD : slbit := '0'; @@ -145,6 +157,7 @@ architecture syn of sys_w11a_b3 is signal RB_SRES_CPU : rb_sres_type := rb_sres_init; signal RB_SRES_HIO : rb_sres_type := rb_sres_init; signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; + signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); @@ -190,13 +203,17 @@ architecture syn of sys_w11a_b3 is constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx + constant sysid_proj : slv16 := x"0201"; -- w11a + constant sysid_board : slv8 := x"06"; -- basys3 + constant sysid_vers : slv8 := x"00"; + begin assert (sys_conf_clksys mod 1000000) = 0 report "assert sys_conf_clksys on MHz grid" severity failure; - GEN_CLKSYS : s7_cmt_sfs -- clock generator ------------------- + GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ generic map ( VCO_DIVIDE => sys_conf_clksys_vcodivide, VCO_MULTIPLY => sys_conf_clksys_vcomultiply, @@ -211,7 +228,7 @@ begin LOCKED => open ); - CLKDIV : clkdivce -- usec/msec clock divider ----------- + CLKDIV_CLK : clkdivce -- usec/msec clock divider system ---- generic map ( CDUWIDTH => 7, USECDIV => sys_conf_clksys_mhz, @@ -222,25 +239,51 @@ begin CE_MSEC => CE_MSEC ); + GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------ + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clkser_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLKS, + LOCKED => open + ); + + CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport --- + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clkser_mhz, + MSECDIV => 1000) + port map ( + CLK => CLKS, + CE_USEC => open, + CE_MSEC => CES_MSEC + ); + IOB_RS232 : bp_rs232_2line_iob -- serport iob ---------------------- port map ( - CLK => CLK, + CLK => CLKS, RXD => RXD, TXD => TXD, I_RXD => I_RXD, O_TXD => O_TXD ); - RLINK : rlink_sp1c -- rlink for serport ----------------- + RLINK : rlink_sp2c -- rlink for serport ----------------- generic map ( BTOWIDTH => 7, -- 128 cycles access timeout RTAWIDTH => 12, - SYSID => (others=>'0'), + SYSID => sysid_proj & sysid_board & sysid_vers, IFAWIDTH => 5, -- 32 word input fifo OFAWIDTH => 5, -- 32 word output fifo ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, - CDWIDTH => 13, + CDWIDTH => 12, CDINIT => sys_conf_ser2rri_cdinit, RBMON_AWIDTH => sys_conf_rbmon_awidth, RBMON_RBADDR => rbaddr_rbmon) @@ -250,6 +293,8 @@ begin CE_MSEC => CE_MSEC, CE_INT => CE_MSEC, RESET => RESET, + CLKS => CLKS, + CES_MSEC => CES_MSEC, ENAXON => '1', ESCFILL => '0', RXSD => RXD, @@ -399,11 +444,19 @@ begin ); end generate SMRB; - RB_SRES_OR : rb_sres_or_3 -- rbus or --------------------------- + UARB : rbd_usracc + port map ( + CLK => CLK, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_USRACC + ); + + RB_SRES_OR : rb_sres_or_4 -- rbus or --------------------------- port map ( RB_SRES_1 => RB_SRES_CPU, RB_SRES_2 => RB_SRES_HIO, RB_SRES_3 => RB_SRES_SYSMON, + RB_SRES_4 => RB_SRES_USRACC, RB_SRES_OR => RB_SRES ); diff --git a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset new file mode 100644 index 00000000..80d81188 --- /dev/null +++ b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset @@ -0,0 +1,46 @@ +# $Id: sys_w11a_b3.vmfset 773 2016-06-05 20:03:15Z mueller $ +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# false_path -hold ignored by synth ---------------------------- +I [Designutils 20-1567] # generic + +# net without driver ------------------------------------------- +# --> snum currently disabled # OK 2016-06-04 +i [Synth 8-3848] DM_STAT_SE[snum].*pdp11_sequencer + +# unconnected ports -------------------------------------------- +I [Synth 8-3331] RB_MREQ # generic +I [Synth 8-3331] DM_STAT_DP # generic + +# unused sequential element ------------------------------------ +I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic +I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*] # generic +# --> usec not used for serport clock domain # OK 2016-06-04 +i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec] +# --> inst_compl logic disabled in pdp11_mmu # OK 2016-06-04 +i [Synth 8-3332] VMBOX/MMU/R_SSR0_reg[inst_compl] +# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2016-06-05 +i [Synth 8-3332] VMBOX/R_REGS_reg[ibcacc] +# --> not yet used # OK 2016-06-04 +i [Synth 8-3332] SEQ/R_STATUS_reg[suspext] +# --> mawidth=4, nblock=11, so some cellen unused # OK 2016-06-05 +i [Synth 8-3332] BRAM_CTL/R_REGS_reg[cellen][1\d] +# --> indeed no types with [3] set # OK 2016-06-04 +i [Synth 8-3332] R_REGS_reg[dtyp][3].*ibdr_rhrp +# --> not yet used # OK 2016-06-04 +i [Synth 8-3332] R_REGS_reg[req_lock].*ibd_iist +i [Synth 8-3332] R_REGS_reg[req_boot].*ibd_iist +# --> [8] is for DZ11TX, not yet available # OK 2016-06-04 +# --> [9] is for DZ11RX, unclear why this one isn't removed too !! +i [Synth 8-3332] SEQ/R_STATUS_reg[intvect][8] +# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2016-06-04 +i [Synth 8-3332] SEQ/R_IDSTAT_reg[res_sel][2] +# --> monitor outputs moneop,monattn currently not used # OK 2016-06-04 +i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop] +i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn] + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization diff --git a/rtl/sys_gen/w11a/basys3/tb/Makefile b/rtl/sys_gen/w11a/basys3/tb/Makefile index 4305605a..62ae8be0 100644 --- a/rtl/sys_gen/w11a/basys3/tb/Makefile +++ b/rtl/sys_gen/w11a/basys3/tb/Makefile @@ -1,30 +1,41 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $ # # Revision History: # Date Rev Version Comment +# 2016-06-18 776 1.1.1 add xsim_clean +# 2016-04-22 763 1.1 add include dep_vsim # 2015-02-21 649 1.0 Initial version # EXE_all = tb_w11a_b3 # include ${RETROBASE}/rtl/make_viv/viv_default_basys3.mk # -.PHONY : all all_ssim clean +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim # all : $(EXE_all) all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) # -clean : viv_clean ghdl_clean +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean # #----- # -include ${RETROBASE}/rtl/make_viv/generic_vivado.mk include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # VBOM_all = $(wildcard *.vbom) # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_vsyn) include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) include $(wildcard *.o.dep_ghdl) endif # diff --git a/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd index 6c07b756..6defde66 100644 --- a/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 742 2016-03-13 14:40:19Z mueller $ +-- $Id: sys_conf_sim.vhd 775 2016-06-18 13:42:00Z mueller $ -- -- Copyright 2015-2016 by Walter F.J. Mueller -- @@ -16,9 +16,14 @@ -- Description: Definitions for sys_w11a_b3 (for simulation) -- -- Dependencies: - --- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 +-- Tool versions: viv 2014.4-2016.2; ghdl 0.31-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-06-18 775 1.3.3 use PLL for clkser_gentype +-- 2016-05-28 770 1.3.2 sys_conf_mem_losize now type natural +-- 2016-05-26 768 1.3.1 set dmscnt=0 (vivado fsm issue) +-- 2016-03-28 755 1.3 use serport_2clock2 -> define clkser +-- 2016-03-22 750 1.2 add sys_conf_cache_twidth -- 2016-03-13 742 1.1.2 add sysmon_bus (but disabled like for fpga) -- 2015-06-26 695 1.1.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) -- 2015-03-14 658 1.1 add sys_conf_ibd_* definitions @@ -34,14 +39,14 @@ package sys_conf is -- configure clocks -------------------------------------------------------- constant sys_conf_clksys_vcodivide : positive := 1; - constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz - constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz constant sys_conf_clksys_gentype : string := "MMCM"; - -- single clock design, clkser = clksys - constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; - constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; - constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; - constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim @@ -54,7 +59,7 @@ package sys_conf is -- configure debug and monitoring units ------------------------------------ constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs - constant sys_conf_dmscnt : boolean := true; + constant sys_conf_dmscnt : boolean := false; constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs constant sys_conf_rbd_sysmon : boolean := false; -- SYSMON(XADC) @@ -62,9 +67,10 @@ package sys_conf is -- configure w11 cpu core -------------------------------------------------- -- sys_conf_mem_losize is highest 64 byte MMU block number -- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks - constant sys_conf_mem_losize : integer := 256*sys_conf_memctl_nblock-1; + constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1; constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + constant sys_conf_cache_twidth : integer := 9; -- 8kB cache -- configure w11 system devices -------------------------------------------- -- configure character and communication devices diff --git a/rtl/sys_gen/w11a/nexys2/sys_conf.vhd b/rtl/sys_gen/w11a/nexys2/sys_conf.vhd index b24b11fe..768a9aab 100644 --- a/rtl/sys_gen/w11a/nexys2/sys_conf.vhd +++ b/rtl/sys_gen/w11a/nexys2/sys_conf.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf.vhd 698 2015-07-05 21:20:18Z mueller $ +-- $Id: sys_conf.vhd 770 2016-05-28 14:15:00Z mueller $ -- --- Copyright 2010-2015 by Walter F.J. Mueller +-- Copyright 2010-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,11 @@ -- Description: Definitions for sys_w11a_n2 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-05-28 770 1.5.1 sys_conf_mem_losize now type natural +-- 2016-03-22 750 1.5 add sys_conf_cache_twidth -- 2015-06-26 695 1.4.2 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) -- 2015-06-21 692 1.4.1 use clksys=52 (no closure after rhrp fixes) -- 2015-03-14 658 1.4 add sys_conf_ibd_* definitions @@ -69,9 +71,10 @@ package sys_conf is constant sys_conf_memctl_writedelay : positive := 4; -- configure w11 cpu core -------------------------------------------------- - constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte + constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + constant sys_conf_cache_twidth : integer := 9; -- 8kB cache -- configure w11 system devices -------------------------------------------- -- configure character and communication devices diff --git a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.mfset b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.imfset similarity index 98% rename from rtl/sys_gen/w11a/nexys2/sys_w11a_n2.mfset rename to rtl/sys_gen/w11a/nexys2/sys_w11a_n2.imfset index 382591d5..6ad00946 100644 --- a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.mfset +++ b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.imfset @@ -1,4 +1,4 @@ -# $Id: sys_w11a_n2.mfset 427 2011-11-19 21:04:11Z mueller $ +# $Id: sys_w11a_n2.imfset 779 2016-06-26 15:37:16Z mueller $ # # ---------------------------------------------------------------------------- [xst] @@ -145,4 +145,4 @@ There are 1 loadless signals in this design Spartan-3 1200E and 1600E devices do not support bitstream The signal is incomplete There is a dangling output parity pin -INFO:.*To achieve optimal frequency synthesis performance \ No newline at end of file +INFO:.*To achieve optimal frequency synthesis performance diff --git a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd index 084665fe..ee731bd6 100644 --- a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd +++ b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd @@ -1,6 +1,6 @@ --- $Id: sys_w11a_n2.vhd 734 2016-02-20 22:43:20Z mueller $ +-- $Id: sys_w11a_n2.vhd 748 2016-03-20 15:18:50Z mueller $ -- --- Copyright 2010-2015 by Walter F.J. Mueller +-- Copyright 2010-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -30,7 +30,7 @@ -- Test bench: tb/tb_sys_w11a_n2 -- -- Target Devices: generic --- Tool versions: xst 8.2-14.7; ghdl 0.26-0.31 +-- Tool versions: xst 8.2-14.7; ghdl 0.26-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -67,6 +67,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-03-19 748 2.1.1 define rlink SYSID -- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul -- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 -- 2015-04-11 666 1.7.2 rearrange XON handling @@ -279,6 +280,10 @@ architecture syn of sys_w11a_n2 is constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx + constant sysid_proj : slv16 := x"0201"; -- w11a + constant sysid_board : slv8 := x"02"; -- nexys2 + constant sysid_vers : slv8 := x"00"; + begin assert (sys_conf_clksys mod 1000000) = 0 @@ -328,7 +333,7 @@ begin generic map ( BTOWIDTH => 7, -- 128 cycles access timeout RTAWIDTH => 12, - SYSID => (others=>'0'), + SYSID => sysid_proj & sysid_board & sysid_vers, IFAWIDTH => 5, -- 32 word input fifo OFAWIDTH => 5, -- 32 word output fifo PETOWIDTH => sys_conf_fx2_petowidth, diff --git a/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd index 91ffe71d..bf70318d 100644 --- a/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf_sim.vhd 698 2015-07-05 21:20:18Z mueller $ +-- $Id: sys_conf_sim.vhd 770 2016-05-28 14:15:00Z mueller $ -- --- Copyright 2010-2015 by Walter F.J. Mueller +-- Copyright 2010-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,11 @@ -- Description: Definitions for sys_w11a_n2 (for simulation) -- -- Dependencies: - --- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-05-28 770 1.5.1 sys_conf_mem_losize now type natural +-- 2016-03-22 750 1.5 add sys_conf_cache_twidth -- 2015-06-26 695 1.4.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) -- 2015-03-14 658 1.4 add sys_conf_ibd_* definitions -- 2015-02-07 643 1.3 drop bram and minisys options @@ -63,9 +65,10 @@ package sys_conf is constant sys_conf_dmcmon_awidth : integer := 9; -- use 0 to disable -- configure w11 cpu core -------------------------------------------------- - constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte + constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + constant sys_conf_cache_twidth : integer := 9; -- 8kB cache -- configure w11 system devices -------------------------------------------- -- configure character and communication devices diff --git a/rtl/sys_gen/w11a/nexys3/sys_conf.vhd b/rtl/sys_gen/w11a/nexys3/sys_conf.vhd index 521f4af4..897dce32 100644 --- a/rtl/sys_gen/w11a/nexys3/sys_conf.vhd +++ b/rtl/sys_gen/w11a/nexys3/sys_conf.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf.vhd 698 2015-07-05 21:20:18Z mueller $ +-- $Id: sys_conf.vhd 770 2016-05-28 14:15:00Z mueller $ -- --- Copyright 2011-2015 by Walter F.J. Mueller +-- Copyright 2011-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,11 @@ -- Description: Definitions for sys_w11a_n3 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-05-28 770 1.5.1 sys_conf_mem_losize now type natural +-- 2016-03-22 750 1.5 add sys_conf_cache_twidth -- 2015-06-26 695 1.4.2 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) -- 2015-06-21 692 1.4.1 use clksys=64 (no closure after rhrp fixes) -- 2015-03-14 658 1.4 add sys_conf_ibd_* definitions @@ -75,9 +77,10 @@ package sys_conf is constant sys_conf_dmcmon_awidth : integer := 9; -- use 0 to disable -- configure w11 cpu core -------------------------------------------------- - constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte + constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + constant sys_conf_cache_twidth : integer := 9; -- 8kB cache -- configure w11 system devices -------------------------------------------- -- configure character and communication devices diff --git a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.mfset b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.imfset similarity index 66% rename from rtl/sys_gen/w11a/nexys3/sys_w11a_n3.mfset rename to rtl/sys_gen/w11a/nexys3/sys_w11a_n3.imfset index e2ec9916..31e2f024 100644 --- a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.mfset +++ b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.imfset @@ -1,14 +1,24 @@ -# $Id: sys_w11a_n3.mfset 440 2011-12-18 20:08:09Z mueller $ +# $Id: sys_w11a_n3.imfset 776 2016-06-18 17:22:51Z mueller $ # # ---------------------------------------------------------------------------- [xst] INFO:.*Case statement is complete. others clause is never selected INFO:.*The small RAM <.*> will be implemented on LUTs -sys_w11a_n3\..*Output port of the instance is unconnected -sys_w11a_n3\..*Output port of the instance is unconnected -sys_w11a_n3\..*Output port of the instance is unconnected -sys_w11a_n3\..*Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +# +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +# +INFO:.*Instance.*has been replaced by RAMB16BWER # # ---------------------------------------------------------------------------- [tra] diff --git a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd index 03e8f5b0..75eb13a4 100644 --- a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd +++ b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd @@ -1,6 +1,6 @@ --- $Id: sys_w11a_n3.vhd 734 2016-02-20 22:43:20Z mueller $ +-- $Id: sys_w11a_n3.vhd 748 2016-03-20 15:18:50Z mueller $ -- --- Copyright 2011-2015 by Walter F.J. Mueller +-- Copyright 2011-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -30,7 +30,7 @@ -- Test bench: tb/tb_sys_w11a_n3 -- -- Target Devices: generic --- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -52,6 +52,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-03-19 748 2.1.1 define rlink SYSID -- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul -- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 -- 2015-04-24 668 1.8.3 added ibd_ibmon @@ -247,6 +248,10 @@ architecture syn of sys_w11a_n3 is constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx + constant sysid_proj : slv16 := x"0201"; -- w11a + constant sysid_board : slv8 := x"03"; -- nexys3 + constant sysid_vers : slv8 := x"00"; + begin assert (sys_conf_clksys mod 1000000) = 0 diff --git a/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd index f808e35a..82a349e0 100644 --- a/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf_sim.vhd 718 2015-12-26 15:59:48Z mueller $ +-- $Id: sys_conf_sim.vhd 770 2016-05-28 14:15:00Z mueller $ -- --- Copyright 2011-2015 by Walter F.J. Mueller +-- Copyright 2011-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,11 @@ -- Description: Definitions for sys_w11a_n3 (for simulation) -- -- Dependencies: - --- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-05-28 770 1.6.1 sys_conf_mem_losize now type natural +-- 2016-03-22 750 1.6 add sys_conf_cache_twidth -- 2015-12-26 718 1.5.2 use clksys=64 (as since r692 in sys_conf.vhd) -- 2015-06-26 695 1.5.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) -- 2015-03-14 658 1.5 add sys_conf_ibd_* definitions @@ -63,9 +65,10 @@ package sys_conf is constant sys_conf_dmcmon_awidth : integer := 9; -- use 0 to disable -- configure w11 cpu core -------------------------------------------------- - constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte + constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + constant sys_conf_cache_twidth : integer := 9; -- 8kB cache -- configure w11 system devices -------------------------------------------- -- configure character and communication devices diff --git a/rtl/sys_gen/w11a/nexys4/sys_conf.vhd b/rtl/sys_gen/w11a/nexys4/sys_conf.vhd index f835e5f8..79b28c1a 100644 --- a/rtl/sys_gen/w11a/nexys4/sys_conf.vhd +++ b/rtl/sys_gen/w11a/nexys4/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 742 2016-03-13 14:40:19Z mueller $ +-- $Id: sys_conf.vhd 775 2016-06-18 13:42:00Z mueller $ -- -- Copyright 2013-2016 by Walter F.J. Mueller -- @@ -16,9 +16,16 @@ -- Description: Definitions for sys_w11a_n4 (for synthesis) -- -- Dependencies: - --- Tool versions: ise 14.5-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 +-- Tool versions: ise 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-06-18 775 1.4.5 use PLL for clkser_gentype +-- 2016-06-04 772 1.4.4 go for 80 MHz and 64 kB cache, best compromise +-- 2016-05-28 771 1.4.3 set dmcmon_awidth=0, useless without dmscnt +-- 2016-05-28 770 1.4.2 sys_conf_mem_losize now type natural +-- 2016-05-26 768 1.4.1 set dmscnt=0 (vivado fsm issue); TW=8 (@90 MHz) +-- 2016-03-28 755 1.4 use serport_2clock2 -> define clkser (@75 MHz) +-- 2016-03-22 750 1.3 add sys_conf_cache_twidth, use TW=8 (16 kByte) -- 2016-03-13 742 1.2.2 add sysmon_bus -- 2015-06-26 695 1.2.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) -- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions @@ -47,11 +54,11 @@ package sys_conf is constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz constant sys_conf_clksys_gentype : string := "MMCM"; - -- single clock design, clkser = clksys - constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; - constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; - constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; - constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud @@ -65,16 +72,17 @@ package sys_conf is -- configure debug and monitoring units ------------------------------------ constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable - constant sys_conf_dmscnt : boolean := true; + constant sys_conf_dmscnt : boolean := false; constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable - constant sys_conf_dmcmon_awidth : integer := 9; -- use 0 to disable + constant sys_conf_dmcmon_awidth : integer := 0; -- use 0 to disable, 9 to use constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) -- configure w11 cpu core -------------------------------------------------- - constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte + constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled - + constant sys_conf_cache_twidth : integer := 6; -- 64kB cache + -- configure w11 system devices -------------------------------------------- -- configure character and communication devices constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 diff --git a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom index 187b650c..1bf3387c 100644 --- a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom +++ b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom @@ -4,6 +4,7 @@ ../../../vlib/genlib/genlib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd +../../../vlib/rbus/rbdlib.vhd ../../../vlib/rlink/rlinklib.vbom ../../../bplib/bpgen/bpgenlib.vbom ../../../bplib/bpgen/bpgenrbuslib.vbom @@ -18,7 +19,7 @@ sys_conf = sys_conf.vhd [ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_4line_iob.vbom -../../../vlib/rlink/rlink_sp1c.vbom +../../../vlib/rlink/rlink_sp2c.vbom ../../../w11a/pdp11_sys70.vbom ../../../ibus/ibdr_maxisys.vbom ../../../bplib/nxcramlib/nx_cram_memctl_as.vbom @@ -26,7 +27,8 @@ sys_conf = sys_conf.vhd ../../../w11a/pdp11_hio70.vbom ../../../bplib/bpgen/sn_humanio_rbus.vbom ../../../bplib/sysmon/sysmonx_rbus_base.vbom -../../../vlib/rbus/rb_sres_or_3.vbom +../../../vlib/rbus/rbd_usracc.vbom +../../../vlib/rbus/rb_sres_or_4.vbom # design sys_w11a_n4.vhd # constraints @@ -34,3 +36,4 @@ sys_w11a_n4.vhd @xdc:../../../bplib/nexys4/nexys4_pclk.xdc @xdc:../../../bplib/nexys4/nexys4_pins.xdc @xdc:../../../bplib/nexys4/nexys4_pins_cram.xdc +#@xdc:sys_w11a_n4.xdc diff --git a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd index 47ea0024..bc5dc8b0 100644 --- a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd +++ b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_n4.vhd 742 2016-03-13 14:40:19Z mueller $ +-- $Id: sys_w11a_n4.vhd 768 2016-05-26 16:47:00Z mueller $ -- -- Copyright 2013-2016 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: vlib/xlib/s7_cmt_sfs -- vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_4line_iob --- vlib/rlink/rlink_sp1c +-- vlib/rlink/rlink_sp2c -- w11a/pdp11_sys70 -- ibus/ibdr_maxisys -- bplib/nxcramlib/nx_cram_memctl_as @@ -26,25 +26,34 @@ -- w11a/pdp11_hio70 -- bplib/bpgen/sn_humanio_rbus -- bplib/sysmon/sysmonx_rbus_base --- vlib/rbus/rb_sres_or_3 +-- vlib/rbus/rbd_usracc +-- vlib/rbus/rb_sres_or_4 -- -- Test bench: tb/tb_sys_w11a_n4 -- -- Target Devices: generic --- Tool versions: ise 14.5-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 +-- Tool versions: ise 14.5-14.7; viv 2014.4-2016.1; ghdl 0.29-0.33 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic MHz +-- 2016-05-26 768 2016.1 xc7a100t-1 2777 5672 150 10.0 1763 90 dms=0 +-- 2016-05-22 767 2016.1 xc7a100t-1 2790 5774 150 11.0 1812 75 fsm +-- 2016-03-29 756 2015.4 xc7a100t-1 2651 4955 150 11.0 1608 75 2clock +-- 2016-03-27 753 2015.4 xc7a100t-1 2545 4850 150 11.0 1576 80 meminf +-- 2016-03-27 752 2015.4 xc7a100t-1 2544 4875 178 13.0 1569 80 +TW=8 -- 2016-03-13 742 2015.4 xc7a100t-1 2536 4868 178 10.5 1542 80 +XADC -- 2015-06-04 686 2014.4 xc7a100t-1 2111 4541 162 7.5 1469 80 +TM11 -- 2015-05-14 680 2014.4 xc7a100t-1 2030 4459 162 7.5 1427 80 -- 2015-02-22 650 2014.4 xc7a100t-1 1606 3652 146 3.5 1158 80 --- 2015-02-22 650 i 17.7 xc7a100t-1 1670 3564 124 1508 80 +-- 2015-02-22 650 i 14.7 xc7a100t-1 1670 3564 124 1508 80 -- -- Revision History: -- Date Rev Version Comment +-- 2016-04-02 758 2.3.1 add rbd_usracc (bitfile+jtag timestamp access) +-- 2016-03-28 755 2.3 use serport_2clock2 +-- 2016-03-19 748 2.2.1 define rlink SYSID -- 2016-03-13 742 2.2 add sysmon_rbus --- 2015-05-09 677 2.1 start/stop/suspend overhaul; ; reset overhaul +-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul -- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 -- 2015-04-11 666 1.4.2 rearrange XON handling -- 2015-02-21 649 1.4.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) @@ -113,6 +122,7 @@ use work.xlib.all; use work.genlib.all; use work.serportlib.all; use work.rblib.all; +use work.rbdlib.all; use work.rlinklib.all; use work.bpgenlib.all; use work.bpgenrbuslib.all; @@ -162,6 +172,9 @@ architecture syn of sys_w11a_n4 is signal CE_USEC : slbit := '0'; signal CE_MSEC : slbit := '0'; + signal CLKS : slbit := '0'; + signal CES_MSEC : slbit := '0'; + signal RXD : slbit := '1'; signal TXD : slbit := '0'; signal RTS_N : slbit := '0'; @@ -172,6 +185,7 @@ architecture syn of sys_w11a_n4 is signal RB_SRES_CPU : rb_sres_type := rb_sres_init; signal RB_SRES_HIO : rb_sres_type := rb_sres_init; signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; + signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); @@ -220,13 +234,17 @@ architecture syn of sys_w11a_n4 is constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx + constant sysid_proj : slv16 := x"0201"; -- w11a + constant sysid_board : slv8 := x"05"; -- nexys4 + constant sysid_vers : slv8 := x"00"; + begin assert (sys_conf_clksys mod 1000000) = 0 report "assert sys_conf_clksys on MHz grid" severity failure; - GEN_CLKSYS : s7_cmt_sfs -- clock generator ------------------- + GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ generic map ( VCO_DIVIDE => sys_conf_clksys_vcodivide, VCO_MULTIPLY => sys_conf_clksys_vcomultiply, @@ -241,7 +259,7 @@ begin LOCKED => open ); - CLKDIV : clkdivce -- usec/msec clock divider ----------- + CLKDIV_CLK : clkdivce -- usec/msec clock divider system ---- generic map ( CDUWIDTH => 7, USECDIV => sys_conf_clksys_mhz, @@ -252,9 +270,35 @@ begin CE_MSEC => CE_MSEC ); + GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------ + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clkser_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLKS, + LOCKED => open + ); + + CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport --- + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clkser_mhz, + MSECDIV => 1000) + port map ( + CLK => CLKS, + CE_USEC => open, + CE_MSEC => CES_MSEC + ); + IOB_RS232 : bp_rs232_4line_iob -- serport iob ---------------------- port map ( - CLK => CLK, + CLK => CLKS, RXD => RXD, TXD => TXD, CTS_N => CTS_N, @@ -265,16 +309,16 @@ begin O_RTS_N => O_RTS_N ); - RLINK : rlink_sp1c -- rlink for serport ----------------- + RLINK : rlink_sp2c -- rlink for serport ----------------- generic map ( BTOWIDTH => 7, -- 128 cycles access timeout RTAWIDTH => 12, - SYSID => (others=>'0'), + SYSID => sysid_proj & sysid_board & sysid_vers, IFAWIDTH => 5, -- 32 word input fifo OFAWIDTH => 5, -- 32 word output fifo ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, - CDWIDTH => 13, + CDWIDTH => 12, CDINIT => sys_conf_ser2rri_cdinit, RBMON_AWIDTH => sys_conf_rbmon_awidth, RBMON_RBADDR => rbaddr_rbmon) @@ -284,6 +328,8 @@ begin CE_MSEC => CE_MSEC, CE_INT => CE_MSEC, RESET => RESET, + CLKS => CLKS, + CES_MSEC => CES_MSEC, ENAXON => SWI(1), ESCFILL => '0', RXSD => RXD, @@ -445,11 +491,19 @@ begin ); end generate SMRB; - RB_SRES_OR : rb_sres_or_3 -- rbus or --------------------------- + UARB : rbd_usracc + port map ( + CLK => CLK, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_USRACC + ); + + RB_SRES_OR : rb_sres_or_4 -- rbus or --------------------------- port map ( RB_SRES_1 => RB_SRES_CPU, RB_SRES_2 => RB_SRES_HIO, RB_SRES_3 => RB_SRES_SYSMON, + RB_SRES_4 => RB_SRES_USRACC, RB_SRES_OR => RB_SRES ); diff --git a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vmfset b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vmfset new file mode 100644 index 00000000..8696945c --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vmfset @@ -0,0 +1,64 @@ +# $Id: sys_w11a_n4.vmfset 774 2016-06-12 17:08:47Z mueller $ +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# false_path -hold ignored by synth ---------------------------- +I [Designutils 20-1567] + +# net without driver ------------------------------------------- +# --> snum currently disabled # OK 2016-05-28 +i [Synth 8-3848] DM_STAT_SE[snum].*pdp11_sequencer + +# port driven by constant -------------------------------------- +# --> RGBLED0 currently unused # OK 2016-05-28 +i [Synth 8-3917] O_RGBLED0[\d] + +# unconnected ports -------------------------------------------- +I [Synth 8-3331] RB_MREQ # generic +I [Synth 8-3331] DM_STAT_DP # generic + +# unused sequential element ------------------------------------ +I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic +I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*] # generic +# --> only 4 MB out of 16 MB used # OK 2016-05-28 +i [Synth 8-3332] IOB_MEM_ADDRH/R_DO_reg[20] +i [Synth 8-3332] IOB_MEM_ADDRH/R_DO_reg[21] +# --> usec not used for serport clock domain # OK 2016-05-28 +i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec] +# --> inst_compl logic disabled in pdp11_mmu # OK 2016-05-28 +i [Synth 8-3332] VMBOX/MMU/R_SSR0_reg[inst_compl] +# --> not yet used # OK 2016-05-28 +i [Synth 8-3332] SEQ/R_STATUS_reg[suspext] +# --> indeed no types with [3] set # OK 2016-05-28 +i [Synth 8-3332] R_REGS_reg[dtyp][3].*ibdr_rhrp +# --> not yet used # OK 2016-05-28 +i [Synth 8-3332] R_REGS_reg[req_lock].*ibd_iist +i [Synth 8-3332] R_REGS_reg[req_boot].*ibd_iist +# --> [8] is for DZ11TX, not yet available # OK 2016-05-28 +# --> [9] is for DZ11RX, unclear why this one isn't removed too !! +i [Synth 8-3332] SEQ/R_STATUS_reg[intvect][8] +# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2016-05-28 +i [Synth 8-3332] SEQ/R_IDSTAT_reg[res_sel][2] +# --> monitor outputs moneop,monattn currently not used # OK 2016-05-28 +i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop] +i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn] + +# INFO: encoded FSM with state register as -------------------- +# test for sys_w11a_n4 that all FSMs are one_hot +r [Synth 8-3354] R_BREGS_reg[state.*'one-hot'.*'rlink_core' +r [Synth 8-3354] R_LREGS_reg[state].*'one-hot'.*'rlink_core' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_autobaud' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_rx' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_core_rbus' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_vmbox' +r [Synth 8-3354] R_STATE_reg.*'one-hot'.*'pdp11_sequencer' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_cache' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rhrp' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rl11' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'nx_cram_memctl_as' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'sysmon_rbus_core' + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization diff --git a/rtl/sys_gen/w11a/nexys4/tb/Makefile b/rtl/sys_gen/w11a/nexys4/tb/Makefile index c24486bf..ba13f2d8 100644 --- a/rtl/sys_gen/w11a/nexys4/tb/Makefile +++ b/rtl/sys_gen/w11a/nexys4/tb/Makefile @@ -1,7 +1,9 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $ # # Revision History: # Date Rev Version Comment +# 2016-06-18 776 1.1.1 add xsim_clean +# 2016-04-22 763 1.1 add include dep_vsim # 2016-02-07 729 1.0.1 add generic_xsim.mk # 2015-02-14 646 1.0 Initial version # 2015-02-01 640 0.1 First draft @@ -10,7 +12,8 @@ EXE_all = tb_w11a_n4 # include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk # -.PHONY : all all_ssim clean +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim # all : $(EXE_all) all_ssim : $(EXE_all:=_ssim) @@ -21,19 +24,20 @@ all_XSim_ssim : $(EXE_all:=_XSim_ssim) all_XSim_osim : $(EXE_all:=_XSim_osim) all_XSim_tsim : $(EXE_all:=_XSim_tsim) # -clean : viv_clean ghdl_clean +clean : viv_clean ghdl_clean xsim_clean # #----- # -include ${RETROBASE}/rtl/make_viv/generic_vivado.mk include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk # VBOM_all = $(wildcard *.vbom) # ifndef DONTINCDEP include $(VBOM_all:.vbom=.dep_vsyn) include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) include $(wildcard *.o.dep_ghdl) endif # diff --git a/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd index b79b0a07..7b95b8f1 100644 --- a/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 742 2016-03-13 14:40:19Z mueller $ +-- $Id: sys_conf_sim.vhd 775 2016-06-18 13:42:00Z mueller $ -- -- Copyright 2013-2016 by Walter F.J. Mueller -- @@ -16,9 +16,16 @@ -- Description: Definitions for sys_w11a_n4 (for simulation) -- -- Dependencies: - --- Tool versions: xst 14.5-14.7; ghdl 0.29-0.33 +-- Tool versions: xst 14.5-14.7; viv 2016.1-2016.2; ghdl 0.29-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-06-18 775 1.4.5 use PLL for clkser_gentype +-- 2016-06-04 772 1.4.4 go for 80 MHz and 64 kB cache, best compromise +-- 2016-05-28 771 1.4.3 set dmcmon_awidth=0, useless without dmscnt +-- 2016-05-28 770 1.4.2 sys_conf_mem_losize now type natural +-- 2016-05-26 768 1.4.1 set dmscnt=0 (vivado fsm issue); TW=8 (@90 MHz) +-- 2016-03-28 755 1.4 use serport_2clock2 -> define clkser +-- 2016-03-22 750 1.3 add sys_conf_cache_twidth -- 2016-03-13 742 1.2.2 add sysmon_bus -- 2015-06-26 695 1.2.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) -- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions @@ -38,11 +45,11 @@ package sys_conf is constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz constant sys_conf_clksys_gentype : string := "MMCM"; - -- single clock design, clkser = clksys - constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; - constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; - constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; - constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim @@ -56,15 +63,16 @@ package sys_conf is -- configure debug and monitoring units ------------------------------------ constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable - constant sys_conf_dmscnt : boolean := true; + constant sys_conf_dmscnt : boolean := false; constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable - constant sys_conf_dmcmon_awidth : integer := 9; -- use 0 to disable + constant sys_conf_dmcmon_awidth : integer := 0; -- use 0 to disable, 9 to use constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) -- configure w11 cpu core -------------------------------------------------- - constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte + constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + constant sys_conf_cache_twidth : integer := 6; -- 64kB cache -- configure w11 system devices -------------------------------------------- -- configure character and communication devices diff --git a/rtl/sys_gen/w11a/s3board/sys_conf.vhd b/rtl/sys_gen/w11a/s3board/sys_conf.vhd index 11c7695f..2ae423db 100644 --- a/rtl/sys_gen/w11a/s3board/sys_conf.vhd +++ b/rtl/sys_gen/w11a/s3board/sys_conf.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf.vhd 698 2015-07-05 21:20:18Z mueller $ +-- $Id: sys_conf.vhd 770 2016-05-28 14:15:00Z mueller $ -- --- Copyright 2007-2015 by Walter F.J. Mueller +-- Copyright 2007-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,11 @@ -- Description: Definitions for sys_w11a_s3 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-05-27 770 1.3.1 sys_conf_mem_losize now type natural +-- 2016-03-22 750 1.3 add sys_conf_cache_twidth -- 2015-06-26 695 1.2.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) -- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions -- 2014-12-22 619 1.1.2 add _rbmon_awidth @@ -46,9 +48,10 @@ package sys_conf is constant sys_conf_dmcmon_awidth : integer := 9; -- use 0 to disable -- configure w11 cpu core -------------------------------------------------- - constant sys_conf_mem_losize : integer := 8#037777#; -- 1 MByte + constant sys_conf_mem_losize : natural := 8#037777#; -- 1 MByte constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + constant sys_conf_cache_twidth : integer := 9; -- 8kB cache -- configure w11 system devices -------------------------------------------- -- configure character and communication devices diff --git a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.mfset b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.imfset similarity index 98% rename from rtl/sys_gen/w11a/s3board/sys_w11a_s3.mfset rename to rtl/sys_gen/w11a/s3board/sys_w11a_s3.imfset index d1b4cbed..99e44529 100644 --- a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.mfset +++ b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.imfset @@ -1,4 +1,4 @@ -# $Id: sys_w11a_s3.mfset 442 2011-12-23 10:03:28Z mueller $ +# $Id: sys_w11a_s3.imfset 769 2016-05-28 11:36:22Z mueller $ # # ---------------------------------------------------------------------------- [xst] diff --git a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd index 4819eed9..bbe124b2 100644 --- a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd +++ b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd @@ -1,6 +1,6 @@ --- $Id: sys_w11a_s3.vhd 734 2016-02-20 22:43:20Z mueller $ +-- $Id: sys_w11a_s3.vhd 748 2016-03-20 15:18:50Z mueller $ -- --- Copyright 2007-2015 by Walter F.J. Mueller +-- Copyright 2007-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -74,6 +74,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-03-19 748 2.1.1 define rlink SYSID -- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul -- 2015-05-02 673 2.0 use pdp11_sys70 and pdp11_hio70; now in std form -- 2015-04-11 666 1.7.1 rearrange XON handling @@ -277,6 +278,10 @@ architecture syn of sys_w11a_s3 is constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx + constant sysid_proj : slv16 := x"0201"; -- w11a + constant sysid_board : slv8 := x"01"; -- s3board + constant sysid_vers : slv8 := x"00"; + begin CLK <= I_CLK50; -- use 50MHz as system clock @@ -313,7 +318,7 @@ begin generic map ( BTOWIDTH => 6, -- 64 cycles access timeout RTAWIDTH => 12, - SYSID => (others=>'0'), + SYSID => sysid_proj & sysid_board & sysid_vers, IFAWIDTH => 5, -- 32 word input fifo OFAWIDTH => 5, -- 32 word output fifo ENAPIN_RLMON => sbcntl_sbf_rlmon, diff --git a/rtl/sys_gen/w11a/s3board/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/s3board/tb/sys_conf_sim.vhd index 7fd21656..7870ff3a 100644 --- a/rtl/sys_gen/w11a/s3board/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/s3board/tb/sys_conf_sim.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf_sim.vhd 698 2015-07-05 21:20:18Z mueller $ +-- $Id: sys_conf_sim.vhd 770 2016-05-28 14:15:00Z mueller $ -- --- Copyright 2007-2015 by Walter F.J. Mueller +-- Copyright 2007-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,11 @@ -- Description: Definitions for sys_w11a_s3 (for simulation) -- -- Dependencies: - --- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-05-28 770 1.3.1 sys_conf_mem_losize now type natural +-- 2016-03-22 750 1.3 add sys_conf_cache_twidth -- 2015-06-26 695 1.2.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) -- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions -- 2014-12-22 619 1.1.2 add _rbmon_awidth @@ -48,14 +50,15 @@ package sys_conf is -- configure w11 cpu core -------------------------------------------------- constant sys_conf_bram : integer := 0; -- no bram, use cache constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB) - constant sys_conf_mem_losize : integer := 8#037777#; -- 1 MByte ---constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) + constant sys_conf_mem_losize : natural := 8#037777#; -- 1 MByte +--constant sys_conf_mem_losize : natural := 8#003777#; -- 128 kByte (debug) -- constant sys_conf_bram : integer := 1; -- bram only -- constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB) --- constant sys_conf_mem_losize : integer := 8#001777#; -- 64 kByte +-- constant sys_conf_mem_losize : natural := 8#001777#; -- 64 kByte constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + constant sys_conf_cache_twidth : integer := 9; -- 8kB cache -- configure w11 system devices -------------------------------------------- -- configure character and communication devices diff --git a/rtl/vlib/Makefile b/rtl/vlib/Makefile deleted file mode 100644 index 2bd801a7..00000000 --- a/rtl/vlib/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# $Id: Makefile 52 2007-06-10 17:14:53Z mueller $ -# -# -include Makefile.xflow -# diff --git a/rtl/vlib/cdclib/Makefile b/rtl/vlib/cdclib/Makefile new file mode 100644 index 00000000..beac4c4c --- /dev/null +++ b/rtl/vlib/cdclib/Makefile @@ -0,0 +1,37 @@ +# $Id: Makefile 757 2016-04-02 11:19:06Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-04-02 757 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +DCP_all = $(VBOM_all:.vbom=_syn.dcp) +# +# reference board for test synthesis is Artix-7 based Nexys4 +ifndef XTW_BOARD + XTW_BOARD=nexys4 +endif +include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk +# +.PHONY : catch all +# +catch : + @echo "no default target defined, use" + @echo " make all" + @echo " make _syn.dcp" + @exit 1 +# +all : $(DCP_all) +# +clean : viv_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/vlib/cdclib/Makefile.ise b/rtl/vlib/cdclib/Makefile.ise new file mode 100644 index 00000000..7c942218 --- /dev/null +++ b/rtl/vlib/cdclib/Makefile.ise @@ -0,0 +1,30 @@ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-04-02 757 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +# reference board for test synthesis is Spartan-6 based Nexys3 +ifndef XTW_BOARD + XTW_BOARD=nexys3 +endif +include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +# +.PHONY : all clean +# +all : $(NGC_all) +# +clean : ise_clean +# +#---- +# +include ${RETROBASE}/rtl/make_ise/generic_xflow.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +endif +# diff --git a/rtl/vlib/genlib/cdc_pulse.vbom b/rtl/vlib/cdclib/cdc_pulse.vbom similarity index 60% rename from rtl/vlib/genlib/cdc_pulse.vbom rename to rtl/vlib/cdclib/cdc_pulse.vbom index d8790786..404bfeab 100644 --- a/rtl/vlib/genlib/cdc_pulse.vbom +++ b/rtl/vlib/cdclib/cdc_pulse.vbom @@ -2,3 +2,4 @@ ../slvtypes.vhd # design cdc_pulse.vhd +@xdc:cdc_pulse.xdc -SCOPE_REF diff --git a/rtl/vlib/genlib/cdc_pulse.vhd b/rtl/vlib/cdclib/cdc_pulse.vhd similarity index 52% rename from rtl/vlib/genlib/cdc_pulse.vhd rename to rtl/vlib/cdclib/cdc_pulse.vhd index 4bf2b0d4..09903352 100644 --- a/rtl/vlib/genlib/cdc_pulse.vhd +++ b/rtl/vlib/cdclib/cdc_pulse.vhd @@ -1,6 +1,6 @@ --- $Id: cdc_pulse.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: cdc_pulse.vhd 774 2016-06-12 17:08:47Z mueller $ -- --- Copyright 2011- by Walter F.J. Mueller +-- Copyright 2011-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -13,14 +13,16 @@ -- ------------------------------------------------------------------------------ -- Module Name: cdc_pulse - syn --- Description: clock domain cross for pulse +-- Description: clock domain crossing for a pulse -- -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 13.1-14.7; viv 2015.4-2016.2; ghdl 0.29-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-06-11 774 1.2 add INIT generic +-- 2016-03-29 756 1.1 rename regs; add ASYNC_REG attributes -- 2011-11-09 422 1.0 Initial version -- ------------------------------------------------------------------------------ @@ -33,11 +35,12 @@ use work.slvtypes.all; entity cdc_pulse is -- clock domain cross for pulse generic ( POUT_SINGLE : boolean := false; -- if true: single cycle pout - BUSY_WACK : boolean := false); -- if true: busy waits for ack + BUSY_WACK : boolean := false; -- if true: busy waits for ack + INIT : slbit := '0'); -- initial state port ( - CLKM : in slbit; -- clock master + CLKM : in slbit; -- M|clock master RESET : in slbit := '0'; -- M|reset - CLKS : in slbit; -- clock slave + CLKS : in slbit; -- S|clock slave PIN : in slbit; -- M|pulse in BUSY : out slbit; -- M|busy POUT : out slbit -- S|pulse out @@ -47,11 +50,18 @@ end entity cdc_pulse; architecture syn of cdc_pulse is - signal R_REQ : slbit := '0'; - signal R_REQ_C : slbit := '0'; - signal R_ACK : slbit := '0'; - signal R_ACK_C : slbit := '0'; - signal R_ACK_S : slbit := '0'; + signal RM_REQ : slbit := INIT; -- request active + signal RS_REQ_S0 : slbit := INIT; -- request: CLKM->CLKS + signal RS_REQ_S1 : slbit := INIT; -- request: CLKS->CLKS + signal RM_ACK_S0 : slbit := '0'; -- acknowledge: CLKS->CLKM + signal RM_ACK_S1 : slbit := '0'; -- acknowledge: CLKM->CLKM + + attribute ASYNC_REG: string; + + attribute ASYNC_REG of RS_REQ_S0 : signal is "true"; + attribute ASYNC_REG of RS_REQ_S1 : signal is "true"; + attribute ASYNC_REG of RM_ACK_S0 : signal is "true"; + attribute ASYNC_REG of RM_ACK_S1 : signal is "true"; begin @@ -59,58 +69,59 @@ begin begin if rising_edge(CLKM) then if RESET = '1' then - R_REQ <= '0'; + RM_REQ <= '0'; else if PIN = '1' then - R_REQ <= '1'; - elsif R_ACK_S = '1' then - R_REQ <= '0'; + RM_REQ <= '1'; + elsif RM_ACK_S1 = '1' then + RM_REQ <= '0'; end if; end if; - R_ACK_C <= R_ACK; - R_ACK_S <= R_ACK_C; + RM_ACK_S0 <= RS_REQ_S1; -- synch 0: CLKS->CLKM + RM_ACK_S1 <= RM_ACK_S0; -- synch 1: CLKM end if; end process proc_master; proc_slave: process (CLKS) begin if rising_edge(CLKS) then - R_REQ_C <= R_REQ; - R_ACK <= R_REQ_C; + RS_REQ_S0 <= RM_REQ; -- synch 0: CLKM->CLKS + RS_REQ_S1 <= RS_REQ_S0; -- synch 1: CLKS end if; end process proc_slave; + -- Note: no pulse at startup when POUT_SINGLE=true, INIT=1 and PIN=1 initially SINGLE1: if POUT_SINGLE = true generate - signal R_ACK_1 : slbit := '0'; - signal R_POUT : slbit := '0'; + signal RS_ACK_1 : slbit := INIT; + signal RS_POUT : slbit := '0'; begin proc_pout: process (CLKS) begin if rising_edge(CLKS) then - R_ACK_1 <= R_ACK; - if R_ACK='1' and R_ACK_1='0' then - R_POUT <= '1'; + RS_ACK_1 <= RS_REQ_S1; + if RS_REQ_S1='1' and RS_ACK_1='0' then + RS_POUT <= '1'; else - R_POUT <= '0'; + RS_POUT <= '0'; end if; end if; end process proc_pout; - POUT <= R_POUT; + POUT <= RS_POUT; end generate SINGLE1; SINGLE0: if POUT_SINGLE = false generate begin - POUT <= R_ACK; + POUT <= RS_REQ_S1; end generate SINGLE0; BUSY1: if BUSY_WACK = true generate begin - BUSY <= R_REQ or R_ACK_S; + BUSY <= RM_REQ or RM_ACK_S1; end generate BUSY1; BUSY0: if BUSY_WACK = false generate begin - BUSY <= R_REQ; + BUSY <= RM_REQ; end generate BUSY0; end syn; diff --git a/rtl/vlib/cdclib/cdc_pulse.xdc b/rtl/vlib/cdclib/cdc_pulse.xdc new file mode 100644 index 00000000..3eeff995 --- /dev/null +++ b/rtl/vlib/cdclib/cdc_pulse.xdc @@ -0,0 +1,30 @@ +# -*- tcl -*- +# $Id: cdc_pulse.xdc 757 2016-04-02 11:19:06Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# cdc constraints for cdc_pulse +# +# Revision History: +# Date Rev Version Comment +# 2016-03-28 756 1.0 Initial version +# +set clkm [get_clocks -of_objects [get_cells RM_ACK_S0_reg]] +set clks [get_clocks -of_objects [get_cells RS_REQ_S0_reg]] + +# +# CLKM->CLKS +# capture REQ +set_max_delay \ + -from [get_cells -regexp "RM_REQ_reg"] \ + -to [get_cells -regexp "RS_REQ_S0_reg"] \ + -datapath_only [get_property -min PERIOD $clks] + +# +# CLKS->CLKM +# capture ACK +set_max_delay \ + -from [get_cells -regexp "RS_REQ_S1_reg"] \ + -to [get_cells -regexp "RM_ACK_S0_reg"] \ + -datapath_only [get_property -min PERIOD $clkm] diff --git a/rtl/vlib/cdclib/cdc_signal_s1.vbom b/rtl/vlib/cdclib/cdc_signal_s1.vbom new file mode 100644 index 00000000..c527faed --- /dev/null +++ b/rtl/vlib/cdclib/cdc_signal_s1.vbom @@ -0,0 +1,5 @@ +# libs +../slvtypes.vhd +# design +cdc_signal_s1.vhd +@xdc:cdc_signal_s1.xdc -SCOPE_REF diff --git a/rtl/vlib/cdclib/cdc_signal_s1.vhd b/rtl/vlib/cdclib/cdc_signal_s1.vhd new file mode 100644 index 00000000..943164d0 --- /dev/null +++ b/rtl/vlib/cdclib/cdc_signal_s1.vhd @@ -0,0 +1,67 @@ +-- $Id: cdc_signal_s1.vhd 774 2016-06-12 17:08:47Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: cdc_signal_s1 - syn +-- Description: clock domain crossing for a signal, 2 stage +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: viv 2015.4-2016.2; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2016-06-11 774 1.1 add INIT generic +-- 2016-04-08 459 1.0 Initial version +-- +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +entity cdc_signal_s1 is -- cdc for signal (2 stage) + generic ( + INIT : slbit := '0'); -- initial state + port ( + CLKO : in slbit; -- O|output clock + DI : in slbit; -- I|input data + DO : out slbit -- O|output data + ); +end entity cdc_signal_s1; + + +architecture syn of cdc_signal_s1 is + + signal R_DO_S0 : slbit := INIT; + signal R_DO_S1 : slbit := INIT; + + attribute ASYNC_REG: string; + + attribute ASYNC_REG of R_DO_S0 : signal is "true"; + attribute ASYNC_REG of R_DO_S1 : signal is "true"; + +begin + + proc_regs: process (CLKO) + begin + if rising_edge(CLKO) then + R_DO_S0 <= DI; -- synch 0: CLKI->CLKO + R_DO_S1 <= R_DO_S0; -- synch 1: CLKO + end if; + end process proc_regs; + + DO <= R_DO_S1; + +end syn; diff --git a/rtl/vlib/cdclib/cdc_signal_s1.xdc b/rtl/vlib/cdclib/cdc_signal_s1.xdc new file mode 100644 index 00000000..a650a5b0 --- /dev/null +++ b/rtl/vlib/cdclib/cdc_signal_s1.xdc @@ -0,0 +1,27 @@ +# -*- tcl -*- +# $Id: cdc_signal_s1.xdc 759 2016-04-09 10:13:57Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# cdc constraints for cdc_signal_s1 +# +# Revision History: +# Date Rev Version Comment +# 2016-04-08 759 1.0 Initial version +# + +set clko [get_clocks -of_objects [get_cells R_DO_S0_reg]] +set clko_per80 [expr {0.8 * [get_property -min PERIOD $clko]}] + +# +# CLKI->CLK0 +# ensure timing delay in DI smaller than a receiver clock cycle +# Note: -datapath_only requires -from to be specified; -from must be a +# clock (or primary port); a -from clock can't be reliably determined +# because 'single signal' synchronizer might be driven by logic or +# even by a constant. So simply use [get_clock], thus all clocks. +set_max_delay \ + -from [get_clocks] \ + -to [get_cells {R_DO_S0_reg}] \ + -datapath_only $clko_per80 diff --git a/rtl/vlib/cdclib/cdc_vector_s0.vbom b/rtl/vlib/cdclib/cdc_vector_s0.vbom new file mode 100644 index 00000000..264a9269 --- /dev/null +++ b/rtl/vlib/cdclib/cdc_vector_s0.vbom @@ -0,0 +1,5 @@ +# libs +../slvtypes.vhd +# design +cdc_vector_s0.vhd +@xdc:cdc_vector_s0.xdc -SCOPE_REF diff --git a/rtl/vlib/cdclib/cdc_vector_s0.vhd b/rtl/vlib/cdclib/cdc_vector_s0.vhd new file mode 100644 index 00000000..20669452 --- /dev/null +++ b/rtl/vlib/cdclib/cdc_vector_s0.vhd @@ -0,0 +1,66 @@ +-- $Id: cdc_vector_s0.vhd 759 2016-04-09 10:13:57Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: cdc_vector_s0 - syn +-- Description: clock domain crossing for a vector, 1 stage +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: viv 2015.4; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2016-04-08 459 1.0 Initial version +-- +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +entity cdc_vector_s0 is -- cdc for vector (1 stage) + generic ( + DWIDTH : positive := 16); -- data port width + port ( + CLKO : in slbit; -- O|output clock + DI : in slv(DWIDTH-1 downto 0); -- I|input data + DO : out slv(DWIDTH-1 downto 0) -- O|output data + ); +end entity cdc_vector_s0; + + +architecture syn of cdc_vector_s0 is + + subtype d_range is integer range DWIDTH-1 downto 0; + + signal R_DO_S0 : slv(d_range) := (others=>'0'); + + attribute ASYNC_REG: string; + + attribute ASYNC_REG of R_DO_S0 : signal is "true"; + +begin + + proc_regs: process (CLKO) + begin + if rising_edge(CLKO) then + R_DO_S0 <= DI; -- synch 0: CLKI->CLKO + end if; + end process proc_regs; + + DO <= R_DO_S0; + +end syn; + diff --git a/rtl/vlib/cdclib/cdc_vector_s0.xdc b/rtl/vlib/cdclib/cdc_vector_s0.xdc new file mode 100644 index 00000000..cef96723 --- /dev/null +++ b/rtl/vlib/cdclib/cdc_vector_s0.xdc @@ -0,0 +1,34 @@ +# -*- tcl -*- +# $Id: cdc_vector_s0.xdc 759 2016-04-09 10:13:57Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# cdc constraints for cdc_vector_s0 +# +# Revision History: +# Date Rev Version Comment +# 2016-04-08 759 1.0 Initial version +# + +# The following determines the input clock assuming that the synchronizer is +# directly connected to a register. Will not work when logic is inbetween or +# when driven by a dual-clocked BRAM. +set clki [get_clocks -of_objects \ + [get_cells -of_objects \ + [get_pins -filter {DIRECTION==OUT && IS_LEAF==1} -of_objects \ + [get_nets -segments -of_objects \ + [get_ports -scoped_to_current_instance {DI[0]} ] ] ] ] ] + +set clki_per80 [expr {0.8 * [get_property -min PERIOD $clki]}] + +# +# CLKI->CLK0 +# ensure delay and thus skew in DI smaller than a sender clock cycle +# Note: the _s0 form should be used for 'quasi static' cases +# this skew and delay control is therefore bit of an overkill +set_max_delay \ + -from $clki \ + -to [get_cells {R_DO_S0_reg[*]}] \ + -datapath_only $clki_per80 + diff --git a/rtl/vlib/cdclib/cdclib.vhd b/rtl/vlib/cdclib/cdclib.vhd new file mode 100644 index 00000000..6bc70c1c --- /dev/null +++ b/rtl/vlib/cdclib/cdclib.vhd @@ -0,0 +1,99 @@ +-- $Id: cdclib.vhd 774 2016-06-12 17:08:47Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: cdclib +-- Description: clock domain crossing components +-- +-- Dependencies: - +-- Tool versions: viv 2016.1-2016.2; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2016-06-11 774 1.0.1 add cdc_signal_s1_as; add INIT generic +-- 2016-04-02 757 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package cdclib is + +component cdc_signal_s1 is -- cdc for signal (2 stage) + generic ( + INIT : slbit := '0'); -- initial state + port ( + CLKO : in slbit; -- O|output clock + DI : in slbit; -- I|input data + DO : out slbit -- O|output data + ); +end component; + +component cdc_signal_s1_as is -- cdc for signal (2 stage), asyn input + generic ( + INIT : slbit := '0'); -- initial state + port ( + CLKO : in slbit; -- O|output clock + DI : in slbit; -- I|input data + DO : out slbit -- O|output data + ); +end component; + +component cdc_vector_s0 is -- cdc for vector (1 stage) + generic ( + DWIDTH : positive := 16); -- data port width + port ( + CLKO : in slbit; -- O|output clock + DI : in slv(DWIDTH-1 downto 0); -- I|input data + DO : out slv(DWIDTH-1 downto 0) -- O|output data + ); +end component; + +component cdc_vector_s1 is -- cdc for vector (2 stage) + generic ( + DWIDTH : positive := 16); -- data port width + port ( + CLKO : in slbit; -- O|output clock + DI : in slv(DWIDTH-1 downto 0); -- I|input data + DO : out slv(DWIDTH-1 downto 0) -- O|output data + ); +end component; + +component cdc_pulse is -- clock domain crossing for a pulse + generic ( + POUT_SINGLE : boolean := false; -- if true: single cycle pout + BUSY_WACK : boolean := false; -- if true: busy waits for ack + INIT : slbit := '0'); -- initial state + port ( + CLKM : in slbit; -- M|clock master + RESET : in slbit := '0'; -- M|reset + CLKS : in slbit; -- S|clock slave + PIN : in slbit; -- M|pulse in + BUSY : out slbit; -- M|busy + POUT : out slbit -- S|pulse out + ); +end component; + +component cdc_value is -- cdc for value (slow change) + generic ( + DWIDTH : positive := 16); -- data port width + port ( + CLKO : in slbit; -- O|output clock + DI : in slv(DWIDTH-1 downto 0); -- I|input data + DO : out slv(DWIDTH-1 downto 0); -- O|output data + DFIX : out slbit -- O|output data frozen + ); +end component; + +end package cdclib; diff --git a/rtl/vlib/comlib/Makefile b/rtl/vlib/comlib/Makefile.ise similarity index 89% rename from rtl/vlib/comlib/Makefile rename to rtl/vlib/comlib/Makefile.ise index 7b7bde7b..50120804 100644 --- a/rtl/vlib/comlib/Makefile +++ b/rtl/vlib/comlib/Makefile.ise @@ -1,4 +1,5 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ # # Revision History: # Date Rev Version Comment diff --git a/rtl/vlib/comlib/byte2word.vbom b/rtl/vlib/comlib/byte2word.vbom deleted file mode 100644 index 32a2542f..00000000 --- a/rtl/vlib/comlib/byte2word.vbom +++ /dev/null @@ -1,4 +0,0 @@ -# libs -../slvtypes.vhd -# design -byte2word.vhd diff --git a/rtl/vlib/comlib/byte2word.vhd b/rtl/vlib/comlib/byte2word.vhd deleted file mode 100644 index 58b18945..00000000 --- a/rtl/vlib/comlib/byte2word.vhd +++ /dev/null @@ -1,147 +0,0 @@ --- $Id: byte2word.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2011- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: byte2word - syn --- Description: 2 byte -> 1 word stream converter --- --- Dependencies: - --- Test bench: - --- Target Devices: generic --- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 --- --- Revision History: --- Date Rev Version Comment --- 2011-11-21 432 1.0.1 now numeric_std clean --- 2011-07-30 400 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; - -entity byte2word is -- 2 byte -> 1 word stream converter - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - DI : in slv8; -- input data (byte) - ENA : in slbit; -- write enable - BUSY : out slbit; -- write port hold - DO : out slv16; -- output data (word) - VAL : out slbit; -- read valid - HOLD : in slbit; -- read hold - ODD : out slbit -- odd byte pending - ); -end byte2word; - - -architecture syn of byte2word is - - type state_type is ( - s_idle, - s_vall, - s_valw - ); - - type regs_type is record - datl : slv8; -- lsb data - dath : slv8; -- msb data - state : state_type; -- state - end record regs_type; - - constant regs_init : regs_type := ( - (others=>'0'), - (others=>'0'), - s_idle - ); - - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs - -begin - - proc_regs: process (CLK) - begin - - if rising_edge(CLK) then - if RESET = '1' then - R_REGS <= regs_init; - else - R_REGS <= N_REGS; - end if; - end if; - - end process proc_regs; - - proc_next: process (R_REGS, DI, ENA, HOLD) - - variable r : regs_type := regs_init; - variable n : regs_type := regs_init; - - variable ival : slbit := '0'; - variable ibusy : slbit := '0'; - variable iodd : slbit := '0'; - - begin - - r := R_REGS; - n := R_REGS; - - ival := '0'; - ibusy := '0'; - iodd := '0'; - - case r.state is - - when s_idle => - if ENA = '1' then - n.datl := DI; - n.state := s_vall; - end if; - - when s_vall => - iodd := '1'; - if ENA = '1' then - n.dath := DI; - n.state := s_valw; - end if; - - when s_valw => - ival := '1'; - if HOLD = '0' then - if ENA = '1' then - n.datl := DI; - n.state := s_vall; - else - n.state := s_idle; - end if; - else - ibusy := '1'; - end if; - - when others => null; - end case; - - N_REGS <= n; - - DO <= r.dath & r.datl; - VAL <= ival; - BUSY <= ibusy; - ODD <= iodd; - - end process proc_next; - - -end syn; diff --git a/rtl/vlib/comlib/comlib.vhd b/rtl/vlib/comlib/comlib.vhd index ae18d016..b95381de 100644 --- a/rtl/vlib/comlib/comlib.vhd +++ b/rtl/vlib/comlib/comlib.vhd @@ -1,4 +1,4 @@ --- $Id: comlib.vhd 746 2016-03-19 13:08:36Z mueller $ +-- $Id: comlib.vhd 749 2016-03-20 22:09:03Z mueller $ -- -- Copyright 2007-2016 by Walter F.J. Mueller -- @@ -19,6 +19,7 @@ -- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-03-20 749 1.6.2 crc*_update*: leave return type unconstraint -- 2016-03-13 744 1.6.1 crc16_update_tbl: work around XSim 2015.4 issue -- 2014-09-27 595 1.6 add crc16 (using CRC-CCITT polynomial) -- 2014-09-14 593 1.5 new iface for cdata2byte and byte2cdata @@ -134,11 +135,16 @@ component crc16 is -- crc-16 generator, checker ); end component; - function crc8_update (crc : in slv8; data : in slv8) return slv8; - function crc8_update_tbl (crc : in slv8; data : in slv8) return slv8; + -- Note: leave return type unconstraint ! A direction constraint return + -- type works fine in ghdl and ISim, but XSim will abort with an + -- run time error (there is indeed a mismatch, some simulators + -- tolerate this, some not, so never constrain a return type...). - function crc16_update (crc : in slv16; data : in slv8) return slv16; - function crc16_update_tbl (crc : in slv16; data : in slv8) return slv16; + function crc8_update (crc : in slv8; data : in slv8) return slv; + function crc8_update_tbl (crc : in slv8; data : in slv8) return slv; + + function crc16_update (crc : in slv16; data : in slv8) return slv; + function crc16_update_tbl (crc : in slv16; data : in slv8) return slv; end package comlib; @@ -153,7 +159,7 @@ package body comlib is -- http://dx.doi.org/10.1109%2FDSN.2004.1311885 -- http://www.ece.cmu.edu/~koopman/roses/dsn04/koopman04_crc_poly_embedded.pdf -- - function crc8_update (crc: in slv8; data: in slv8) return slv8 is + function crc8_update (crc: in slv8; data: in slv8) return slv is variable t : slv8 := (others=>'0'); variable n : slv8 := (others=>'0'); begin @@ -173,7 +179,7 @@ package body comlib is end function crc8_update; - function crc8_update_tbl (crc: in slv8; data: in slv8) return slv8 is + function crc8_update_tbl (crc: in slv8; data: in slv8) return slv is type crc8_tbl_type is array (0 to 255) of integer; variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl @@ -220,7 +226,7 @@ package body comlib is -- crc16_update and crc16_update_tbl implement the CCITT polynomial -- x^16 + x^12 + x^5 + 1 (0x1021) -- - function crc16_update (crc: in slv16; data: in slv8) return slv16 is + function crc16_update (crc: in slv16; data: in slv8) return slv is variable n : slv16 := (others=>'0'); variable t : slv8 := (others=>'0'); begin @@ -249,7 +255,7 @@ package body comlib is end function crc16_update; - function crc16_update_tbl (crc: in slv16; data: in slv8) return slv16 is + function crc16_update_tbl (crc: in slv16; data: in slv8) return slv is type crc16_tbl_type is array (0 to 255) of integer; variable crc16_tbl : crc16_tbl_type := @@ -298,13 +304,7 @@ package body comlib is ch := crc(7 downto 0) & "00000000"; t := data xor crc(15 downto 8); td := crc16_tbl(to_integer(unsigned(t))); - cu := slv(to_unsigned(td, 16)); - ch := ch xor cu; - return ch; - --- original code was simply --- return ch xor slv(to_unsigned(td, 16)); --- vivado 2015.4 xsim failed on this, issue worked around by equivalent code + return ch xor slv(to_unsigned(td, 16)); end function crc16_update_tbl; diff --git a/rtl/vlib/comlib/tb/Makefile.ise b/rtl/vlib/comlib/tb/Makefile.ise index ef6f4070..eaeea055 100644 --- a/rtl/vlib/comlib/tb/Makefile.ise +++ b/rtl/vlib/comlib/tb/Makefile.ise @@ -1,4 +1,5 @@ -# $Id: Makefile.ise 744 2016-03-13 20:28:25Z mueller $ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ # # Revision History: # Date Rev Version Comment diff --git a/rtl/vlib/comlib/tb/tb_cdata2byte.vbom b/rtl/vlib/comlib/tb/tb_cdata2byte.vbom index c8cc3151..62ba912e 100644 --- a/rtl/vlib/comlib/tb/tb_cdata2byte.vbom +++ b/rtl/vlib/comlib/tb/tb_cdata2byte.vbom @@ -5,6 +5,6 @@ # components ../../simlib/simclk.vbom ../../simlib/simclkcnt.vbom -@uut: ${uut := tbd_cdata2byte.vbom} +${uut := tbd_cdata2byte.vbom} -UUT # design tb_cdata2byte.vhd diff --git a/rtl/vlib/comlib/tb/tbd_cdata2byte.vbom b/rtl/vlib/comlib/tb/tbd_cdata2byte.vbom index a896cb8d..0e2b0889 100644 --- a/rtl/vlib/comlib/tb/tbd_cdata2byte.vbom +++ b/rtl/vlib/comlib/tb/tbd_cdata2byte.vbom @@ -6,3 +6,4 @@ ../byte2cdata.vbom # design tbd_cdata2byte.vhd +@xdc:../../generic_clk_100mhz.xdc diff --git a/rtl/vlib/comlib/word2byte.vbom b/rtl/vlib/comlib/word2byte.vbom deleted file mode 100644 index fa861c5e..00000000 --- a/rtl/vlib/comlib/word2byte.vbom +++ /dev/null @@ -1,4 +0,0 @@ -# libs -../slvtypes.vhd -# design -word2byte.vhd diff --git a/rtl/vlib/comlib/word2byte.vhd b/rtl/vlib/comlib/word2byte.vhd deleted file mode 100644 index 715e367b..00000000 --- a/rtl/vlib/comlib/word2byte.vhd +++ /dev/null @@ -1,151 +0,0 @@ --- $Id: word2byte.vhd 649 2015-02-21 21:10:16Z mueller $ --- --- Copyright 2011- by Walter F.J. Mueller --- --- This program is free software; you may redistribute and/or modify it under --- the terms of the GNU General Public License as published by the Free --- Software Foundation, either version 2, or at your option any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY --- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License --- for complete details. --- ------------------------------------------------------------------------------- --- Module Name: word2byte - syn --- Description: 1 word -> 2 byte stream converter --- --- Dependencies: - --- Test bench: - --- Target Devices: generic --- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 --- --- Revision History: --- Date Rev Version Comment --- 2011-11-21 432 1.0.1 now numeric_std clean --- 2011-07-30 400 1.0 Initial version ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.slvtypes.all; - -entity word2byte is -- 1 word -> 2 byte stream converter - port ( - CLK : in slbit; -- clock - RESET : in slbit; -- reset - DI : in slv16; -- input data (word) - ENA : in slbit; -- write enable - BUSY : out slbit; -- write port hold - DO : out slv8; -- output data (byte) - VAL : out slbit; -- read valid - HOLD : in slbit; -- read hold - ODD : out slbit -- odd byte pending - ); -end word2byte; - - -architecture syn of word2byte is - - type state_type is ( - s_idle, - s_valw, - s_valh - ); - - type regs_type is record - datl : slv8; -- lsb data - dath : slv8; -- msb data - state : state_type; -- state - end record regs_type; - - constant regs_init : regs_type := ( - (others=>'0'), - (others=>'0'), - s_idle - ); - - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs - -begin - - proc_regs: process (CLK) - begin - - if rising_edge(CLK) then - if RESET = '1' then - R_REGS <= regs_init; - else - R_REGS <= N_REGS; - end if; - end if; - - end process proc_regs; - - proc_next: process (R_REGS, DI, ENA, HOLD) - - variable r : regs_type := regs_init; - variable n : regs_type := regs_init; - - variable ival : slbit := '0'; - variable ibusy : slbit := '0'; - variable iodd : slbit := '0'; - - begin - - r := R_REGS; - n := R_REGS; - - ival := '0'; - ibusy := '0'; - iodd := '0'; - - case r.state is - - when s_idle => - if ENA = '1' then - n.datl := DI( 7 downto 0); - n.dath := DI(15 downto 8); - n.state := s_valw; - end if; - - when s_valw => - ibusy := '1'; - ival := '1'; - if HOLD = '0' then - n.datl := r.dath; - n.state := s_valh; - end if; - - when s_valh => - ival := '1'; - iodd := '1'; - if HOLD = '0' then - if ENA = '1' then - n.datl := DI( 7 downto 0); - n.dath := DI(15 downto 8); - n.state := s_valw; - else - n.state := s_idle; - end if; - else - ibusy := '1'; - end if; - - when others => null; - end case; - - N_REGS <= n; - - DO <= r.datl; - VAL <= ival; - BUSY <= ibusy; - ODD <= iodd; - - end process proc_next; - - -end syn; diff --git a/rtl/vlib/generic_clk_100mhz.xdc b/rtl/vlib/generic_clk_100mhz.xdc new file mode 100644 index 00000000..912cd15f --- /dev/null +++ b/rtl/vlib/generic_clk_100mhz.xdc @@ -0,0 +1,14 @@ +# -*- tcl -*- +# $Id: generic_clk_100mhz.xdc 777 2016-06-19 20:24:15Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Generic constraint for pin CLK with a 100 MHz clock +# Helpful for test benches and generic test synthesis +# +# Revision History: +# Date Rev Version Comment +# 2016-06-19 777 1.0 Initial version + +create_clock -name CLK -period 10 -waveform {0 5} [get_ports CLK] diff --git a/rtl/vlib/genlib/Makefile b/rtl/vlib/genlib/Makefile.ise similarity index 90% rename from rtl/vlib/genlib/Makefile rename to rtl/vlib/genlib/Makefile.ise index 4986c9e2..34baec6a 100644 --- a/rtl/vlib/genlib/Makefile +++ b/rtl/vlib/genlib/Makefile.ise @@ -1,4 +1,5 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ # # Revision History: # Date Rev Version Comment diff --git a/rtl/vlib/genlib/clkdivce.vhd b/rtl/vlib/genlib/clkdivce.vhd index ce012bd8..e41310d6 100644 --- a/rtl/vlib/genlib/clkdivce.vhd +++ b/rtl/vlib/genlib/clkdivce.vhd @@ -1,4 +1,4 @@ --- $Id: clkdivce.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: clkdivce.vhd 751 2016-03-25 19:46:11Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment -- 2011-10-22 418 1.0.3 now numeric_std clean @@ -69,7 +69,7 @@ begin assert USECDIV <= 2**CDUWIDTH and MSECDIV <= 1024 report "assert(USECDIV <= 2**CDUWIDTH and MSECDIV <= 1024): " & "USECDIV too large for given CDUWIDTH or MSECDIV>1024" - severity FAILURE; + severity failure; proc_regs: process (CLK) begin diff --git a/rtl/vlib/genlib/debounce_gen.vhd b/rtl/vlib/genlib/debounce_gen.vhd index 8b7490d0..712701df 100644 --- a/rtl/vlib/genlib/debounce_gen.vhd +++ b/rtl/vlib/genlib/debounce_gen.vhd @@ -1,4 +1,4 @@ --- $Id: debounce_gen.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: debounce_gen.vhd 751 2016-03-25 19:46:11Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_debounce_gen -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment -- 2011-10-22 418 1.0.3 now numeric_std clean diff --git a/rtl/vlib/genlib/genlib.vhd b/rtl/vlib/genlib/genlib.vhd index 94762984..3806a99e 100644 --- a/rtl/vlib/genlib/genlib.vhd +++ b/rtl/vlib/genlib/genlib.vhd @@ -1,6 +1,6 @@ --- $Id: genlib.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: genlib.vhd 757 2016-04-02 11:19:06Z mueller $ -- --- Copyright 2007-2012 by Walter F.J. Mueller +-- Copyright 2007-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,11 @@ -- Description: some general purpose components -- -- Dependencies: - --- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-04-02 757 1.1 move cdc_pulse to cdclib +-- 2016-03-25 751 1.0.10 add gray_cnt_6 -- 2012-12-29 466 1.0.9 add led_pulse_stretch -- 2011-11-09 421 1.0.8 add cdc_pulse -- 2010-04-17 277 1.0.7 timer: no default for START,DONE,BUSY; drop STOP @@ -120,6 +122,15 @@ component gray_cnt_5 is -- 5 bit gray code counter (ROM based) ); end component; +component gray_cnt_6 is -- 6 bit gray code counter (ROM based) + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE : in slbit := '1'; -- count enable + DATA : out slv5 -- data out + ); +end component; + component gray_cnt_n is -- n bit gray code counter generic ( DWIDTH : positive := 8); -- data width @@ -155,20 +166,6 @@ component timer is -- retriggerable timer ); end component; -component cdc_pulse is -- clock domain cross for pulse - generic ( - POUT_SINGLE : boolean := false; -- if true: single cycle pout - BUSY_WACK : boolean := false); -- if true: busy waits for ack - port ( - CLKM : in slbit; -- clock master - RESET : in slbit := '0'; -- M|reset - CLKS : in slbit; -- clock slave - PIN : in slbit; -- M|pulse in - BUSY : out slbit; -- M|busy - POUT : out slbit -- S|pulse out - ); -end component; - component led_pulse_stretch is -- pulse stretcher for leds port ( CLK : in slbit; -- clock diff --git a/rtl/vlib/genlib/gray2bin_gen.vhd b/rtl/vlib/genlib/gray2bin_gen.vhd index 5619a72a..94cde472 100644 --- a/rtl/vlib/genlib/gray2bin_gen.vhd +++ b/rtl/vlib/genlib/gray2bin_gen.vhd @@ -1,4 +1,4 @@ --- $Id: gray2bin_gen.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: gray2bin_gen.vhd 751 2016-03-25 19:46:11Z mueller $ -- -- Copyright 2007- by Walter F.J. Mueller -- @@ -16,9 +16,9 @@ -- Description: Gray code to binary converter -- -- Dependencies: - --- Test bench: tb/tb_debounce_gen +-- Test bench: tb/tb_gray_cnt_n -- Target Devices: generic --- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 +-- Tool versions: xst 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment -- 2007-12-26 106 1.0 Initial version diff --git a/rtl/vlib/genlib/gray_cnt_4.vhd b/rtl/vlib/genlib/gray_cnt_4.vhd index 6dcdd2ef..077897cd 100644 --- a/rtl/vlib/genlib/gray_cnt_4.vhd +++ b/rtl/vlib/genlib/gray_cnt_4.vhd @@ -1,4 +1,4 @@ --- $Id: gray_cnt_4.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: gray_cnt_4.vhd 751 2016-03-25 19:46:11Z mueller $ -- -- Copyright 2007- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 +-- Tool versions: xst 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment -- 2007-12-26 106 1.0 Initial version diff --git a/rtl/vlib/genlib/gray_cnt_5.vhd b/rtl/vlib/genlib/gray_cnt_5.vhd index 48b929c8..15136a1f 100644 --- a/rtl/vlib/genlib/gray_cnt_5.vhd +++ b/rtl/vlib/genlib/gray_cnt_5.vhd @@ -1,4 +1,4 @@ --- $Id: gray_cnt_5.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: gray_cnt_5.vhd 751 2016-03-25 19:46:11Z mueller $ -- -- Copyright 2007- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 +-- Tool versions: xst 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment -- 2007-12-26 106 1.0 Initial version diff --git a/rtl/vlib/genlib/gray_cnt_gen.vhd b/rtl/vlib/genlib/gray_cnt_gen.vhd index 49984112..ccaea42e 100644 --- a/rtl/vlib/genlib/gray_cnt_gen.vhd +++ b/rtl/vlib/genlib/gray_cnt_gen.vhd @@ -1,4 +1,4 @@ --- $Id: gray_cnt_gen.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: gray_cnt_gen.vhd 751 2016-03-25 19:46:11Z mueller $ -- -- Copyright 2007- by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 +-- Tool versions: xst 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment -- 2007-12-26 106 1.0 Initial version diff --git a/rtl/vlib/genlib/gray_cnt_n.vhd b/rtl/vlib/genlib/gray_cnt_n.vhd index b88906d2..d7dd1f34 100644 --- a/rtl/vlib/genlib/gray_cnt_n.vhd +++ b/rtl/vlib/genlib/gray_cnt_n.vhd @@ -1,4 +1,4 @@ --- $Id: gray_cnt_n.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: gray_cnt_n.vhd 751 2016-03-25 19:46:11Z mueller $ -- -- Copyright 2007- by Walter F.J. Mueller -- @@ -16,14 +16,23 @@ -- Description: Genric width Gray code counter -- -- Dependencies: - --- Test bench: tb/tb_debounce_gen +-- Test bench: tb/tb_gray_cnt_n -- Target Devices: generic --- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment -- 2007-12-26 106 1.0 Initial version -- -- Some synthesis results: +-- - 2016-03-25 ise 14.7 for xc6slx16-csg324-2: +-- DWIDTH LUT Flop clock(xst est.) +-- 4 5 5 421MHz/ 2.37ns +-- 5 6 6 414MHz/ 2.41ns +-- 6 8 7 361MHz/ 2.77ns +-- 8 10 9 321MHz/ 3.11ns +-- 16 29 17 252MHz/ 3.96ns +-- 32 70 33 214MHz/ 4.65ns +-- 64 173 65 176MHz/ 5.66ns -- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4: -- DWIDTH LUT Flop clock(xst est.) -- 4 6 5 305MHz/ 3.28ns @@ -38,7 +47,6 @@ library ieee; use ieee.std_logic_1164.all; use work.slvtypes.all; -use work.genlib.all; entity gray_cnt_n is -- n bit gray code counter generic ( diff --git a/rtl/vlib/memlib/Makefile b/rtl/vlib/memlib/Makefile.ise similarity index 89% rename from rtl/vlib/memlib/Makefile rename to rtl/vlib/memlib/Makefile.ise index 5c6dccb5..5d413b3c 100644 --- a/rtl/vlib/memlib/Makefile +++ b/rtl/vlib/memlib/Makefile.ise @@ -1,4 +1,5 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ # # Revision History: # Date Rev Version Comment diff --git a/rtl/vlib/memlib/fifo_1c_dram_raw.vbom b/rtl/vlib/memlib/fifo_1c_dram_raw.vbom index 8b308895..433d18ff 100644 --- a/rtl/vlib/memlib/fifo_1c_dram_raw.vbom +++ b/rtl/vlib/memlib/fifo_1c_dram_raw.vbom @@ -3,6 +3,7 @@ memlib.vhd # components [sim]ram_1swar_1ar_gen.vbom -[xst,vsyn]ram_1swar_1ar_gen_unisim.vbom +[xst]ram_1swar_1ar_gen_unisim.vbom +[vsyn]ram_1swar_1ar_gen.vbom # design fifo_1c_dram_raw.vhd diff --git a/rtl/vlib/memlib/fifo_2c_dram.vbom b/rtl/vlib/memlib/fifo_2c_dram.vbom index acd26333..c8c70a89 100644 --- a/rtl/vlib/memlib/fifo_2c_dram.vbom +++ b/rtl/vlib/memlib/fifo_2c_dram.vbom @@ -4,7 +4,8 @@ memlib.vhd # components [sim]ram_1swar_1ar_gen.vbom -[xst,vsyn]ram_1swar_1ar_gen_unisim.vbom +[xst]ram_1swar_1ar_gen_unisim.vbom +[vsyn]ram_1swar_1ar_gen.vbom ../genlib/gray_cnt_gen.vbom ../genlib/gray2bin_gen.vbom # design diff --git a/rtl/vlib/memlib/fifo_2c_dram.vhd b/rtl/vlib/memlib/fifo_2c_dram.vhd index 6aaf487e..1bf9b1e5 100644 --- a/rtl/vlib/memlib/fifo_2c_dram.vhd +++ b/rtl/vlib/memlib/fifo_2c_dram.vhd @@ -1,4 +1,4 @@ --- $Id: fifo_2c_dram.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: fifo_2c_dram.vhd 751 2016-03-25 19:46:11Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -22,7 +22,7 @@ -- -- Test bench: tb/tb_fifo_2c_dram -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment -- 2011-11-13 424 1.1 use capture+sync flops; reset now glitch free @@ -175,13 +175,16 @@ begin G2B_WR : gray2bin_gen -- gray->bin for waddr on read side generic map (DWIDTH => AWIDTH) port map (DI => R_REGR.waddr_s, DO => WADDR_S_BIN); - G2B_RW : gray2bin_gen -- gray->bin for raddr on write side + G2B_RR : gray2bin_gen -- gray->bin for raddr on read side generic map (DWIDTH => AWIDTH) port map (DI => RADDR, DO => RADDR_BIN); - G2B_RR : gray2bin_gen -- gray->bin for raddr on read side + G2B_RW : gray2bin_gen -- gray->bin for raddr on write side generic map (DWIDTH => AWIDTH) port map (DI => R_REGW.raddr_s, DO => RADDR_S_BIN); + -- + -- write side -------------------------------------------------------------- + -- proc_regw: process (CLKW) begin if rising_edge(CLKW) then @@ -257,6 +260,9 @@ begin end process proc_nextw; + -- + -- read side --------------------------------------------------------------- + -- proc_regr: process (CLKR) begin if rising_edge(CLKR) then diff --git a/rtl/vlib/memlib/fifo_2c_dram2.vbom b/rtl/vlib/memlib/fifo_2c_dram2.vbom new file mode 100644 index 00000000..053365f3 --- /dev/null +++ b/rtl/vlib/memlib/fifo_2c_dram2.vbom @@ -0,0 +1,11 @@ +# libs +../slvtypes.vhd +../genlib/genlib.vhd +memlib.vhd +# components +ram_1swar_1ar_gen.vbom +../genlib/gray_cnt_gen.vbom +../genlib/gray2bin_gen.vbom +# design +fifo_2c_dram2.vhd +@xdc:fifo_2c_dram2.xdc -SCOPE_REF diff --git a/rtl/vlib/memlib/fifo_2c_dram2.vhd b/rtl/vlib/memlib/fifo_2c_dram2.vhd new file mode 100644 index 00000000..80d78051 --- /dev/null +++ b/rtl/vlib/memlib/fifo_2c_dram2.vhd @@ -0,0 +1,322 @@ +-- $Id: fifo_2c_dram2.vhd 752 2016-03-27 17:57:18Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: fifo_2c_dram2 - syn +-- Description: FIFO, two clock domain, distributed RAM based, with +-- enable/busy/valid/hold interface. +-- +-- Dependencies: ram_1swar_1ar_gen +-- genlib/gray_cnt_n +-- genlib/gray2bin_gen +-- +-- Test bench: tb/tb_fifo_2c_dram +-- Target Devices: generic +-- Tool versions: viv 2015.4; ghdl 0.33 +-- Revision History: +-- Date Rev Version Comment +-- 2016-03-24 751 1.0 Initial version (derived from fifo_2c_dram, is +-- exactly same logic, re-written to allow proper +-- usage of vivado constraints) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.memlib.all; + +entity fifo_2c_dram2 is -- fifo, 2 clock, dram based (v2) + generic ( + AWIDTH : positive := 5; -- address width (sets size) + DWIDTH : positive := 16); -- data width + port ( + CLKW : in slbit; -- clock (write side) + CLKR : in slbit; -- clock (read side) + RESETW : in slbit; -- W|reset from write side + RESETR : in slbit; -- R|reset from read side + DI : in slv(DWIDTH-1 downto 0); -- W|input data + ENA : in slbit; -- W|write enable + BUSY : out slbit; -- W|write port hold + DO : out slv(DWIDTH-1 downto 0); -- R|output data + VAL : out slbit; -- R|read valid + HOLD : in slbit; -- R|read hold + SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write + SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read + ); +end fifo_2c_dram2; + + +architecture syn of fifo_2c_dram2 is + + subtype a_range is integer range AWIDTH-1 downto 0; -- addr value regs + + signal RW_RADDR_S0 : slv(a_range) := (others=>'0'); -- read addr: CLKR->CLKW + signal RW_RADDR_S1 : slv(a_range) := (others=>'0'); -- read addr: CLKW->CLKW + signal RW_SIZEW : slv(a_range) := (others=>'0'); -- slots to write + signal RW_BUSY : slbit := '0'; -- busy flag + signal RW_RSTW : slbit := '0'; -- resetw active + signal RW_RSTW_E_S0 : slbit := '0'; -- rstw-echo: CLKR->CLKW + signal RW_RSTW_E_S1 : slbit := '0'; -- rstw-echo: CLKW->CLKW + signal RW_RSTR_S0 : slbit := '0'; -- resetr: CLKR->CLKW + signal RW_RSTR_S1 : slbit := '0'; -- resetr: CLKW->CLKW + + signal NW_SIZEW : slv(a_range) := (others=>'0'); -- slots to write + signal NW_BUSY : slbit := '0'; -- busy flag + signal NW_RSTW : slbit := '0'; -- resetw active + + signal RR_WADDR_S0 : slv(a_range) := (others=>'0'); -- write addr: CLKW->CLKR + signal RR_WADDR_S1 : slv(a_range) := (others=>'0'); -- write addr: CLKR->CLKR + signal RR_SIZER : slv(a_range) := (others=>'0'); -- slots to read + signal RR_VAL: slbit := '0'; -- valid flag + signal RR_RSTR : slbit := '0'; -- resetr active + signal RR_RSTR_E_S0 : slbit := '0'; -- rstr-echo: CLKW->CLKR + signal RR_RSTR_E_S1 : slbit := '0'; -- rstr-echo: CLKR->CLKR + signal RR_RSTW_S0 : slbit := '0'; -- resetw: CLKW->CLKR + signal RR_RSTW_S1 : slbit := '0'; -- resetw: CLKR->CLKR + + signal NR_SIZER : slv(a_range) := (others=>'0'); -- slots to read + signal NR_VAL: slbit := '0'; -- valid flag + signal NR_RSTR : slbit := '0'; -- resetr active + + signal WADDR : slv(AWIDTH-1 downto 0) := (others=>'0'); + signal RADDR : slv(AWIDTH-1 downto 0) := (others=>'0'); + signal WADDR_BIN_W : slv(AWIDTH-1 downto 0) := (others=>'0'); + signal RADDR_BIN_R : slv(AWIDTH-1 downto 0) := (others=>'0'); + signal WADDR_BIN_R : slv(AWIDTH-1 downto 0) := (others=>'0'); + signal RADDR_BIN_W : slv(AWIDTH-1 downto 0) := (others=>'0'); + + signal GCW_RST : slbit := '0'; + signal GCW_CE : slbit := '0'; + signal GCR_RST : slbit := '0'; + signal GCR_CE : slbit := '0'; + + attribute ASYNC_REG: string; + + attribute ASYNC_REG of RW_RADDR_S0 : signal is "true"; + attribute ASYNC_REG of RW_RADDR_S1 : signal is "true"; + attribute ASYNC_REG of RW_RSTW_E_S0 : signal is "true"; + attribute ASYNC_REG of RW_RSTW_E_S1 : signal is "true"; + attribute ASYNC_REG of RW_RSTR_S0 : signal is "true"; + attribute ASYNC_REG of RW_RSTR_S1 : signal is "true"; + + attribute ASYNC_REG of RR_WADDR_S0 : signal is "true"; + attribute ASYNC_REG of RR_WADDR_S1 : signal is "true"; + attribute ASYNC_REG of RR_RSTR_E_S0 : signal is "true"; + attribute ASYNC_REG of RR_RSTR_E_S1 : signal is "true"; + attribute ASYNC_REG of RR_RSTW_S0 : signal is "true"; + attribute ASYNC_REG of RR_RSTW_S1 : signal is "true"; + +begin + + RAM : ram_1swar_1ar_gen -- dual ported memory + generic map ( + AWIDTH => AWIDTH, + DWIDTH => DWIDTH) + port map ( + CLK => CLKW, + WE => GCW_CE, + ADDRA => WADDR, + ADDRB => RADDR, + DI => DI, + DOA => open, + DOB => DO + ); + + GCW : gray_cnt_gen -- gray counter for write address + generic map ( + DWIDTH => AWIDTH) + port map ( + CLK => CLKW, + RESET => GCW_RST, + CE => GCW_CE, + DATA => WADDR + ); + + GCR : gray_cnt_gen -- gray counter for read address + generic map ( + DWIDTH => AWIDTH) + port map ( + CLK => CLKR, + RESET => GCR_RST, + CE => GCR_CE, + DATA => RADDR + ); + + G2B_WW : gray2bin_gen -- gray->bin for waddr on write side + generic map (DWIDTH => AWIDTH) + port map (DI => WADDR, DO => WADDR_BIN_W); + G2B_WR : gray2bin_gen -- gray->bin for waddr on read side + generic map (DWIDTH => AWIDTH) + port map (DI => RR_WADDR_S1, DO => WADDR_BIN_R); + G2B_RR : gray2bin_gen -- gray->bin for raddr on read side + generic map (DWIDTH => AWIDTH) + port map (DI => RADDR, DO => RADDR_BIN_R); + G2B_RW : gray2bin_gen -- gray->bin for raddr on write side + generic map (DWIDTH => AWIDTH) + port map (DI => RW_RADDR_S1, DO => RADDR_BIN_W); + + -- + -- write side -------------------------------------------------------------- + -- + proc_regw: process (CLKW) + begin + if rising_edge(CLKW) then + RW_RADDR_S0 <= RADDR; -- sync 0: CLKR->CLKW + RW_RADDR_S1 <= RW_RADDR_S0; -- sync 1: CLKW + RW_SIZEW <= NW_SIZEW; + RW_BUSY <= NW_BUSY; + RW_RSTW <= NW_RSTW; + RW_RSTW_E_S0 <= RR_RSTW_S1; -- sync 0: CLKR->CLKW + RW_RSTW_E_S1 <= RW_RSTW_E_S0; -- sync 1: CLKW + RW_RSTR_S0 <= RR_RSTR; -- sync 0: CLKR->CLKW + RW_RSTR_S1 <= RW_RSTR_S0; -- sync 1: CLKW + end if; + end process proc_regw; + + proc_nextw: process (RW_BUSY, RW_SIZEW, RW_RSTW, RW_RSTW_E_S1, RW_RSTR_S1, + ENA, RESETW, RADDR_BIN_W, WADDR_BIN_W) + + variable ibusy : slbit := '0'; + variable irstw : slbit := '0'; + variable igcw_ce : slbit := '0'; + variable igcw_rst : slbit := '0'; + variable isizew : slv(a_range) := (others=>'0'); + begin + + isizew := slv(unsigned(RADDR_BIN_W) + unsigned(not WADDR_BIN_W)); + ibusy := '0'; + igcw_ce := '0'; + igcw_rst := '0'; + + if unsigned(isizew) = 0 then -- if no free slots + ibusy := '1'; -- next cycle busy=1 + end if; + + if ENA='1' and RW_BUSY='0' then -- if ena=1 and this cycle busy=0 + igcw_ce := '1'; -- write this value + if unsigned(isizew) = 1 then -- if this last free slot + ibusy := '1'; -- next cycle busy=1 + end if; + end if; + + irstw := RW_RSTW; + if RESETW = '1' then -- reset(write side) request + irstw := '1'; -- set RSTW flag + elsif RW_RSTW_E_S1 = '1' then -- request gone and return seen + irstw := '0'; -- clear RSTW flag + end if; + + if RW_RSTW='1' and RW_RSTW_E_S1='1' then -- RSTW seen on write and read side + igcw_rst := '1'; -- clear write address counter + end if; + if RW_RSTR_S1 = '1' then -- RSTR active + igcw_rst := '1'; -- clear write address counter + end if; + + if RESETW='1' or RW_RSTW='1' or RW_RSTW_E_S1='1' or RW_RSTR_S1='1' + then -- RESETW or RESETR active + ibusy := '1'; -- signal write side busy + isizew := (others=>'1'); + end if; + + NW_BUSY <= ibusy; + NW_RSTW <= irstw; + NW_SIZEW <= isizew; + + GCW_CE <= igcw_ce; + GCW_RST <= igcw_rst; + BUSY <= RW_BUSY; + SIZEW <= RW_SIZEW; + + end process proc_nextw; + + -- + -- read side --------------------------------------------------------------- + -- + proc_regr: process (CLKR) + begin + if rising_edge(CLKR) then + RR_WADDR_S0 <= WADDR; -- sync 0: CLKW->CLKR + RR_WADDR_S1 <= RR_WADDR_S0; -- sync 1: CLKW + RR_SIZER <= NR_SIZER; + RR_VAL <= NR_VAL; + RR_RSTR <= NR_RSTR; + RR_RSTR_E_S0 <= RW_RSTR_S1; -- sync 0: CLKW->CLKR + RR_RSTR_E_S1 <= RR_RSTR_E_S0; -- sync 1: CLKW + RR_RSTW_S0 <= RW_RSTW; -- sync 0: CLKW->CLKR + RR_RSTW_S1 <= RR_RSTW_S0; -- sync 1: CLKW + end if; + end process proc_regr; + + proc_nextr: process (RR_VAL, RR_SIZER, RR_RSTR, RR_RSTR_E_S1, RR_RSTW_S1, + HOLD, RESETR, RADDR_BIN_R, WADDR_BIN_R) + + variable ival : slbit := '0'; + variable irstr : slbit := '0'; + variable igcr_ce : slbit := '0'; + variable igcr_rst : slbit := '0'; + variable isizer : slv(a_range) := (others=>'0'); + + begin + + isizer := slv(unsigned(WADDR_BIN_R) - unsigned(RADDR_BIN_R)); + ival := '1'; + igcr_ce := '0'; + igcr_rst := '0'; + + if unsigned(isizer) = 0 then -- if nothing to read + ival := '0'; -- next cycle val=0 + end if; + + if RR_VAL='1' and HOLD='0' then -- this cycle val=1 and no hold + igcr_ce := '1'; -- retire this value + if unsigned(isizer) = 1 then -- if this is last one + ival := '0'; -- next cycle val=0 + end if; + end if; + + irstr := RR_RSTR; + if RESETR = '1' then -- reset(read side) request + irstr := '1'; -- set RSTR flag + elsif RR_RSTR_E_S1 = '1' then -- request gone and return seen + irstr := '0'; -- clear RSTR flag + end if; + + if RR_RSTR='1' and RR_RSTR_E_S1='1' then -- RSTR seen on read and write side + igcr_rst := '1'; -- clear read address counter + end if; + if RR_RSTW_S1 = '1' then -- RSTW active + igcr_rst := '1'; -- clear read address counter + end if; + + if RESETR='1' or RR_RSTR='1' or RR_RSTR_E_S1='1' or RR_RSTW_S1='1' + then -- RESETR or RESETW active + ival := '0'; -- signal read side empty + isizer := (others=>'0'); + end if; + + NR_VAL <= ival; + NR_RSTR <= irstr; + NR_SIZER <= isizer; + + GCR_CE <= igcr_ce; + GCR_RST <= igcr_rst; + VAL <= RR_VAL; + SIZER <= RR_SIZER; + + end process proc_nextr; + +end syn; diff --git a/rtl/vlib/memlib/fifo_2c_dram2.xdc b/rtl/vlib/memlib/fifo_2c_dram2.xdc new file mode 100644 index 00000000..d6e759fb --- /dev/null +++ b/rtl/vlib/memlib/fifo_2c_dram2.xdc @@ -0,0 +1,59 @@ +# -*- tcl -*- +# $Id: fifo_2c_dram2.xdc 761 2016-04-17 08:53:48Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# cdc constraints for fifo_2c_dram2 core +# +# Revision History: +# Date Rev Version Comment +# 2016-04-17 761 1.1 add false path for hold time through DRAM +# 2016-03-26 752 1.0 Initial version +# + +set clkw [get_clocks -of_objects [get_cells RW_RADDR_S0_reg[0]]] +set clkr [get_clocks -of_objects [get_cells RR_WADDR_S0_reg[0]]] +set clkw_per80 [expr {0.8 * [get_property -min PERIOD $clkw]}] +set clkr_per80 [expr {0.8 * [get_property -min PERIOD $clkr]}] + +# +# CLKR->CLKW +# read address +set_max_delay \ + -from [get_cells -regexp "GCR/.*/R_DATA_reg.*"] \ + -to [get_cells -regexp "RW_RADDR_S0_reg.*"] \ + -datapath_only $clkw_per80 +# reset +set_max_delay \ + -from $clkr \ + -to [get_cells -regexp "RW_(RSTW_E|RSTR)_S0_reg.*"] \ + -datapath_only $clkw_per80 +# +# CLKW->CLKR +# read address +set_max_delay \ + -from [get_cells -regexp "GCW/.*/R_DATA_reg.*"] \ + -to [get_cells -regexp "RR_WADDR_S0_reg.*"] \ + -datapath_only $clkr_per80 +# reset +set_max_delay \ + -from $clkw \ + -to [get_cells -regexp "RR_(RSTR_E|RSTW)_S0_reg.*"] \ + -datapath_only $clkr_per80 +# +# handle path from write clock to data output of dual port distributed RAM it's +# conceptualy a false path (this timing should not be relevant). To be on the +# save side only hold timing is set as false path and a set set_max_delay with +# read side period is used to constrain setup time. +# +set_max_delay \ + -from $clkw \ + -to $clkr \ + -through [get_cells -regexp "RAM/.*"] \ + [get_property -min PERIOD $clkr] + +set_false_path -hold \ + -from $clkw \ + -to $clkr \ + -through [get_cells -regexp "RAM/.*"] diff --git a/rtl/vlib/memlib/memlib.vhd b/rtl/vlib/memlib/memlib.vhd index 6344c69b..297e1f73 100644 --- a/rtl/vlib/memlib/memlib.vhd +++ b/rtl/vlib/memlib/memlib.vhd @@ -1,6 +1,6 @@ --- $Id: memlib.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: memlib.vhd 751 2016-03-25 19:46:11Z mueller $ -- --- Copyright 2006-2007 by Walter F.J. Mueller +-- Copyright 2006-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -17,9 +17,10 @@ -- asynchronus rams; Fifo's. -- -- Dependencies: - --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-03-25 751 1.1 add fifo_2c_dram2 -- 2008-03-08 123 1.0.3 add ram_2swsr_xfirst_gen_unisim -- 2008-03-02 122 1.0.2 change generic default for BRAM models -- 2007-12-27 106 1.0.1 add fifo_2c_dram @@ -235,4 +236,24 @@ component fifo_2c_dram is -- fifo, 2 clock, dram based ); end component; +component fifo_2c_dram2 is -- fifo, 2 clock, dram based (v2) + generic ( + AWIDTH : positive := 4; -- address width (sets size) + DWIDTH : positive := 16); -- data width + port ( + CLKW : in slbit; -- clock (write side) + CLKR : in slbit; -- clock (read side) + RESETW : in slbit; -- W|reset from write side + RESETR : in slbit; -- R|reset from read side + DI : in slv(DWIDTH-1 downto 0); -- W|input data + ENA : in slbit; -- W|write enable + BUSY : out slbit; -- W|write port hold + DO : out slv(DWIDTH-1 downto 0); -- R|output data + VAL : out slbit; -- R|read valid + HOLD : in slbit; -- R|read hold + SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write + SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read + ); +end component; + end package memlib; diff --git a/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd b/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd index 46b3ac59..ed2647da 100644 --- a/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd +++ b/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd @@ -1,4 +1,4 @@ --- $Id: ram_1swar_1ar_gen.vhd 686 2015-06-04 21:08:08Z mueller $ +-- $Id: ram_1swar_1ar_gen.vhd 750 2016-03-24 23:11:51Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -30,13 +30,13 @@ -- 2007-06-03 45 1.0 Initial version -- -- Some synthesis results: --- - 2010-06-03 ise 11.4 for xc3s1000-ft256-4: --- AWIDTH DWIDTH LUTl LUTm Comments --- 4 16 - 32 16*RAM16X1D --- 5 16 34 64 32*RAM16X1D --- 6 16 68 128 64*RAM16X1D, 32*MUXF5 --- 7 16 136 256 128*RAM16X1D, 64*MUXF5, 32*MUXF6 --- 8 16 292 512 256*RAM16X1D,144*MUXF5, 64*MUXF6, 32*MUXF7 +-- - 2010-06-03 (r123) with ise 11.4 for xc3s1000-ft256-4: +-- AWIDTH DWIDTH LUTl LUTm RAM16X1D MUXF5 MUXF6 MUXF7 +-- 4 16 - 32 16 0 0 0 +-- 5 16 34 64 32 0 0 0 +-- 6 16 68 128 64 32 0 0 +-- 7 16 136 256 128 64 32 0 +-- 8 16 292 512 256 144 64 32 -- - 2007-12-31 ise 8.2.03 for xc3s1000-ft256-4: -- {same results as above for AW=4 and 6} ------------------------------------------------------------------------------ diff --git a/rtl/vlib/rlink/Makefile b/rtl/vlib/rbus/Makefile.ise similarity index 89% rename from rtl/vlib/rlink/Makefile rename to rtl/vlib/rbus/Makefile.ise index e439cce4..1dd200de 100644 --- a/rtl/vlib/rlink/Makefile +++ b/rtl/vlib/rbus/Makefile.ise @@ -1,4 +1,5 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ # # Revision History: # Date Rev Version Comment diff --git a/rtl/vlib/rbus/rb_sel.vhd b/rtl/vlib/rbus/rb_sel.vhd index 9b103d84..c949de09 100644 --- a/rtl/vlib/rbus/rb_sel.vhd +++ b/rtl/vlib/rbus/rb_sel.vhd @@ -1,6 +1,6 @@ --- $Id: rb_sel.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: rb_sel.vhd 758 2016-04-02 18:01:39Z mueller $ -- --- Copyright 2010-2014 by Walter F.J. Mueller +-- Copyright 2010-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,10 +18,11 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: ise 12.1-14.7; viv 2014.4; ghdl 0.29-0.31 +-- Tool versions: ise 12.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 -- -- Revision History: -- Date Rev Version Comment +-- 2016-04-02 758 4.1 streamline code -- 2014-08-15 583 4.0 rb_mreq addr now 16 bit -- 2010-12-26 349 1.0 Initial version (cloned from ibus/ib_sel) ------------------------------------------------------------------------------ @@ -53,15 +54,14 @@ begin report "assert(SAWIDTH<=15)" severity failure; proc_regs: process (CLK) - variable isel : slbit := '0'; begin if rising_edge(CLK) then - isel := '0'; if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto SAWIDTH)=RB_ADDR(15 downto SAWIDTH) then - isel := '1'; + R_SEL <= '1'; + else + R_SEL <= '0'; end if; - R_SEL <= isel; end if; end process proc_regs; diff --git a/rtl/vlib/rbus/rb_sres_or_6.vbom b/rtl/vlib/rbus/rb_sres_or_6.vbom new file mode 100644 index 00000000..d12052bb --- /dev/null +++ b/rtl/vlib/rbus/rb_sres_or_6.vbom @@ -0,0 +1,7 @@ +# libs +../slvtypes.vhd +rblib.vhd +# components +[sim]rb_sres_or_mon.vbom +# design +rb_sres_or_6.vhd diff --git a/rtl/vlib/rbus/rb_sres_or_6.vhd b/rtl/vlib/rbus/rb_sres_or_6.vhd new file mode 100644 index 00000000..3915c500 --- /dev/null +++ b/rtl/vlib/rbus/rb_sres_or_6.vhd @@ -0,0 +1,97 @@ +-- $Id: rb_sres_or_6.vhd 758 2016-04-02 18:01:39Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rb_sres_or_6 - syn +-- Description: rbus result or, 6 input +-- +-- Dependencies: rb_sres_or_mon [sim only] +-- Test bench: - +-- Target Devices: generic +-- Tool versions: xst 14.7; viv 2015.4; ghdl 0.33 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-04-02 758 1.0 Initial version +-- 2016-03-12 741 0.1 First draft +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.rblib.all; + +-- ---------------------------------------------------------------------------- + +entity rb_sres_or_6 is -- rbus result or, 6 input + port ( + RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 + RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2 + RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 + RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4 + RB_SRES_5 : in rb_sres_type := rb_sres_init; -- rb_sres input 5 + RB_SRES_6 : in rb_sres_type := rb_sres_init; -- rb_sres input 6 + RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output + ); +end rb_sres_or_6; + +architecture syn of rb_sres_or_6 is + +begin + + proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3, + RB_SRES_4, RB_SRES_5, RB_SRES_6) + + begin + + RB_SRES_OR.ack <= RB_SRES_1.ack or + RB_SRES_2.ack or + RB_SRES_3.ack or + RB_SRES_4.ack or + RB_SRES_5.ack or + RB_SRES_6.ack; + RB_SRES_OR.busy <= RB_SRES_1.busy or + RB_SRES_2.busy or + RB_SRES_3.busy or + RB_SRES_4.busy or + RB_SRES_5.busy or + RB_SRES_6.busy; + RB_SRES_OR.err <= RB_SRES_1.err or + RB_SRES_2.err or + RB_SRES_3.err or + RB_SRES_4.err or + RB_SRES_5.err or + RB_SRES_6.err; + RB_SRES_OR.dout <= RB_SRES_1.dout or + RB_SRES_2.dout or + RB_SRES_3.dout or + RB_SRES_4.dout or + RB_SRES_5.dout or + RB_SRES_6.dout; + + end process proc_comb; + +-- synthesis translate_off + ORMON : rb_sres_or_mon + port map ( + RB_SRES_1 => RB_SRES_1, + RB_SRES_2 => RB_SRES_2, + RB_SRES_3 => RB_SRES_3, + RB_SRES_4 => RB_SRES_4, + RB_SRES_5 => RB_SRES_5, + RB_SRES_6 => RB_SRES_6 + ); +-- synthesis translate_on + +end syn; diff --git a/rtl/vlib/rbus/rbd_bram.vbom b/rtl/vlib/rbus/rbd_bram.vbom index 18c13613..26bcd36b 100644 --- a/rtl/vlib/rbus/rbd_bram.vbom +++ b/rtl/vlib/rbus/rbd_bram.vbom @@ -4,6 +4,7 @@ rblib.vhd # components [sim]../memlib/ram_1swsr_wfirst_gen.vbom -[xst,vsyn]../memlib/ram_1swsr_wfirst_gen_unisim.vbom +[xst]../memlib/ram_1swsr_wfirst_gen_unisim.vbom +[vsyn]../memlib/ram_1swsr_wfirst_gen.vbom # design rbd_bram.vhd diff --git a/rtl/vlib/rbus/rbd_eyemon.vbom b/rtl/vlib/rbus/rbd_eyemon.vbom index ccbe7584..4a056cd6 100644 --- a/rtl/vlib/rbus/rbd_eyemon.vbom +++ b/rtl/vlib/rbus/rbd_eyemon.vbom @@ -4,6 +4,7 @@ rblib.vhd # components [sim]../memlib/ram_2swsr_wfirst_gen.vbom -[xst,vsyn]../memlib/ram_2swsr_wfirst_gen_unisim.vbom +[xst]../memlib/ram_2swsr_wfirst_gen_unisim.vbom +[vsyn]../memlib/ram_2swsr_wfirst_gen.vbom # design rbd_eyemon.vhd diff --git a/rtl/vlib/rbus/rbd_eyemon.vhd b/rtl/vlib/rbus/rbd_eyemon.vhd index afd7b5fb..cbdf76b3 100644 --- a/rtl/vlib/rbus/rbd_eyemon.vhd +++ b/rtl/vlib/rbus/rbd_eyemon.vhd @@ -1,6 +1,6 @@ --- $Id: rbd_eyemon.vhd 593 2014-09-14 22:21:33Z mueller $ +-- $Id: rbd_eyemon.vhd 767 2016-05-26 07:47:51Z mueller $ -- --- Copyright 2010-2014 by Walter F.J. Mueller +-- Copyright 2010-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,7 +20,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 12.1-14.7; viv 2014.4-2016.1; ghdl 0.29-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -29,6 +29,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-05-22 787 4.1.1 don't init N_REGS (vivado fix for fsm inference) -- 2014-09-13 593 4.1 no default rbus addess anymore, def=0 -- 2014-08-15 583 4.0 rb_mreq addr now 16 bit -- 2011-11-19 427 1.0.3 now numeric_std clean @@ -131,7 +132,7 @@ architecture syn of rbd_eyemon is ); signal R_REGS : regs_type := regs_init; - signal N_REGS : regs_type := regs_init; + signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) signal BRAM_ENA : slbit := '0'; signal BRAM_DIA : slv32 := (others=>'0'); @@ -296,6 +297,7 @@ begin end if; when s_char => -- s_char: processing a char --------- + n.state := s_char; -- needed to prevent vivado iSTATE if RXACT = '0' then -- uart went unactive if RXSD = '1' then -- line idle -> to s_idle n.state := s_idle; diff --git a/rtl/vlib/rbus/rbd_rbmon.vbom b/rtl/vlib/rbus/rbd_rbmon.vbom index 7acdae02..a0487ace 100644 --- a/rtl/vlib/rbus/rbd_rbmon.vbom +++ b/rtl/vlib/rbus/rbd_rbmon.vbom @@ -4,6 +4,7 @@ rblib.vhd # components [sim]../memlib/ram_1swsr_wfirst_gen.vbom -[xst,vsyn]../memlib/ram_1swsr_wfirst_gen_unisim.vbom +[xst]../memlib/ram_1swsr_wfirst_gen_unisim.vbom +[vsyn]../memlib/ram_1swsr_wfirst_gen.vbom # design rbd_rbmon.vhd diff --git a/rtl/vlib/rbus/rbd_rbmon.vhd b/rtl/vlib/rbus/rbd_rbmon.vhd index 557e6a7a..f8d6c0b2 100644 --- a/rtl/vlib/rbus/rbd_rbmon.vhd +++ b/rtl/vlib/rbus/rbd_rbmon.vhd @@ -1,4 +1,4 @@ --- $Id: rbd_rbmon.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: rbd_rbmon.vhd 758 2016-04-02 18:01:39Z mueller $ -- -- Copyright 2010-2015 by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- Test bench: rlink/tb/tb_rlink_tba_ttcombo -- -- Target Devices: generic --- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 12.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/vlib/rbus/rbd_tester.vhd b/rtl/vlib/rbus/rbd_tester.vhd index 9e59dcd6..58957536 100644 --- a/rtl/vlib/rbus/rbd_tester.vhd +++ b/rtl/vlib/rbus/rbd_tester.vhd @@ -1,4 +1,4 @@ --- $Id: rbd_tester.vhd 593 2014-09-14 22:21:33Z mueller $ +-- $Id: rbd_tester.vhd 758 2016-04-02 18:01:39Z mueller $ -- -- Copyright 2010-2014 by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- Test bench: rlink/tb/tb_rlink (used as test target) -- -- Target Devices: generic --- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 12.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/vlib/rbus/rbd_timer.vhd b/rtl/vlib/rbus/rbd_timer.vhd index af21f4dc..6a651ddb 100644 --- a/rtl/vlib/rbus/rbd_timer.vhd +++ b/rtl/vlib/rbus/rbd_timer.vhd @@ -1,4 +1,4 @@ --- $Id: rbd_timer.vhd 593 2014-09-14 22:21:33Z mueller $ +-- $Id: rbd_timer.vhd 758 2016-04-02 18:01:39Z mueller $ -- -- Copyright 2010-2014 by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 12.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri diff --git a/rtl/vlib/rbus/rbd_usracc.vbom b/rtl/vlib/rbus/rbd_usracc.vbom new file mode 100644 index 00000000..03d2208a --- /dev/null +++ b/rtl/vlib/rbus/rbd_usracc.vbom @@ -0,0 +1,8 @@ +# libs +../slvtypes.vhd +../xlib/xlib.vhd +rblib.vhd +# components +../xlib/usr_access_unisim.vbom +# design +rbd_usracc.vhd diff --git a/rtl/vlib/rbus/rbd_usracc.vhd b/rtl/vlib/rbus/rbd_usracc.vhd new file mode 100644 index 00000000..995f0de7 --- /dev/null +++ b/rtl/vlib/rbus/rbd_usracc.vhd @@ -0,0 +1,108 @@ +-- $Id: rbd_usracc.vhd 758 2016-04-02 18:01:39Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rbd_usracc - syn +-- Description: rbus dev: return usr_access register (bitfile+jtag timestamp) +-- +-- Dependencies: xlib/usr_access_unisim +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: viv 2015.4; ghdl 0.33 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-04-02 758 1.0 Initial version +------------------------------------------------------------------------------ +-- +-- rbus registers: +-- +-- Addr Bits Name r/w/f Function +-- 0 time r/-/- use_accress lsb +-- 1 time r/-/- use_accress msb +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.rblib.all; +use work.rbdlib.all; + +entity rbd_usracc is -- rbus dev: return usr_access register + generic ( + RB_ADDR : slv16 := rbaddr_usracc); + port ( + CLK : in slbit; -- clock + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type -- rbus: response + ); +end entity rbd_usracc; + + +architecture syn of rbd_usracc is + + signal R_SEL : slbit := '0'; + signal DATA : slv32 := (others=>'0'); + +begin + + RBSEL : rb_sel + generic map ( + RB_ADDR => RB_ADDR, + SAWIDTH => 1) + port map ( + CLK => CLK, + RB_MREQ => RB_MREQ, + SEL => R_SEL + ); + + UA : usr_access_unisim + port map (DATA => DATA); + + proc_next : process (R_SEL, RB_MREQ, DATA) + variable irb_ack : slbit := '0'; + variable irb_err : slbit := '0'; + variable irb_dout : slv16 := (others=>'0'); + begin + + irb_ack := '0'; + irb_err := '0'; + irb_dout := (others=>'0'); + + -- rbus transactions + if R_SEL = '1' then + irb_ack := RB_MREQ.re or RB_MREQ.we; + if RB_MREQ.we = '1' then + irb_err := '1'; + end if; + if RB_MREQ.re = '1' then + case (RB_MREQ.addr(0)) is + when '0' => irb_dout := DATA(15 downto 0); + when '1' => irb_dout := DATA(31 downto 16); + when others => null; + end case; + end if; + end if; + + RB_SRES.dout <= irb_dout; + RB_SRES.ack <= irb_ack; + RB_SRES.err <= irb_err; + RB_SRES.busy <= '0'; + + end process proc_next; + +end syn; diff --git a/rtl/vlib/rbus/rbdlib.vhd b/rtl/vlib/rbus/rbdlib.vhd index 40dd911f..956664e0 100644 --- a/rtl/vlib/rbus/rbdlib.vhd +++ b/rtl/vlib/rbus/rbdlib.vhd @@ -1,6 +1,6 @@ --- $Id: rbdlib.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: rbdlib.vhd 758 2016-04-02 18:01:39Z mueller $ -- --- Copyright 2010-2014 by Walter F.J. Mueller +-- Copyright 2010-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,10 +16,11 @@ -- Description: Definitions for rbus devices -- -- Dependencies: - --- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 12.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 -- -- Revision History: -- Date Rev Version Comment +-- 2016-04-02 758 4.1 add rbd_usracc -- 2014-09-13 593 4.0 use new rlink v4 iface and 4 bit STAT -- 2014-08-15 583 3.5 rb_mreq addr now 16 bit -- 2011-11-19 427 1.2.1 now numeric_std clean @@ -43,6 +44,7 @@ use work.rblib.all; package rbdlib is +constant rbaddr_usracc : slv16 := x"fffa"; -- fffa/8: 1111 1111 1111 1010 constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/8: 1111 1111 1110 1xxx constant rbaddr_tester : slv16 := x"ffe0"; -- ffe0/8: 1111 1111 1110 0xxx @@ -113,4 +115,14 @@ component rbd_timer is -- rbus dev: usec precision timer ); end component; +component rbd_usracc is -- rbus dev: return usr_access register + generic ( + RB_ADDR : slv16 := rbaddr_usracc); + port ( + CLK : in slbit; -- clock + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type -- rbus: response + ); +end component; + end package rbdlib; diff --git a/rtl/vlib/rbus/Makefile b/rtl/vlib/rlink/Makefile.ise similarity index 89% rename from rtl/vlib/rbus/Makefile rename to rtl/vlib/rlink/Makefile.ise index e439cce4..1dd200de 100644 --- a/rtl/vlib/rbus/Makefile +++ b/rtl/vlib/rlink/Makefile.ise @@ -1,4 +1,5 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ # # Revision History: # Date Rev Version Comment diff --git a/rtl/vlib/rlink/rlink_core.vbom b/rtl/vlib/rlink/rlink_core.vbom index 2c147f36..3499f202 100644 --- a/rtl/vlib/rlink/rlink_core.vbom +++ b/rtl/vlib/rlink/rlink_core.vbom @@ -6,7 +6,8 @@ rlinklib.vbom # components [sim]../memlib/ram_2swsr_rfirst_gen.vbom -[xst,vsyn]../memlib/ram_2swsr_rfirst_gen_unisim.vbom +[xst]../memlib/ram_2swsr_rfirst_gen_unisim.vbom +[vsyn]../memlib/ram_2swsr_rfirst_gen.vbom ../memlib/fifo_1c_dram.vbom ../comlib/crc16.vbom ../rbus/rb_sel.vbom diff --git a/rtl/vlib/rlink/rlink_core.vhd b/rtl/vlib/rlink/rlink_core.vhd index 6ddd04b1..e15a8c41 100644 --- a/rtl/vlib/rlink/rlink_core.vhd +++ b/rtl/vlib/rlink/rlink_core.vhd @@ -1,6 +1,6 @@ --- $Id: rlink_core.vhd 718 2015-12-26 15:59:48Z mueller $ +-- $Id: rlink_core.vhd 767 2016-05-26 07:47:51Z mueller $ -- --- Copyright 2007-2015 by Walter F.J. Mueller +-- Copyright 2007-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -28,7 +28,7 @@ -- tb/tb_rlink_tba_ttcombo -- -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -39,6 +39,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-05-22 787 4.1.2 don't init N_REGS (vivado fix for fsm inference) -- 2015-12-26 718 4.1.1 add proc_sres: strip 'x' from RB_SRES.dout -- 2014-12-21 617 4.1 use stat(_rbf_rbtout) to signal rbus timeout -- 2014-12-20 614 4.0 largely rewritten; 2 FSMs; v3 protocol; 4 bit STAT @@ -389,9 +390,9 @@ architecture syn of rlink_core is ); signal R_LREGS : lregs_type := lregs_init; -- state registers link FSM - signal N_LREGS : lregs_type := lregs_init; -- next value state regs link FSM + signal N_LREGS : lregs_type; -- don't init (vivado fix for fsm infer) signal R_BREGS : bregs_type := bregs_init; -- state registers bus FSM - signal N_BREGS : bregs_type := bregs_init; -- next value state regs bus FSM + signal N_BREGS : bregs_type; -- don't init (vivado fix for fsm infer) signal R_CREGS : cregs_type := cregs_init; -- state registers config signal N_CREGS : cregs_type := cregs_init; -- next value state regs config @@ -757,6 +758,7 @@ begin end if; when sl_txeop => -- sl_txeop: send eop ---------------- + n.state := sl_txeop; -- needed to prevent vivado iSTATE ido := c_rlink_dat_eop; -- send eop character ival := '1'; if RL_HOLD = '0' then -- wait for accept diff --git a/rtl/vlib/rlink/rlink_sp2c.vbom b/rtl/vlib/rlink/rlink_sp2c.vbom new file mode 100644 index 00000000..359713c9 --- /dev/null +++ b/rtl/vlib/rlink/rlink_sp2c.vbom @@ -0,0 +1,13 @@ +# libs +../slvtypes.vhd +../rbus/rblib.vhd +../rbus/rbdlib.vhd +rlinklib.vbom +../serport/serportlib.vbom +# components +rlink_core8.vbom +../serport/serport_2clock2.vbom +../rbus/rbd_rbmon.vbom +../rbus/rb_sres_or_2.vbom +# design +rlink_sp2c.vhd diff --git a/rtl/vlib/rlink/rlink_sp2c.vhd b/rtl/vlib/rlink/rlink_sp2c.vhd new file mode 100644 index 00000000..821c0efa --- /dev/null +++ b/rtl/vlib/rlink/rlink_sp2c.vhd @@ -0,0 +1,173 @@ +-- $Id: rlink_sp2c.vhd 755 2016-03-28 17:59:59Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rlink_sp2c - syn +-- Description: rlink_core8 + serport_2clock2 combo +-- +-- Dependencies: rlink_core8 +-- serport/serport_2clock2 +-- rbus/rbd_rbmon +-- rbus/rb_sres_or_2 +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: viv 2015.4; ghdl 0.33 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-03-28 755 1.0 Initial version (derived from rlink_sp1c) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.rblib.all; +use work.rbdlib.all; +use work.rlinklib.all; +use work.serportlib.all; + +entity rlink_sp2c is -- rlink_core8+serport_2clock2 combo + generic ( + BTOWIDTH : positive := 5; -- rbus timeout counter width + RTAWIDTH : positive := 12; -- retransmit buffer address width + SYSID : slv32 := (others=>'0'); -- rlink system id + IFAWIDTH : natural := 5; -- input fifo address width (0=none) + OFAWIDTH : natural := 5; -- output fifo address width (0=none) + ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none) + ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none) + ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none) + CDWIDTH : positive := 13; -- clk divider width + CDINIT : natural := 15; -- clk divider initial/reset setting + RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none) + RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr + port ( + CLK : in slbit; -- U|clock (user design) + CE_USEC : in slbit; -- U|1 usec clock enable + CE_MSEC : in slbit; -- U|1 msec clock enable + CE_INT : in slbit := '0'; -- U|rri ato time unit clock enable + RESET : in slbit; -- U|reset + CLKS : in slbit; -- S|clock (frontend:serial) + CES_MSEC : in slbit; -- S|1 msec clock enable + ENAXON : in slbit; -- U|enable xon/xoff handling + ESCFILL : in slbit; -- U|enable fill escaping + RXSD : in slbit; -- S|receive serial data (board view) + TXSD : out slbit; -- S|transmit serial data (board view) + CTS_N : in slbit := '0'; -- S|clear to send (act.low, board view) + RTS_N : out slbit; -- S|request to send (act.low, brd view) + RB_MREQ : out rb_mreq_type; -- U|rbus: request + RB_SRES : in rb_sres_type; -- U|rbus: response + RB_LAM : in slv16; -- U|rbus: look at me + RB_STAT : in slv4; -- U|rbus: status flags + RL_MONI : out rl_moni_type; -- U|rlink_core: monitor port + SER_MONI : out serport_moni_type -- U|serport: monitor port + ); +end entity rlink_sp2c; + + +architecture syn of rlink_sp2c is + + signal RLB_DI : slv8 := (others=>'0'); + signal RLB_ENA : slbit := '0'; + signal RLB_BUSY : slbit := '0'; + signal RLB_DO : slv8 := (others=>'0'); + signal RLB_VAL : slbit := '0'; + signal RLB_HOLD : slbit := '0'; + + signal RB_MREQ_M : rb_mreq_type := rb_mreq_init; + signal RB_SRES_M : rb_sres_type := rb_sres_init; + signal RB_SRES_RBMON : rb_sres_type := rb_sres_init; + +begin + + CORE : rlink_core8 -- rlink master ---------------------- + generic map ( + BTOWIDTH => BTOWIDTH, + RTAWIDTH => RTAWIDTH, + SYSID => SYSID, + ENAPIN_RLMON => ENAPIN_RLMON, + ENAPIN_RLBMON=> ENAPIN_RLBMON, + ENAPIN_RBMON => ENAPIN_RBMON) + port map ( + CLK => CLK, + CE_INT => CE_INT, + RESET => RESET, + ESCXON => ENAXON, + ESCFILL => ESCFILL, + RLB_DI => RLB_DI, + RLB_ENA => RLB_ENA, + RLB_BUSY => RLB_BUSY, + RLB_DO => RLB_DO, + RLB_VAL => RLB_VAL, + RLB_HOLD => RLB_HOLD, + RL_MONI => RL_MONI, + RB_MREQ => RB_MREQ_M, + RB_SRES => RB_SRES_M, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT + ); + + SERPORT : serport_2clock2 -- serport interface ----------------- + generic map ( + CDWIDTH => CDWIDTH, + CDINIT => CDINIT, + RXFAWIDTH => IFAWIDTH, + TXFAWIDTH => OFAWIDTH) + port map ( + CLKU => CLK, + RESET => RESET, + CLKS => CLKS, + CES_MSEC => CES_MSEC, + ENAXON => ENAXON, + ENAESC => '0', -- escaping now in rlink_core8 + RXDATA => RLB_DI, + RXVAL => RLB_ENA, + RXHOLD => RLB_BUSY, + TXDATA => RLB_DO, + TXENA => RLB_VAL, + TXBUSY => RLB_HOLD, + MONI => SER_MONI, + RXSD => RXSD, + TXSD => TXSD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N + ); + + RBMON : if RBMON_AWIDTH > 0 generate -- rbus monitor -------------- + begin + I0 : rbd_rbmon + generic map ( + RB_ADDR => RBMON_RBADDR, + AWIDTH => RBMON_AWIDTH) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ_M, + RB_SRES => RB_SRES_RBMON, + RB_SRES_SUM => RB_SRES_M + ); + end generate RBMON; + + RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- + port map ( + RB_SRES_1 => RB_SRES, + RB_SRES_2 => RB_SRES_RBMON, + RB_SRES_OR => RB_SRES_M + ); + + RB_MREQ <= RB_MREQ_M; -- setup output signals + +end syn; diff --git a/rtl/vlib/rlink/rlinklib.vhd b/rtl/vlib/rlink/rlinklib.vhd index 53f57487..0576425f 100644 --- a/rtl/vlib/rlink/rlinklib.vhd +++ b/rtl/vlib/rlink/rlinklib.vhd @@ -1,6 +1,6 @@ --- $Id: rlinklib.vhd 672 2015-05-02 21:58:28Z mueller $ +-- $Id: rlinklib.vhd 755 2016-03-28 17:59:59Z mueller $ -- --- Copyright 2007-2015 by Walter F.J. Mueller +-- Copyright 2007-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,11 +16,12 @@ -- Description: Definitions for rlink interface and bus entities -- -- Dependencies: - --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- -- Revision History: -- Date Rev Version Comment -- +-- 2016-03-28 755 4.2 add rlink_sp2c -- 2015-04-11 666 4.1.2 rlink_core8: add ESC(XON|FILL); -- rlink_sp1c: rename ENAESC->ESCFILL -- 2015-02-21 649 4.1.1 add ioleds_sp1c @@ -253,6 +254,42 @@ component rlink_sp1c is -- rlink_core8+serport_1clock combo ); end component; +component rlink_sp2c is -- rlink_core8+serport_2clock2 combo + generic ( + BTOWIDTH : positive := 5; -- rbus timeout counter width + RTAWIDTH : positive := 12; -- retransmit buffer address width + SYSID : slv32 := (others=>'0'); -- rlink system id + IFAWIDTH : natural := 5; -- input fifo address width (0=none) + OFAWIDTH : natural := 5; -- output fifo address width (0=none) + ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none) + ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none) + ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none) + CDWIDTH : positive := 13; -- clk divider width + CDINIT : natural := 15; -- clk divider initial/reset setting + RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none) + RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr + port ( + CLK : in slbit; -- U|clock (user design) + CE_USEC : in slbit; -- U|1 usec clock enable + CE_MSEC : in slbit; -- U|1 msec clock enable + CE_INT : in slbit := '0'; -- U|rri ato time unit clock enable + RESET : in slbit; -- U|reset + CLKS : in slbit; -- S|clock (frontend:serial) + CES_MSEC : in slbit; -- S|1 msec clock enable + ENAXON : in slbit; -- U|enable xon/xoff handling + ESCFILL : in slbit; -- U|enable fill escaping + RXSD : in slbit; -- S|receive serial data (board view) + TXSD : out slbit; -- S|transmit serial data (board view) + CTS_N : in slbit := '0'; -- S|clear to send (act.low, board view) + RTS_N : out slbit; -- S|request to send (act.low, brd view) + RB_MREQ : out rb_mreq_type; -- U|rbus: request + RB_SRES : in rb_sres_type; -- U|rbus: response + RB_LAM : in slv16; -- U|rbus: look at me + RB_STAT : in slv4; -- U|rbus: status flags + RL_MONI : out rl_moni_type; -- U|rlink_core: monitor port + SER_MONI : out serport_moni_type -- U|serport: monitor port + ); +end component; -- -- io activity leds -- diff --git a/rtl/vlib/rlink/tb/Makefile.ise b/rtl/vlib/rlink/tb/Makefile.ise index 9ce67720..5966b72e 100644 --- a/rtl/vlib/rlink/tb/Makefile.ise +++ b/rtl/vlib/rlink/tb/Makefile.ise @@ -1,4 +1,5 @@ -# $Id: Makefile.ise 744 2016-03-13 20:28:25Z mueller $ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ # # Revision History: # Date Rev Version Comment diff --git a/rtl/vlib/rlink/tb/tb_rlink.vbom b/rtl/vlib/rlink/tb/tb_rlink.vbom index e1afed26..f152e92e 100644 --- a/rtl/vlib/rlink/tb/tb_rlink.vbom +++ b/rtl/vlib/rlink/tb/tb_rlink.vbom @@ -16,7 +16,7 @@ ../../simlib/simclkcnt.vbom ../../genlib/clkdivce.vbom ../../rbus/rbd_tester.vbom -@uut: ${uut := tbd_rlink_direct.vbom} +${uut := tbd_rlink_direct.vbom} -UUT # design tb_rlink.vhd @top:tb_rlink diff --git a/rtl/vlib/rlink/tb/tbd_rlink_direct.vbom b/rtl/vlib/rlink/tb/tbd_rlink_direct.vbom index b35ffad0..7b3b444b 100644 --- a/rtl/vlib/rlink/tb/tbd_rlink_direct.vbom +++ b/rtl/vlib/rlink/tb/tbd_rlink_direct.vbom @@ -6,3 +6,4 @@ ../rlink_core.vbom # design tbd_rlink_direct.vhd +@xdc:../../generic_clk_100mhz.xdc diff --git a/rtl/vlib/rlink/tb/tbd_rlink_sp1c.vbom b/rtl/vlib/rlink/tb/tbd_rlink_sp1c.vbom index 761c6b32..2d79a82e 100644 --- a/rtl/vlib/rlink/tb/tbd_rlink_sp1c.vbom +++ b/rtl/vlib/rlink/tb/tbd_rlink_sp1c.vbom @@ -15,3 +15,4 @@ ${tbu_rlink_sp1c := tbu_rlink_sp1c.vbom} ../../simlib/simclkcnt.vbom # design tbd_rlink_sp1c.vhd +@xdc:../../generic_clk_100mhz.xdc diff --git a/rtl/vlib/rlink/tb/tbu_rlink_sp1c.vbom b/rtl/vlib/rlink/tb/tbu_rlink_sp1c.vbom index 68641d02..81a92177 100644 --- a/rtl/vlib/rlink/tb/tbu_rlink_sp1c.vbom +++ b/rtl/vlib/rlink/tb/tbu_rlink_sp1c.vbom @@ -6,3 +6,4 @@ ../rlink_sp1c.vbom # design tbu_rlink_sp1c.vhd +@xdc:../../generic_clk_100mhz.xdc diff --git a/rtl/vlib/rlink/tbcore/rlink_cext_iface_dpi.sv b/rtl/vlib/rlink/tbcore/rlink_cext_iface_dpi.sv index c8e500b7..1cc35b72 100644 --- a/rtl/vlib/rlink/tbcore/rlink_cext_iface_dpi.sv +++ b/rtl/vlib/rlink/tbcore/rlink_cext_iface_dpi.sv @@ -1,4 +1,4 @@ -// $Id: rlink_cext_iface_dpi.sv 731 2016-02-14 21:07:14Z mueller $ +// $Id: rlink_cext_iface_dpi.sv 778 2016-06-25 15:18:01Z mueller $ // // Copyright 2016- by Walter F.J. Mueller // @@ -20,13 +20,16 @@ // To test: - // // Target Devices: generic -// Tool versions: viv 2015.4 +// Tool versions: viv 2015.4-2016.3 // Revision History: // Date Rev Version Comment +// 2016-06-25 778 1.0.1 add timescale +// 2016-04-17 762 1.0 Initial version // 2016-02-07 729 0.1 First draft //---------------------------------------------------------------------------- `default_nettype none +`timescale 1 ps / 1 ps package rlink_cext_dpi; import "DPI-C" function int rlink_cext_getbyte_dpi(input int clk); @@ -46,26 +49,26 @@ module rlink_cext_iface(input wire clk, int itxrc = 0; int icycle = 0; int irxdata = 0; - reg r_rxval = 1'b0; - int r_rxdata = 0; initial rx_data = 8'b00000000; initial rx_val = 1'b0; always @ (posedge clk) begin + //$display("+++tx1: ena: %b; data: %b", tx_ena, tx_data); if (tx_ena) begin itxdata = tx_data; itxrc = rlink_cext_dpi::rlink_cext_putbyte_dpi(itxdata); if (itxrc != 0) begin - $display("rlink_cext_putbyte error: ", itxrc); + $display("rlink_cext_putbyte error: %d", itxrc); $finish; end end end always @ (posedge clk) begin - if (~rx_hold | ~r_rxval ) begin - icycle = clk_cycle; + icycle = clk_cycle; + //$display("+++rx1: cyc: %4d; hold: %b; val: %b", icycle, rx_hold, rx_val); + if (~rx_hold | ~rx_val ) begin irxdata = rlink_cext_dpi::rlink_cext_getbyte_dpi(icycle); rx_data <= irxdata; rx_val <= irxdata >= 0; diff --git a/rtl/vlib/serport/Makefile b/rtl/vlib/serport/Makefile.ise similarity index 89% rename from rtl/vlib/serport/Makefile rename to rtl/vlib/serport/Makefile.ise index 674d3367..434f1da9 100644 --- a/rtl/vlib/serport/Makefile +++ b/rtl/vlib/serport/Makefile.ise @@ -1,4 +1,5 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ # # Revision History: # Date Rev Version Comment diff --git a/rtl/vlib/serport/serport_1clock.vhd b/rtl/vlib/serport/serport_1clock.vhd index 448ec5e2..d7c0d6ad 100644 --- a/rtl/vlib/serport/serport_1clock.vhd +++ b/rtl/vlib/serport/serport_1clock.vhd @@ -1,4 +1,4 @@ --- $Id: serport_1clock.vhd 666 2015-04-12 21:17:54Z mueller $ +-- $Id: serport_1clock.vhd 748 2016-03-20 15:18:50Z mueller $ -- -- Copyright 2011-2015 by Walter F.J. Mueller -- @@ -185,7 +185,7 @@ begin SIZE => RXFIFO_SIZE ); - TXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based + TXFIFO : fifo_1c_dram -- output fifo, 1 clock, dram based generic map ( AWIDTH => TXFAWIDTH, DWIDTH => 8) diff --git a/rtl/vlib/serport/serport_2clock.vbom b/rtl/vlib/serport/serport_2clock.vbom index 0dff738a..ba3d2b61 100644 --- a/rtl/vlib/serport/serport_2clock.vbom +++ b/rtl/vlib/serport/serport_2clock.vbom @@ -1,10 +1,10 @@ # libs ../slvtypes.vhd serportlib.vbom -../genlib/genlib.vhd +../cdclib/cdclib.vhd ../memlib/memlib.vhd # components -../genlib/cdc_pulse.vbom +../cdclib/cdc_pulse.vbom serport_uart_rxtx_ab.vbom serport_xonrx.vbom serport_xontx.vbom diff --git a/rtl/vlib/serport/serport_2clock.vhd b/rtl/vlib/serport/serport_2clock.vhd index bad11409..439c8035 100644 --- a/rtl/vlib/serport/serport_2clock.vhd +++ b/rtl/vlib/serport/serport_2clock.vhd @@ -1,4 +1,4 @@ --- $Id: serport_2clock.vhd 666 2015-04-12 21:17:54Z mueller $ +-- $Id: serport_2clock.vhd 757 2016-04-02 11:19:06Z mueller $ -- -- Copyright 2011-2015 by Walter F.J. Mueller -- @@ -15,7 +15,7 @@ -- Module Name: serport_2clock - syn -- Description: serial port: serial port module, 2 clock domain -- --- Dependencies: genlib/cdc_pulse +-- Dependencies: cdclib/cdc_pulse -- serport_uart_rxtx_ab -- serport_xonrx -- serport_xontx @@ -31,6 +31,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-03-28 755 1.1.2 check assertions only at raising clock -- 2015-04-11 666 1.1.1 add sim assertions for RXOVR and RXERR -- 2015-02-01 641 1.1 add CLKDIV_F for autobaud; -- 2011-12-10 438 1.0.2 internal reset on abact @@ -45,7 +46,7 @@ use ieee.numeric_std.all; use work.slvtypes.all; use work.serportlib.all; -use work.genlib.all; +use work.cdclib.all; use work.memlib.all; entity serport_2clock is -- serial port module, 2 clock domain @@ -389,12 +390,16 @@ begin proc_check: process (CLKS) begin - assert RXOVR = '0' - report "serport_2clock-W: RXOVR = '1'; data loss in receive fifo" - severity warning; - assert RXERR = '0' - report "serport_2clock-W: RXERR = '1'; spurious receive error" - severity warning; + if rising_edge(CLKS) then + assert RXOVR = '0' + report "serport_2clock-W: RXOVR = " & slbit'image(RXOVR) & + "; data loss in receive fifo" + severity warning; + assert RXERR = '0' + report "serport_2clock-W: RXERR = " & slbit'image(RXERR) & + "; spurious receive error" + severity warning; + end if; end process proc_check; -- synthesis translate_on diff --git a/rtl/vlib/serport/serport_2clock2.vbom b/rtl/vlib/serport/serport_2clock2.vbom new file mode 100644 index 00000000..d06a3854 --- /dev/null +++ b/rtl/vlib/serport/serport_2clock2.vbom @@ -0,0 +1,15 @@ +# libs +../slvtypes.vhd +serportlib.vbom +../cdclib/cdclib.vhd +../memlib/memlib.vhd +# components +../cdclib/cdc_pulse.vbom +../cdclib/cdc_signal_s1.vbom +../cdclib/cdc_vector_s0.vbom +serport_uart_rxtx_ab.vbom +serport_xonrx.vbom +serport_xontx.vbom +../memlib/fifo_2c_dram2.vbom +# design +serport_2clock2.vhd diff --git a/rtl/vlib/serport/serport_2clock2.vhd b/rtl/vlib/serport/serport_2clock2.vhd new file mode 100644 index 00000000..3db8fc09 --- /dev/null +++ b/rtl/vlib/serport/serport_2clock2.vhd @@ -0,0 +1,386 @@ +-- $Id: serport_2clock2.vhd 759 2016-04-09 10:13:57Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: serport_2clock2 - syn +-- Description: serial port: serial port module, 2 clock domain (v2) +-- +-- Dependencies: cdclib/cdc_pulse +-- cdclib/cdc_signal_s1 +-- cdclib/cdc_vector_s0 +-- serport_uart_rxtx_ab +-- serport_xonrx +-- serport_xontx +-- memlib/fifo_2c_dram2 +-- Test bench: - +-- Target Devices: generic +-- Tool versions: viv 2015.4; ghdl 0.33 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-04-08 759 1.1 all cdc's via cdc_(pulse|signal|vector) +-- 2016-03-28 755 1.0.1 check assertions only at raising clock +-- 2016-03-25 752 1.0 Initial version (derived from serport_2clock, is +-- exactly same logic, re-written to allow proper +-- usage of vivado constraints) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.serportlib.all; +use work.cdclib.all; +use work.memlib.all; + +entity serport_2clock2 is -- serial port module, 2 clock dom. (v2) + generic ( + CDWIDTH : positive := 13; -- clk divider width + CDINIT : natural := 15; -- clk divider initial/reset setting + RXFAWIDTH : natural := 5; -- rx fifo address width + TXFAWIDTH : natural := 5); -- tx fifo address width + port ( + CLKU : in slbit; -- U|clock (backend:user) + RESET : in slbit; -- U|reset + CLKS : in slbit; -- S|clock (frontend:serial) + CES_MSEC : in slbit; -- S|1 msec clock enable + ENAXON : in slbit; -- U|enable xon/xoff handling + ENAESC : in slbit; -- U|enable xon/xoff escaping + RXDATA : out slv8; -- U|receiver data out + RXVAL : out slbit; -- U|receiver data valid + RXHOLD : in slbit; -- U|receiver data hold + TXDATA : in slv8; -- U|transmit data in + TXENA : in slbit; -- U|transmit data enable + TXBUSY : out slbit; -- U|transmit busy + MONI : out serport_moni_type; -- U|serport monitor port + RXSD : in slbit; -- S|receive serial data (uart view) + TXSD : out slbit; -- S|transmit serial data (uart view) + RXRTS_N : out slbit; -- S|receive rts (uart view, act.low) + TXCTS_N : in slbit -- S|transmit cts (uart view, act.low) + ); +end serport_2clock2; + + +architecture syn of serport_2clock2 is + + subtype cd_range is integer range CDWIDTH-1 downto 0; -- clk div value regs + + signal RXACT_U : slbit := '0'; -- rxact in CLKU + signal TXACT_U : slbit := '0'; -- txact in CLKU + signal ABACT_U : slbit := '0'; -- abact in CLKU + signal RXOK_U : slbit := '0'; -- rxok in CLKU + signal TXOK_U : slbit := '0'; -- txok in CLKU + + signal ABCLKDIV_U : slv(cd_range) := (others=>'0'); -- abclkdiv + signal ABCLKDIV_F_U: slv3 := (others=>'0'); -- abclkdiv_f + + signal ENAXON_S : slbit := '0'; -- enaxon in CLKS + signal ENAESC_S : slbit := '0'; -- enaesc in CLKS + + signal R_RXOK : slbit := '1'; + + signal RESET_INT : slbit := '0'; + signal RESET_CLKS : slbit := '0'; + + signal UART_RXDATA : slv8 := (others=>'0'); + signal UART_RXVAL : slbit := '0'; + signal UART_TXDATA : slv8 := (others=>'0'); + signal UART_TXENA : slbit := '0'; + signal UART_TXBUSY : slbit := '0'; + + signal XONTX_TXENA : slbit := '0'; + signal XONTX_TXBUSY : slbit := '0'; + + signal RXFIFO_DI : slv8 := (others=>'0'); + signal RXFIFO_ENA : slbit := '0'; + signal RXFIFO_BUSY : slbit := '0'; + signal RXFIFO_SIZEW : slv(RXFAWIDTH-1 downto 0) := (others=>'0'); + signal TXFIFO_DO : slv8 := (others=>'0'); + signal TXFIFO_VAL : slbit := '0'; + signal TXFIFO_HOLD : slbit := '0'; + + signal RXERR : slbit := '0'; + signal RXOVR : slbit := '0'; + signal RXACT : slbit := '0'; + signal ABACT : slbit := '0'; + signal ABDONE : slbit := '0'; + signal ABCLKDIV : slv(cd_range) := (others=>'0'); + signal ABCLKDIV_F : slv3 := (others=>'0'); + + signal TXOK : slbit := '0'; + signal RXOK : slbit := '0'; + + signal RXERR_U : slbit := '0'; + signal RXOVR_U : slbit := '0'; + signal ABDONE_U : slbit := '0'; + +begin + + assert CDWIDTH<=16 + report "assert(CDWIDTH<=16): max width of UART clock divider" + severity failure; + + -- sync CLKU->CLKS + CDC_RESET : cdc_pulse -- provide CLKS side RESET + generic map ( + POUT_SINGLE => false, + BUSY_WACK => false) + port map ( + CLKM => CLKU, + RESET => '0', + CLKS => CLKS, + PIN => RESET, + BUSY => open, + POUT => RESET_CLKS + ); + + CDC_ENAXON: cdc_signal_s1 + port map (CLKO => CLKS, DI => ENAXON, DO => ENAXON_S); + CDC_ENAESC: cdc_signal_s1 + port map (CLKO => CLKS, DI => ENAESC, DO => ENAESC_S); + + UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo + generic map ( + CDWIDTH => CDWIDTH, + CDINIT => CDINIT) + port map ( + CLK => CLKS, + CE_MSEC => CES_MSEC, + RESET => RESET_CLKS, + RXSD => RXSD, + RXDATA => UART_RXDATA, + RXVAL => UART_RXVAL, + RXERR => RXERR, + RXACT => RXACT, + TXSD => TXSD, + TXDATA => UART_TXDATA, + TXENA => UART_TXENA, + TXBUSY => UART_TXBUSY, + ABACT => ABACT, + ABDONE => ABDONE, + ABCLKDIV => ABCLKDIV, + ABCLKDIV_F => ABCLKDIV_F + ); + + RESET_INT <= RESET_CLKS or ABACT; + + XONRX : serport_xonrx -- xon/xoff logic rx path + port map ( + CLK => CLKS, + RESET => RESET_INT, + ENAXON => ENAXON_S, + ENAESC => ENAESC_S, + UART_RXDATA => UART_RXDATA, + UART_RXVAL => UART_RXVAL, + RXDATA => RXFIFO_DI, + RXVAL => RXFIFO_ENA, + RXHOLD => RXFIFO_BUSY, + RXOVR => RXOVR, + TXOK => TXOK + ); + + XONTX : serport_xontx -- xon/xoff logic tx path + port map ( + CLK => CLKS, + RESET => RESET_INT, + ENAXON => ENAXON_S, + ENAESC => ENAESC_S, + UART_TXDATA => UART_TXDATA, + UART_TXENA => XONTX_TXENA, + UART_TXBUSY => XONTX_TXBUSY, + TXDATA => TXFIFO_DO, + TXENA => TXFIFO_VAL, + TXBUSY => TXFIFO_HOLD, + RXOK => RXOK, + TXOK => TXOK + ); + + RXFIFO : fifo_2c_dram2 -- input fifo, 2 clock, dram based + generic map ( + AWIDTH => RXFAWIDTH, + DWIDTH => 8) + port map ( + CLKW => CLKS, + CLKR => CLKU, + RESETW => ABACT, -- clear fifo on abact + RESETR => RESET, + DI => RXFIFO_DI, + ENA => RXFIFO_ENA, + BUSY => RXFIFO_BUSY, + DO => RXDATA, + VAL => RXVAL, + HOLD => RXHOLD, + SIZEW => RXFIFO_SIZEW, + SIZER => open + ); + + TXFIFO : fifo_2c_dram2 -- output fifo, 2 clock, dram based + generic map ( + AWIDTH => TXFAWIDTH, + DWIDTH => 8) + port map ( + CLKW => CLKU, + CLKR => CLKS, + RESETW => RESET, + RESETR => ABACT, -- clear fifo on abact + DI => TXDATA, + ENA => TXENA, + BUSY => TXBUSY, + DO => TXFIFO_DO, + VAL => TXFIFO_VAL, + HOLD => TXFIFO_HOLD, + SIZEW => open, + SIZER => open + ); + + -- receive back preasure + -- on if fifo more than 3/4 full (less than 1/4 free) + -- off if fifo less than 1/2 full (more than 1/2 free) + proc_rxok: process (CLKS) + constant rxsize_rxok_off : slv2 := "01"; + constant rxsize_rxok_on : slv2 := "10"; + variable rxsize_msb : slv2 := "00"; + begin + if rising_edge(CLKS) then + if RESET_INT = '1' then + R_RXOK <= '1'; + else + rxsize_msb := RXFIFO_SIZEW(RXFAWIDTH-1 downto RXFAWIDTH-2); + if unsigned(rxsize_msb) < unsigned(rxsize_rxok_off) then + R_RXOK <= '0'; + elsif unsigned(RXSIZE_MSB) >= unsigned(rxsize_rxok_on) then + R_RXOK <= '1'; + end if; + end if; + end if; + end process proc_rxok; + + RXOK <= R_RXOK; + RXRTS_N <= not R_RXOK; + + proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY) + begin + if TXCTS_N = '0' then -- transmit cts asserted + UART_TXENA <= XONTX_TXENA; + XONTX_TXBUSY <= UART_TXBUSY; + else -- transmit cts not asserted + UART_TXENA <= '0'; + XONTX_TXBUSY <= '1'; + end if; + end process proc_cts; + + -- sync CLKS->CLKU + CDC_RXACT : cdc_signal_s1 + port map (CLKO => CLKU, DI => RXACT, DO => RXACT_U); + CDC_TXACT : cdc_signal_s1 + port map (CLKO => CLKU, DI => UART_TXBUSY, DO => TXACT_U); + CDC_ABACT : cdc_signal_s1 + port map (CLKO => CLKU, DI => ABACT, DO => ABACT_U); + CDC_RXOK : cdc_signal_s1 + port map (CLKO => CLKU, DI => RXOK, DO => RXOK_U); + CDC_TXOK : cdc_signal_s1 + port map (CLKO => CLKU, DI => TXOK, DO => TXOK_U); + + CDC_CDIV : cdc_vector_s0 + generic map ( + DWIDTH => CDWIDTH) + port map ( + CLKO => CLKU, + DI => ABCLKDIV, + DO => ABCLKDIV_U + ); + + CDC_CDIVF : cdc_vector_s0 + generic map ( + DWIDTH => 3) + port map ( + CLKO => CLKU, + DI => ABCLKDIV_F, + DO => ABCLKDIV_F_U + ); + + CDC_RXERR : cdc_pulse + generic map ( + POUT_SINGLE => true, + BUSY_WACK => false) + port map ( + CLKM => CLKS, + RESET => '0', + CLKS => CLKU, + PIN => RXERR, + BUSY => open, + POUT => RXERR_U + ); + + CDC_RXOVR : cdc_pulse + generic map ( + POUT_SINGLE => true, + BUSY_WACK => false) + port map ( + CLKM => CLKS, + RESET => '0', + CLKS => CLKU, + PIN => RXOVR, + BUSY => open, + POUT => RXOVR_U + ); + + CDC_ABDONE : cdc_pulse + generic map ( + POUT_SINGLE => true, + BUSY_WACK => false) + port map ( + CLKM => CLKS, + RESET => '0', + CLKS => CLKU, + PIN => ABDONE, + BUSY => open, + POUT => ABDONE_U + ); + + MONI.rxerr <= RXERR_U; + MONI.rxovr <= RXOVR_U; + MONI.rxact <= RXACT_U; + MONI.txact <= TXACT_U; + MONI.abact <= ABACT_U; + MONI.abdone <= ABDONE_U; + MONI.rxok <= RXOK_U; + MONI.txok <= TXOK_U; + + proc_abclkdiv: process (ABCLKDIV_U, ABCLKDIV_F_U) + begin + MONI.abclkdiv <= (others=>'0'); + MONI.abclkdiv(ABCLKDIV_U'range) <= ABCLKDIV_U; + MONI.abclkdiv_f <= ABCLKDIV_F_U; + end process proc_abclkdiv; + +-- synthesis translate_off + + proc_check: process (CLKS) + begin + if rising_edge(CLKS) then + assert RXOVR = '0' + report "serport_2clock2-W: RXOVR = " & slbit'image(RXOVR) & + "; data loss in receive fifo" + severity warning; + assert RXERR = '0' + report "serport_2clock2-W: RXERR = " & slbit'image(RXERR) & + "; spurious receive error" + severity warning; + end if; + end process proc_check; + +-- synthesis translate_on + +end syn; diff --git a/rtl/vlib/serport/serport_uart_autobaud.vhd b/rtl/vlib/serport/serport_uart_autobaud.vhd index 2abe3497..965b3ca3 100644 --- a/rtl/vlib/serport/serport_uart_autobaud.vhd +++ b/rtl/vlib/serport/serport_uart_autobaud.vhd @@ -1,4 +1,4 @@ --- $Id: serport_uart_autobaud.vhd 734 2016-02-20 22:43:20Z mueller $ +-- $Id: serport_uart_autobaud.vhd 774 2016-06-12 17:08:47Z mueller $ -- -- Copyright 2007-2016 by Walter F.J. Mueller -- @@ -18,9 +18,10 @@ -- Dependencies: - -- Test bench: tb/tb_serport_autobaud -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-05-22 787 1.1.1 don't init N_REGS (vivado fix for fsm inference) -- 2015-02-01 641 1.1 add CLKDIV_F -- 2011-10-22 417 1.0.4 now numeric_std clean -- 2010-04-18 279 1.0.3 change ccnt start value to -3, better rounding @@ -28,9 +29,9 @@ -- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned -- 2007-06-30 62 1.0 Initial version ------------------------------------------------------------------------------ --- Note: for test bench usage a copy of all serport_* entities, with _tb --- appended to the name, has been created in the /tb sub folder. --- Ensure to update the copy when this file is changed !! +-- NOTE: for test bench usage a copy of all serport_* entities, with _tb +-- !!!! appended to the name, has been created in the /tb sub folder. +-- !!!! Ensure to update the copy when this file is changed !! library ieee; use ieee.std_logic_1164.all; @@ -91,14 +92,14 @@ architecture syn of serport_uart_autobaud is s_idle ); - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs - + signal R_REGS : regs_type := regs_init; + signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) + begin assert CDINIT <= 2**CDWIDTH-1 report "assert(CDINIT <= 2**CDWIDTH-1): CDINIT too large for given CDWIDTH" - severity FAILURE; + severity failure; proc_regs: process (CLK) begin diff --git a/rtl/vlib/serport/serport_uart_rx.vhd b/rtl/vlib/serport/serport_uart_rx.vhd index d5219d63..8d4c259d 100644 --- a/rtl/vlib/serport/serport_uart_rx.vhd +++ b/rtl/vlib/serport/serport_uart_rx.vhd @@ -1,4 +1,4 @@ --- $Id: serport_uart_rx.vhd 734 2016-02-20 22:43:20Z mueller $ +-- $Id: serport_uart_rx.vhd 774 2016-06-12 17:08:47Z mueller $ -- -- Copyright 2007-2016 by Walter F.J. Mueller -- @@ -24,9 +24,10 @@ -- Dependencies: - -- Test bench: tb/tb_serport_uart_rxtx -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-05-22 787 2.0.4 don't init N_REGS (vivado fix for fsm inference) -- 2011-10-22 417 2.0.3 now numeric_std clean -- 2009-07-12 233 2.0.2 remove snoopers -- 2008-03-02 121 2.0.1 comment out snoopers @@ -41,9 +42,9 @@ -- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned -- 2007-06-30 62 1.0 Initial version ------------------------------------------------------------------------------ --- Note: for test bench usage a copy of all serport_* entities, with _tb --- appended to the name, has been created in the /tb sub folder. --- Ensure to update the copy when this file is changed !! +-- NOTE: for test bench usage a copy of all serport_* entities, with _tb +-- !!!! appended to the name, has been created in the /tb sub folder. +-- !!!! Ensure to update the copy when this file is changed !! library ieee; use ieee.std_logic_1164.all; @@ -97,9 +98,9 @@ architecture syn of serport_uart_rx is (others=>'0') -- sreg ); - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs - + signal R_REGS : regs_type := regs_init; + signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) + begin proc_regs: process (CLK) diff --git a/rtl/vlib/serport/serport_uart_rxtx.vhd b/rtl/vlib/serport/serport_uart_rxtx.vhd index 8282d9aa..887c6cb7 100644 --- a/rtl/vlib/serport/serport_uart_rxtx.vhd +++ b/rtl/vlib/serport/serport_uart_rxtx.vhd @@ -1,4 +1,4 @@ --- $Id: serport_uart_rxtx.vhd 734 2016-02-20 22:43:20Z mueller $ +-- $Id: serport_uart_rxtx.vhd 774 2016-06-12 17:08:47Z mueller $ -- -- Copyright 2007-2016 by Walter F.J. Mueller -- @@ -19,14 +19,14 @@ -- serport_uart_tx -- Test bench: tb/tb_serport_uart_rxtx -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment -- 2007-06-24 60 1.0 Initial version ------------------------------------------------------------------------------ --- Note: for test bench usage a copy of all serport_* entities, with _tb --- appended to the name, has been created in the /tb sub folder. --- Ensure to update the copy when this file is changed !! +-- NOTE: for test bench usage a copy of all serport_* entities, with _tb +-- !!!! appended to the name, has been created in the /tb sub folder. +-- !!!! Ensure to update the copy when this file is changed !! library ieee; use ieee.std_logic_1164.all; diff --git a/rtl/vlib/serport/serport_uart_rxtx_ab.vhd b/rtl/vlib/serport/serport_uart_rxtx_ab.vhd index 63d80cd5..9905c9d4 100644 --- a/rtl/vlib/serport/serport_uart_rxtx_ab.vhd +++ b/rtl/vlib/serport/serport_uart_rxtx_ab.vhd @@ -1,4 +1,4 @@ --- $Id: serport_uart_rxtx_ab.vhd 734 2016-02-20 22:43:20Z mueller $ +-- $Id: serport_uart_rxtx_ab.vhd 774 2016-06-12 17:08:47Z mueller $ -- -- Copyright 2007-2016 by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- serport_uart_rxtx -- Test bench: - -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -33,9 +33,9 @@ -- 2010-12-26 348 1.1 add ABCLKDIV port for clock divider setting -- 2007-06-24 60 1.0 Initial version ------------------------------------------------------------------------------ --- Note: for test bench usage a copy of all serport_* entities, with _tb --- appended to the name, has been created in the /tb sub folder. --- Ensure to update the copy when this file is changed !! +-- NOTE: for test bench usage a copy of all serport_* entities, with _tb +-- !!!! appended to the name, has been created in the /tb sub folder. +-- !!!! Ensure to update the copy when this file is changed !! library ieee; use ieee.std_logic_1164.all; diff --git a/rtl/vlib/serport/serport_uart_tx.vhd b/rtl/vlib/serport/serport_uart_tx.vhd index 1ec37e12..aaa8e7d6 100644 --- a/rtl/vlib/serport/serport_uart_tx.vhd +++ b/rtl/vlib/serport/serport_uart_tx.vhd @@ -1,4 +1,4 @@ --- $Id: serport_uart_tx.vhd 734 2016-02-20 22:43:20Z mueller $ +-- $Id: serport_uart_tx.vhd 774 2016-06-12 17:08:47Z mueller $ -- -- Copyright 2007-2016 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_serport_uart_rxtx -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment -- 2011-10-22 417 1.0.4 now numeric_std clean @@ -27,9 +27,9 @@ -- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned -- 2007-06-30 62 1.0 Initial version ------------------------------------------------------------------------------ --- Note: for test bench usage a copy of all serport_* entities, with _tb --- appended to the name, has been created in the /tb sub folder. --- Ensure to update the copy when this file is changed !! +-- NOTE: for test bench usage a copy of all serport_* entities, with _tb +-- !!!! appended to the name, has been created in the /tb sub folder. +-- !!!! Ensure to update the copy when this file is changed !! library ieee; use ieee.std_logic_1164.all; diff --git a/rtl/vlib/serport/serport_xonrx.vhd b/rtl/vlib/serport/serport_xonrx.vhd index f8832deb..181f186e 100644 --- a/rtl/vlib/serport/serport_xonrx.vhd +++ b/rtl/vlib/serport/serport_xonrx.vhd @@ -1,4 +1,4 @@ --- $Id: serport_xonrx.vhd 734 2016-02-20 22:43:20Z mueller $ +-- $Id: serport_xonrx.vhd 774 2016-06-12 17:08:47Z mueller $ -- -- Copyright 2011-2016 by Walter F.J. Mueller -- @@ -18,14 +18,14 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31 +-- Tool versions: ise 13.1-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33 -- Revision History: -- Date Rev Version Comment -- 2011-10-22 417 1.0 Initial version ------------------------------------------------------------------------------ --- Note: for test bench usage a copy of all serport_* entities, with _tb --- appended to the name, has been created in the /tb sub folder. --- Ensure to update the copy when this file is changed !! +-- NOTE: for test bench usage a copy of all serport_* entities, with _tb +-- !!!! appended to the name, has been created in the /tb sub folder. +-- !!!! Ensure to update the copy when this file is changed !! library ieee; use ieee.std_logic_1164.all; diff --git a/rtl/vlib/serport/serportlib.vhd b/rtl/vlib/serport/serportlib.vhd index 127c9b76..19069dd2 100644 --- a/rtl/vlib/serport/serportlib.vhd +++ b/rtl/vlib/serport/serportlib.vhd @@ -1,4 +1,4 @@ --- $Id: serportlib.vhd 724 2016-01-03 22:53:53Z mueller $ +-- $Id: serportlib.vhd 755 2016-03-28 17:59:59Z mueller $ -- -- Copyright 2007-2016 by Walter F.J. Mueller -- @@ -16,10 +16,11 @@ -- Description: serial port interface components -- -- Dependencies: - --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- -- Revision History: -- Date Rev Version Comment +-- 2016-03-25 752 1.3.2 add serport_2clock2 -- 2015-04-11 666 1.3.1 add serport_master -- 2015-02-01 641 1.3 add CLKDIV_F for autobaud -- 2013-01-26 476 1.2.6 renamed package to serportlib @@ -32,7 +33,7 @@ -- 2007-10-22 88 1.1 renames (in prev revs); remove std_logic_unsigned -- 2007-06-03 45 1.0 Initial version ------------------------------------------------------------------------------ --- Note: for test bench usage a copy of all serport_* entities, with -tb +-- Note: for test bench usage a copy of many serport_* entities, with -tb -- appended to the name, has been created in the /tb sub folder. -- Ensure to update the copy when this file is changed !! @@ -243,6 +244,33 @@ component serport_2clock is -- serial port module, 2 clock domain ); end component; +component serport_2clock2 is -- serial port module, 2 clock dom. (v2) + generic ( + CDWIDTH : positive := 13; -- clk divider width + CDINIT : natural := 15; -- clk divider initial/reset setting + RXFAWIDTH : natural := 5; -- rx fifo address width + TXFAWIDTH : natural := 5); -- tx fifo address width + port ( + CLKU : in slbit; -- U|clock (backend:user) + RESET : in slbit; -- U|reset + CLKS : in slbit; -- S|clock (frontend:serial) + CES_MSEC : in slbit; -- S|1 msec clock enable + ENAXON : in slbit; -- U|enable xon/xoff handling + ENAESC : in slbit; -- U|enable xon/xoff escaping + RXDATA : out slv8; -- U|receiver data out + RXVAL : out slbit; -- U|receiver data valid + RXHOLD : in slbit; -- U|receiver data hold + TXDATA : in slv8; -- U|transmit data in + TXENA : in slbit; -- U|transmit data enable + TXBUSY : out slbit; -- U|transmit busy + MONI : out serport_moni_type; -- U|serport monitor port + RXSD : in slbit; -- S|receive serial data (uart view) + TXSD : out slbit; -- S|transmit serial data (uart view) + RXRTS_N : out slbit; -- S|receive rts (uart view, act.low) + TXCTS_N : in slbit -- S|transmit cts (uart view, act.low) + ); +end component; + component serport_master is -- serial port module, master side generic ( CDWIDTH : positive := 13); -- clk divider width diff --git a/rtl/vlib/serport/tb/Makefile b/rtl/vlib/serport/tb/Makefile new file mode 100644 index 00000000..5dc14047 --- /dev/null +++ b/rtl/vlib/serport/tb/Makefile @@ -0,0 +1,44 @@ +# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2016-02-06 727 1.0 Initial version +# +EXE_all = tb_serport_uart_rx +EXE_all += tb_serport_uart_rxtx +EXE_all += tb_serport_autobaud +# +# reference board for test synthesis is Artix-7 based Nexys4 +ifndef XTW_BOARD + XTW_BOARD=nexys4 +endif +include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk +# +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) +endif +# diff --git a/rtl/vlib/serport/tb/Makefile.ise b/rtl/vlib/serport/tb/Makefile.ise index 5b4b7b07..63857d28 100644 --- a/rtl/vlib/serport/tb/Makefile.ise +++ b/rtl/vlib/serport/tb/Makefile.ise @@ -1,4 +1,5 @@ -# $Id: Makefile.ise 733 2016-02-20 12:24:13Z mueller $ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ # # Revision History: # Date Rev Version Comment diff --git a/rtl/vlib/serport/tb/serport_uart_rx_tb.vhd b/rtl/vlib/serport/tb/serport_uart_rx_tb.vhd index 8a89f1ad..2521a5dd 100644 --- a/rtl/vlib/serport/tb/serport_uart_rx_tb.vhd +++ b/rtl/vlib/serport/tb/serport_uart_rx_tb.vhd @@ -1,4 +1,4 @@ --- $Id: serport_uart_rx_tb.vhd 724 2016-01-03 22:53:53Z mueller $ +-- $Id: serport_uart_rx_tb.vhd 767 2016-05-26 07:47:51Z mueller $ -- -- Copyright 2007-2016 by Walter F.J. Mueller -- @@ -26,6 +26,7 @@ -- Tool versions: ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment +-- 2016-05-22 787 1.0.1 don't init N_REGS (vivado fix for fsm inference) -- 2016-01-03 724 1.0 Initial version (copied from serport_uart_rx) ------------------------------------------------------------------------------ @@ -81,9 +82,9 @@ architecture sim of serport_uart_rx_tb is (others=>'0') -- sreg ); - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs - + signal R_REGS : regs_type := regs_init; + signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) + begin proc_regs: process (CLK) diff --git a/rtl/vlib/serport/tb/tb_serport_autobaud.vbom b/rtl/vlib/serport/tb/tb_serport_autobaud.vbom index d0760d6a..9bc971f1 100644 --- a/rtl/vlib/serport/tb/tb_serport_autobaud.vbom +++ b/rtl/vlib/serport/tb/tb_serport_autobaud.vbom @@ -5,6 +5,6 @@ # components ../../simlib/simclk.vbom ../../simlib/simclkcnt.vbom -@uut: ${uut := tbd_serport_autobaud.vbom} +${uut := tbd_serport_autobaud.vbom} -UUT # design tb_serport_autobaud.vhd diff --git a/rtl/vlib/serport/tb/tb_serport_uart_rx.vbom b/rtl/vlib/serport/tb/tb_serport_uart_rx.vbom index 9618919b..867f0400 100644 --- a/rtl/vlib/serport/tb/tb_serport_uart_rx.vbom +++ b/rtl/vlib/serport/tb/tb_serport_uart_rx.vbom @@ -5,6 +5,6 @@ # components ../../simlib/simclk.vbom ../../simlib/simclkcnt.vbom -@uut: ${uut := tbd_serport_uart_rx.vbom} +${uut := tbd_serport_uart_rx.vbom} -UUT # design tb_serport_uart_rx.vhd diff --git a/rtl/vlib/serport/tb/tb_serport_uart_rxtx.vbom b/rtl/vlib/serport/tb/tb_serport_uart_rxtx.vbom index d960e188..c1e36dee 100644 --- a/rtl/vlib/serport/tb/tb_serport_uart_rxtx.vbom +++ b/rtl/vlib/serport/tb/tb_serport_uart_rxtx.vbom @@ -5,6 +5,6 @@ # components ../../simlib/simclk.vbom ../../simlib/simclkcnt.vbom -@uut: ${uut := tbd_serport_uart_rxtx.vbom} +${uut := tbd_serport_uart_rxtx.vbom} -UUT # design tb_serport_uart_rxtx.vhd diff --git a/rtl/vlib/serport/tb/tbd_serport_autobaud.vbom b/rtl/vlib/serport/tb/tbd_serport_autobaud.vbom index 9936d14f..a2c25e9e 100644 --- a/rtl/vlib/serport/tb/tbd_serport_autobaud.vbom +++ b/rtl/vlib/serport/tb/tbd_serport_autobaud.vbom @@ -9,3 +9,4 @@ ../serport_uart_rx.vbom # design tbd_serport_autobaud.vhd +@xdc:../../generic_clk_100mhz.xdc diff --git a/rtl/vlib/serport/tb/tbd_serport_uart_rx.vbom b/rtl/vlib/serport/tb/tbd_serport_uart_rx.vbom index b4f45d34..fddd9d13 100644 --- a/rtl/vlib/serport/tb/tbd_serport_uart_rx.vbom +++ b/rtl/vlib/serport/tb/tbd_serport_uart_rx.vbom @@ -5,3 +5,4 @@ ../serport_uart_rx.vbom # design tbd_serport_uart_rx.vhd +@xdc:../../generic_clk_100mhz.xdc diff --git a/rtl/vlib/serport/tb/tbd_serport_uart_rxtx.vbom b/rtl/vlib/serport/tb/tbd_serport_uart_rxtx.vbom index 77301ddf..aea349f6 100644 --- a/rtl/vlib/serport/tb/tbd_serport_uart_rxtx.vbom +++ b/rtl/vlib/serport/tb/tbd_serport_uart_rxtx.vbom @@ -5,3 +5,4 @@ ../serport_uart_rxtx.vbom # design tbd_serport_uart_rxtx.vhd +@xdc:../../generic_clk_100mhz.xdc diff --git a/rtl/vlib/simlib/simlib.vhd b/rtl/vlib/simlib/simlib.vhd index fde5cee3..689a4e2e 100644 --- a/rtl/vlib/simlib/simlib.vhd +++ b/rtl/vlib/simlib/simlib.vhd @@ -1,6 +1,6 @@ --- $Id: simlib.vhd 599 2014-10-25 13:43:56Z mueller $ +-- $Id: simlib.vhd 774 2016-06-12 17:08:47Z mueller $ -- --- Copyright 2006-2014 by Walter F.J. Mueller +-- Copyright 2006-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,10 +18,11 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- Tool versions: xst 8.2-14.7; viv 2015.4-2016.2; ghdl 0.18-0.33 -- -- Revision History: -- Date Rev Version Comment +-- 2016-06-12 774 2.1.2 add writetimens() -- 2014-10-25 599 2.1.1 add wait_* procedures; writeoptint: no dat clear -- 2014-10-18 597 2.1 add simfifo_*, writetrace procedures -- 2014-09-06 591 2.0.1 add readint_ea() with range check @@ -206,6 +207,11 @@ procedure writegen( -- write slv in generic base (arb. lth) field: in width:=0; -- field width base: in integer:= 2); -- default base +procedure writetimens( -- write time as fractional ns + L: inout line; -- line + t : in time; -- time + field : in width:=0); -- number of ns digits + procedure writetimestamp( -- write time stamp L: inout line; -- line str : in string := null_string); -- 1st string field @@ -1162,10 +1168,10 @@ begin end procedure writegen; -- ------------------------------------- - -procedure writetimestamp( - L: inout line; - str : in string := null_string) is +procedure writetimens( -- write time as fractional ns + L: inout line; -- line + t : in time; -- time + field : in width:=0) is -- number of ns digits variable t_nsec : integer := 0; variable t_psec : integer := 0; @@ -1173,15 +1179,26 @@ procedure writetimestamp( begin - t_nsec := now / 1 ns; - t_psec := (now - t_nsec * 1 ns) / 1 ps; + t_nsec := t / 1 ns; + t_psec := (t - t_nsec * 1 ns) / 1 ps; t_dnsec := t_psec/100; - write(L, t_nsec, right, 8); + write(L, t_nsec, right, field); write(L,'.'); write(L, t_dnsec, right, 1); write(L, string'(" ns")); + +end procedure writetimens; +-- ------------------------------------- + +procedure writetimestamp( + L: inout line; + str : in string := null_string) is + +begin + + writetimens(L, now, 8); if str /= null_string then write(L, str); end if; diff --git a/rtl/vlib/xlib/Makefile b/rtl/vlib/xlib/Makefile.ise similarity index 89% rename from rtl/vlib/xlib/Makefile rename to rtl/vlib/xlib/Makefile.ise index fe839b03..eadc5218 100644 --- a/rtl/vlib/xlib/Makefile +++ b/rtl/vlib/xlib/Makefile.ise @@ -1,4 +1,5 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ # # Revision History: # Date Rev Version omment diff --git a/rtl/vlib/xlib/iob_keeper_gen.vbom b/rtl/vlib/xlib/iob_keeper_gen.vbom index 9ab3a257..78151d33 100644 --- a/rtl/vlib/xlib/iob_keeper_gen.vbom +++ b/rtl/vlib/xlib/iob_keeper_gen.vbom @@ -1,4 +1,5 @@ # libs ../slvtypes.vhd +xlib.vhd # design iob_keeper_gen.vhd diff --git a/rtl/vlib/xlib/iob_reg_i_gen.vbom b/rtl/vlib/xlib/iob_reg_i_gen.vbom index b8e64c4a..dc6b7576 100644 --- a/rtl/vlib/xlib/iob_reg_i_gen.vbom +++ b/rtl/vlib/xlib/iob_reg_i_gen.vbom @@ -1,4 +1,5 @@ # libs ../slvtypes.vhd +xlib.vhd # design iob_reg_i_gen.vhd diff --git a/rtl/vlib/xlib/iob_reg_io_gen.vbom b/rtl/vlib/xlib/iob_reg_io_gen.vbom index 4b127b59..bee12630 100644 --- a/rtl/vlib/xlib/iob_reg_io_gen.vbom +++ b/rtl/vlib/xlib/iob_reg_io_gen.vbom @@ -1,5 +1,6 @@ # libs ../slvtypes.vhd +xlib.vhd # components [sim]iob_keeper_gen.vbom # design diff --git a/rtl/vlib/xlib/iob_reg_io_gen.vhd b/rtl/vlib/xlib/iob_reg_io_gen.vhd index b3397553..b944d1d9 100644 --- a/rtl/vlib/xlib/iob_reg_io_gen.vhd +++ b/rtl/vlib/xlib/iob_reg_io_gen.vhd @@ -1,4 +1,4 @@ --- $Id: iob_reg_io_gen.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: iob_reg_io_gen.vhd 771 2016-05-29 17:39:06Z mueller $ -- -- Copyright 2007-2008 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: iob_keeper_gen [sim only] -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment -- 2008-05-22 149 1.0.4 use internally TE to match OBUFT T polarity @@ -99,8 +99,7 @@ begin DI <= R_DI; -- Note: PULL (UP, DOWN or KEEP) is only implemented for simulation, not --- for inference in synthesis. Use pin attributes in UCF's or use --- iob_reg_io_gen_unisim +-- for inference in synthesis. Use pin attributes in UCF's or XDC's -- -- synthesis translate_off diff --git a/rtl/vlib/xlib/iob_reg_o_gen.vbom b/rtl/vlib/xlib/iob_reg_o_gen.vbom index 83f20617..b829b8ec 100644 --- a/rtl/vlib/xlib/iob_reg_o_gen.vbom +++ b/rtl/vlib/xlib/iob_reg_o_gen.vbom @@ -1,4 +1,5 @@ # libs ../slvtypes.vhd +xlib.vhd # design iob_reg_o_gen.vhd diff --git a/rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd b/rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd index e38a3e76..c93b3598 100644 --- a/rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd +++ b/rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd @@ -1,6 +1,6 @@ --- $Id: s7_cmt_sfs_gsim.vhd 734 2016-02-20 22:43:20Z mueller $ +-- $Id: s7_cmt_sfs_gsim.vhd 760 2016-04-09 16:17:13Z mueller $ -- --- Copyright 2013- by Walter F.J. Mueller +-- Copyright 2013-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -23,6 +23,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-04-09 760 1.1 BUGFIX: correct mmcm range check boundaries -- 2013-09-28 535 1.0 Initial version (derived from dcm_sfs_gsim) ------------------------------------------------------------------------------ -- Note: for test bench usage a copy of s7_cmt_sfs_gsim, with _tb instead @@ -123,10 +124,10 @@ begin severity failure; end if; -- setup VCO and PD range check boundaries - t_vcomin := (1000 ns / f_vcomax_pll) - 1 ps; - t_vcomax := (1000 ns / f_vcomin_pll) + 1 ps; - t_pdmin := (1000 ns / f_pdmax_pll) - 1 ps; - t_pdmax := (1000 ns / f_pdmin_pll) + 1 ps; + t_vcomin := (1000 ns / f_vcomax_mmcm) - 1 ps; + t_vcomax := (1000 ns / f_vcomin_mmcm) + 1 ps; + t_pdmin := (1000 ns / f_pdmax_mmcm) - 1 ps; + t_pdmax := (1000 ns / f_pdmin_mmcm) + 1 ps; end if; -- GEN_TYPE = "MMCM" diff --git a/rtl/vlib/xlib/tb/s7_cmt_sfs_tb.vhd b/rtl/vlib/xlib/tb/s7_cmt_sfs_tb.vhd index cb20947b..0ca6ce61 100644 --- a/rtl/vlib/xlib/tb/s7_cmt_sfs_tb.vhd +++ b/rtl/vlib/xlib/tb/s7_cmt_sfs_tb.vhd @@ -1,4 +1,4 @@ --- $Id: s7_cmt_sfs_tb.vhd 734 2016-02-20 22:43:20Z mueller $ +-- $Id: s7_cmt_sfs_tb.vhd 760 2016-04-09 16:17:13Z mueller $ -- -- Copyright 2016- by Walter F.J. Mueller -- @@ -23,6 +23,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2016-04-09 760 1.1 BUGFIX: correct mmcm range check boundaries -- 2016-02-20 734 1.0 Initial version (copied from s7_cmt_sfs_gsim) ------------------------------------------------------------------------------ @@ -120,10 +121,10 @@ begin severity failure; end if; -- setup VCO and PD range check boundaries - t_vcomin := (1000 ns / f_vcomax_pll) - 1 ps; - t_vcomax := (1000 ns / f_vcomin_pll) + 1 ps; - t_pdmin := (1000 ns / f_pdmax_pll) - 1 ps; - t_pdmax := (1000 ns / f_pdmin_pll) + 1 ps; + t_vcomin := (1000 ns / f_vcomax_mmcm) - 1 ps; + t_vcomax := (1000 ns / f_vcomin_mmcm) + 1 ps; + t_pdmin := (1000 ns / f_pdmax_mmcm) - 1 ps; + t_pdmax := (1000 ns / f_pdmin_mmcm) + 1 ps; end if; -- GEN_TYPE = "MMCM" @@ -133,7 +134,8 @@ begin if t_vcot_vcomax then assert false - report "assert(VCO frequency out of range)" + report "assert(VCO frequency out of range); t_cvo: " + & time'image(t_vco) severity failure; end if; diff --git a/rtl/vlib/xlib/usr_access_unisim.vbom b/rtl/vlib/xlib/usr_access_unisim.vbom new file mode 100644 index 00000000..f2871611 --- /dev/null +++ b/rtl/vlib/xlib/usr_access_unisim.vbom @@ -0,0 +1,5 @@ +# libs +../slvtypes.vhd +@lib:unisim +# design +usr_access_unisim.vhd diff --git a/rtl/vlib/xlib/usr_access_unisim.vhd b/rtl/vlib/xlib/usr_access_unisim.vhd new file mode 100644 index 00000000..7570a434 --- /dev/null +++ b/rtl/vlib/xlib/usr_access_unisim.vhd @@ -0,0 +1,69 @@ +-- $Id: usr_access_unisim.vhd 758 2016-04-02 18:01:39Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: usr_access_unisim - syn +-- Description: Wrapper for USR_ACCESS* entities +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic Series-7 +-- Tool versions: viv 2015.4; ghdl 0.33 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-04-02 758 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +use unisim.vcomponents.ALL; + +use work.slvtypes.all; + +entity usr_access_unisim is -- wrapper for USR_ACCESS family + port ( + DATA : out slv32 -- usr_access register value + ); +end usr_access_unisim; + + +architecture syn of usr_access_unisim is + + signal DATA_RAW : slv32 := (others=>'0'); + +begin + + UA : USR_ACCESSE2 + port map ( + CFGCLK => open, + DATA => DATA_RAW, + DATAVALID => open + ); + + -- the USR_ACCESSE2 simulation model unfortunately returns always 'UUUU' + -- no way to configure it for reasonable simulation behavior + -- there this sanitiser + proc_data: process (DATA_RAW) + variable idata : slv32 := (others=>'0'); + begin + idata := to_x01(DATA_RAW); + if is_x(idata) then + idata := (others=>'0'); + end if; + DATA <= idata; + end process proc_data; + +end syn; diff --git a/rtl/vlib/xlib/xlib.vhd b/rtl/vlib/xlib/xlib.vhd index 7f376dd5..fbd982f7 100644 --- a/rtl/vlib/xlib/xlib.vhd +++ b/rtl/vlib/xlib/xlib.vhd @@ -1,6 +1,6 @@ --- $Id: xlib.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: xlib.vhd 758 2016-04-02 18:01:39Z mueller $ -- --- Copyright 2007-2013 by Walter F.J. Mueller +-- Copyright 2007-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Xilinx specific components -- -- Dependencies: - --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-04-02 758 1.0.11 add usr_access_unisim -- 2013-10-06 538 1.0.10 add s6_cmt_sfs -- 2013-09-28 535 1.0.9 add s7_cmt_sfs -- 2011-11-24 432 1.0.8 add iob_oddr2_simple @@ -214,4 +215,10 @@ component s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth. ); end component; +component usr_access_unisim is -- wrapper for USR_ACCESS family + port ( + DATA : out slv32 -- usr_access register value + ); +end component; + end package xlib; diff --git a/rtl/w11a/Makefile b/rtl/w11a/Makefile.ise similarity index 89% rename from rtl/w11a/Makefile rename to rtl/w11a/Makefile.ise index f51dc9d4..35da5977 100644 --- a/rtl/w11a/Makefile +++ b/rtl/w11a/Makefile.ise @@ -1,4 +1,5 @@ -# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ # # Revision History: # Date Rev Version Comment diff --git a/rtl/w11a/pdp11.vhd b/rtl/w11a/pdp11.vhd index 0249da72..0bc83a79 100644 --- a/rtl/w11a/pdp11.vhd +++ b/rtl/w11a/pdp11.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11.vhd 712 2015-11-01 22:53:45Z mueller $ +-- $Id: pdp11.vhd 750 2016-03-24 23:11:51Z mueller $ -- -- Copyright 2006-2015 by Walter F.J. Mueller -- @@ -1056,6 +1056,8 @@ component pdp11_mem70 is -- 11/70 memory system registers end component; component pdp11_cache is -- cache + generic ( + TWIDTH : positive := 9); -- tag width (5 to 9) port ( CLK : in slbit; -- clock GRESET : in slbit; -- general reset @@ -1163,7 +1165,7 @@ end component; component pdp11_bram_memctl is -- BRAM based memctl generic ( MAWIDTH : positive := 4; -- mux address width - NBLOCK : positive := 11); -- write delay in clock cycles + NBLOCK : positive := 11); -- number of 16 kByte blocks port ( CLK : in slbit; -- clock RESET : in slbit; -- reset diff --git a/rtl/w11a/pdp11_bram.vbom b/rtl/w11a/pdp11_bram.vbom index cf52651e..d0ad6beb 100644 --- a/rtl/w11a/pdp11_bram.vbom +++ b/rtl/w11a/pdp11_bram.vbom @@ -4,6 +4,7 @@ pdp11.vbom # components [sim]../vlib/memlib/ram_2swsr_rfirst_gen.vbom -[xst,vsyn]../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vbom +[xst]../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vbom +[vsyn]../vlib/memlib/ram_2swsr_rfirst_gen.vbom # design pdp11_bram.vhd diff --git a/rtl/w11a/pdp11_bram_memctl.vbom b/rtl/w11a/pdp11_bram_memctl.vbom index 875d8e83..fb11fc0f 100644 --- a/rtl/w11a/pdp11_bram_memctl.vbom +++ b/rtl/w11a/pdp11_bram_memctl.vbom @@ -1,8 +1,8 @@ # libs ../vlib/slvtypes.vhd pdp11.vbom -@lib:unisim -@lib:unimacro +../vlib/memlib/memlib.vhd # components +../vlib/memlib/ram_1swsr_wfirst_gen.vbom # design pdp11_bram_memctl.vhd diff --git a/rtl/w11a/pdp11_bram_memctl.vhd b/rtl/w11a/pdp11_bram_memctl.vhd index 14ec0b7b..c457edb2 100644 --- a/rtl/w11a/pdp11_bram_memctl.vhd +++ b/rtl/w11a/pdp11_bram_memctl.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_bram_memctl.vhd 644 2015-02-08 22:56:54Z mueller $ +-- $Id: pdp11_bram_memctl.vhd 767 2016-05-26 07:47:51Z mueller $ -- --- Copyright 2015- by Walter F.J. Mueller +-- Copyright 2015-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,10 +18,12 @@ -- Dependencies: - -- Test bench: - -- Target Devices: 7-Series --- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 +-- Tool versions: ise 14.7; viv 2014.4-2016.1; ghdl 0.31-0.33 -- -- Revision History: -- Date Rev Version Comment +-- 2016-05-22 787 1.1.1 don't init N_REGS (vivado fix for fsm inference) +-- 2016-03-20 749 1.1 use ram_1swsr_wfirst_gen rather BRAM_SINGLE_MACRO -- 2015-02-08 644 1.0 Initial version ------------------------------------------------------------------------------ @@ -29,12 +31,8 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -library unisim; -use unisim.vcomponents.all; -library unimacro; -use unimacro.vcomponents.all; - use work.slvtypes.all; +use work.memlib.all; use work.pdp11.all; -- ---------------------------------------------------------------------------- @@ -42,7 +40,7 @@ use work.pdp11.all; entity pdp11_bram_memctl is -- BRAM based memctl generic ( MAWIDTH : positive := 4; -- mux address width - NBLOCK : positive := 11); -- write delay in clock cycles + NBLOCK : positive := 11); -- number of 16 kByte blocks port ( CLK : in slbit; -- clock RESET : in slbit; -- reset @@ -93,8 +91,8 @@ architecture syn of pdp11_bram_memctl is '0' -- ackr ); - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs + signal R_REGS : regs_type := regs_init; + signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) type mem_do_type is array (NBLOCK-1 downto 0) of slv32; signal MEM_DO : mem_do_type := (others=> (others => '0')); @@ -112,25 +110,18 @@ begin MARRAY: for row in NBLOCK-1 downto 0 generate MROW: for col in 3 downto 0 generate - signal WE : slv(0 downto 0) := "0"; begin - WE(0) <= R_REGS.cellwe(col); - MCELL : BRAM_SINGLE_MACRO + MCELL : ram_1swsr_wfirst_gen generic map ( - BRAM_SIZE => "36Kb", - DEVICE => "7SERIES", - WRITE_WIDTH => 8, - READ_WIDTH => 8, - WRITE_MODE => "WRITE_FIRST") + AWIDTH => 12, -- 4 Kb blocks + DWIDTH => 8) -- byte wide port map ( - CLK => CLK, - RST => '0', - REGCE => '1', - ADDR => R_REGS.celladdr, - EN => R_REGS.cellen(row), - WE => WE, - DI => R_REGS.dibuf(8*col+7 downto 8*col), - DO => MEM_DO(row)(8*col+7 downto 8*col) + CLK => CLK, + EN => R_REGS.cellen(row), + WE => R_REGS.cellwe(col), + ADDR => R_REGS.celladdr, + DI => R_REGS.dibuf(8*col+7 downto 8*col), + DO => MEM_DO(row)(8*col+7 downto 8*col) ); end generate MROW; end generate MARRAY; diff --git a/rtl/w11a/pdp11_cache.vbom b/rtl/w11a/pdp11_cache.vbom index afb45e2c..840b5c38 100644 --- a/rtl/w11a/pdp11_cache.vbom +++ b/rtl/w11a/pdp11_cache.vbom @@ -4,6 +4,7 @@ pdp11.vbom # components [sim]../vlib/memlib/ram_2swsr_rfirst_gen.vbom -[xst,vsyn]../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vbom +[xst]../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vbom +[vsyn]../vlib/memlib/ram_2swsr_rfirst_gen.vbom # design pdp11_cache.vhd diff --git a/rtl/w11a/pdp11_cache.vhd b/rtl/w11a/pdp11_cache.vhd index 9e860df7..cc7e0679 100644 --- a/rtl/w11a/pdp11_cache.vhd +++ b/rtl/w11a/pdp11_cache.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_cache.vhd 677 2015-05-09 21:52:32Z mueller $ +-- $Id: pdp11_cache.vhd 767 2016-05-26 07:47:51Z mueller $ -- --- Copyright 2008-2011 by Walter F.J. Mueller +-- Copyright 2008-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,9 +18,23 @@ -- Dependencies: memlib/ram_2swsr_rfirst_gen -- Test bench: - -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33 +-- +-- Synthesis results +-- clw = cache line width (tag+data) +-- eff = efficiency (fraction of used BRAM colums) +-- - 2016-03-22 (r750) with viv 2015.4 for xc7a100t-1 +-- TWIDTH flop lutl lutm RAMB36 RAMB18 bram clw eff +-- 9 43 106 0 0 5 2.5 45 100% +-- 8 43 109 0 5 0 5.0 44 97% +-- 7 43 107 0 10 4 12.0 43 89% +-- 6 43 106 0 19 4 21.0 42 100% +-- 5 58! 106 0 41 0 41.0 41 100% +-- -- Revision History: -- Date Rev Version Comment +-- 2016-05-22 787 1.1.1 don't init N_REGS (vivado fix for fsm inference) +-- 2016-03-22 751 1.1 now configurable size (8,16,32,64,128 kB) -- 2011-11-18 427 1.0.3 now numeric_std clean -- 2008-02-23 118 1.0.2 ce cache in s_idle to avoid U's in sim -- factor invariants out of if's; fix tag rmiss logic @@ -38,6 +52,8 @@ use work.memlib.all; use work.pdp11.all; entity pdp11_cache is -- cache + generic ( + TWIDTH : positive := 9); -- tag width (5 to 9) port ( CLK : in slbit; -- clock GRESET : in slbit; -- general reset @@ -59,6 +75,22 @@ end pdp11_cache; architecture syn of pdp11_cache is + constant lwidth: positive := 22-2-TWIDTH; -- line address width + + subtype t_range is integer range TWIDTH-1 downto 0; -- tag value regs + subtype l_range is integer range lwidth-1 downto 0; -- line addr regs + + subtype af_tag is integer range 22-1 downto 22-TWIDTH; -- tag address + subtype af_line is integer range 22-TWIDTH-1 downto 2; -- line address + + subtype df_byte3 is integer range 31 downto 24; + subtype df_byte2 is integer range 23 downto 16; + subtype df_byte1 is integer range 15 downto 8; + subtype df_byte0 is integer range 7 downto 0; + + subtype df_word1 is integer range 31 downto 16; + subtype df_word0 is integer range 15 downto 0; + type state_type is ( s_idle, -- s_idle: wait for req s_read, -- s_read: read cycle @@ -69,8 +101,8 @@ architecture syn of pdp11_cache is type regs_type is record state : state_type; -- state addr_w : slbit; -- address - word select - addr_l : slv11; -- address - cache line address - addr_t : slv9; -- address - cache tag part + addr_l : slv(l_range); -- address - cache line address + addr_t : slv(t_range); -- address - cache tag part be : slv4; -- byte enables (at 4 byte level) di : slv16; -- data end record regs_type; @@ -78,21 +110,21 @@ architecture syn of pdp11_cache is constant regs_init : regs_type := ( s_idle, -- state '0', -- addr_w - (others=>'0'), -- addr_l - (others=>'0'), -- addr_t + slv(to_unsigned(0,lwidth)), -- addr_l + slv(to_unsigned(0,TWIDTH)), -- addr_t (others=>'0'), -- be (others=>'0') -- di ); - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs + signal R_REGS : regs_type := regs_init; + signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) signal CMEM_TAG_CEA : slbit := '0'; signal CMEM_TAG_CEB : slbit := '0'; signal CMEM_TAG_WEA : slbit := '0'; signal CMEM_TAG_WEB : slbit := '0'; - signal CMEM_TAG_DIB : slv9 := (others=>'0'); - signal CMEM_TAG_DOA : slv9 := (others=>'0'); + signal CMEM_TAG_DIB : slv(t_range) := (others=>'0'); + signal CMEM_TAG_DOA : slv(t_range) := (others=>'0'); signal CMEM_DAT_CEA : slbit := '0'; signal CMEM_DAT_CEB : slbit := '0'; signal CMEM_DAT_WEA : slv4 := "0000"; @@ -112,10 +144,14 @@ architecture syn of pdp11_cache is begin + assert TWIDTH>=5 and TWIDTH<=9 + report "assert(TWIDTH>=5 and TWIDTH<=9): unsupported TWIDTH" + severity failure; + CMEM_TAG : ram_2swsr_rfirst_gen generic map ( - AWIDTH => 11, - DWIDTH => 9) + AWIDTH => lwidth, + DWIDTH => twidth) port map ( CLKA => CLK, CLKB => CLK, @@ -123,9 +159,9 @@ begin ENB => CMEM_TAG_CEB, WEA => CMEM_TAG_WEA, WEB => CMEM_TAG_WEB, - ADDRA => EM_MREQ.addr(12 downto 2), + ADDRA => EM_MREQ.addr(af_line), ADDRB => R_REGS.addr_l, - DIA => EM_MREQ.addr(21 downto 13), + DIA => EM_MREQ.addr(af_tag), DIB => CMEM_TAG_DIB, DOA => CMEM_TAG_DOA, DOB => open @@ -133,7 +169,7 @@ begin CMEM_DAT0 : ram_2swsr_rfirst_gen generic map ( - AWIDTH => 11, + AWIDTH => lwidth, DWIDTH => 9) port map ( CLKA => CLK, @@ -142,7 +178,7 @@ begin ENB => CMEM_DAT_CEB, WEA => CMEM_DAT_WEA(0), WEB => CMEM_DAT_WEB(0), - ADDRA => EM_MREQ.addr(12 downto 2), + ADDRA => EM_MREQ.addr(af_line), ADDRB => R_REGS.addr_l, DIA => CMEM_DIA_0, DIB => CMEM_DIB_0, @@ -152,7 +188,7 @@ begin CMEM_DAT1 : ram_2swsr_rfirst_gen generic map ( - AWIDTH => 11, + AWIDTH => lwidth, DWIDTH => 9) port map ( CLKA => CLK, @@ -161,7 +197,7 @@ begin ENB => CMEM_DAT_CEB, WEA => CMEM_DAT_WEA(1), WEB => CMEM_DAT_WEB(1), - ADDRA => EM_MREQ.addr(12 downto 2), + ADDRA => EM_MREQ.addr(af_line), ADDRB => R_REGS.addr_l, DIA => CMEM_DIA_1, DIB => CMEM_DIB_1, @@ -171,7 +207,7 @@ begin CMEM_DAT2 : ram_2swsr_rfirst_gen generic map ( - AWIDTH => 11, + AWIDTH => lwidth, DWIDTH => 9) port map ( CLKA => CLK, @@ -180,7 +216,7 @@ begin ENB => CMEM_DAT_CEB, WEA => CMEM_DAT_WEA(2), WEB => CMEM_DAT_WEB(2), - ADDRA => EM_MREQ.addr(12 downto 2), + ADDRA => EM_MREQ.addr(af_line), ADDRB => R_REGS.addr_l, DIA => CMEM_DIA_2, DIB => CMEM_DIB_2, @@ -190,7 +226,7 @@ begin CMEM_DAT3 : ram_2swsr_rfirst_gen generic map ( - AWIDTH => 11, + AWIDTH => lwidth, DWIDTH => 9) port map ( CLKA => CLK, @@ -199,7 +235,7 @@ begin ENB => CMEM_DAT_CEB, WEA => CMEM_DAT_WEA(3), WEB => CMEM_DAT_WEB(3), - ADDRA => EM_MREQ.addr(12 downto 2), + ADDRA => EM_MREQ.addr(af_line), ADDRB => R_REGS.addr_l, DIA => CMEM_DIA_3, DIB => CMEM_DIB_3, @@ -229,8 +265,8 @@ begin variable n : regs_type := regs_init; variable iaddr_w : slbit := '0'; - variable iaddr_l : slv11 := (others=>'0'); - variable iaddr_t : slv9 := (others=>'0'); + variable iaddr_l : slv(l_range) := (others=>'0'); + variable iaddr_t : slv(t_range) := (others=>'0'); variable itagok : slbit := '0'; variable ivalok : slbit := '0'; @@ -239,7 +275,7 @@ begin variable icmem_tag_ceb : slbit := '0'; variable icmem_tag_wea : slbit := '0'; variable icmem_tag_web : slbit := '0'; - variable icmem_tag_dib : slv9 := (others=>'0'); + variable icmem_tag_dib : slv(t_range) := (others=>'0'); variable icmem_dat_cea : slbit := '0'; variable icmem_dat_ceb : slbit := '0'; variable icmem_dat_wea : slv4 := "0000"; @@ -264,8 +300,8 @@ begin n := R_REGS; iaddr_w := EM_MREQ.addr(1); -- get word select - iaddr_l := EM_MREQ.addr(12 downto 2); -- get cache line addr - iaddr_t := EM_MREQ.addr(21 downto 13); -- get cache tag part + iaddr_l := EM_MREQ.addr(af_line); -- get cache line addr + iaddr_t := EM_MREQ.addr(af_tag); -- get cache tag part icmem_tag_cea := '0'; icmem_tag_ceb := '0'; @@ -279,14 +315,14 @@ begin icmem_val_dib := "0000"; icmem_dat_dib := MEM_DO; -- default, local define whenver used - icmem_val_doa(0) := CMEM_DOA_0(8); - icmem_dat_doa( 7 downto 0) := CMEM_DOA_0(7 downto 0); - icmem_val_doa(1) := CMEM_DOA_1(8); - icmem_dat_doa(15 downto 8) := CMEM_DOA_1(7 downto 0); - icmem_val_doa(2) := CMEM_DOA_2(8); - icmem_dat_doa(23 downto 16) := CMEM_DOA_2(7 downto 0); - icmem_val_doa(3) := CMEM_DOA_3(8); - icmem_dat_doa(31 downto 24) := CMEM_DOA_3(7 downto 0); + icmem_val_doa(0) := CMEM_DOA_0(8); + icmem_dat_doa(df_byte0) := CMEM_DOA_0(df_byte0); + icmem_val_doa(1) := CMEM_DOA_1(8); + icmem_dat_doa(df_byte1) := CMEM_DOA_1(df_byte0); + icmem_val_doa(2) := CMEM_DOA_2(8); + icmem_dat_doa(df_byte2) := CMEM_DOA_2(df_byte0); + icmem_val_doa(3) := CMEM_DOA_3(8); + icmem_dat_doa(df_byte3) := CMEM_DOA_3(df_byte0); itagok := '0'; if CMEM_TAG_DOA = r.addr_t then -- cache tag hit @@ -405,32 +441,32 @@ begin CMEM_DAT_WEA <= icmem_dat_wea; CMEM_DAT_WEB <= icmem_dat_web; - CMEM_DIA_0(8) <= '1'; - CMEM_DIA_0(7 downto 0) <= EM_MREQ.din( 7 downto 0); - CMEM_DIA_1(8) <= '1'; - CMEM_DIA_1(7 downto 0) <= EM_MREQ.din(15 downto 8); - CMEM_DIA_2(8) <= '1'; - CMEM_DIA_2(7 downto 0) <= EM_MREQ.din( 7 downto 0); - CMEM_DIA_3(8) <= '1'; - CMEM_DIA_3(7 downto 0) <= EM_MREQ.din(15 downto 8); + CMEM_DIA_0(8) <= '1'; + CMEM_DIA_0(df_byte0) <= EM_MREQ.din(df_byte0); + CMEM_DIA_1(8) <= '1'; + CMEM_DIA_1(df_byte0) <= EM_MREQ.din(df_byte1); + CMEM_DIA_2(8) <= '1'; + CMEM_DIA_2(df_byte0) <= EM_MREQ.din(df_byte0); + CMEM_DIA_3(8) <= '1'; + CMEM_DIA_3(df_byte0) <= EM_MREQ.din(df_byte1); - CMEM_DIB_0(8) <= icmem_val_dib(0); - CMEM_DIB_0(7 downto 0) <= icmem_dat_dib(7 downto 0); - CMEM_DIB_1(8) <= icmem_val_dib(1); - CMEM_DIB_1(7 downto 0) <= icmem_dat_dib(15 downto 8); - CMEM_DIB_2(8) <= icmem_val_dib(2); - CMEM_DIB_2(7 downto 0) <= icmem_dat_dib(23 downto 16); - CMEM_DIB_3(8) <= icmem_val_dib(3); - CMEM_DIB_3(7 downto 0) <= icmem_dat_dib(31 downto 24); + CMEM_DIB_0(8) <= icmem_val_dib(0); + CMEM_DIB_0(df_byte0) <= icmem_dat_dib(df_byte0); + CMEM_DIB_1(8) <= icmem_val_dib(1); + CMEM_DIB_1(df_byte0) <= icmem_dat_dib(df_byte1); + CMEM_DIB_2(8) <= icmem_val_dib(2); + CMEM_DIB_2(df_byte0) <= icmem_dat_dib(df_byte2); + CMEM_DIB_3(8) <= icmem_val_dib(3); + CMEM_DIB_3(df_byte0) <= icmem_dat_dib(df_byte3); EM_SRES <= em_sres_init; EM_SRES.ack_r <= iackr; EM_SRES.ack_w <= iackw; case iosel is - when "00" => EM_SRES.dout <= icmem_dat_doa(15 downto 0); - when "01" => EM_SRES.dout <= icmem_dat_doa(31 downto 16); - when "10" => EM_SRES.dout <= MEM_DO(15 downto 0); - when "11" => EM_SRES.dout <= MEM_DO(31 downto 16); + when "00" => EM_SRES.dout <= icmem_dat_doa(df_word0); + when "01" => EM_SRES.dout <= icmem_dat_doa(df_word1); + when "10" => EM_SRES.dout <= MEM_DO(df_word0); + when "11" => EM_SRES.dout <= MEM_DO(df_word1); when others => null; end case; diff --git a/rtl/w11a/pdp11_core_rbus.vhd b/rtl/w11a/pdp11_core_rbus.vhd index 53978c0c..0346aae5 100644 --- a/rtl/w11a/pdp11_core_rbus.vhd +++ b/rtl/w11a/pdp11_core_rbus.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_core_rbus.vhd 700 2015-07-12 19:28:31Z mueller $ +-- $Id: pdp11_core_rbus.vhd 767 2016-05-26 07:47:51Z mueller $ -- --- Copyright 2007-2015 by Walter F.J. Mueller +-- Copyright 2007-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,7 +19,7 @@ -- Test bench: tb/tb_rlink_tba_pdp11core -- -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -27,6 +27,7 @@ -- -- Revision History: - -- Date Rev Version Comment +-- 2016-05-22 787 1.5.2 don't init N_REGS (vivado fix for fsm inference) -- 2015-07-10 700 1.5.1 add cpuact logic, redefine lam as cpuact 1->0 -- 2015-05-09 677 1.5 start/stop/suspend overhaul; reset overhaul -- 2014-12-26 621 1.4 use full size 4k word ibus window @@ -163,8 +164,8 @@ architecture syn of pdp11_core_rbus is '0','0' -- doinc, waitstep ); - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs + signal R_REGS : regs_type := regs_init; + signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) begin @@ -380,7 +381,8 @@ architecture syn of pdp11_core_rbus is end if; when s_cpstep => -- s_cpstep: wait for cpustep done --- - if r.rbselc='0' or irbena='0' then -- rbus cycle abort + n.state := s_cpstep; -- needed to prevent vivado iSTATE + if r.rbselc='0' or irbena='0' then -- rbus cycle abort n.state := s_idle; -- quit else if CP_STAT.cpustep = '0' then -- cpustep done diff --git a/rtl/w11a/pdp11_dmcmon.vbom b/rtl/w11a/pdp11_dmcmon.vbom index 5d0d7413..27e5cc86 100644 --- a/rtl/w11a/pdp11_dmcmon.vbom +++ b/rtl/w11a/pdp11_dmcmon.vbom @@ -5,8 +5,10 @@ pdp11.vbom # components [sim]../vlib/memlib/ram_2swsr_rfirst_gen.vbom -[xst,vsyn]../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vbom +[xst]../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vbom +[vsyn]../vlib/memlib/ram_2swsr_rfirst_gen.vbom [sim]../vlib/memlib/ram_1swar_1ar_gen.vbom -[xst,vsyn]../vlib/memlib/ram_1swar_1ar_gen_unisim.vbom +[xst]../vlib/memlib/ram_1swar_1ar_gen_unisim.vbom +[vsyn]../vlib/memlib/ram_1swar_1ar_gen.vbom # design pdp11_dmcmon.vhd diff --git a/rtl/w11a/pdp11_dmscnt.vbom b/rtl/w11a/pdp11_dmscnt.vbom index 82212b32..fda12752 100644 --- a/rtl/w11a/pdp11_dmscnt.vbom +++ b/rtl/w11a/pdp11_dmscnt.vbom @@ -5,6 +5,7 @@ pdp11.vbom # components [sim]../vlib/memlib/ram_2swsr_rfirst_gen.vbom -[xst,vsyn]../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vbom +[xst]../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vbom +[vsyn]../vlib/memlib/ram_2swsr_rfirst_gen.vbom # design pdp11_dmscnt.vhd diff --git a/rtl/w11a/pdp11_dmscnt.vhd b/rtl/w11a/pdp11_dmscnt.vhd index a2b62bbd..074769b2 100644 --- a/rtl/w11a/pdp11_dmscnt.vhd +++ b/rtl/w11a/pdp11_dmscnt.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_dmscnt.vhd 721 2015-12-29 17:50:50Z mueller $ +-- $Id: pdp11_dmscnt.vhd 767 2016-05-26 07:47:51Z mueller $ -- --- Copyright 2015- by Walter F.J. Mueller +-- Copyright 2015-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,7 +19,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 +-- Tool versions: ise 14.7; viv 2014.4-2016.1; ghdl 0.31-0.33 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -27,6 +27,7 @@ -- -- Revision History: - -- Date Rev Version Comment +-- 2016-05-22 787 1.1.1 don't init N_REGS (vivado fix for fsm inference) -- 2015-12-28 721 1.1 use laddr/waddr; use ena instead of cnt; -- 2015-07-19 702 1.0 Initial version -- 2015-06-26 695 1.0 First draft @@ -115,8 +116,8 @@ architecture syn of pdp11_dmscnt is (others=>'0') -- mbuf ); - signal R_REGS : regs_type := regs_init; -- state registers - signal N_REGS : regs_type := regs_init; -- next value state regs + signal R_REGS : regs_type := regs_init; + signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) signal CMEM_CEA : slbit := '0'; signal CMEM_CEB : slbit := '0'; diff --git a/rtl/w11a/pdp11_gpr.vbom b/rtl/w11a/pdp11_gpr.vbom index a40dd120..7e02e914 100644 --- a/rtl/w11a/pdp11_gpr.vbom +++ b/rtl/w11a/pdp11_gpr.vbom @@ -5,6 +5,7 @@ pdp11.vbom # components [sim]../vlib/memlib/ram_1swar_1ar_gen.vbom -[xst,vsyn]../vlib/memlib/ram_1swar_1ar_gen_unisim.vbom +[xst]../vlib/memlib/ram_1swar_1ar_gen_unisim.vbom +[vsyn]../vlib/memlib/ram_1swar_1ar_gen.vbom # design pdp11_gpr.vhd diff --git a/rtl/w11a/pdp11_mmu_sadr.vbom b/rtl/w11a/pdp11_mmu_sadr.vbom index f598c1dc..5090ee40 100644 --- a/rtl/w11a/pdp11_mmu_sadr.vbom +++ b/rtl/w11a/pdp11_mmu_sadr.vbom @@ -5,6 +5,7 @@ pdp11.vbom # components [sim]../vlib/memlib/ram_1swar_gen.vbom -[xst,vsyn]../vlib/memlib/ram_1swar_gen_unisim.vbom +[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom +[vsyn]../vlib/memlib/ram_1swar_gen.vbom # design pdp11_mmu_sadr.vhd diff --git a/rtl/w11a/pdp11_reg70.vbom b/rtl/w11a/pdp11_reg70.vbom index c6326362..0655a280 100644 --- a/rtl/w11a/pdp11_reg70.vbom +++ b/rtl/w11a/pdp11_reg70.vbom @@ -2,7 +2,6 @@ ../vlib/slvtypes.vhd ../ibus/iblib.vhd pdp11.vbom -${sys_conf := sys_conf.vhd} # components # design pdp11_reg70.vhd diff --git a/rtl/w11a/pdp11_reg70.vhd b/rtl/w11a/pdp11_reg70.vhd index a6449846..347ac29f 100644 --- a/rtl/w11a/pdp11_reg70.vhd +++ b/rtl/w11a/pdp11_reg70.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_reg70.vhd 677 2015-05-09 21:52:32Z mueller $ +-- $Id: pdp11_reg70.vhd 768 2016-05-26 16:47:00Z mueller $ -- -- Copyright 2008-2015 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33 -- -- Revision History: -- Date Rev Version Comment @@ -36,7 +36,6 @@ use ieee.numeric_std.all; use work.slvtypes.all; use work.pdp11.all; use work.iblib.all; -use work.sys_conf.all; -- ---------------------------------------------------------------------------- diff --git a/rtl/w11a/pdp11_sequencer.vbom b/rtl/w11a/pdp11_sequencer.vbom index daa627c6..36ddae5b 100644 --- a/rtl/w11a/pdp11_sequencer.vbom +++ b/rtl/w11a/pdp11_sequencer.vbom @@ -2,6 +2,7 @@ ../vlib/slvtypes.vhd ../ibus/iblib.vhd pdp11.vbom +${sys_conf := sys_conf.vhd} # components ../ibus/ib_sel.vbom # design diff --git a/rtl/w11a/pdp11_sequencer.vhd b/rtl/w11a/pdp11_sequencer.vhd index 642f44fa..8cb62e10 100644 --- a/rtl/w11a/pdp11_sequencer.vhd +++ b/rtl/w11a/pdp11_sequencer.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_sequencer.vhd 708 2015-08-03 06:41:43Z mueller $ +-- $Id: pdp11_sequencer.vhd 768 2016-05-26 16:47:00Z mueller $ -- --- Copyright 2006-2015 by Walter F.J. Mueller +-- Copyright 2006-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,10 +18,12 @@ -- Dependencies: ib_sel -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33 -- -- Revision History: -- Date Rev Version Comment +-- 2016-05-26 768 1.6.6 don't init N_REGS (vivado fix for fsm inference) +-- proc_snum conditional (vivado fsm workaround) -- 2015-08-02 708 1.6.5 BUGFIX: proper trap_mmu and trap_ysv handling -- 2015-08-01 707 1.6.4 set dm_idone in s_(trap_10|op_trap); add dm_vfetch -- 2015-07-19 702 1.6.3 add DM_STAT_SE, drop SNUM port @@ -76,6 +78,7 @@ use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; use work.pdp11.all; +use work.sys_conf.all; -- ---------------------------------------------------------------------------- @@ -248,8 +251,11 @@ architecture syn of pdp11_sequencer is s_cpufail ); - signal R_STATE : state_type := s_idle; -- state register - signal N_STATE : state_type := s_idle; + signal R_STATE : state_type := s_idle;-- state register + signal N_STATE : state_type; -- don't init (vivado fix for fsm infer) + + attribute fsm_encoding : string; + attribute fsm_encoding of R_STATE : signal is "one_hot"; signal R_STATUS : cpustat_type := cpustat_init; signal N_STATUS : cpustat_type := cpustat_init; @@ -2395,143 +2401,148 @@ begin CP_STAT.suspext <= R_STATUS.suspext; end process proc_cpstat; - proc_snum : process (R_STATE) - variable isnum : slv8 := (others=>'0'); + -- state number creation logic is conditional, only done when monitor + -- enabled. Due to sythnesis impact in vivado + SNUM : if sys_conf_dmscnt generate begin - isnum := (others=>'0'); - case R_STATE is - -- STATE2SNUM mapper begin - when s_idle => isnum := x"00"; - when s_cp_regread => isnum := x"01"; - when s_cp_rps => isnum := x"02"; - when s_cp_memr_w => isnum := x"03"; - when s_cp_memw_w => isnum := x"04"; - when s_ifetch => isnum := x"05"; - when s_ifetch_w => isnum := x"06"; - when s_idecode => isnum := x"07"; - - when s_srcr_def => isnum := x"08"; - when s_srcr_def_w => isnum := x"09"; - when s_srcr_inc => isnum := x"0a"; - when s_srcr_inc_w => isnum := x"0b"; - when s_srcr_dec => isnum := x"0c"; - when s_srcr_dec1 => isnum := x"0d"; - when s_srcr_ind => isnum := x"0e"; - when s_srcr_ind1_w => isnum := x"0f"; - when s_srcr_ind2 => isnum := x"10"; - when s_srcr_ind2_w => isnum := x"11"; - - when s_dstr_def => isnum := x"12"; - when s_dstr_def_w => isnum := x"13"; - when s_dstr_inc => isnum := x"14"; - when s_dstr_inc_w => isnum := x"15"; - when s_dstr_dec => isnum := x"16"; - when s_dstr_dec1 => isnum := x"17"; - when s_dstr_ind => isnum := x"18"; - when s_dstr_ind1_w => isnum := x"19"; - when s_dstr_ind2 => isnum := x"1a"; - when s_dstr_ind2_w => isnum := x"1b"; - - when s_dstw_def => isnum := x"1c"; - when s_dstw_def_w => isnum := x"1d"; - when s_dstw_inc => isnum := x"1e"; - when s_dstw_inc_w => isnum := x"1f"; - when s_dstw_incdef_w => isnum := x"20"; - when s_dstw_dec => isnum := x"21"; - when s_dstw_dec1 => isnum := x"22"; - when s_dstw_ind => isnum := x"23"; - when s_dstw_ind_w => isnum := x"24"; - when s_dstw_def246 => isnum := x"25"; - - when s_dsta_inc => isnum := x"26"; - when s_dsta_incdef_w => isnum := x"27"; - when s_dsta_dec => isnum := x"28"; - when s_dsta_dec1 => isnum := x"29"; - when s_dsta_ind => isnum := x"2a"; - when s_dsta_ind_w => isnum := x"2b"; - - when s_op_halt => isnum := x"2c"; - when s_op_wait => isnum := x"2d"; - when s_op_trap => isnum := x"2e"; - when s_op_reset => isnum := x"2f"; - when s_op_rts => isnum := x"30"; - when s_op_rts_pop => isnum := x"31"; - when s_op_rts_pop_w => isnum := x"32"; - when s_op_spl => isnum := x"33"; - when s_op_mcc => isnum := x"34"; - when s_op_br => isnum := x"35"; - when s_op_mark => isnum := x"36"; - when s_op_mark1 => isnum := x"37"; - when s_op_mark_pop => isnum := x"38"; - when s_op_mark_pop_w => isnum := x"39"; - when s_op_sob => isnum := x"3a"; - when s_op_sob1 => isnum := x"3b"; - - when s_opg_gen => isnum := x"3c"; - when s_opg_gen_rmw_w => isnum := x"3d"; - when s_opg_mul => isnum := x"3e"; - when s_opg_mul1 => isnum := x"3f"; - when s_opg_div => isnum := x"40"; - when s_opg_div_cn => isnum := x"41"; - when s_opg_div_cr => isnum := x"42"; - when s_opg_div_sq => isnum := x"43"; - when s_opg_div_sr => isnum := x"44"; - when s_opg_div_quit => isnum := x"45"; - when s_opg_ash => isnum := x"46"; - when s_opg_ash_cn => isnum := x"47"; - when s_opg_ashc => isnum := x"48"; - when s_opg_ashc_cn => isnum := x"49"; - when s_opg_ashc_wl => isnum := x"4a"; - - when s_opa_jsr => isnum := x"4b"; - when s_opa_jsr1 => isnum := x"4c"; - when s_opa_jsr_push => isnum := x"4d"; - when s_opa_jsr_push_w => isnum := x"4e"; - when s_opa_jsr2 => isnum := x"4f"; - when s_opa_jmp => isnum := x"50"; - when s_opa_mtp => isnum := x"51"; - when s_opa_mtp_pop_w => isnum := x"52"; - when s_opa_mtp_reg => isnum := x"53"; - when s_opa_mtp_mem => isnum := x"54"; - when s_opa_mtp_mem_w => isnum := x"55"; - when s_opa_mfp_reg => isnum := x"56"; - when s_opa_mfp_mem => isnum := x"57"; - when s_opa_mfp_mem_w => isnum := x"58"; - when s_opa_mfp_dec => isnum := x"59"; - when s_opa_mfp_push => isnum := x"5a"; - when s_opa_mfp_push_w => isnum := x"5b"; - - when s_trap_4 => isnum := x"5c"; - when s_trap_10 => isnum := x"5d"; - when s_trap_disp => isnum := x"5e"; - - when s_int_ext => isnum := x"5f"; - - when s_int_getpc => isnum := x"60"; - when s_int_getpc_w => isnum := x"61"; - when s_int_getps => isnum := x"62"; - when s_int_getps_w => isnum := x"63"; - when s_int_getsp => isnum := x"64"; - when s_int_decsp => isnum := x"65"; - when s_int_pushps => isnum := x"66"; - when s_int_pushps_w => isnum := x"67"; - when s_int_pushpc => isnum := x"68"; - when s_int_pushpc_w => isnum := x"69"; - - when s_rti_getpc => isnum := x"6a"; - when s_rti_getpc_w => isnum := x"6b"; - when s_rti_getps => isnum := x"6c"; - when s_rti_getps_w => isnum := x"6d"; - when s_rti_newpc => isnum := x"6e"; - - when s_vmerr => isnum := x"6f"; - when s_cpufail => isnum := x"70"; - - -- STATE2SNUM mapper end - when others => isnum := x"ff"; - end case; - DM_STAT_SE.snum <= isnum; - end process proc_snum; - + proc_snum : process (R_STATE) + variable isnum : slv8 := (others=>'0'); + begin + isnum := (others=>'0'); + case R_STATE is + -- STATE2SNUM mapper begin + when s_idle => isnum := x"00"; + when s_cp_regread => isnum := x"01"; + when s_cp_rps => isnum := x"02"; + when s_cp_memr_w => isnum := x"03"; + when s_cp_memw_w => isnum := x"04"; + when s_ifetch => isnum := x"05"; + when s_ifetch_w => isnum := x"06"; + when s_idecode => isnum := x"07"; + + when s_srcr_def => isnum := x"08"; + when s_srcr_def_w => isnum := x"09"; + when s_srcr_inc => isnum := x"0a"; + when s_srcr_inc_w => isnum := x"0b"; + when s_srcr_dec => isnum := x"0c"; + when s_srcr_dec1 => isnum := x"0d"; + when s_srcr_ind => isnum := x"0e"; + when s_srcr_ind1_w => isnum := x"0f"; + when s_srcr_ind2 => isnum := x"10"; + when s_srcr_ind2_w => isnum := x"11"; + + when s_dstr_def => isnum := x"12"; + when s_dstr_def_w => isnum := x"13"; + when s_dstr_inc => isnum := x"14"; + when s_dstr_inc_w => isnum := x"15"; + when s_dstr_dec => isnum := x"16"; + when s_dstr_dec1 => isnum := x"17"; + when s_dstr_ind => isnum := x"18"; + when s_dstr_ind1_w => isnum := x"19"; + when s_dstr_ind2 => isnum := x"1a"; + when s_dstr_ind2_w => isnum := x"1b"; + + when s_dstw_def => isnum := x"1c"; + when s_dstw_def_w => isnum := x"1d"; + when s_dstw_inc => isnum := x"1e"; + when s_dstw_inc_w => isnum := x"1f"; + when s_dstw_incdef_w => isnum := x"20"; + when s_dstw_dec => isnum := x"21"; + when s_dstw_dec1 => isnum := x"22"; + when s_dstw_ind => isnum := x"23"; + when s_dstw_ind_w => isnum := x"24"; + when s_dstw_def246 => isnum := x"25"; + + when s_dsta_inc => isnum := x"26"; + when s_dsta_incdef_w => isnum := x"27"; + when s_dsta_dec => isnum := x"28"; + when s_dsta_dec1 => isnum := x"29"; + when s_dsta_ind => isnum := x"2a"; + when s_dsta_ind_w => isnum := x"2b"; + + when s_op_halt => isnum := x"2c"; + when s_op_wait => isnum := x"2d"; + when s_op_trap => isnum := x"2e"; + when s_op_reset => isnum := x"2f"; + when s_op_rts => isnum := x"30"; + when s_op_rts_pop => isnum := x"31"; + when s_op_rts_pop_w => isnum := x"32"; + when s_op_spl => isnum := x"33"; + when s_op_mcc => isnum := x"34"; + when s_op_br => isnum := x"35"; + when s_op_mark => isnum := x"36"; + when s_op_mark1 => isnum := x"37"; + when s_op_mark_pop => isnum := x"38"; + when s_op_mark_pop_w => isnum := x"39"; + when s_op_sob => isnum := x"3a"; + when s_op_sob1 => isnum := x"3b"; + + when s_opg_gen => isnum := x"3c"; + when s_opg_gen_rmw_w => isnum := x"3d"; + when s_opg_mul => isnum := x"3e"; + when s_opg_mul1 => isnum := x"3f"; + when s_opg_div => isnum := x"40"; + when s_opg_div_cn => isnum := x"41"; + when s_opg_div_cr => isnum := x"42"; + when s_opg_div_sq => isnum := x"43"; + when s_opg_div_sr => isnum := x"44"; + when s_opg_div_quit => isnum := x"45"; + when s_opg_ash => isnum := x"46"; + when s_opg_ash_cn => isnum := x"47"; + when s_opg_ashc => isnum := x"48"; + when s_opg_ashc_cn => isnum := x"49"; + when s_opg_ashc_wl => isnum := x"4a"; + + when s_opa_jsr => isnum := x"4b"; + when s_opa_jsr1 => isnum := x"4c"; + when s_opa_jsr_push => isnum := x"4d"; + when s_opa_jsr_push_w => isnum := x"4e"; + when s_opa_jsr2 => isnum := x"4f"; + when s_opa_jmp => isnum := x"50"; + when s_opa_mtp => isnum := x"51"; + when s_opa_mtp_pop_w => isnum := x"52"; + when s_opa_mtp_reg => isnum := x"53"; + when s_opa_mtp_mem => isnum := x"54"; + when s_opa_mtp_mem_w => isnum := x"55"; + when s_opa_mfp_reg => isnum := x"56"; + when s_opa_mfp_mem => isnum := x"57"; + when s_opa_mfp_mem_w => isnum := x"58"; + when s_opa_mfp_dec => isnum := x"59"; + when s_opa_mfp_push => isnum := x"5a"; + when s_opa_mfp_push_w => isnum := x"5b"; + + when s_trap_4 => isnum := x"5c"; + when s_trap_10 => isnum := x"5d"; + when s_trap_disp => isnum := x"5e"; + + when s_int_ext => isnum := x"5f"; + + when s_int_getpc => isnum := x"60"; + when s_int_getpc_w => isnum := x"61"; + when s_int_getps => isnum := x"62"; + when s_int_getps_w => isnum := x"63"; + when s_int_getsp => isnum := x"64"; + when s_int_decsp => isnum := x"65"; + when s_int_pushps => isnum := x"66"; + when s_int_pushps_w => isnum := x"67"; + when s_int_pushpc => isnum := x"68"; + when s_int_pushpc_w => isnum := x"69"; + + when s_rti_getpc => isnum := x"6a"; + when s_rti_getpc_w => isnum := x"6b"; + when s_rti_getps => isnum := x"6c"; + when s_rti_getps_w => isnum := x"6d"; + when s_rti_newpc => isnum := x"6e"; + + when s_vmerr => isnum := x"6f"; + when s_cpufail => isnum := x"70"; + + -- STATE2SNUM mapper end + when others => isnum := x"ff"; + end case; + DM_STAT_SE.snum <= isnum; + end process proc_snum; + end generate SNUM; + end syn; diff --git a/rtl/w11a/pdp11_sys70.vhd b/rtl/w11a/pdp11_sys70.vhd index 7c2382a5..44ad58aa 100644 --- a/rtl/w11a/pdp11_sys70.vhd +++ b/rtl/w11a/pdp11_sys70.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_sys70.vhd 712 2015-11-01 22:53:45Z mueller $ +-- $Id: pdp11_sys70.vhd 750 2016-03-24 23:11:51Z mueller $ -- --- Copyright 2015- by Walter F.J. Mueller +-- Copyright 2015-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -27,10 +27,11 @@ -- -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 +-- Tool versions: ise 14.7; viv 2014.4-2015.5; ghdl 0.33 -- -- Revision History: -- Date Rev Version Comment +-- 2016-03-22 750 1.2 pdp11_cache now configurable size -- 2015-11-01 712 1.1.4 use sbcntl_sbf_tmu -- 2015-07-19 702 1.1.3 use DM_STAT_SE -- 2015-07-04 697 1.1.2 change DM_STAT_SY setup; add dmcmon, dmhbpt; @@ -172,6 +173,8 @@ begin ); CACHE: pdp11_cache + generic map ( + TWIDTH => sys_conf_cache_twidth) port map ( CLK => CLK, GRESET => GRESET_L, diff --git a/rtl/w11a/pdp11_ubmap.vbom b/rtl/w11a/pdp11_ubmap.vbom index ad80e09a..92d9ed27 100644 --- a/rtl/w11a/pdp11_ubmap.vbom +++ b/rtl/w11a/pdp11_ubmap.vbom @@ -5,7 +5,8 @@ pdp11.vbom # components [sim]../vlib/memlib/ram_1swar_gen.vbom -[xst,vsyn]../vlib/memlib/ram_1swar_gen_unisim.vbom +[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom +[vsyn]../vlib/memlib/ram_1swar_gen.vbom ../ibus/ib_sel.vbom # design pdp11_ubmap.vhd diff --git a/rtl/w11a/pdp11_vmbox.vhd b/rtl/w11a/pdp11_vmbox.vhd index 26fe1330..825526dd 100644 --- a/rtl/w11a/pdp11_vmbox.vhd +++ b/rtl/w11a/pdp11_vmbox.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_vmbox.vhd 697 2015-07-05 14:23:26Z mueller $ +-- $Id: pdp11_vmbox.vhd 767 2016-05-26 07:47:51Z mueller $ -- --- Copyright 2006-2015 by Walter F.J. Mueller +-- Copyright 2006-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -23,10 +23,11 @@ -- -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33 -- -- Revision History: -- Date Rev Version Comment +-- 2016-05-22 787 1.6.6 don't init N_REGS (vivado fix for fsm inference) -- 2015-07-03 697 1.6.5 much wider DM_STAT_VM -- 2015-04-04 662 1.6.4 atowidth now 6 (was 5) to support ibdr_rprm reset -- 2011-11-18 427 1.6.3 now numeric_std clean @@ -152,7 +153,7 @@ architecture syn of pdp11_vmbox is ); signal R_REGS : regs_type := regs_init; - signal N_REGS : regs_type := regs_init; + signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) signal R_SLIM : slv8 := (others=>'0'); -- stack limit register diff --git a/rtl/w11a/sys_conf.vhd b/rtl/w11a/sys_conf.vhd index 1033c463..1654db9a 100644 --- a/rtl/w11a/sys_conf.vhd +++ b/rtl/w11a/sys_conf.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf.vhd 695 2015-06-28 11:22:52Z mueller $ +-- $Id: sys_conf.vhd 770 2016-05-28 14:15:00Z mueller $ -- --- Copyright 2007-2015 by Walter F.J. Mueller +-- Copyright 2007-2016 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Default definitions -- -- Dependencies: - --- Tool versions: xst 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: xst 8.1-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment +-- 2016-05-28 770 1.1.2 sys_conf_mem_losize now type natural -- 2015-06-26 695 1.1.1 add sys_conf_dmscnt -- 2015-05-01 672 1.1 adopt to pdp11_sys70 -- 2008-02-23 118 1.0 Initial version @@ -34,7 +35,7 @@ package sys_conf is constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled constant sys_conf_bram_awidth : integer := 15; -- 32 kB BRAM - constant sys_conf_mem_losize : integer := 8#000777#;-- 32 kByte + constant sys_conf_mem_losize : natural := 8#000777#;-- 32 kByte constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon constant sys_conf_dmscnt : boolean := true; diff --git a/rtl/w11a/tb/Makefile.ise b/rtl/w11a/tb/Makefile.ise index ea461c00..59794241 100644 --- a/rtl/w11a/tb/Makefile.ise +++ b/rtl/w11a/tb/Makefile.ise @@ -1,4 +1,5 @@ -# $Id: Makefile.ise 744 2016-03-13 20:28:25Z mueller $ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ # # Revision History: # Date Rev Version Comment diff --git a/rtl/w11a/tb/tb_pdp11core.vbom b/rtl/w11a/tb/tb_pdp11core.vbom index b28b20b7..351374e2 100644 --- a/rtl/w11a/tb/tb_pdp11core.vbom +++ b/rtl/w11a/tb/tb_pdp11core.vbom @@ -7,6 +7,6 @@ # components ../../vlib/simlib/simclk.vbom ../../vlib/simlib/simclkcnt.vbom -@uut: ${uut := tbd_pdp11core.vbom} +${uut := tbd_pdp11core.vbom} -UUT # design tb_pdp11core.vhd diff --git a/rtl/w11a/tb/tbd_pdp11core.vbom b/rtl/w11a/tb/tbd_pdp11core.vbom index 00107217..0f0e03da 100644 --- a/rtl/w11a/tb/tbd_pdp11core.vbom +++ b/rtl/w11a/tb/tbd_pdp11core.vbom @@ -13,3 +13,4 @@ ${sys_conf := ../sys_conf.vhd} [sim]../pdp11_tmu_sb.vbom # design tbd_pdp11core.vhd +@xdc:../../vlib/generic_clk_100mhz.xdc diff --git a/tools/bin/makeise b/tools/bin/makeise new file mode 100755 index 00000000..ac1a4045 --- /dev/null +++ b/tools/bin/makeise @@ -0,0 +1,8 @@ +#!/bin/bash +# $Id: makeise 761 2016-04-17 08:53:48Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# + +exec make -f Makefile.ise "$@" diff --git a/tools/bin/tbrun_tbw b/tools/bin/tbrun_tbw index fb868bff..6f4c98bc 100755 --- a/tools/bin/tbrun_tbw +++ b/tools/bin/tbrun_tbw @@ -1,11 +1,14 @@ #!/bin/bash -# $Id: tbrun_tbw 727 2016-02-07 13:58:47Z mueller $ +# $Id: tbrun_tbw 779 2016-06-26 15:37:16Z mueller $ # # Copyright 2014-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2016-06-25 778 1.1.3 drop make ghdl_tmp_clean logic +# 2016-06-05 773 1.1.2 use _bsim.log for behavioral sim log +# 2016-04-17 762 1.1.1 don't create '-run' for [IX]Sim anymore (now default) # 2016-02-06 727 1.1 add vivado xsim support; Makefile.ise support # 2014-12-27 622 1.0.1 add --stack, --ghw, --tbw, --pcom # 2014-12-26 621 1.0 Initial version @@ -76,32 +79,21 @@ if [[ $tbench =~ _XSim ]] ; then isghdl="" fi -# check for ghdl with _ssim, _fsim, _osim, _tsim -isghdlxsim="" -if [[ -n "$isghdl" ]] && [[ $tbench =~ _[sfot]sim$ ]] ; then - isghdlxsim=true - logsuff="" -fi - # issue makes -if [[ -n "$isghdlxsim" ]] ; then docmd "make ghdl_tmp_clean"; fi docmd "make $makeopts $tbench" exitstat=$? -if [[ -n "$isghdlxsim" ]] ; then docmd "make ghdl_tmp_clean"; fi if (( $exitstat > 0 )) ; then exit $exitstat; fi # determine logfile name -logsuff="_dsim" -if [[ $tbench =~ _[sfot]sim$ ]] ; then logsuff=""; fi +logsuff="_bsim" +if [[ $tbench =~ _[fsorept]sim$ ]] ; then logsuff=""; fi if [[ -n "$optlsuf" ]] ; then logsuff="_$optlsuf"; fi logfile="${tbench}${logsuff}.log" # now build actual test command (a tbw|filter|tee|egrep pipe) cmd="time tbw $tbench" -if [[ -n "$isisim" ]] ; then cmd+=" -run"; fi -if [[ -n "$isxsim" ]] ; then cmd+=" -run"; fi if [[ -n "$stimfile" ]] ; then cmd+=" $stimfile"; fi if [[ -n "$opttbw" ]] ; then cmd+=" $opttbw"; fi if [[ -n "$optstack" ]] ; then cmd+=" --stack-max-size=$optstack"; fi diff --git a/tools/bin/tbrun_tbwrri b/tools/bin/tbrun_tbwrri index 907b8315..db4bad4b 100755 --- a/tools/bin/tbrun_tbwrri +++ b/tools/bin/tbrun_tbwrri @@ -1,11 +1,16 @@ #!/bin/bash -# $Id: tbrun_tbwrri 745 2016-03-18 22:10:34Z mueller $ +# $Id: tbrun_tbwrri 778 2016-06-25 15:18:01Z mueller $ # # Copyright 2014-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2016-06-25 778 1.2.4 drop make ghdl_tmp_clean logic +# 2016-06-18 776 1.2.3 use ti_rri --tout to set connection timeout +# 2016-06-05 773 1.2.2 use _bsim.log for behavioural sim log +# 2016-03-20 748 1.2.1 BUGFIX: add portsel oob for -hxon +# use 120 sec timeout for simulation # 2016-03-18 745 1.2 use --sxon and --hxon instead of --xon # 2015-04-11 666 1.1 add --fusp,--xon # 2014-12-27 622 1.0 Initial version @@ -98,23 +103,14 @@ shift 1 tbenchname=$(basename $tbench) tbenchpath=$(dirname $tbench) -# check for ghdl with _ssim, _fsim, _tsim -isghdlxsim="" -if [[ $tbench =~ _[sft]sim$ ]] ; then - isghdlxsim=true - logsuff="" -fi - # issue makes -if [[ -n "$isghdlxsim" ]] ; then docmd "make -C $tbenchpath ghdl_tmp_clean"; fi docmd "make -C $tbenchpath $tbenchname" exitstat=$? -if [[ -n "$isghdlxsim" ]] ; then docmd "make -C $tbenchpath ghdl_tmp_clean"; fi if (( $exitstat > 0 )) ; then exit $exitstat; fi # determine logfile name -logsuff="_dsim" +logsuff="_bsim" if [[ $tbenchname =~ _[sft]sim$ ]] ; then logsuff=""; fi if [[ -n "$optlsuf" ]] ; then logsuff="_$optlsuf"; fi @@ -144,6 +140,7 @@ else fi cmd+=" --logl=3" +cmd+=" --tout=120." # 120 sec timeout for simulation if [[ -n "$optpack" ]] ; then cmd+=" --pack=$optpack"; fi if [[ -n "$optrri" ]] ; then cmd+=" $optrri"; fi @@ -165,6 +162,10 @@ if [[ -n "$optsxon" ]] ; then cmd+=" \"rlc oob -sbdata 16 0x2\"" # swi = 0010 -> 1st ser XON fi +if [[ -n "$opthxon" ]] ; then + cmd+=" \"rlc oob -sbdata 8 0x2\"" # portsel = 0010 -> 1st ser XON +fi + if (( $ncfxcount > 0 )) ; then cmd+=" \"rlc init\""; fi while (( $# > 0 )) ; do diff --git a/tools/bin/tbw b/tools/bin/tbw index fc5a3b61..3fac7aa9 100755 --- a/tools/bin/tbw +++ b/tools/bin/tbw @@ -1,5 +1,5 @@ #!/usr/bin/perl -w -# $Id: tbw 727 2016-02-07 13:58:47Z mueller $ +# $Id: tbw 778 2016-06-25 15:18:01Z mueller $ # # Copyright 2007-2016 by Walter F.J. Mueller # @@ -14,6 +14,9 @@ # # Revision History: # Date Rev Version Comment +# 2016-06-25 778 1.5.1 support all sim modes +# 2016-04-17 762 1.5 make '-run' default for [IX]Sim, add '-norun' +# 2016-03-20 748 1.4 recode OPTIONS handling and -fifo handling # 2016-02-06 727 1.3 add XSim support # 2015-01-04 629 1.2.6 BUGFIX: setup proper dsc values after -fifo # 2014-12-23 619 1.2.5 add -fifo and -verbose options @@ -43,13 +46,17 @@ use 5.005; # require Perl 5.005 or higher use strict; # require strict checking use POSIX qw(mkfifo); use FileHandle; +use File::Spec; +use Cwd 'abs_path'; my $tb_code; my $is_isim; my $is_isim_run; my $is_xsim; -my $is_fifo; -my $is_verbose; +my $opt_run; +my $opt_norun; +my $opt_fifo; +my $opt_verbose; my @args_pos; # list of positional args my @args_nam; # list of named args @@ -59,7 +66,7 @@ sub print_usage; autoflush STDOUT 1; # autoflush, so nothing lost on exec later -if (scalar(@ARGV) && $ARGV[0] =~ /^-*help$/) { # -help or --help given +if (scalar(@ARGV) && $ARGV[0] =~ m/^-+help$/) { # -help or --help given print_usage; exit 0; } @@ -70,6 +77,8 @@ if (scalar(@ARGV) == 0) { exit 1; } +# process test-bench-filename + $tb_code = shift @ARGV; my $tb_code_path = "."; my $tb_code_name = $tb_code; @@ -78,37 +87,33 @@ if ($tb_code =~ m|^(.*)/(.*)$|) { $tb_code_name = $2; } -my $tb_code_stem = $tb_code_name; -$tb_code_stem =~ s/_[fost]sim$//; # drop _ssim,_fsim, _osim, or _tsim +# process -run, -fifo and -verbose options (can be in any order now) -if ($tb_code_stem =~ /_ISim$/) { # is it an ISim executable ? - $is_isim = 1; - $tb_code_stem =~ s/_ISim$//; # drop _ISim - if (scalar(@ARGV) && $ARGV[0] eq "-run") { - $is_isim_run = 1; +while (scalar(@ARGV)) { + my $opt = $ARGV[0]; + if ($opt =~ m/^-+norun$/) { $opt_norun = 1; shift @ARGV;} + elsif ($opt =~ m/^-+fifo$/) { $opt_fifo = 1; shift @ARGV;} + elsif ($opt =~ m/^-+verbose$/) { $opt_verbose = 1; shift @ARGV;} + elsif ($opt =~ m/^-+run$/) { + print "tbw-I: legacy option '-run' seen and ignored; is now default\n"; shift @ARGV; } + else { last;} +} + +my $tb_code_stem = $tb_code_name; +$tb_code_stem =~ s/_[fsorept]sim$//; # drop sim mode suffix + +if ($tb_code_stem =~ /_ISim$/) { # is it an ISim executable ? + $tb_code_stem =~ s/_ISim$//; # drop _ISim + $is_isim = 1; + $is_isim_run = not $opt_norun; } if ($tb_code_stem =~ /_XSim$/) { # is it an XSim executable ? - $is_xsim = 1; $tb_code_stem =~ s/_XSim$//; # drop _XSim - if (scalar(@ARGV) && $ARGV[0] eq "-run") { # map -run to '-R' - $ARGV[0] = "-R"; - } -} - - -if (scalar(@ARGV) && $ARGV[0] eq "-fifo") { - push @file_dsc, {tag=>'rlink_cext_fifo_rx', val=>''}; - push @file_dsc, {tag=>'rlink_cext_fifo_tx', val=>''}; - push @file_dsc, {tag=>'rlink_cext_conf', val=>''}; - $is_fifo = 1; - shift @ARGV; -} -if (scalar(@ARGV) && $ARGV[0] eq "-verbose") { - $is_verbose = 1; - shift @ARGV; + $is_xsim = 1; + unshift @ARGV,'-R' unless $opt_norun; # run all unless '-norun' given } if (not -e $tb_code) { @@ -124,7 +129,7 @@ if (not -e $tb_code) { my $tbwdat_file = "tbw.dat"; $tbwdat_file = "$tb_code_path/tbw.dat" unless (-r "tbw.dat"); -if ((!$is_fifo) && -r $tbwdat_file) { +if (-r $tbwdat_file) { my $ok = 0; my $done = 0; @@ -145,20 +150,22 @@ if ((!$is_fifo) && -r $tbwdat_file) { print "tbw-E: bad line in tbw.dat:\n $_\n"; } } +} else { + print "tbw-W: failed to find $tbwdat_file\n"; } # # if no tbw.dat or no matching stanza found, setup defaults # - -if (!$is_fifo) { - unless (scalar (@file_dsc)) { +unless (scalar (@file_dsc)) { + if ($opt_fifo) { + push @file_dsc, {tag=>'rlink_cext_fifo_rx', val=>''}; + push @file_dsc, {tag=>'rlink_cext_fifo_tx', val=>''}; + push @file_dsc, {tag=>'rlink_cext_conf', val=>''}; + } else { push @file_dsc, {tag=>$tb_code_stem . "_stim", val=>$tb_code_stem . "_stim.dat"}; } -} else { - push @file_dsc, {tag=>"rlink_cext_fifo_rx", - val=>""}; } # @@ -199,7 +206,7 @@ if (!$is_fifo) { } } -if ($is_verbose) { +if ($opt_verbose) { foreach my $dsc (@file_dsc) { my $tag = $dsc->{tag}; my $val = $dsc->{val}; @@ -238,10 +245,21 @@ foreach my $dsc (@file_dsc) { $val = "/dev/null" if ($val eq ""); # null file case } + # handle file names + # - if absolute path keep then + # - if relative path seen note that it is relative to test bench code path + # --> prepent test bench path, canonize, and convert to a relative path + # name relavive to cwd ! + unless ($val =~ m|^/|) { + $val = $tb_code_path . '/' . $val; + $val = File::Spec->abs2rel(abs_path($val)); + } + if (not -r $val) { print "tbw-F: file for $tag not existing or not readable: $val\n"; exit 1; } + if (-l $tag) { my $cur_link = readlink $tag; if ($cur_link ne $val) { diff --git a/tools/bin/ti_rri b/tools/bin/ti_rri index bf4bd9a7..f6dd826e 100755 --- a/tools/bin/ti_rri +++ b/tools/bin/ti_rri @@ -1,8 +1,8 @@ #! /usr/bin/env tclshcpp # -*- tcl -*- -# $Id: ti_rri 631 2015-01-09 21:36:51Z mueller $ +# $Id: ti_rri 776 2016-06-18 17:22:51Z mueller $ # -# Copyright 2011-2015 by Walter F.J. Mueller +# Copyright 2011-2016 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -15,6 +15,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-01-09 776 1.2.2 add --tout option to setup rlc timeout before connect # 2015-01-09 631 1.2.1 use rlc get/set rather config # 2014-11-07 601 1.2 use tclshcpp (C++ based) rather tclsh # 2013-05-19 521 1.1.6 setup proper interactive handling; add --run reap @@ -41,6 +42,7 @@ # --logl=n ; default 2 # --dmpl=n ; default 0 # --tiol=n ; default 0 +# --tout=n ; default 1. # --int # --help # -- @@ -63,6 +65,7 @@ array set opts { logl_ 2 dmpl_ 0 tiol_ 0 + tout_ 1. int 0 help 0 } @@ -119,6 +122,7 @@ foreach arg $argv { ^--?logl=.+$ { regexp -- {=(.*)} $arg dummy opts(logl_) } ^--?dmpl=.+$ { regexp -- {=(.*)} $arg dummy opts(dmpl_) } ^--?tiol=.+$ { regexp -- {=(.*)} $arg dummy opts(tiol_) } + ^--?tout=.+$ { regexp -- {=(.*)} $arg dummy opts(tout_) } ^--?int$ { set opts(int) 1 } ^--?help$ { set opts(help) 1 } ^--$ { set optsendseen 1 } @@ -152,10 +156,11 @@ if { $opts(help) } { puts { --term=[NAME[,BAUD[,OPTS]]]} puts { --cuff[=ARGS] open cuff type rlink port. Optional arguments are:} puts { --cuff=[NAME[,OPTS]]} - puts { --log=FILE set log file name. Default is to write to stdout.} - puts { --logl=LVL set log level, default is '2' allowed values 0-3.} + puts { --log=FILE set log file name. Default is to write to stdout} + puts { --logl=LVL set log level, default is '2' allowed values 0-3} puts { --dmpl=LVL set dump level, default is '0', values like logl} - puts { --tiol=LVL set i/o trace level, default is '0', allowed 0-2.} + puts { --tiol=LVL set i/o trace level, default is '0', allowed 0-2} + puts { --tout=dt set timeout, default is '1.', must be >0.} puts { --int enter interactive mode even when commands given} puts { --help display this help and exit} puts { -- all following arguments are treated as tcl commands} @@ -216,6 +221,7 @@ if { $opts(log_) ne "-" } { rlc set printlevel $opts(logl_) rlc set dumplevel $opts(dmpl_) rlc set tracelevel $opts(tiol_) +rlc set timeout $opts(tout_) # first start, if specified with --run, the test bench # exec sh -c $cmd is used to execute a shell command including [], '',"" diff --git a/tools/bin/ti_w11 b/tools/bin/ti_w11 index e55a5ebb..ce3976d1 100755 --- a/tools/bin/ti_w11 +++ b/tools/bin/ti_w11 @@ -1,11 +1,14 @@ #!/usr/bin/perl -w -# $Id: ti_w11 745 2016-03-18 22:10:34Z mueller $ +# $Id: ti_w11 776 2016-06-18 17:22:51Z mueller $ # # Copyright 2013-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2016-06-18 776 1.3.5 use ti_rri --tout now +# 2016-03-20 748 1.3.4 BUGFIX: add portsel oob for -fx; +# use 120 sec timeout for simulation; add -ll,-dl,-tl # 2016-03-18 745 1.3.3 add arty support, add -fx # 2015-11-01 712 1.3.2 use sb_cntl pin 12 for tmu; add -ghw option # 2015-05-14 680 1.3.1 use now -f1,-f1e,-f2,-f2e (fx now f1e) @@ -31,6 +34,10 @@ my $opt_dry; my $opt_b; my $opt_io = ''; my $opt_f = ''; +my $opt_ll = '2'; +my $opt_dl = ''; +my $opt_tl = ''; +my $opt_to = ''; my $opt_tmu; my $opt_ghw; my $tirri; @@ -150,6 +157,15 @@ while (scalar(@ARGV)) { exit 1; } } + } elsif ($curarg =~ m{^-ll(\d)$} ) { # -ll (setup --logl) + $opt_ll = $1; + shift @ARGV; + } elsif ($curarg =~ m{^-dl(\d)$} ) { # -dl (setup --dmpl) + $opt_dl = $1; + shift @ARGV; + } elsif ($curarg =~ m{^-tl(\d)$} ) { # -tl (setup --tiol) + $opt_tl = $1; + shift @ARGV; } else { last; } @@ -203,11 +219,19 @@ if ($opt_io eq 'f') { exit 1; } +# setup timeout +if ($opt_io eq 'f') { + $opt_to = '120.'; # 120 sec timeout for simulation +} + # # setup all other ti_rri options # -push @arglist, '--logl=2'; +push @arglist, "--logl=${opt_ll}"; +push @arglist, "--dmpl=${opt_dl}" if $opt_dl ne ''; +push @arglist, "--tiol=${opt_tl}" if $opt_tl ne ''; +push @arglist, "--tout=${opt_to}" if $opt_to ne ''; push @arglist, '--int' unless $opt_b; push @arglist, '--pack=rw11'; push @arglist, @tiopts; # add options from ARGV @@ -225,6 +249,8 @@ if ($opt_io eq 'f') { if ($opt_f eq 'c') { push @arglist, 'rlc oob -sbdata 8 0x4'; # portsel = 0100 -> fx2 push @arglist, 'rlc oob -sbdata 16 0x4'; # swi = 0100 -> fx2 + } elsif ($opt_f eq 'x') { + push @arglist, 'rlc oob -sbdata 8 0x2'; # portsel = 0010 -> 1st ser XON } elsif ($opt_f eq '1x') { push @arglist, 'rlc oob -sbdata 8 0x2'; # portsel = 0010 -> 1st ser XON push @arglist, 'rlc oob -sbdata 16 0x2'; # swi = 0010 -> 1st ser XON @@ -310,9 +336,10 @@ sub print_usage { print " -fx use 1st serport with hardwired xon\n"; print " -f1 use 1st serport\n"; print " -f1x use 1st serport with switched xon\n"; - print " -f2 use 2nd serport (fusp)\n"; + print " -f2 use 2nd serport (fusp)\n"; print " -f2x use 2nd serport with switched xon\n"; print " -tmu activate trace and monitoring unit\n"; + print " -ghw activate ghdl wave dump with --wave=.ghw\n"; print " setup options for FPGA connects:\n"; print " -u use --cuff connect\n"; print " -t.. use --term connect\n"; diff --git a/tools/bin/vbomconv b/tools/bin/vbomconv index 27158b39..b4165011 100755 --- a/tools/bin/vbomconv +++ b/tools/bin/vbomconv @@ -1,5 +1,5 @@ #!/usr/bin/perl -w -# $Id: vbomconv 734 2016-02-20 22:43:20Z mueller $ +# $Id: vbomconv 778 2016-06-25 15:18:01Z mueller $ # # Copyright 2007-2016 by Walter F.J. Mueller # @@ -14,6 +14,14 @@ # # Revision History: # Date Rev Version Comment +# 2016-06-24 778 1.17.1 -vsyn_prj: add [rep]sim models & VBOMCONV_XSIM_LANG +# -ghdl_(i|m|a): use --workdir +# 2016-06-19 777 1.17 -vsyn_prj: sim and syn source sets based on -UUT +# -vsim_prj: finally functioning tsim builds +# 2016-04-30 766 1.16.2 use -UUT property instead of @uut +# 2016-04-23 764 1.16.1 --vsim_prj: use 'nosort' +# 2016-04-22 763 1.16 --vsim_prj: use bash+pipefail, check exit status +# 2016-03-27 752 1.15 1st support for file properties (xdc -SCOPE_REF) # 2016-02-20 734 1.14 add [ise,viv]; add preliminary --(vsyn|vsim)_export; # 2016-02-14 731 1.13 add @uut tag handling; # 2016-02-07 728 1.12 add vivado xsim support; protect for empty xdc set @@ -58,6 +66,7 @@ use 5.005; # require Perl 5.005 or higher use strict; # require strict checking use FileHandle; +use Cwd 'getcwd'; use Getopt::Long; @@ -88,6 +97,8 @@ sub scan_synsim; sub copy_edir; sub write_vbomdep; sub canon_fname; +sub parse_props; +sub setup_props; my @vbom_queue; # list of pending vbom's my @srcfile_list; # list of sources in compile order @@ -101,6 +112,7 @@ my %vbom_done; # key=vbom; val=done flags my %vbom_rank; # key=vbom; val=vbom ranks my %srcfile_rank; # key=source file; val=file rank my %srcfile_synsim; # key=source file; val=syn or sim +my %srcfile_prop; # key=source file; hash of props my %para_tbl; # substitution table my @ucf_cpp_list; my $is_ghdl = 0; # ghdl simulation target @@ -112,6 +124,10 @@ my $is_sim = 0; # simulation target (generic) my $is_ise = 0; # ISE target my $is_viv = 0; # vivado target my $is_any = 0; # ignore tags (for --flist) +my $is_bsim = 0; # is behavioural simulation +my $is_fsim = 0; # is functional simulation +my $is_tsim = 0; # is timing simulation +my $is_veri = 0; # is verilog model based my $nactions = 0; # number of action commands my $top_vbom; # top level vbom (from argv) my $eff_vbom; # effective vbom ([fot]sim->ssim map) @@ -122,15 +138,22 @@ my $uut; # uut level name my $has_unisim; # @lib:unisim seen or implied my $has_unimacro; # @lib:unimacro seen my $has_simprim; # @lib:simprim seen or implied -my $is_ssim; -my $is_fsim; -my $is_osim; -my $is_tsim; +my $sim_mode = 'bsim'; my $do_trace = exists $opts{trace}; my $level = 0; # vbom nesting level my $xst_writevhdl = 1; my $xlpath=$opts{xlpath}; my $no_xlpath = ! defined $xlpath || $xlpath eq ""; +my $xsim_lang = 'verilog'; # xsim model language + +$xsim_lang = $ENV{VBOMCONV_XSIM_LANG} if defined $ENV{VBOMCONV_XSIM_LANG}; +if ($xsim_lang ne 'verilog' && $xsim_lang ne 'vhdl') { + print STDERR "vbomconv-E: VBOMCONV_XSIM_LANG is '$xsim_lang'\n"; + print STDERR "vbomconv-E: VBOMCONV_XSIM_LANG must be 'verilog' or 'vhdl'\n"; + exit 1; +} + +$is_veri = $xsim_lang eq 'verilog'; autoflush STDOUT 1; # autoflush, so nothing lost on exec later @@ -147,6 +170,10 @@ if (scalar(@ARGV) != 1) { exit 1; } +# get number of CPUs (used later....) +my $nproc = `nproc`; +chomp $nproc; + # check that only one action is defined, mark xst, gdhl, or isim class foreach (keys %opts) { @@ -198,16 +225,19 @@ $stem =~ s{\..*$}{}; $top = $stem; $top =~ s{^.*/}{}; -# now prepare virtual _fsim, _osim, and _tsim vbom's +# now prepare virtual _[forept]sim vbom's # they are inferred from the _ssim vbom's -$is_ssim = 1 if $top_vbom =~ m{_ssim\.vbom$}; # detect _ssim -$is_fsim = 1 if $top_vbom =~ m{_fsim\.vbom$}; # detect _fsim -$is_osim = 1 if $top_vbom =~ m{_osim\.vbom$}; # detect _osim -$is_tsim = 1 if $top_vbom =~ m{_tsim\.vbom$}; # detect _tsim +if ($top_vbom =~ m{_([sforept]sim)\.vbom$}) { + $sim_mode = $1; +} + +$is_bsim = 1 if $sim_mode eq 'bsim'; +$is_fsim = 1 if $sim_mode =~ m/^[fsor]sim$/; +$is_tsim = 1 if $sim_mode =~ m/^[ept]sim$/; $eff_vbom = $top_vbom; -$eff_vbom =~ s{_[fot]sim\.vbom$}{_ssim.vbom}; # map [fot]sim -> ssim +$eff_vbom =~ s{_[forept]sim\.vbom$}{_ssim.vbom}; # map [forept]sim -> ssim # traverse all vbom's start with command line argument @@ -294,7 +324,7 @@ if ($do_trace) { print STDERR "\n"; print STDERR "properties:\n"; print STDERR " \@top: $top\n"; - print STDERR " \@uut: $uut\n" if defined $uut; + print STDERR " \-UUT: $uut\n" if defined $uut; } # --ghdh_a -- ghdl analysis command ---------------------------------- @@ -304,10 +334,11 @@ if (exists $opts{ghdl_a} || exists $opts{ghdl_a_cmd}) { print STDERR "vbomconv-E: --xlpath required with ghdl_a or ghdl_a_cmd"; exit 1; } + my $workdir = "ghdl.${sim_mode}"; foreach (@srcfile_list) { my $file = $_; - my $cmd = "ghdl -a"; + my $cmd = "ghdl -a --workdir=${workdir}"; $cmd .= " -P$xlpath/unisim" if $has_unisim; $cmd .= " -P$xlpath/unimacro" if $has_unimacro; $cmd .= " -P$xlpath/simprim" if $has_simprim; @@ -334,16 +365,19 @@ if (exists $opts{ghdl_a} || exists $opts{ghdl_a_cmd}) { # --ghdh_i -- ghdl inspection command -------------------------------- if (exists $opts{ghdl_i} || exists $opts{ghdl_i_cmd}) { + my $workdir = "ghdl.${sim_mode}"; my %ghdl_work; + system "mkdir ${workdir}" unless -d ${workdir}; + # read ghdl "work-obj93.cf" file. It has the format # file . "" "" "ghdl -i or -a date>": # entity at nn( nn) + nn on nn; # architecture of at nn( nn) + nn on nn; - if (-r "work-obj93.cf") { - open (WFILE, "work-obj93.cf") or - die "can't open for read work-obj93.cf: $!"; + if (-r "${workdir}/work-obj93.cf") { + open (WFILE, "${workdir}/work-obj93.cf") or + die "can't open for ${workdir}/read work-obj93.cf: $!"; while () { if (m{^file \. \"(.*?)\"}) { $ghdl_work{$1} = 1; @@ -352,7 +386,7 @@ if (exists $opts{ghdl_i} || exists $opts{ghdl_i_cmd}) { close (WFILE); } - my $cmd = "ghdl -i"; + my $cmd = "ghdl -i --workdir=${workdir}"; my $nfile = 0; foreach (@srcfile_list) { @@ -382,6 +416,7 @@ if (exists $opts{ghdl_i} || exists $opts{ghdl_i_cmd}) { # the right thing. if (exists $opts{ghdl_m} || exists $opts{ghdl_m_cmd} ) { + my $workdir = "ghdl.${sim_mode}"; my $cmd = ""; if ($no_xlpath && ($has_unisim || $has_unimacro || $has_simprim) ) { @@ -393,7 +428,7 @@ if (exists $opts{ghdl_m} || exists $opts{ghdl_m_cmd} ) { $cmd .= "rm $stem\n" ; # rm to force elaboration } - $cmd .= "ghdl -m"; + $cmd .= "ghdl -m --workdir=${workdir}"; $cmd .= " -o $stem"; # -fexplicit needed for ISE 13.1,13.3 $cmd .= ' -fexplicit' if $has_unisim or $has_unimacro or $has_simprim; @@ -401,7 +436,7 @@ if (exists $opts{ghdl_m} || exists $opts{ghdl_m_cmd} ) { $cmd .= " -P$xlpath/unimacro" if $has_unimacro; $cmd .= " -P$xlpath/simprim" if $has_simprim; $cmd .= " --ieee=synopsys"; - $cmd .= " --no-vital-checks" if $is_ssim or $is_fsim or $is_osim or $is_tsim; + $cmd .= " --no-vital-checks" if $sim_mode ne 'bsim'; foreach (@srcfile_list) { next unless /\.c$/; # C source ? @@ -442,20 +477,46 @@ if (exists $opts{isim_prj}) { # --vsyn_prj --------------------------------------------------------- if (exists $opts{vsyn_prj}) { - # setup sources + # determine source and simulation file sets + my @fl_syn; + my @fl_sim; + foreach my $fi (@srcfile_list) { + if ($srcfile_synsim{$fi} eq 'syn') { + push @fl_syn, $fi; + } else { + push @fl_sim, $fi; + } + } print "#\n"; - print "# setup sources\n"; + print "# setup sources for synthesis\n"; print "#\n"; - print "set src_files {\n"; - foreach (@srcfile_list) { + print "set syn_files {\n"; + foreach (@fl_syn) { print " $_\n"; } print "}\n"; print "\n"; print "set obj [get_filesets sources_1]\n"; - print "add_files -norecurse -fileset \$obj \$src_files\n"; - print "set_property \"top\" \"$top\" \$obj\n"; + print "add_files -norecurse -fileset \$obj \$syn_files\n"; + # defined top only when not doing test bench + print "set_property \"top\" \"$top\" \$obj\n" unless defined $uut; + + if (defined $uut) { + print "#\n"; + print "# setup sources for simulation\n"; + print "#\n"; + print "set sim_files {\n"; + foreach (@fl_sim) { + print " $_\n"; + } + print "}\n"; + print "\n"; + + print "set obj [get_filesets sim_1]\n"; + print "add_files -norecurse -fileset \$obj \$sim_files\n"; + print "set_property SOURCE_SET sources_1 \$obj\n"; + } # setup constraints print "#\n"; @@ -473,6 +534,15 @@ if (exists $opts{vsyn_prj}) { if (scalar @xdcfile_list) { print "set obj [get_filesets constrs_1]\n"; print "add_files -norecurse -fileset \$obj \$xdc_files\n"; + print "\n"; + foreach my $fnam (@xdcfile_list) { + if (exists $srcfile_prop{$fnam}->{-SCOPE_REF}) { + my $target = $srcfile_prop{$fnam}->{-SCOPE_REF}; + $target = $srcfile_prop{$fnam}->{VBstem} if $target eq ''; + print "set_property SCOPED_TO_REF $target \\\n"; + print " [get_files $fnam]\n"; + } + } } print "\n"; @@ -481,31 +551,54 @@ if (exists $opts{vsyn_prj}) { # --vsim_prj --------------------------------------------------------- if (exists $opts{vsim_prj}) { - print "#!/bin/sh\n"; + my $workdir = "xsim.${sim_mode}"; + my $fname_forwarder = "${stem}_XSim"; + $fname_forwarder =~ s/_([sorept]sim)_XSim/_XSim_$1/; + + print "#!/bin/bash\n"; + # pipefail ensures that in pipes like xvlog | tee ect the exits status is + # from the last failed command, and not simply from last command (tee). + # that ensures that the xvlog exit codes can be tested + print "set -o pipefail\n"; print "#\n"; print "# generated by vbomconv -vsim_prj $top_vbom\n"; print "#\n"; + print "# ---------- delete old forwarder\n"; + print "rm -f $fname_forwarder\n"; + print "#\n"; + + print "# ---------- setup fresh working directory\n"; + print "rm -rf ${workdir}\n"; + print "mkdir ${workdir}\n"; + print "pushd ${workdir}\n"; + print "#\n"; + # compile verilog before vhdl ! - # currently verilog only used for DPI interface code + # currently verilog only used for DPI interface code or simulation models # xvhdl relies in strict compilation order, also across languages, and fails - # when a not yet compiles module is instantiated via entiry work.... + # when a not yet compiled module is instantiated via entiry work.xxx if (scalar @srcfile_list_v) { print "# ---------- xvlog step\n"; my $tfile_xvlog_prj = "tmp_${stem}_xvlog.prj"; print "cat > $tfile_xvlog_prj <&1 |\\\n"; print " tee xvlog_${stem}.log\n"; + print 'exitstatus=$?' . "\n"; print "rm -f $tfile_xvlog_prj\n"; + print 'if (($exitstatus > 0)); then exit $exitstatus; fi' . "\n"; print "#\n"; } @@ -513,16 +606,21 @@ if (exists $opts{vsim_prj}) { print "# ---------- xvhdl step\n"; my $tfile_xvhdl_prj = "tmp_${stem}_xvhdl.prj"; print "cat > $tfile_xvhdl_prj <&1 |\\\n"; print " tee xvhdl_${stem}.log\n"; + print 'exitstatus=$?' . "\n"; print "rm -f $tfile_xvhdl_prj\n"; + print 'if (($exitstatus > 0)); then exit $exitstatus; fi' . "\n"; print "#\n"; } @@ -530,30 +628,49 @@ if (exists $opts{vsim_prj}) { print "# ---------- xsc step\n"; print "xtwv xsc"; foreach (@srcfile_list_c) { - print " \\\n $_"; + print " \\\n ../$_"; } print "\n"; + print 'exitstatus=$?' . "\n"; + print 'if (($exitstatus > 0)); then exit $exitstatus; fi' . "\n"; print "#\n"; } + # Note: xelab -mt auto doesn't seem to work, use --mt `nproc` print "# ---------- xelab step\n"; - print "xtwv xelab --relax --debug typical --mt auto -m64 \\\n"; - print " -L work \\\n"; + print "xtwv xelab --relax --debug typical --mt $nproc -m64 \\\n"; + print " -L xil_defaultlib"; + print " -L simprims_ver" if $is_tsim; + print " -L unisims_ver" if $is_veri && ! ($is_bsim || $is_tsim); + print " \\\n"; if (scalar @srcfile_list_c) { print " --sv_lib dpi \\\n"; } - print " --snapshot $stem work.$top \\\n"; - print " -log xelab_${stem}.log\n"; - print "\n"; + if ($is_tsim) { + print " -transport_int_delays -pulse_r 0 -pulse_int_r 0 \\\n"; + } + print " --snapshot $stem \\\n"; + print " -log xelab_${stem}.log \\\n"; + print " xil_defaultlib.$top"; + print " xil_defaultlib.glbl" if $is_tsim || ($is_veri && ! $is_bsim); + print " \n"; + print 'exitstatus=$?' . "\n"; + print 'if (($exitstatus > 0)); then exit $exitstatus; fi' . "\n"; + print "#\n"; + + my $cwd = getcwd(); + # use in forwarder full absolute path to relevant xsim.dir + # this allows to call the tb from every directory print "# ---------- create forwarder\n"; - my $fname_forwarder = "${stem}_XSim"; - $fname_forwarder =~ s/_([sot]sim)_XSim/_XSim_$1/; - print "if [ -x \"xsim.dir/${stem}/xsimk\" ]\n"; + print "popd\n"; + print "if [ -x \"${workdir}/xsim.dir/${stem}/xsimk\" ]\n"; print "then\n"; print "#\n"; print "cat > $fname_forwarder <$ofile.dep_ghdl") or + open (ODEPFILE, ">$ofile.dep_ghdl") or die "can't write $ofile.dep_ghdl: $!"; print ODEPFILE "$ofile : $_\n"; print ODEPFILE "\t\$(COMPILE.c) \$(OUTPUT_OPTION) \$<\n"; @@ -599,42 +712,24 @@ if (exists $opts{dep_ghdl}) { } } - if ($is_ssim) { + # Notes: _fsim only for ISE useful + # _tsim only for VIV useful + if ($sim_mode eq 'ssim') { + foreach my $type (qw(f o r t)) { + my $stem_ghdl = $stem; + $stem_ghdl =~ s/_ssim$/_${type}sim/; - print "#\n"; - foreach (@srcfile_list) { - my $file = $_; # copy to break alias for following s/// - if (/\.c$/) { - $file =~ s{^.*/}{}; # remove directory path - $file =~ s/\.c$/.o/; # depend on object file for C sources - } else { - $file =~ s/_ssim\.vhd$/_fsim.vhd/; + print "#\n"; + foreach (@srcfile_list) { + my $file = $_; # copy to break alias for following s/// + if (/\.c$/) { + $file =~ s{^.*/}{}; # remove directory path + $file =~ s/\.c$/.o/; # depend on object file for C sources + } else { + $file =~ s/_ssim\.vhd$/_${type}sim.vhd/; + } + print "$stem_ghdl : $file\n"; } - print "$stem_fsim : $file\n"; - } - - print "#\n"; - foreach (@srcfile_list) { - my $file = $_; # copy to break alias for following s/// - if (/\.c$/) { - $file =~ s{^.*/}{}; # remove directory path - $file =~ s/\.c$/.o/; # depend on object file for C sources - } else { - $file =~ s/_ssim\.vhd$/_osim.vhd/; - } - print "$stem_osim : $file\n"; - } - - print "#\n"; - foreach (@srcfile_list) { - my $file = $_; # copy to break alias for following s/// - if (/\.c$/) { - $file =~ s{^.*/}{}; # remove directory path - $file =~ s/\.c$/.o/; # depend on object file for C sources - } else { - $file =~ s/_ssim\.vhd$/_tsim.vhd/; - } - print "$stem_tsim : $file\n"; } } @@ -673,7 +768,7 @@ if (exists $opts{dep_xst}) { if (exists $opts{dep_isim}) { my $stem_isim = $stem . "_ISim"; - $stem_isim =~ s/_ssim_ISim$/_ISim_ssim/ if ($is_ssim); + $stem_isim =~ s/_ssim_ISim$/_ISim_ssim/ if ($sim_mode eq 'ssim'); my $stem_fsim_isim = $stem_isim; my $stem_tsim_isim = $stem_isim; @@ -682,7 +777,7 @@ if (exists $opts{dep_isim}) { print "#\n"; print "$stem_isim : $stem.dep_isim\n"; - if ($is_ssim) { + if ($sim_mode eq 'ssim') { print "$stem_fsim_isim : $stem.dep_isim\n"; print "$stem_tsim_isim : $stem.dep_isim\n"; } @@ -692,7 +787,7 @@ if (exists $opts{dep_isim}) { print "$stem_isim : $_\n"; } - if ($is_ssim) { + if ($sim_mode eq 'ssim') { print "#\n"; foreach (@srcfile_list) { @@ -741,18 +836,17 @@ if (exists $opts{dep_vsyn}) { if (exists $opts{dep_vsim}) { my $stem_vsim = $stem . "_XSim"; - $stem_vsim =~ s/_ssim_XSim$/_XSim_ssim/ if ($is_ssim); - - my $stem_osim_vsim = $stem_vsim; - my $stem_tsim_vsim = $stem_vsim; - $stem_osim_vsim =~ s/_ssim$/_osim/; - $stem_tsim_vsim =~ s/_ssim$/_tsim/; + $stem_vsim =~ s/_ssim_XSim$/_XSim_ssim/ if ($sim_mode eq 'ssim'); print "#\n"; print "$stem_vsim : $stem.dep_vsim\n"; - if ($is_ssim) { - print "$stem_osim_vsim : $stem.dep_vsim\n"; - print "$stem_tsim_vsim : $stem.dep_vsim\n"; + + if ($sim_mode eq 'ssim') { + foreach my $type (qw(o r e p t)) { + my $stem_xsim = $stem_vsim; + $stem_xsim =~ s/_ssim$/_${type}sim/; + print "$stem_xsim : $stem.dep_vsim\n"; + } } print "#\n"; @@ -760,22 +854,24 @@ if (exists $opts{dep_vsim}) { print "$stem_vsim : $_\n"; } - if ($is_ssim) { + if ($sim_mode eq 'ssim') { - print "#\n"; - foreach (@srcfile_list) { - my $file = $_; # copy to break alias for following s/// - $file =~ s/_ssim\.vhd$/_osim.vhd/; - print "$stem_osim_vsim : $file\n"; - } + # Note: when --dep_vsim is used for a _ssim.vbom read_vbom will remap + # _ssim.vhd to _ssim.v depending on $xsim_lang. [ept]sim always uses + # verilog, that's why there is a explict mapping below. - print "#\n"; - foreach (@srcfile_list) { - my $file = $_; # copy to break alias for following s/// - $file =~ s/_ssim\.vhd$/_tsim.v/; - print "$stem_tsim_vsim : $file\n"; + foreach my $type (qw(o r e p t)) { + my $stem_xsim = $stem_vsim; + $stem_xsim =~ s/_ssim$/_${type}sim/; + + print "#\n"; + foreach (@srcfile_list) { + my $file = $_; # copy to break alias for following s/// + $file =~ s/_ssim\.(v|vhd)$/_${type}sim.$1/; + $file =~ s/_([ept])sim\.vhd$/_${1}sim.v/; # see Note above + print "$stem_xsim : $file\n"; + } } -# } write_vbomdep("$stem.dep_vsim"); @@ -874,7 +970,7 @@ if (exists $opts{vsyn_export} or } elsif ($fname =~ m{\.xdc}) { # .xdc push @fl_xdc, $fname; } else { - print STDERR "vbomconv-W: file $fname not procesed (unknown type)\n"; + print STDERR "vbomconv-W: file $fname not processed (unknown type)\n"; } } @@ -1064,7 +1160,6 @@ sub read_vbom { my $tag; my $val = $_; - my $uut_seen; # detect tag:val lines if (m{^\s*(.*?)\s*:\s*(.*?)\s*$}) { @@ -1083,7 +1178,10 @@ sub read_vbom { # process @xdc: lines } elsif ($tag eq '@xdc') { - push @{$vbom_xdc{$vbom}}, canon_fname($vbom_path, $val); + my ($fname,$rphash) = parse_props($val); + $fname = canon_fname($vbom_path, $fname); + setup_props($fname, $rphash); + push @{$vbom_xdc{$vbom}}, $fname; next; # process @lib: lines @@ -1100,12 +1198,6 @@ sub read_vbom { } next; - # process @uut: lines - } elsif ($tag eq '@uut') { - $uut_seen = 1; - # Note: fall through in this case, process as normal file name - # actual @uut tag handling later with canonized file names. - # catch invalid @ tags } else { print STDERR "vbomconv-E: invalid \'$tag:\' line in $vbom_file\n"; @@ -1114,35 +1206,59 @@ sub read_vbom { } - # now do _fsim, _osim, _tsim mapping - $val =~ s{_ssim\.vhd$}{_fsim.vhd} if $is_fsim; - $val =~ s{_ssim\.vhd$}{_osim.vhd} if $is_osim; - $val =~ s{_ssim\.vhd$}{_tsim.vhd} if $is_tsim && $is_ise; # ISE - $val =~ s{_ssim\.vhd$}{_tsim.v} if $is_tsim && $is_viv; # Vivado + # split in filename and property list + my ($fname,$rphash) = parse_props($val); - # process normal .vhd or .vbom file lines + # now do model source file mapping + my $fname_old = $fname; + if ($is_ise || $is_ghdl) { + $fname =~ s{_ssim\.vhd$}{_fsim.vhd} if $sim_mode eq 'fsim'; + $fname =~ s{_ssim\.vhd$}{_osim.vhd} if $sim_mode eq 'osim'; + $fname =~ s{_ssim\.vhd$}{_rsim.vhd} if $sim_mode eq 'rsim'; + $fname =~ s{_ssim\.vhd$}{_tsim.vhd} if $sim_mode eq 'tsim'; + } + if ($is_viv) { + $fname =~ s{_ssim\.vhd$}{_esim.v} if $sim_mode eq 'esim'; + $fname =~ s{_ssim\.vhd$}{_psim.v} if $sim_mode eq 'psim'; + $fname =~ s{_ssim\.vhd$}{_tsim.v} if $sim_mode eq 'tsim'; + if ($is_veri) { + $fname =~ s{_ssim\.vhd$}{_ssim.v} if $sim_mode eq 'ssim'; + $fname =~ s{_ssim\.vhd$}{_osim.v} if $sim_mode eq 'osim'; + $fname =~ s{_ssim\.vhd$}{_rsim.v} if $sim_mode eq 'rsim'; + } else { + $fname =~ s{_ssim\.vhd$}{_osim.vhd} if $sim_mode eq 'osim'; + $fname =~ s{_ssim\.vhd$}{_rsim.vhd} if $sim_mode eq 'rsim'; + } + } + print STDERR "--- map $fname_old -> $fname\n" + if $do_trace && $fname_old ne $fname; + + # process normal .vhd, .v, or .vbom file lines # canonize file name unless not already done by filename substitution my $fullname; - if ($val =~ m{^!(.*)$}) { + if ($fname =~ m{^!(.*)$}) { $fullname = $1; } else { - $fullname = canon_fname($vbom_path, $val); + $fullname = canon_fname($vbom_path, $fname); } - # process @uut tag here, with canonized file names - if ($uut_seen) { + # handle properties + setup_props($fullname, $rphash); + + # process -UUT property here, with canonized file names + if (exists $rphash->{-UUT}) { if (defined $uut) { - print STDERR "vbomconv-E: duplicate \@uut:, 1st '$uut' 2nd '$val'\n"; + print STDERR "vbomconv-E: duplicate -UUT:, 1st '$uut' 2nd '$val'\n"; exit 1; } $uut = $fullname; } # determine whether additional libs needed - if ($fullname =~ m{_[so]sim\.vhd$}) { # ends in _ssim.vhd or _osim.vhd + if ($fullname =~ m{_[sor]sim\.vhd$}) { # is ssim, osim or rsim $has_unisim = 1; } - if ($fullname =~ m{_[ft]sim\.vhd$}) { # ends in _fsim.vhd or _tsim.vhd + if ($fullname =~ m{_[ft]sim\.vhd$}) { # is fsim or tsim $has_simprim = 1; } @@ -1219,7 +1335,7 @@ sub do_synsim { # if @uut seen separate them if (defined $uut) { - if ($uut =~ m{\.vbom}) { # uut is vbom (functional sim) + if ($uut =~ m{\.vbom}) { # uut is vbom (behavioral sim) scan_synsim($uut); } else { # uut is file (post syn sim) $srcfile_synsim{$uut} = 'syn'; @@ -1282,6 +1398,49 @@ sub canon_fname { return join "/", @flist; } +#------------------------------------------------------------------------------- +sub parse_props { + my ($val) = @_; + my $fname = $val; + my %phash = (); + if ($val =~ /^\s*(\S+)\s+(-.+)$/) { # "fname -xxx..." seen + $fname = $1; + my $plist = $2; + foreach my $pitem (split /\s+/,$plist) { + if ($pitem =~ m/^(.*)\:(.*)$/) { # -key:val (not k=v !!) + $phash{$1} = $2; + } else { + $phash{$pitem} = ''; + } + } + } + + return ($fname, \%phash); + +} + +#------------------------------------------------------------------------------- +sub setup_props { + my ($fname, $rphash) = @_; + $srcfile_prop{$fname} = $rphash; + my $path = '.'; + my $name = $fname; + if ($fname =~ m|^(.+)/(.+)$|) { + $path = $1; + $name = $2; + } + my $stem = $name; + my $type = ''; + if ($name =~ m/^(.+)(\..*)/) { + $stem = $1; + $type = $2; + } + $srcfile_prop{$fname}->{VBpath} = $path; + $srcfile_prop{$fname}->{VBstem} = $stem; + $srcfile_prop{$fname}->{VBtype} = $type; + return; +} + #------------------------------------------------------------------------------- sub print_help { diff --git a/tools/bin/xise_msg_summary b/tools/bin/xise_msg_summary new file mode 100755 index 00000000..42955a56 --- /dev/null +++ b/tools/bin/xise_msg_summary @@ -0,0 +1,27 @@ +#!/bin/bash +# $Id: xise_msg_summary 772 2016-06-05 12:55:11Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Vers Comment +# 2016-06-05 772 1.0 Initial version +# + +for f in `find -name "*.imfset" | sort` +do + dnam=`dirname $f` + bnam=`basename $f .imfset` + echo "" + echo "####################################################################" + echo "### ${dnam}/${bnam} ###" + pushd ${dnam} > /dev/null + if [ ! -r ${bnam}_xst.log ] + then + echo No ${bnam}_xst.log available + else + make ${bnam}.mfsum + fi + popd > /dev/null +done diff --git a/tools/bin/xviv_ghdl_unisim b/tools/bin/xviv_ghdl_unisim index a74da50f..0d20c438 100755 --- a/tools/bin/xviv_ghdl_unisim +++ b/tools/bin/xviv_ghdl_unisim @@ -1,11 +1,12 @@ #!/bin/bash -# $Id: xviv_ghdl_unisim 642 2015-02-06 18:53:12Z mueller $ +# $Id: xviv_ghdl_unisim 762 2016-04-17 21:33:42Z mueller $ # -# Copyright 2015- by Walter F.J. Mueller +# Copyright 2015-2016 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Vers Comment +# 2016-04-17 762 1.1 update for viv 2016.1 # 2015-02-02 642 1.0 Initial version # @@ -114,8 +115,15 @@ fi cd unimacro # cp $XTWV_PATH/data/vhdl/src/unimacro/*.vhd . + +if [ -r $XTWV_PATH/data/vhdl/src/unimacro/vhdl_analyze_order ] +then + cp $XTWV_PATH/data/vhdl/src/unimacro/vhdl_analyze_order . +else + ls -1 *.vhd > vhdl_analyze_order +fi # -for file in *.vhd +for file in `cat vhdl_analyze_order` do echo "# ghdl ... $file" ghdl -a -P../unisim -fexplicit --ieee=synopsys --work=unimacro \ diff --git a/tools/bin/xviv_msg_filter b/tools/bin/xviv_msg_filter new file mode 100755 index 00000000..fee3c3c5 --- /dev/null +++ b/tools/bin/xviv_msg_filter @@ -0,0 +1,270 @@ +#!/usr/bin/perl -w +# $Id: xviv_msg_filter 772 2016-06-05 12:55:11Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# +# This program is free software; you may redistribute and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation, either version 2, or at your option any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for complete details. +# +# Revision History: +# Date Rev Version Comment +# 2016-06-04 772 1.0 Initial version +# + +use 5.14.0; # require Perl 5.14 or higher +use strict; # require strict checking +use FileHandle; + +use Getopt::Long; + +my %opts = (); + +GetOptions(\%opts, "help", "pacc") || exit 1; + +sub print_help; +sub read_mfs; +sub read_log; + +my $type = shift @ARGV; +my $mfsnam = shift @ARGV; +my $lognam = shift @ARGV; +my @flist; +my @mlist; +my $nackcnt = 0; +my $ackcnt = 0; +my $imisscnt = 0; +my $rmisscnt = 0; +my $timebad = 0; +my $timegood = 0; + +my $retrobase = $ENV{RETROBASE}; + +autoflush STDOUT 1 if (-p STDOUT); # autoflush if output into pipe + +if (exists $opts{help}) { + print_help; + exit 0; +} + +if (!defined $type || !defined $mfsnam || !defined $lognam) { + print STDERR "xviv_msg_filter-E: one of 'type mfset log' missing \n\n"; + print_help; + exit 1; +} + +if ($type !~ m{^(syn|imp)$}) { + print STDERR "xviv_msg_filter-E: type must be syn or imp\n"; + exit 1; +} + +if (read_mfs($mfsnam)) {exit 1;} +if (read_log($lognam)) {exit 1;} + +foreach my $m (@mlist) { + my $msev = $m->[0]; + my $mcode = $m->[1]; + my $mtext = $m->[2]; + my $msgmatch = 0; + + # check for timing closure + # bad: [Route 35-39] The design did not meet timing requirements + # bad: [Timing 38-282] The design failed to meet the timing ... + # good: [Route 35-61] The design met the timing requirement + $timebad += 1 if $type eq 'imp' && $mcode eq 'Route 35-39'; + $timebad += 1 if $type eq 'imp' && $mcode eq 'Timing 38-282'; + $timegood += 1 if $type eq 'imp' && $mcode eq 'Route 35-61'; + + foreach my $f (@flist) { + my $fmode = $f->[0]; + my $fcode = $f->[1]; + my $frege = $f->[2]; + if ($frege eq '') { + $msgmatch = $mcode eq $fcode; + } else { + $msgmatch = $mcode eq $fcode && $mtext =~ m{$frege}; + } + if ($msgmatch) { + #print "+++m '$fmode' '$fcode' '$frege' : '$mcode' '$mtext'\n"; + $f->[3] += 1; + last; + } + } + + $msgmatch = 1 if $msev eq 'INFO'; # accept all INFO + + if ($msgmatch) { + $m->[3] += 1; + } else { + $nackcnt += 1; + } +} + +if ($nackcnt) { + print "Unexpected messages of type [$type] from $lognam:\n"; + foreach my $m (@mlist) { + next if $m->[3]; + + # now prety print the message + # remove $RETROBASE from file names + my $mtext = $m->[2]; + $mtext =~ s/${retrobase}/.../g if defined $retrobase; + # and break it up into 80 character wide lines + my @mwl = split /\s+/,$mtext; + unshift @mwl, '[' . $m->[1] . ']'; + unshift @mwl, $m->[0] . ':'; + my $pref = ' '; + my $line = ' '; + while (scalar(@mwl)) { + my $word = shift @mwl; + if (length($line) + length($word) + 1 > 80) { + print "$line\n"; + $line = $pref; + } + $line .= ' ' . $word; + } + print "$line\n" if $line ne $pref; + } + print "\n"; +} + +foreach my $f (@flist) { + if ($f->[3] != 0) { # matches seen + $ackcnt += 1; + } else { # matches not seen + if ($f->[0] eq 'i') { # complain if 'i' + $imisscnt += 1; + } elsif ($f->[0] eq 'r') { # complain if 'r' + $rmisscnt += 1; + } + } +} + +if ($ackcnt && exists $opts{pacc}) { + print "Accepted messages for type [$type] from $lognam:\n"; + foreach my $f (@flist) { + next if $f->[3] == 0; + printf "%4d: [%s] %s\n", $f->[3], $f->[1], $f->[2]; + } + print "\n"; +} + +if ($imisscnt) { + print "Ignore filter rules with no matches for type [$type] from $lognam:\n"; + foreach my $f (@flist) { + next if $f->[3] != 0; + printf "%4d: [%s] %s\n", $f->[3], $f->[1], $f->[2] if $f->[0] eq 'i'; + } + print "\n"; +} + +if ($rmisscnt) { + print "Missed required messages for type [$type] from $lognam:\n"; + foreach my $f (@flist) { + next if $f->[3] != 0; + printf "%4d: [%s] %s\n", $f->[3], $f->[1], $f->[2] if $f->[0] eq 'r'; + } + print "\n"; +} + +if ($type eq 'imp' && ($timebad > 0 || $timegood == 0)) { + printf "!! ------------------------------ !!\n"; + printf "!! FAILED TO REACH TIMING CLOSURE !!\n"; + printf "!! ------------------------------ !!\n"; +} + +#------------------------------------------------------------------------------- +sub read_mfs { + my ($fname) = @_; + + if (not -r $fname) { + print STDERR "xviv_msg_filter-E: \'$fname\' not existing or readable\n"; + return 1; + } + + my $fh = new FileHandle; + $fh->open($fname) or die "can't open for read $fname: $!"; + + my $intyp = 0; + + while (<$fh>) { + chomp; + s/#.*//; # remove comments after # + s/\s+$//; # remove trailing blanks + next if /^\s*$/; # drop empty lines + + if (/^\@(.+)$/) { # @ found + my $rc = read_mfs($1); + return $rc if $rc; + next; + } + + if (m{^\[([a-z]{3})\]$}) { # [typ] tag found + if ($1 eq $type) { + $intyp = 1; + } else { + $intyp = 0; + } + next; + } + + next unless $intyp; # only process relevant lines + + if (/^([iIr])\s+\[(.+?)\]\s*(.*)\s*$/) { + #print "+++0m '$1' '$2' '$3'\n"; + my $fmode = $1; + my $fcode = $2; + my $frege = $3; + $frege =~ s/\[/\\\[/g; + $frege =~ s/\]/\\\]/g; + push @flist, [$fmode,$fcode,$frege, 0]; + } else { + printf STDERR "xviv_msg_filter-E: bad line in mfset: '%s'\n", $_; + } + } + + $fh->close(); + + return 0; +} + +#------------------------------------------------------------------------------- +sub read_log { + my ($fname) = @_; + + if (not -r $fname) { + print STDERR "xviv_msg_filter-E: \'$fname\' not existing or readable\n"; + return 1; + } + + open (LFILE, $fname) or die "can't open for read $fname: $!"; + + while () { + chomp; + if (m{^(INFO|WARNING|CRITICAL WARNING|ERROR):\s*\[(.+?)\]\s*(.*)}) { + #print "+++0l '$1' '$2' '$3'\n"; + push @mlist, [$1,$2,$3,0]; + } + } + + close (LFILE); + + return 0; +} + +#------------------------------------------------------------------------------- + +sub print_help { + print "usage: xviv_msg_filter [options] type mfset log\n"; + print " type log file type: syn or imp\n"; + print " mfset message filter set file\n"; + print " log log file\n"; + print " Options:\n"; + print " --pacc print summary of accepted messages\n"; + print " --help this message\n"; +} diff --git a/tools/bin/xviv_msg_summary b/tools/bin/xviv_msg_summary new file mode 100755 index 00000000..fe6bdbc7 --- /dev/null +++ b/tools/bin/xviv_msg_summary @@ -0,0 +1,27 @@ +#!/bin/bash +# $Id: xviv_msg_summary 772 2016-06-05 12:55:11Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Vers Comment +# 2016-06-05 772 1.0 Initial version +# + +for f in `find -name "*.vmfset" | sort` +do + dnam=`dirname $f` + bnam=`basename $f .vmfset` + echo "" + echo "####################################################################" + echo "### ${dnam}/${bnam} ###" + pushd ${dnam} > /dev/null + if [ ! -r ${bnam}_syn.log ] + then + echo No ${bnam}_syn.log available + else + make ${bnam}.mfsum + fi + popd > /dev/null +done diff --git a/tools/bin/xviv_sim_vhdl_cleanup b/tools/bin/xviv_sim_vhdl_cleanup new file mode 100755 index 00000000..43b84407 --- /dev/null +++ b/tools/bin/xviv_sim_vhdl_cleanup @@ -0,0 +1,16 @@ +#!/bin/bash +# $Id: xviv_sim_vhdl_cleanup 774 2016-06-12 17:08:47Z mueller $ +# +# Copyright 2014-2016 by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2016-06-12 774 1.0 Initial version +# + +# cleanup vivado generated vhdl models for ghdl +# 1. remove 'attribute RTL_KEEP' decorations +# ghdl 0.33 does not accept decorations of port signals ! + +sed -i.bak -e '/^ *attribute *RTL_KEEP/ d' $1 diff --git a/tools/dox/w11_cpp.Doxyfile b/tools/dox/w11_cpp.Doxyfile index e6237282..6d5b5810 100644 --- a/tools/dox/w11_cpp.Doxyfile +++ b/tools/dox/w11_cpp.Doxyfile @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - cpp" -PROJECT_NUMBER = 0.72 +PROJECT_NUMBER = 0.73 PROJECT_BRIEF = "Backend server for Rlink and w11" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/cpp diff --git a/tools/dox/w11_tcl.Doxyfile b/tools/dox/w11_tcl.Doxyfile index d7d60adc..80fda3c1 100644 --- a/tools/dox/w11_tcl.Doxyfile +++ b/tools/dox/w11_tcl.Doxyfile @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - tcl" -PROJECT_NUMBER = 0.72 +PROJECT_NUMBER = 0.73 PROJECT_BRIEF = "Backend server for Rlink and w11" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/tcl diff --git a/tools/dox/w11_vhd_all.Doxyfile b/tools/dox/w11_vhd_all.Doxyfile index d18b4fe0..75cd3dcc 100644 --- a/tools/dox/w11_vhd_all.Doxyfile +++ b/tools/dox/w11_vhd_all.Doxyfile @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - vhd" -PROJECT_NUMBER = 0.72 +PROJECT_NUMBER = 0.73 PROJECT_BRIEF = "W11 CPU core and support modules" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/vhd diff --git a/tools/src/librlink/RlinkConnect.cpp b/tools/src/librlink/RlinkConnect.cpp index a05ae7dd..71fe7896 100644 --- a/tools/src/librlink/RlinkConnect.cpp +++ b/tools/src/librlink/RlinkConnect.cpp @@ -1,6 +1,6 @@ -// $Id: RlinkConnect.cpp 679 2015-05-13 17:38:46Z mueller $ +// $Id: RlinkConnect.cpp 758 2016-04-02 18:01:39Z mueller $ // -// Copyright 2011-2015 by Walter F.J. Mueller +// Copyright 2011-2016 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,8 @@ // // Revision History: // Date Rev Version Comment +// 2016-04-02 758 2.5 add USR_ACCESS register support (RLUA0/RLUA1) +// 2016-03-20 748 2.4 add fTimeout,(Set)Timeout(); // 2015-05-10 678 2.3.1 WaitAttn(): BUGFIX: return 0. (not -1.) if poll // 2015-04-12 666 2.3 add LinkInit,LinkInitDone; transfer xon // 2015-04-02 661 2.2 expect logic: stat expect in Command, invert mask @@ -36,7 +38,7 @@ /*! \file - \version $Id: RlinkConnect.cpp 679 2015-05-13 17:38:46Z mueller $ + \version $Id: RlinkConnect.cpp 758 2016-04-02 18:01:39Z mueller $ \brief Implemenation of RlinkConnect. */ @@ -72,6 +74,8 @@ const uint16_t RlinkConnect::kRbaddr_RLCNTL; const uint16_t RlinkConnect::kRbaddr_RLSTAT; const uint16_t RlinkConnect::kRbaddr_RLID1; const uint16_t RlinkConnect::kRbaddr_RLID0; +const uint16_t RlinkConnect::kRbaddr_RLUA1; +const uint16_t RlinkConnect::kRbaddr_RLUA0; const uint16_t RlinkConnect::kRLCNTL_M_AnEna; const uint16_t RlinkConnect::kRLCNTL_M_AtoEna; @@ -108,11 +112,13 @@ RlinkConnect::RlinkConnect() fPrintLevel(2), // default print: error and checks fDumpLevel(0), // default dump: no fTraceLevel(0), // default trace: no + fTimeout(10.), // default timeout: 10 sec fspLog(new RlogFile(&cout)), fConnectMutex(), fAttnNotiPatt(0), fTsLastAttnNoti(-1), fSysId(0xffffffff), + fUsrAcc(0x00000000), fRbufSize(2048) { for (size_t i=0; i<8; i++) fSeqNumber[i] = 0; @@ -174,6 +180,7 @@ bool RlinkConnect::Open(const std::string& name, RerrMsg& emsg) fLinkInitDone = false; fRbufSize = 2048; // use minimum (2kB) as startup fSysId = 0xffffffff; + fUsrAcc = 0x00000000; if (! fpPort->Url().FindOpt("noinit")) { if (!LinkInit(emsg)) { @@ -216,10 +223,22 @@ bool RlinkConnect::LinkInit(RerrMsg& emsg) clist.AddRreg(kRbaddr_RLID1); clist.AddRreg(kRbaddr_RLID0); + // RLUA0/1 are optional registers, available for 7Series and higher + clist.AddRreg(kRbaddr_RLUA1); + clist.SetLastExpectStatus(0,0); // disable stat check + clist.AddRreg(kRbaddr_RLUA0); + clist.SetLastExpectStatus(0,0); // disable stat check + if (!Exec(clist, emsg)) return false; fLinkInitDone = true; - + + // handle rlink core registers: setup mappings, keep data + AddrMapInsert("rl.cntl", kRbaddr_RLCNTL); + AddrMapInsert("rl.stat", kRbaddr_RLSTAT); + AddrMapInsert("rl.id1", kRbaddr_RLID1); + AddrMapInsert("rl.id0", kRbaddr_RLID0); + uint16_t rlstat = clist[0].Data(); uint16_t rlid1 = clist[1].Data(); uint16_t rlid0 = clist[2].Data(); @@ -227,6 +246,21 @@ bool RlinkConnect::LinkInit(RerrMsg& emsg) fRbufSize = size_t(1) << (10 + (rlstat & kRLSTAT_M_RBSize)); fSysId = uint32_t(rlid1)<<16 | uint32_t(rlid0); + // handle rlink optional registers: USR_ACCESS + const uint8_t staterr = RlinkCommand::kStat_M_RbTout | + RlinkCommand::kStat_M_RbNak | + RlinkCommand::kStat_M_RbErr; + if ((clist[3].Status() & staterr) == 0 && // RLUA1 ok + (clist[4].Status() & staterr) == 0) { // RLUA0 ok + + AddrMapInsert("rl.ua1", kRbaddr_RLUA1); + AddrMapInsert("rl.ua0", kRbaddr_RLUA0); + + uint16_t rlua1 = clist[3].Data(); + uint16_t rlua0 = clist[4].Data(); + fUsrAcc = uint32_t(rlua1)<<16 | uint32_t(rlua0); + } + return true; } @@ -575,6 +609,15 @@ void RlinkConnect::SetTraceLevel(uint32_t lvl) //------------------------------------------+----------------------------------- //! FIXME_docs +void RlinkConnect::SetTimeout(double timeout) +{ + fTimeout = timeout; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + bool RlinkConnect::LogOpen(const std::string& name, RerrMsg& emsg) { if (!fspLog->Open(name, emsg)) { @@ -702,8 +745,8 @@ bool RlinkConnect::ExecPart(RlinkCommandList& clist, size_t ibeg, size_t iend, if (!fSndPkt.SndPacket(fpPort.get(), emsg)) return false; // FIXME_code: handle recoveries - // FIXME_code: use proper value for timeout - bool ok = ReadResponse(15., emsg); + // FIXME_code: use proper value for timeout (rest time for Exec ?) + bool ok = ReadResponse(fTimeout, emsg); if (!ok) Rexception("RlinkConnect::ExecPart()","faulty response"); int ncmd = DecodeResponse(clist, ibeg, iend); diff --git a/tools/src/librlink/RlinkConnect.hpp b/tools/src/librlink/RlinkConnect.hpp index be07d296..1aba5257 100644 --- a/tools/src/librlink/RlinkConnect.hpp +++ b/tools/src/librlink/RlinkConnect.hpp @@ -1,6 +1,6 @@ -// $Id: RlinkConnect.hpp 666 2015-04-12 21:17:54Z mueller $ +// $Id: RlinkConnect.hpp 758 2016-04-02 18:01:39Z mueller $ // -// Copyright 2011-2015 by Walter F.J. Mueller +// Copyright 2011-2016 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,8 @@ // // Revision History: // Date Rev Version Comment +// 2016-04-02 758 2.5 add USR_ACCESS register support (RLUA0/RLUA1) +// 2016-03-20 748 2.4 add fTimeout,(Set)Timeout(); // 2015-04-12 666 2.3 add LinkInit,LinkInitDone; transfer xon // 2015-04-02 661 2.2 expect logic: stat expect in Command, invert mask // 2015-01-06 631 2.1 full rlink v4 implementation @@ -37,7 +39,7 @@ /*! \file - \version $Id: RlinkConnect.hpp 666 2015-04-12 21:17:54Z mueller $ + \version $Id: RlinkConnect.hpp 758 2016-04-02 18:01:39Z mueller $ \brief Declaration of class \c RlinkConnect. */ @@ -109,6 +111,7 @@ namespace Retro { bool SndAttn(RerrMsg& emsg); uint32_t SysId() const; + uint32_t UsrAcc() const; size_t RbufSize() const; size_t BlockSizeMax() const; size_t BlockSizePrudent() const; @@ -129,6 +132,7 @@ namespace Retro { void SetPrintLevel(uint32_t lvl); void SetDumpLevel(uint32_t lvl); void SetTraceLevel(uint32_t lvl); + void SetTimeout(double timeout); uint32_t LogBaseAddr() const; uint32_t LogBaseData() const; @@ -136,6 +140,7 @@ namespace Retro { uint32_t PrintLevel() const; uint32_t DumpLevel() const; uint32_t TraceLevel() const; + double Timeout() const; bool LogOpen(const std::string& name, RerrMsg& emsg); void LogUseStream(std::ostream* pstr, @@ -156,6 +161,8 @@ namespace Retro { static const uint16_t kRbaddr_RLSTAT = 0xfffe; //!< rlink core reg RLSTAT static const uint16_t kRbaddr_RLID1 = 0xfffd; //!< rlink core reg RLID1 static const uint16_t kRbaddr_RLID0 = 0xfffc; //!< rlink core reg RLID0 + static const uint16_t kRbaddr_RLUA1 = 0xfffb; //!< rlink opt. reg RLUA1 + static const uint16_t kRbaddr_RLUA0 = 0xfffa; //!< rlink opt. reg RLUA0 static const uint16_t kRLCNTL_M_AnEna = kWBit15;//!< RLCNTL: an enable static const uint16_t kRLCNTL_M_AtoEna= kWBit14;//!< RLCNTL: ato enable @@ -236,11 +243,13 @@ namespace Retro { uint32_t fPrintLevel; //!< print 0=off,1=err,2=chk,3=all uint32_t fDumpLevel; //!< dump 0=off,1=err,2=chk,3=all uint32_t fTraceLevel; //!< trace 0=off,1=buf,2=char + double fTimeout; //!< response timeout boost::shared_ptr fspLog; //!< log file ptr boost::recursive_mutex fConnectMutex; //!< mutex to lock whole connect uint16_t fAttnNotiPatt; //!< attn notifier pattern double fTsLastAttnNoti; //!< time stamp last attn notify uint32_t fSysId; //!< SYSID of connected device + uint32_t fUsrAcc; //!< USR_ACCESS of connected device size_t fRbufSize; //!< Rbuf size (in bytes) }; diff --git a/tools/src/librlink/RlinkConnect.ipp b/tools/src/librlink/RlinkConnect.ipp index de5798d4..8f14136b 100644 --- a/tools/src/librlink/RlinkConnect.ipp +++ b/tools/src/librlink/RlinkConnect.ipp @@ -1,6 +1,6 @@ -// $Id: RlinkConnect.ipp 666 2015-04-12 21:17:54Z mueller $ +// $Id: RlinkConnect.ipp 758 2016-04-02 18:01:39Z mueller $ // -// Copyright 2011-2015 by Walter F.J. Mueller +// Copyright 2011-2016 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,8 @@ // // Revision History: // Date Rev Version Comment +// 2016-04-02 758 2.4 add USR_ACCESS register support (RLUA0/RLUA1) +// 2016-03-20 748 2.3 add fTimeout,(Set)Timeout(); // 2015-04-12 666 2.2 add LinkInit,LinkInitDone; transfer xon // 2015-01-06 631 2.1 full rlink v4 implementation // 2013-03-05 495 1.2.1 add Exec() without emsg (will send emsg to LogFile) @@ -26,7 +28,7 @@ /*! \file - \version $Id: RlinkConnect.ipp 666 2015-04-12 21:17:54Z mueller $ + \version $Id: RlinkConnect.ipp 758 2016-04-02 18:01:39Z mueller $ \brief Implemenation (inline) of RlinkConnect. */ @@ -104,6 +106,13 @@ inline uint32_t RlinkConnect::SysId() const return fSysId; } +//------------------------------------------+----------------------------------- +//! FIXME_docs +inline uint32_t RlinkConnect::UsrAcc() const +{ + return fUsrAcc; +} + //------------------------------------------+----------------------------------- //! FIXME_docs inline size_t RlinkConnect::RbufSize() const @@ -240,6 +249,14 @@ inline uint32_t RlinkConnect::TraceLevel() const //------------------------------------------+----------------------------------- //! FIXME_docs +inline double RlinkConnect::Timeout() const +{ + return fTimeout; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + inline RlogFile& RlinkConnect::LogFile() const { return *fspLog; diff --git a/tools/src/librlinktpp/RtclRlinkConnect.cpp b/tools/src/librlinktpp/RtclRlinkConnect.cpp index 1ce38b80..d526db82 100644 --- a/tools/src/librlinktpp/RtclRlinkConnect.cpp +++ b/tools/src/librlinktpp/RtclRlinkConnect.cpp @@ -1,6 +1,6 @@ -// $Id: RtclRlinkConnect.cpp 676 2015-05-09 16:31:54Z mueller $ +// $Id: RtclRlinkConnect.cpp 758 2016-04-02 18:01:39Z mueller $ // -// Copyright 2011-2015 by Walter F.J. Mueller +// Copyright 2011-2016 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,8 @@ // // Revision History: // Date Rev Version Comment +// 2016-04-02 758 1.4.6 add USR_ACCESS register support (UsrAcc->usracc) +// 2016-03-20 748 1.4.5 M_get/set: add timeout // 2015-05-09 676 1.4.3 M_errcnt: add -increment; M_log: add -bare,-info.. // 2015-04-19 668 1.4.2 M_wtlam: allow tout=0 for pending attn cleanup // 2015-04-12 666 1.4.1 add M_init @@ -38,7 +40,7 @@ /*! \file - \version $Id: RtclRlinkConnect.cpp 676 2015-05-09 16:31:54Z mueller $ + \version $Id: RtclRlinkConnect.cpp 758 2016-04-02 18:01:39Z mueller $ \brief Implemenation of class RtclRlinkConnect. */ @@ -115,6 +117,8 @@ RtclRlinkConnect::RtclRlinkConnect(Tcl_Interp* interp, const char* name) boost::bind(&RlinkConnect::DumpLevel, pobj)); fGets.Add ("tracelevel", boost::bind(&RlinkConnect::TraceLevel, pobj)); + fGets.Add ("timeout", + boost::bind(&RlinkConnect::Timeout, pobj)); fGets.Add ("logfile", boost::bind(&RlinkConnect::LogFileName, pobj)); @@ -122,6 +126,8 @@ RtclRlinkConnect::RtclRlinkConnect(Tcl_Interp* interp, const char* name) boost::bind(&RlinkConnect::LinkInitDone, pobj)); fGets.Add ("sysid", boost::bind(&RlinkConnect::SysId, pobj)); + fGets.Add ("usracc", + boost::bind(&RlinkConnect::UsrAcc, pobj)); fGets.Add ("rbufsize", boost::bind(&RlinkConnect::RbufSize, pobj)); fGets.Add ("bsizemax", @@ -141,6 +147,8 @@ RtclRlinkConnect::RtclRlinkConnect(Tcl_Interp* interp, const char* name) boost::bind(&RlinkConnect::SetDumpLevel, pobj, _1)); fSets.Add ("tracelevel", boost::bind(&RlinkConnect::SetTraceLevel, pobj, _1)); + fSets.Add ("timeout", + boost::bind(&RlinkConnect::SetTimeout, pobj, _1)); fSets.Add ("logfile", boost::bind(&RlinkConnect::SetLogFileName, pobj, _1)); diff --git a/tools/tcl/rbtest/test_all.tcl b/tools/tcl/rbtest/test_all.tcl index d2aa0b19..635ed2be 100644 --- a/tools/tcl/rbtest/test_all.tcl +++ b/tools/tcl/rbtest/test_all.tcl @@ -1,6 +1,6 @@ -# $Id: test_all.tcl 662 2015-04-05 08:02:54Z mueller $ +# $Id: test_all.tcl 777 2016-06-19 20:24:15Z mueller $ # -# Copyright 2011-2015 by Walter F.J. Mueller +# Copyright 2011-2016 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2016-06-18 777 1.2 add test_flow # 2015-04-03 662 1.1 add test_labo # 2011-03-27 374 1.0 Initial version # 2011-03-13 369 0.1 First draft @@ -32,6 +33,7 @@ namespace eval rbtest { incr errcnt [rbtest::test_labo] incr errcnt [rbtest::test_stat $statmsk] incr errcnt [rbtest::test_attn $attnmsk] + incr errcnt [rbtest::test_flow 256] return $errcnt } } diff --git a/tools/tcl/rbtest/test_data.tcl b/tools/tcl/rbtest/test_data.tcl index 3f4dea01..c16d2207 100644 --- a/tools/tcl/rbtest/test_data.tcl +++ b/tools/tcl/rbtest/test_data.tcl @@ -1,6 +1,6 @@ -# $Id: test_data.tcl 661 2015-04-03 18:28:41Z mueller $ +# $Id: test_data.tcl 777 2016-06-19 20:24:15Z mueller $ # -# Copyright 2011-2015 by Walter F.J. Mueller +# Copyright 2011-2016 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2016-06-19 777 2.1.1 add dinc tests # 2015-04-03 661 2.1 drop estatdef, use estattout # 2014-12-21 617 2.0.1 use rbtout stat bit for timeout # 2014-11-09 603 2.0 use rlink v4 address layout and iface @@ -119,6 +120,37 @@ namespace eval rbtest { -rreg te.ncyc -edata [expr {$nbusy + 1 }] } # + # ------------------------------------------------------------------------- + rlc log " test 5a: test dinc: post-increment on read" + rlc exec \ + -wreg te.data 0x1100 \ + -rreg te.dinc -edata 0x1100 \ + -rreg te.dinc -edata 0x1101 \ + -rreg te.dinc -edata 0x1102 \ + -rreg te.data -edata 0x1103 + # + # ------------------------------------------------------------------------- + rlc log " test 5b: test dinc: write-check and post-increment on write" + # clear wchk, do proper writes + rlc exec \ + -wreg te.cntl [regbld rbtest::CNTL {wchk 0} {nbusy 0}] \ + -wreg te.data 0x1200 \ + -wreg te.dinc 0x1200 \ + -wreg te.dinc 0x1201 \ + -wreg te.dinc 0x1202 \ + -rreg te.data -edata 0x1203 \ + -rreg te.cntl -edata [regbld rbtest::CNTL {wchk 0}] + # wchk still clear; bad write (ff03, expected 1203); check wchk; + # good write; check wchk (must stick); check that data write clears wchk + rlc exec \ + -wreg te.dinc 0xff03 \ + -rreg te.cntl -edata [regbld rbtest::CNTL {wchk 1}] \ + -wreg te.dinc 0x1204 \ + -rreg te.cntl -edata [regbld rbtest::CNTL {wchk 1}] \ + -rreg te.dinc -edata 0x1205 \ + -wreg te.data 0x1300 \ + -rreg te.cntl -edata [regbld rbtest::CNTL {wchk 0}] + # #------------------------------------------------------------------------- rlc log "rbtest::test_data - cleanup: clear cntl and data" rlc exec -init te.cntl [regbld rbtest::INIT data cntl] diff --git a/tools/tcl/rbtest/test_flow.tcl b/tools/tcl/rbtest/test_flow.tcl new file mode 100644 index 00000000..811ff38d --- /dev/null +++ b/tools/tcl/rbtest/test_flow.tcl @@ -0,0 +1,70 @@ +# $Id: test_flow.tcl 777 2016-06-19 20:24:15Z mueller $ +# +# Copyright 2016- by Walter F.J. Mueller +# +# This program is free software; you may redistribute and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation, either version 2, or at your option any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for complete details. +# +# Revision History: +# Date Rev Version Comment +# 2016-06-18 777 1.0 Initial version +# + +package provide rbtest 1.0 + +package require rutiltpp +package require rutil +package require rlink + +namespace eval rbtest { + # + # Test flow control + # + proc test_flow {{bufmax 512} {bufmin 4}} { + # + set errcnt 0 + rlc errcnt -clear + # + rlc log "rbtest::test_flow - init: clear cntl" + rlc exec -init te.cntl [regbld rbtest::INIT cntl] + # + #------------------------------------------------------------------------- + rlc log " test 1: create back pressure with wreg after a rblk" + set rbase 0x8000 + set wbase 0xc000 + set nw $bufmin + set nmax [expr {[rlc get bsizeprudent] / 2}]; # /2 because rblk and wblk ! + if {$bufmax < $nmax} {set nmax $bufmax} + while {$nw <= $nmax} { + rlc log [format " buffer size: %4d" $nw] + set rbuf {} + set wbuf {} + for {set i 0} {$i < $nw} {incr i} { + lappend rbuf [expr {$rbase + $i}] + lappend wbuf [expr {$wbase + $i}] + } + rlc exec \ + -wreg te.data $rbase \ + -rblk te.dinc $nw -edata $rbuf -edone $nw \ + -wreg te.data $wbase \ + -wblk te.dinc $wbuf \ + -rreg te.cntl -edata 0 + set nw [expr {2*$nw}] + incr rbase 0x0400 + incr wbase 0x0400 + } + # + #------------------------------------------------------------------------- + rlc log "rbtest::test_flow - cleanup: clear cntl" + rlc exec -init te.cntl [regbld rbtest::INIT cntl] + # + incr errcnt [rlc errcnt -clear] + return $errcnt + } +} diff --git a/tools/tcl/rlink/util.tcl b/tools/tcl/rlink/util.tcl index 0ba08af9..96d4109a 100644 --- a/tools/tcl/rlink/util.tcl +++ b/tools/tcl/rlink/util.tcl @@ -1,6 +1,6 @@ -# $Id: util.tcl 661 2015-04-03 18:28:41Z mueller $ +# $Id: util.tcl 758 2016-04-02 18:01:39Z mueller $ # -# Copyright 2011-2014 by Walter F.J. Mueller +# Copyright 2011-2016 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2016-04-02 758 2.1 add USR_ACCESS register support (RLUA0/RLUA1) # 2014-12-21 617 2.0.1 add rbtout definition in STAT # 2014-12-07 609 2.0 use new rlink v4 iface; remove SINIT again # 2014-08-09 580 1.0.2 add run_rri @@ -32,6 +33,10 @@ namespace eval rlink { regdsc RLCNTL {anena 15} {atoena 14} {atoval 7 8} regdsc RLSTAT {lcmd 15 8} {babo 7} {rbsize 2 3} + # RLUSRACC describes the 32 bit value returned by the usracc property + # assuming that standart Xilinx TIMESTAMP format is used for USR_ACCESS + regdsc RLUSRACC {day 31 5} {mon 26 4} {yr 22 6} {hr 16 5} {min 11 6} {sec 5 6} + # 'pseudo register', describes 3rd word in return list element for -rlist regdsc FLAGS {vol 16} \ {chkdata 13} {chkstat 12} \ @@ -44,16 +49,16 @@ namespace eval rlink { variable ADDR_RLSTAT 0xfffe variable ADDR_RLID1 0xfffd variable ADDR_RLID0 0xfffc + # define rlink optinal regs addresses (are system constants too) + variable ADDR_RLUA1 0xfffb + variable ADDR_RLUA0 0xfffa # - # setup: amap definitions for core config regs + # setup: currently noop, amap definitions done at cpp level # proc setup {} { - rlc amap -insert rl.cntl $rlink::ADDR_RLCNTL - rlc amap -insert rl.stat $rlink::ADDR_RLSTAT - rlc amap -insert rl.id1 $rlink::ADDR_RLID1 - rlc amap -insert rl.id0 $rlink::ADDR_RLID0 } + # # init: reset rlink: disable enables; clear attn register # @@ -63,6 +68,7 @@ namespace eval rlink { -attn return "" } + # # anena: enable/disable attn notify messages # @@ -70,6 +76,7 @@ namespace eval rlink { rlc exec \ -wreg $rlink::ADDR_RLCNTL [regbld rlink::RLCNTL [list anena $ena]] } + # # isopen: returns 1 if open and 0 if close # @@ -77,6 +84,7 @@ namespace eval rlink { if {[rlc open] eq ""} { return 0 } return 1 } + # # isfifo: returns 1 if open and fifo, 0 otherwise # @@ -85,6 +93,7 @@ namespace eval rlink { if {$name ne "" && [regexp -- {^fifo:} $name]} { return 1 } return 0 } + # # issim: returns 1 if open and in simulation mode, 0 otherwise # @@ -107,4 +116,16 @@ namespace eval rlink { return $errcnt } + # + # format_usracc: format usracc timestamp + # + proc format_usracc {usracc} { + reggetkv rlink::RLUSRACC $usracc "ua_" + set ua_yr [expr {$ua_yr + 2000}] + set rval [format "%04d-%02d-%02d %02d:%02d:%02d" \ + $ua_yr $ua_mon $ua_day $ua_hr $ua_min $ua_sec] + return $rval + } + + }