diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index baa5505d..2068d819 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -35,6 +35,7 @@ The full set of tests is only run for tagged releases. - for Digilent Nexys4 DDR - sys_tst_mig_n4d: low level MIG interface test - sys_tst_sram_n4d: memory test + - sys_w11a_n4d: w11a with full 3840 MB memory - new components - s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper - s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk diff --git a/rtl/sys_gen/w11a/nexys4d/Makefile b/rtl/sys_gen/w11a/nexys4d/Makefile new file mode 100644 index 00000000..5b418303 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d/Makefile @@ -0,0 +1,25 @@ +# $Id: Makefile 1101 2019-01-02 21:22:37Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2019-01-02 1101 1.0 Initial version +# +VBOM_all = sys_w11a_n4d.vbom +BIT_all = $(VBOM_all:.vbom=.bit) +# +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4d.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# diff --git a/rtl/sys_gen/w11a/nexys4d/sys_conf.vhd b/rtl/sys_gen/w11a/nexys4d/sys_conf.vhd new file mode 100644 index 00000000..08883cac --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d/sys_conf.vhd @@ -0,0 +1,93 @@ +-- $Id: sys_conf.vhd 1101 2019-01-02 21:22:37Z mueller $ +-- +-- Copyright 2019- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_n4d (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2017.2; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2019-01-02 1101 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- configure memory controller --------------------------------------------- + + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable + constant sys_conf_dmscnt : boolean := false; + constant sys_conf_dmpcnt : boolean := true; + constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable + constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use + + -- configure w11 cpu core -------------------------------------------------- + constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + constant sys_conf_cache_twidth : integer := 7; -- 32kB cache + + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + constant sys_conf_ibd_deuna : boolean := true; -- DEUNA + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + constant sys_conf_ibd_kw11p : boolean := true; -- KW11P + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clkser/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; diff --git a/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vbom b/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vbom new file mode 100644 index 00000000..e1525196 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vbom @@ -0,0 +1,36 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/cdclib/cdclib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rbus/rbdlib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/sysmon/sysmonrbuslib.vbom +../../../bplib/mig/miglib.vbom +../../../bplib/nexys4d/miglib_nexys4d.vbom +../../../ibus/iblib.vhd +../../../ibus/ibdlib.vhd +../../../w11a/pdp11.vhd +${sys_conf := sys_conf.vhd} +@lib:unisim +# components +../../../bplib/bpgen/s7_cmt_1ce1ce2c.vbom +../../../vlib/cdclib/cdc_signal_s1_as.vbom +../../../bplib/bpgen/bp_rs232_4line_iob.vbom +../../../vlib/rlink/rlink_sp2c.vbom +../../../w11a/pdp11_sys70.vbom +../../../ibus/ibdr_maxisys.vbom +../../../bplib/nexys4d/sramif_mig_nexys4d.vbom +../../../vlib/rlink/ioleds_sp1c.vbom +../../../w11a/pdp11_hio70.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../bplib/sysmon/sysmonx_rbus_base.vbom +../../../vlib/rbus/rbd_usracc.vbom +../../../vlib/rbus/rb_sres_or_4.vbom +# design +sys_w11a_n4d.vhd +# constraints +@xdc:../../../bplib/nexys4d/nexys4d_pclk.xdc +@xdc:../../../bplib/nexys4d/nexys4d_pins.xdc diff --git a/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vhd b/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vhd new file mode 100644 index 00000000..d9f34437 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vhd @@ -0,0 +1,517 @@ +-- $Id: sys_w11a_n4d.vhd 1105 2019-01-12 19:52:45Z mueller $ +-- +-- Copyright 2019- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_w11a_n4d - syn +-- Description: w11a design for nexys4 DDR (with dram via mig) +-- +-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce +-- cdclib/cdc_signal_s1_as +-- bplib/bpgen/bp_rs232_4line_iob +-- vlib/rlink/rlink_sp2c +-- w11a/pdp11_sys70 +-- ibus/ibdr_maxisys +-- bplib//nexys4d/sramif_mig_nexys4d +-- bplib/fx2rlink/ioleds_sp1c +-- w11a/pdp11_hio70 +-- bplib/bpgen/sn_humanio_rbus +-- bplib/sysmon/sysmonx_rbus_base +-- vlib/rbus/rbd_usracc +-- vlib/rbus/rb_sres_or_4 +-- +-- Test bench: tb/tb_sys_w11a_n4d +-- +-- Target Devices: generic +-- Tool versions: viv 2017.2; ghdl 0.34 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic MHz +-- 2019-01-02 1101 2017.2 xc7a100t-1 xxxx xxxx xxx xx.x xxxx 80 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2019-01-02 1101 1.0 Initial version (derived from sys_w11a_n4 and arty) +------------------------------------------------------------------------------ +-- +-- w11a test design for nexys4d +-- w11a + rlink + serport +-- +-- Usage of Nexys 4 DDR Switches, Buttons, LEDs +-- +-- SWI(15:5): no function (only connected to sn_humanio_rbus) +-- (5): select DSP(7:4) display +-- 0 abclkdiv & abclkdiv_f +-- 1 PC +-- (4): select DSP(3:0) display +-- 0 DISPREG +-- 1 DR emulation +-- (3): select LED display +-- 0 overall status +-- 1 DR emulation +-- (2): unused-reserved (USB port select) +-- (1): 1 enable XON +-- (0): unused-reserved (serial port select) +-- +-- LEDs if SWI(3) = 1 +-- (15:0) DR emulation; shows R0 during wait like 11/45+70 +-- +-- LEDs if SWI(3) = 0 +-- (7) MEM_ACT_W +-- (6) MEM_ACT_R +-- (5) cmdbusy (all rlink access, mostly rdma) +-- (4:0) if cpugo=1 show cpu mode activity +-- (4) kernel mode, pri>0 +-- (3) kernel mode, pri=0 +-- (2) kernel mode, wait +-- (1) supervisor mode +-- (0) user mode +-- if cpugo=0 shows cpurust +-- (4) '1' +-- (3:0) cpurust code +-- +-- DSP(7:4) shows abclkdiv & abclkdiv_f or PS, depending on SWI(5) +-- DSP(3:0) shows DISPREG or DR emulation, depending on SWI(4) +-- DP(3:0) shows IO activity +-- (3) not SER_MONI.txok (shows tx back pressure) +-- (2) SER_MONI.txact (shows tx activity) +-- (1) not SER_MONI.rxok (shows rx back pressure) +-- (0) SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.cdclib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rbdlib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.sysmonrbuslib.all; +use work.miglib.all; +use work.miglib_nexys4d.all; +use work.iblib.all; +use work.ibdlib.all; +use work.pdp11.all; +use work.sys_conf.all; + +library unisim; +use unisim.vcomponents.ALL; + +-- ---------------------------------------------------------------------------- + +entity sys_w11a_n4d is -- top level + -- implements nexys4d_dram_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4 switches + I_BTN : in slv5; -- n4 buttons + I_BTNRST_N : in slbit; -- n4 reset button + O_LED : out slv16; -- n4 leds + O_RGBLED0 : out slv3; -- n4 rgb-led 0 + O_RGBLED1 : out slv3; -- n4 rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + DDR2_DQ : inout slv16; -- dram: data in/out + DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p) + DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n) + DDR2_ADDR : out slv13; -- dram: address + DDR2_BA : out slv3; -- dram: bank address + DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low) + DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low) + DDR2_WE_N : out slbit; -- dram: write enable (act.low) + DDR2_CK_P : out slv1; -- dram: clock (diff-p) + DDR2_CK_N : out slv1; -- dram: clock (diff-n) + DDR2_CKE : out slv1; -- dram: clock enable + DDR2_CS_N : out slv1; -- dram: chip select (act.low) + DDR2_DM : out slv2; -- dram: data input mask + DDR2_ODT : out slv1 -- dram: on-die termination + ); +end sys_w11a_n4d; + +architecture syn of sys_w11a_n4d is + + signal CLK100_BUF : slbit := '0'; + + signal CLK : slbit := '0'; + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal CLKS : slbit := '0'; + signal CES_MSEC : slbit := '0'; + + signal CLKMIG : slbit := '0'; + signal CLKREF : slbit := '0'; + + signal LOCKED : slbit := '0'; -- raw LOCKED + signal LOCKED_CLK : slbit := '0'; -- sync'ed to CLK + + signal GBL_RESET : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; + signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + + signal GRESET : slbit := '0'; -- general reset (from rbus) + signal CRESET : slbit := '0'; -- cpu reset (from cp) + signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) + signal PERFEXT : slv8 := (others=>'0'); + + signal EI_PRI : slv3 := (others=>'0'); + signal EI_VECT : slv9_2 := (others=>'0'); + signal EI_ACKM : slbit := '0'; + + signal CP_STAT : cp_stat_type := cp_stat_init; + signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init; + + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv20 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + signal MIG_MONI : sramif2migui_moni_type := sramif2migui_moni_init; + + signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK + + signal IB_MREQ : ib_mreq_type := ib_mreq_init; + signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; + + signal DISPREG : slv16 := (others=>'0'); + signal ABCLKDIV : slv16 := (others=>'0'); + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv32 := (others=>'0'); + signal DSP_DP : slv8 := (others=>'0'); + + constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx + constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx + + constant sysid_proj : slv16 := x"0201"; -- w11a + constant sysid_board : slv8 := x"08"; -- nexys4d + constant sysid_vers : slv8 := x"00"; + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + CLK100_BUFG: bufg + port map ( + I => I_CLK100, + O => CLK100_BUF + ); + + GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------ + generic map ( + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + CLK0_VCODIV => sys_conf_clksys_vcodivide, + CLK0_VCOMUL => sys_conf_clksys_vcomultiply, + CLK0_OUTDIV => sys_conf_clksys_outdivide, + CLK0_GENTYPE => sys_conf_clksys_gentype, + CLK0_CDUWIDTH => 7, + CLK0_USECDIV => sys_conf_clksys_mhz, + CLK0_MSECDIV => 1000, + CLK1_VCODIV => sys_conf_clkser_vcodivide, + CLK1_VCOMUL => sys_conf_clkser_vcomultiply, + CLK1_OUTDIV => sys_conf_clkser_outdivide, + CLK1_GENTYPE => sys_conf_clkser_gentype, + CLK1_CDUWIDTH => 7, + CLK1_USECDIV => sys_conf_clkser_mhz, + CLK1_MSECDIV => 1000, + CLK23_VCODIV => 1, + CLK23_VCOMUL => 12, -- vco 1000 MHz + CLK2_OUTDIV => 8, -- mig sys 150.0 MHz + CLK3_OUTDIV => 6, -- mig ref 200.0 MHz + CLK23_GENTYPE => "PLL") + port map ( + CLKIN => CLK100_BUF, + CLK0 => CLK, + CE0_USEC => CE_USEC, + CE0_MSEC => CE_MSEC, + CLK1 => CLKS, + CE1_USEC => open, + CE1_MSEC => CES_MSEC, + CLK2 => CLKMIG, + CLK3 => CLKREF, + LOCKED => LOCKED + ); + + CDC_CLK_LOCKED : cdc_signal_s1_as + port map ( + CLKO => CLK, + DI => LOCKED, + DO => LOCKED_CLK + ); + + GBL_RESET <= not LOCKED_CLK; + + IOB_RS232 : bp_rs232_4line_iob -- serport iob ---------------------- + port map ( + CLK => CLKS, + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_CTS_N => I_CTS_N, + O_RTS_N => O_RTS_N + ); + + RLINK : rlink_sp2c -- rlink for serport ----------------- + generic map ( + BTOWIDTH => 9, -- 512 cycles, for slow mem iface + RTAWIDTH => 12, + SYSID => sysid_proj & sysid_board & sysid_vers, + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 12, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => sys_conf_rbmon_awidth, + RBMON_RBADDR => rbaddr_rbmon) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + CLKS => CLKS, + CES_MSEC => CES_MSEC, + ENAXON => SWI(1), + ESCFILL => '0', + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + PERFEXT(0) <= MIG_MONI.rdrhit; -- ext_rdrhit + PERFEXT(1) <= MIG_MONI.wrrhit; -- ext_wrrhit + PERFEXT(2) <= MIG_MONI.wrflush; -- ext_wrflush + PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact + PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback + PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact + PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback + PERFEXT(7) <= CE_USEC; -- ext_usec + + SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM_CPU => RB_LAM(0), + GRESET => GRESET, + CRESET => CRESET, + BRESET => BRESET, + CP_STAT => CP_STAT, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + PERFEXT => PERFEXT, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO, + DM_STAT_EXP => DM_STAT_EXP + ); + + IBDR_SYS : ibdr_maxisys -- IO system ------------------------- + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => GRESET, + BRESET => BRESET, + ITIMER => DM_STAT_EXP.se_itimer, + IDEC => DM_STAT_EXP.se_idec, + CPUSUSP => CP_STAT.cpususp, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG + ); + + MEMCTL: sramif_mig_nexys4d -- SRAM to MIG iface ----------------- + port map ( + CLK => CLK, + RESET => GBL_RESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => open, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO, + CLKMIG => CLKMIG, + CLKREF => CLKREF, + TEMP => XADC_TEMP, + MONI => MIG_MONI, + DDR2_DQ => DDR2_DQ, + DDR2_DQS_P => DDR2_DQS_P, + DDR2_DQS_N => DDR2_DQS_N, + DDR2_ADDR => DDR2_ADDR, + DDR2_BA => DDR2_BA, + DDR2_RAS_N => DDR2_RAS_N, + DDR2_CAS_N => DDR2_CAS_N, + DDR2_WE_N => DDR2_WE_N, + DDR2_CK_P => DDR2_CK_P, + DDR2_CK_N => DDR2_CK_N, + DDR2_CKE => DDR2_CKE, + DDR2_CS_N => DDR2_CS_N, + DDR2_DM => DDR2_DM, + DDR2_ODT => DDR2_ODT + ); + + LED_IO : ioleds_sp1c -- hio leds from serport ------------- + port map ( + SER_MONI => SER_MONI, + IOLEDS => DSP_DP(3 downto 0) + ); + DSP_DP(7 downto 4) <= "0010"; + ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; + + HIO70 : pdp11_hio70 -- hio from sys70 -------------------- + generic map ( + LWIDTH => LED'length, + DCWIDTH => 3) + port map ( + SEL_LED => SWI(3), + SEL_DSP => SWI(5 downto 4), + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + CP_STAT => CP_STAT, + DM_STAT_EXP => DM_STAT_EXP, + ABCLKDIV => ABCLKDIV, + DISPREG => DISPREG, + LED => LED, + DSP_DAT => DSP_DAT + ); + + HIO : sn_humanio_rbus -- hio manager ----------------------- + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DCWIDTH => 3, + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + SMRB : sysmonx_rbus_base -- always instantiated, needed for mig + generic map ( -- use default INIT_ (Vccint=1.00) + CLK_MHZ => sys_conf_clksys_mhz, + RB_ADDR => rbaddr_sysmon) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_SYSMON, + ALM => open, + OT => open, + TEMP => XADC_TEMP + ); + + UARB : rbd_usracc + port map ( + CLK => CLK, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_USRACC + ); + + RB_SRES_OR : rb_sres_or_4 -- rbus or --------------------------- + port map ( + RB_SRES_1 => RB_SRES_CPU, + RB_SRES_2 => RB_SRES_HIO, + RB_SRES_3 => RB_SRES_SYSMON, + RB_SRES_4 => RB_SRES_USRACC, + RB_SRES_OR => RB_SRES + ); + + -- setup unused outputs in nexys4 + O_RGBLED0 <= (others=>'0'); + O_RGBLED1 <= (others=>not I_BTNRST_N); + +end syn; diff --git a/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vmfset b/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vmfset new file mode 100644 index 00000000..334b8bcb --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vmfset @@ -0,0 +1,104 @@ +# $Id: sys_w11a_n4d.vmfset 1101 2019-01-02 21:22:37Z mueller $ +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# general issues ----------------------------------------------- +{2018.2:} +# stupid new warning, Xilinx suggests to safely ingnore +i [Constraints 18-5210] # generic +{:} + +# binding instance .. which has no pins ------------------------ +I [Synth 8-115] # generic + +# false_path -hold ignored by synth ---------------------------- +I [Designutils 20-1567] + +# port driven by constant -------------------------------------- +# --> RGBLED0 currently unused # OK 2019-01-02 +i [Synth 8-3917] O_RGBLED0[\d] + +# unconnected ports -------------------------------------------- +I [Synth 8-3331] IB_MREQ # generic +I [Synth 8-3331] RB_MREQ # generic +I [Synth 8-3331] DM_STAT_CO # generic +I [Synth 8-3331] DM_STAT_DP # generic +I [Synth 8-3331] DM_STAT_EXP # generic +I [Synth 8-3331] DM_STAT_SE # generic +I [Synth 8-3331] DM_STAT_VM # generic +I [Synth 8-3331] CP_STAT # generic +I [Synth 8-3331] SER_MONI # generic +# --> ireg indeed not fully used # OK 2019-01-02 +i [Synth 8-3331] pdp11_sequencer .* IREG[1(1|2|3|4)] +# --> ccin indedd not fully used # OK 2019-01-02 +i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)] +# --> some psr bits are used # OK 2019-01-02 +i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)] +# --> not all moni fields used # OK 2019-01-02 +i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)] +# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2019-01-02 +i [Synth 8-3331] pdp11_mmu .* CNTL[trap_done] +i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)] +# --> so far no usage of usec and msec pulse # OK 2019-01-02 +i [Synth 8-3331] rlink_sp2c .* (CE_USEC|CE_MSEC) +# --> msec indeed not used # OK 2019-01-02 +i [Synth 8-3331] ibdr_rl11 .* CE_MSEC +# --> ei_ack not used, interrupt request cleared via register # OK 2019-01-02 +i [Synth 8-3331] ibdr_deuna .* EI_ACK +i [Synth 8-3331] ibd_iist .* EI_ACK +# --> data end marker not used # OK 2019-01-02 +i [Synth 8-3331] sramif2migui_core .*APP_RD_DATA_END + +# sequential element removed (2017.1 nonsense) ----------------- +I [Synth 8-6014] _reg # generic + +# unused sequential element ------------------------------------ +{:} +I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic +I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic +# --> not yet used # OK 2019-01-02 +i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_sequencer +# --> indeed no types with [3] set # OK 2019-01-02 +i [Synth 8-3332] R_REGS_reg[dtyp][3].* ibdr_rhrp +# --> not yet used # OK 2019-01-02 +i [Synth 8-3332] R_REGS_reg[req_lock].* ibd_iist +i [Synth 8-3332] R_REGS_reg[req_boot].* ibd_iist +# --> [8] is for DZ11TX, not yet available # OK 2019-01-02 +# --> [9] is for DZ11RX, unclear why this one isn't removed too !! +i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_sequencer +# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2019-01-02 +i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer +# --> inst_compl logic disabled in pdp11_mmu # OK 2019-01-02 +i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox + +{:} + +# INFO: encoded FSM with state register as -------------------- +# test for sys_w11a_n4 that all FSMs are one_hot +r [Synth 8-3354] R_BREGS_reg[state.*'one-hot'.*'rlink_core' +r [Synth 8-3354] R_LREGS_reg[state].*'one-hot'.*'rlink_core' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_autobaud' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_rx' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_core_rbus' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_vmbox' +r [Synth 8-3354] R_STATE_reg.*'one-hot'.*'pdp11_sequencer' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_cache' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rhrp' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rl11' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'sysmon_rbus_core' + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization +{:2017.2} +# --> spurious Invalid VCCINTIO messages # OK 2018-12-28 +i [Designutils 20-266] Invalid Voltage Source VCCINTIO + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[bit] +# see https://www.xilinx.com/support/answers/64180.html # OK 2018-12-28 +i [DRC REQP-1709] PLLE2_ADV +# --> DSP multiplier is not pipelined, ok # OK 2019-01-02 +i [DRC DPOP-1] PREG Output pipelining +i [DRC DPOP-2] MREG Output pipelining diff --git a/rtl/sys_gen/w11a/nexys4d/tb/.gitignore b/rtl/sys_gen/w11a/nexys4d/tb/.gitignore new file mode 100644 index 00000000..7d8d9387 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d/tb/.gitignore @@ -0,0 +1,2 @@ +tb_w11a_n4d +sysmon_stim diff --git a/rtl/sys_gen/w11a/nexys4d/tb/Makefile b/rtl/sys_gen/w11a/nexys4d/tb/Makefile new file mode 100644 index 00000000..1503e3c8 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d/tb/Makefile @@ -0,0 +1,39 @@ +# $Id: Makefile 1101 2019-01-02 21:22:37Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2019-01-02 1101 1.0 Initial version +# +EXE_all = tb_w11a_n4d +# +include ${RETROBASE}/rtl/make_viv/viv_default_nexys4d.mk +# +.PHONY : all all_ssim all_osim clean +.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_osim : $(EXE_all:=_osim) +# +all_XSim : $(EXE_all:=_XSim) +all_XSim_ssim : $(EXE_all:=_XSim_ssim) +all_XSim_osim : $(EXE_all:=_XSim_osim) +all_XSim_tsim : $(EXE_all:=_XSim_tsim) +# +clean : viv_clean ghdl_clean xsim_clean +# +#----- +# +include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk +include ${RETROBASE}/rtl/make_viv/generic_xsim.mk +include ${RETROBASE}/rtl/make_viv/generic_vivado.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_vsim) +include $(wildcard *.o.dep_ghdl) +endif +# diff --git a/rtl/sys_gen/w11a/nexys4d/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/nexys4d/tb/sys_conf_sim.vhd new file mode 100644 index 00000000..807aec43 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d/tb/sys_conf_sim.vhd @@ -0,0 +1,90 @@ +-- $Id: sys_conf_sim.vhd 1101 2019-01-02 21:22:37Z mueller $ +-- +-- Copyright 2019- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_n4d (for simulation) +-- +-- Dependencies: - +-- Tool versions: viv 2017.2; ghdl 0.34 +-- Revision History: +-- Date Rev Version Comment +-- 2019-01-02 1101 1.0 Initial version (cloned from _n4) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- dual clock design, clkser = 120 MHz + constant sys_conf_clkser_vcodivide : positive := 1; + constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz + constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz + constant sys_conf_clkser_gentype : string := "PLL"; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- configure memory controller --------------------------------------------- + + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable + constant sys_conf_dmscnt : boolean := false; + constant sys_conf_dmpcnt : boolean := true; + constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable + constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use + + -- configure w11 cpu core -------------------------------------------------- + constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + constant sys_conf_cache_twidth : integer := 7; -- 32kB cache + + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + constant sys_conf_ibd_deuna : boolean := true; -- DEUNA + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + constant sys_conf_ibd_kw11p : boolean := true; -- KW11P + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; diff --git a/rtl/sys_gen/w11a/nexys4d/tb/tb_w11a_n4d.vbom b/rtl/sys_gen/w11a/nexys4d/tb/tb_w11a_n4d.vbom new file mode 100644 index 00000000..3d35e9be --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d/tb/tb_w11a_n4d.vbom @@ -0,0 +1,9 @@ +# configure tb_nexys4d_dram with sys_w11a_n4d target; +# use vhdl configure file (tb_w11a_n4d.vhd) to allow +# that all configurations will co-exist in work library +# configure +nexys4d_dram_aif = ../sys_w11a_n4d.vbom +sys_conf = sys_conf_sim.vhd +# design +../../../../bplib/nexys4d/tb/tb_nexys4d_dram.vbom +tb_w11a_n4d.vhd diff --git a/rtl/sys_gen/w11a/nexys4d/tb/tb_w11a_n4d.vhd b/rtl/sys_gen/w11a/nexys4d/tb/tb_w11a_n4d.vhd new file mode 100644 index 00000000..bfd3d46c --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d/tb/tb_w11a_n4d.vhd @@ -0,0 +1,35 @@ +-- $Id: tb_w11a_n4d.vhd 1101 2019-01-02 21:22:37Z mueller $ +-- +-- Copyright 2019- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_w11a_n4d +-- Description: Configuration for tb_w11a_n4d for tb_nexys4d_dram +-- +-- Dependencies: sys_w11a_n4d +-- +-- To test: sys_w11a_n4d +-- +-- Revision History: +-- Date Rev Version Comment +-- 2019-01-02 1101 1.0 Initial version (cloned from _n4) +------------------------------------------------------------------------------ + +configuration tb_w11a_n4d of tb_nexys4d_dram is + + for sim + for all : nexys4d_dram_aif + use entity work.sys_w11a_n4d; + end for; + end for; + +end tb_w11a_n4d; diff --git a/rtl/sys_gen/w11a/nexys4d/tb/tbrun.yml b/rtl/sys_gen/w11a/nexys4d/tb/tbrun.yml new file mode 100644 index 00000000..3166d2fc --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d/tb/tbrun.yml @@ -0,0 +1,29 @@ +# $Id: tbrun.yml 1103 2019-01-04 13:18:54Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2019-01-02 1101 1.0 Initial version +# +- default: + mode: ${viv_modes} +# +- tag: [viv, sys_w11a, n4d, stim1] + test: | + tbrun_tbwrri --lsuf stim1 tb_w11a_n4d${ms} \ + "rlink::run_rri ../../../../w11a/tb/tb_rlink_tba_pdp11core_stim.dat" + +- tag: [viv, sys_w11a, n4d, stim2] + test: | + tbrun_tbwrri --lsuf stim2 --pack rw11 tb_w11a_n4d${ms} \ + "rw11::setup_cpu" \ + "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat 60." + +- tag: [viv, sys_w11a, n4d, tbcpu] + test: | + tbrun_tbwrri --lsuf tbcpu --pack rw11 tb_w11a_n4d${ms} \ + "rw11::setup_cpu" "rw11::tbench @cpu_all.dat" + +- tag: [viv, sys_w11a, n4d, tbdev] + test: | + tbrun_tbwrri --lsuf tbdev --pack rw11 tb_w11a_n4d${ms} \ + "rw11::setup_cpu" "rw11::tbench @dev_all.dat" diff --git a/rtl/sys_gen/w11a/nexys4d/tb/tbw.dat b/rtl/sys_gen/w11a/nexys4d/tb/tbw.dat new file mode 100644 index 00000000..312a6754 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d/tb/tbw.dat @@ -0,0 +1,7 @@ +# $Id: tbw.dat 1101 2019-01-02 21:22:37Z mueller $ +# +[tb_w11a_n4d] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = +sysmon_stim = ../../../../bplib/sysmon/tb/sysmon_stim_n4.dat diff --git a/rtl/sys_gen/w11a/tbrun.yml b/rtl/sys_gen/w11a/tbrun.yml index 0ecd6fc2..5884cd37 100644 --- a/rtl/sys_gen/w11a/tbrun.yml +++ b/rtl/sys_gen/w11a/tbrun.yml @@ -1,8 +1,8 @@ -# $Id: tbrun.yml 1102 2019-01-03 08:46:04Z mueller $ +# $Id: tbrun.yml 1103 2019-01-04 13:18:54Z mueller $ # # Revision History: # Date Rev Version Comment -# 2019-01-03 1102 1.2 add arty(dram) +# 2019-01-04 1103 1.2 add arty(dram),nexys4d(dram) # 2018-08-11 1038 1.1 add artys7 # 2017-06-25 914 1.1 add cmoda7 # 2016-08-22 800 1.0 Initial version @@ -11,6 +11,8 @@ - include: nexys2/tb/tbrun.yml - include: nexys3/tb/tbrun.yml - include: nexys4/tb/tbrun.yml +- include: nexys4d/tb/tbrun.yml +- include: nexys4d_bram/tb/tbrun.yml - include: basys3/tb/tbrun.yml - include: arty/tb/tbrun.yml - include: arty_bram/tb/tbrun.yml