diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index da2c46eb..62b95628 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -32,6 +32,8 @@ The full set of tests is only run for tagged releases. - general changes - rename _gpr to _gr, use 'general registers' not 'general purpose registers' ### Bug Fixes + - rtl/w11a + - pdp11_sequencer: BUGFIX: use is_kstackdst1246 also in dstr flow --- diff --git a/rtl/w11a/pdp11_sequencer.vhd b/rtl/w11a/pdp11_sequencer.vhd index c0f6112b..011f3805 100644 --- a/rtl/w11a/pdp11_sequencer.vhd +++ b/rtl/w11a/pdp11_sequencer.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_sequencer.vhd 1312 2022-10-29 15:03:06Z mueller $ +-- $Id: pdp11_sequencer.vhd 1316 2022-11-18 15:26:40Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2006-2022 by Walter F.J. Mueller -- @@ -13,6 +13,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2022-11-18 1316 1.6.18 BUGFIX: use is_kstackdst1246 also in dstr flow -- 2022-10-29 1312 1.6.17 rename s_int_* -> s_vec_*, s_trap_* -> s_abort_* -- 2022-10-25 1309 1.6.16 rename _gpr -> _gr -- 2022-10-03 1301 1.6.15 finalize fix for I space mode=1 in s_dstr_def @@ -47,7 +48,7 @@ -- CNTL.cpdout_we instead of CPDOUT_WE -- 2010-06-12 304 1.2.8 signal cpuwait when spinning in s_op_wait -- 2009-05-30 220 1.2.7 final removal of snoopers (were already commented) --- 2009-05-09 213 1.2.6 BUGFIX: use is_dstkstack1246, stklim for mode=6 +-- 2009-05-09 213 1.2.6 BUGFIX: use is_kstackdst1246, stklim for mode=6 -- 2009-05-02 211 1.2.5 BUGFIX: 11/70 spl semantics again in kernel mode -- 2009-04-26 209 1.2.4 BUGFIX: give interrupts priority over trap handling -- 2008-12-14 177 1.2.3 BUGFIX: use is_dstkstack124, fix stklim check bug @@ -363,7 +364,7 @@ begin variable brcond : slbit := '0'; -- br condition value variable is_kmode : slbit := '0'; -- cmode is kernel mode - variable is_dstkstack1246 : slbit := '0'; -- dest is k-stack & mode= 1,2,4,6 + variable is_kstackdst1246 : slbit := '0'; -- dest is k-stack & mode= 1,2,4,6 variable int_pending : slbit := '0'; -- an interrupt is pending @@ -399,13 +400,15 @@ begin pwstate : in state_type; pbytop : in slbit := '0'; pmacc : in slbit := '0'; - pispace : in slbit := '0') is + pispace : in slbit := '0'; + kstack : in slbit := '0') is begin pnvmcntl.dspace := not pispace; -- bytop := R_IDSTAT.is_bytop and not is_addr; - pnvmcntl.bytop := pbytop; - pnvmcntl.macc := pmacc; - pnvmcntl.req := '1'; + pnvmcntl.bytop := pbytop; + pnvmcntl.macc := pmacc; + pnvmcntl.kstack := kstack; + pnvmcntl.req := '1'; pnstate := pwstate; end procedure do_memread_d; @@ -639,14 +642,14 @@ begin brcond := '1'; is_kmode := '0'; - is_dstkstack1246 := '0'; + is_kstackdst1246 := '0'; if PSW.cmode = c_psw_kmode then is_kmode := '1'; if DSTREG = c_gr_sp and (DSTMODF="001" or DSTMODF="010" or DSTMODF="100" or DSTMODF="110") then - is_dstkstack1246 := '1'; + is_kstackdst1246 := '1'; end if; end if; @@ -1192,7 +1195,8 @@ begin ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST do_memread_d(nstate, nvmcntl, s_dstr_def_w, pbytop=>R_IDSTAT.is_bytop, pmacc=>R_IDSTAT.is_rmwop, - pispace=>R_IDSTAT.is_dstpcmode1); + pispace=>R_IDSTAT.is_dstpcmode1, + kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop); when s_dstr_def_w => -- ----------------------------------- nstate := s_dstr_def_w; @@ -1217,7 +1221,8 @@ begin macc := R_IDSTAT.is_rmwop and not DSTDEF; bytop := R_IDSTAT.is_bytop and not DSTDEF; do_memread_d(nstate, nvmcntl, s_dstr_inc_w, - pbytop=>bytop, pmacc=>macc, pispace=>R_IDSTAT.is_dstpc); + pbytop=>bytop, pmacc=>macc, pispace=>R_IDSTAT.is_dstpc, + kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop); when s_dstr_inc_w => -- ----------------------------------- nstate := s_dstr_inc_w; @@ -1252,7 +1257,8 @@ begin macc := R_IDSTAT.is_rmwop and not DSTDEF; bytop := R_IDSTAT.is_bytop and not DSTDEF; do_memread_d(nstate, nvmcntl, s_dstr_inc_w, - pbytop=>bytop, pmacc=>macc); + pbytop=>bytop, pmacc=>macc, + kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop); when s_dstr_ind => -- ----------------------------------- do_memread_i(nstate, ndpcntl, nvmcntl, s_dstr_ind1_w); @@ -1278,7 +1284,8 @@ begin macc := R_IDSTAT.is_rmwop and not DSTDEF; bytop := R_IDSTAT.is_bytop and not DSTDEF; do_memread_d(nstate, nvmcntl, s_dstr_ind2_w, - pbytop=>bytop, pmacc=>macc); + pbytop=>bytop, pmacc=>macc, + kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop); when s_dstr_ind2_w => -- ----------------------------------- nstate := s_dstr_ind2_w; @@ -1335,12 +1342,12 @@ begin -- s_dstw_def246 wreq @n(r) -- s_dstw_def_w ack @n(r) -- -> do_fork_next - + when s_dstw_def => -- ----------------------------------- ndpcntl.psr_ccwe := '1'; ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST - nvmcntl.kstack := is_dstkstack1246; + nvmcntl.kstack := is_kstackdst1246; do_memwrite(nstate, nvmcntl, s_dstw_def_w, pispace=>R_IDSTAT.is_dstpc); when s_dstw_def_w => -- ----------------------------------- @@ -1359,7 +1366,7 @@ begin ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (for else) if DSTDEF = '0' then ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec - nvmcntl.kstack := is_dstkstack1246; + nvmcntl.kstack := is_kstackdst1246; do_memwrite(nstate, nvmcntl, s_dstw_inc_w, pispace=>R_IDSTAT.is_dstpc); nstatus.do_grwe := '1'; else @@ -1421,7 +1428,7 @@ begin ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = from idec (for if) if DSTDEF = '0' then - nvmcntl.kstack := is_dstkstack1246; + nvmcntl.kstack := is_kstackdst1246; do_memwrite(nstate, nvmcntl, s_dstw_def_w); else do_memread_d(nstate, nvmcntl, s_dstw_incdef_w); diff --git a/tools/asm-11/lib/defs_cpu.mac b/tools/asm-11/lib/defs_cpu.mac index fcb2a4f9..6d00bc76 100644 --- a/tools/asm-11/lib/defs_cpu.mac +++ b/tools/asm-11/lib/defs_cpu.mac @@ -1,11 +1,11 @@ -; $Id: defs_cpu.mac 1184 2019-07-10 20:39:44Z mueller $ +; $Id: defs_cpu.mac 1316 2022-11-18 15:26:40Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later -; Copyright 2014-2019 by Walter F.J. Mueller +; Copyright 2014-2022 by Walter F.J. Mueller ; ; definitions for basic CPU registers (as in defs_cpu.das) ; cp.psw=177776 - cp.sli=177774 ; stack limit + cp.slr=177774 ; stack limit cp.pir=177772 ; pirq cp.mbr=177770 ; mbrk cp.err=177766 ; cpuerr diff --git a/tools/asm-11/lib/halt_checks.mac b/tools/asm-11/lib/halt_checks.mac index 51bc0df0..2e67b9b8 100644 --- a/tools/asm-11/lib/halt_checks.mac +++ b/tools/asm-11/lib/halt_checks.mac @@ -1,4 +1,4 @@ -; $Id: halt_checks.mac 1262 2022-07-25 09:44:55Z mueller $ +; $Id: halt_checks.mac 1316 2022-11-18 15:26:40Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later ; Copyright 2022- by Walter F.J. Mueller ; @@ -40,3 +40,15 @@ beq .+4 halt .endm +; tst on ne + .macro htstne,src + tst src + bne .+4 + halt + .endm +; tstb on ne + .macro htsbne,src + tstb src + bne .+4 + halt + .endm diff --git a/tools/tcode/cpu_basics.mac b/tools/tcode/cpu_basics.mac index 38c89c21..e56c617a 100644 --- a/tools/tcode/cpu_basics.mac +++ b/tools/tcode/cpu_basics.mac @@ -1,4 +1,4 @@ -; $Id: cpu_basics.mac 1287 2022-08-27 09:40:43Z mueller $ +; $Id: cpu_basics.mac 1316 2022-11-18 15:26:40Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later ; Copyright 2015-2022 by Walter F.J. Mueller ; @@ -3005,13 +3005,13 @@ tf0201: mov #cp.psw,r0 hbitne #kl.ie,kl.csr ; check that kl.ie bit is set movb #bit01,cp.pir+1 ; set PIRQ bit hcmbeq #bit01,cp.pir+1 ; check - mov #400,cp.sli ; bump STKLIM - hcmpeq #400,cp.sli ; check + mov #400,cp.slr ; bump STKLIM + hcmpeq #400,cp.slr ; check ; reset ; and RESET hbiteq #kl.ie,kl.csr ; check that kl.ie bit is cleared htsbeq cp.pir+1 ; check that PIRQ cleared - htsteq cp.sli ; check that STKLIM cleared + htsteq cp.slr ; check that STKLIM cleared ccc ; clear cc hcmpeq (r0),#cp.pr7 ; check that prio still 7 (CPU not(!) reset) clr (r0) ; back to normal diff --git a/tools/tcode/cpu_details.mac b/tools/tcode/cpu_details.mac index 38e9134f..75205ddc 100644 --- a/tools/tcode/cpu_details.mac +++ b/tools/tcode/cpu_details.mac @@ -1,10 +1,10 @@ -; $Id: cpu_details.mac 1305 2022-10-23 07:44:21Z mueller $ +; $Id: cpu_details.mac 1316 2022-11-18 15:26:40Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later ; Copyright 2022- by Walter F.J. Mueller ; ; Revision History: ; Date Rev Version Comment -; 2022-07-28 1264 1.0 Initial version +; 2022-11-18 1316 1.0 Initial version ; 2022-07-18 1259 0.1 First draft ; ; Test CPU details @@ -355,6 +355,180 @@ ta0210: cmpb systyp,#sy.sih ; this fatal stack error fails in SimH ; end of A2.* tests, restore iit handler mov v..iit+2,v..iit ; restore iit handler ; +; Test A3: STKLIM +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +; This sub-section verifies operation of STKLIM register +; and the yellow stack trap and red stack abort functionality. +; +; Test A3.1 -- STKLIM write/read test ++++++++++++++++++++++++++++++++ +; STKLIM is a 16 bit register, upper byte is retained, lower reads always 0 +; +ta0301: mov #1000$,r0 ; ptr to value list + mov #<1010$-1000$>/2,r1 ; # of values + mov #377,r2 ; LSB byte mask + mov #cp.slr,r3 ; ptr to STKLIM +; +100$: mov (r0)+,r4 ; get value + mov r4,(r3) ; load STKLIM + bic r2,r4 ; clear LSB + hcmpeq r4,(r3) ; read and ckeck STKLIM + sob r1,100$ ; go for next STKLIM value + br 9999$ +; +1000$: .word ^b0101010101010101 + .word ^b1010101010101010 + .word ^b0000000011001100 ; STKLIM = 0 at end of test +1010$: +; +9999$: iot ; end of test A3.1 +; +; Test A3.2 -- yellow trap + red abort boundary ++++++++++++++++++++++ +; Verifies push to STKLIM+376 to STKLIM+340 causes a yellow trap +; and a push to STKLIM+336 causes a red stack abort for STKLIM +; 0 yellow below 000400 +; 1400 yellow below 002000 +; 157400 yellow below 156000 +; +ta0302: mov #2000$,r0 ; ptr to value list + mov #<2010$-2000$>/2,r1 ; # of values + mov #1000$,v..iit ; set up iit handler + clr v..iit+2 +; +100$: mov (r0)+,r5 ; get value + mov r5,cp.slr ; load STKLIM + clr 336(r5) ; clear word on red boundary + mov r5,sp ; load SP + add #400,sp ; to yellow boundary + clr r2 ; clear yellow trap counter + mov #1.,-(sp) ; push to STKLIM+376 -> trap + mov #2.,-(sp) ; push to STKLIM+374 -> trap + mov #3.,-(sp) ; push to STKLIM+372 -> trap + mov #4.,-(sp) ; push to STKLIM+370 -> trap + mov #5.,-(sp) ; push to STKLIM+366 -> trap + mov #6.,-(sp) ; push to STKLIM+364 -> trap + mov #7.,-(sp) ; push to STKLIM+362 -> trap + mov #8.,-(sp) ; push to STKLIM+360 -> trap + mov #9.,-(sp) ; push to STKLIM+356 -> trap + mov #10.,-(sp) ; push to STKLIM+354 -> trap + mov #11.,-(sp) ; push to STKLIM+352 -> trap + mov #12.,-(sp) ; push to STKLIM+350 -> trap + mov #13.,-(sp) ; push to STKLIM+346 -> trap + mov #14.,-(sp) ; push to STKLIM+344 -> trap + sub #6,sp ; avoid abort in vector flow + mov #123456,-(sp) ; push to STKLIM+336 -> abort + halt +; +1000$: clr cp.err ; HACK: clear CPUERR !!! + tst sp + beq 1010$ + inc r2 + rti +1010$: hcmpeq #14.,r2 ; all traps taken ? + htsteq 336(r5) ; red zone border clean ? + sob r1,100$ ; go for next STKLIM value +; + clr cp.slr ; STKLIM to default + mov #stack,sp ; SP to default + mov #v..iit+2,v..iit ; v..iit to catcher + br 9999$ +; +2000$: .word 000000 + .word 001400 + .word 157400 +2010$: +; +9999$: iot ; end of test A3.2 +; +; Test A3.3 -- stack trap address modes ++++++++++++++++++++++++++++++ +; Verifies that mode 1,2,4,6 trap for dstw flows and dstr when rmw +; Verifies that mode 3,5,7 writes do not trap +; Verifies that mode 1-7 reads do not trap +; Notes: +; - dstw (mov,clr,..) and dstr (add,bis,...) flows write to stack -> test both +; - inspired by eqkce0 test 041 that verifies do/dont trap instruction cases +; - SimH and e11 currently do not support full 11/70 mode semantics +; +ta0303: tstb systyp ; skip if not on w11 + bge 100$ + jmp 9999$ +; +100$: mov #1000$,v..iit ; set up iit handler + clr v..iit+2 + mov #1100$,v..emt ; set up emt handler + clr v..emt+2 + mov #1200$,v..trp ; set up trap handler + clr v..trp+2 + mov #1400,cp.slr ; set yellow limit to 1776 + clr r2 ; clear trap counter +; +; part 1: test instructions that should trap ------------------------- +; +; dstw mode 1,2,4,6 + mov #1000,-(sp) ; dstw mode 4: SP now 1776 (1) + clr -(sp) ; dstw mode 4: SP now 1774 (2) + mov (sp),(sp) ; dstw mode 1: SP now 1774 (3) + clr (sp) ; dstw mode 1: SP now 1774 (4) + mov (sp),(sp)+ ; dstw mode 2: SP now 1776 (5) + clr 0(sp) ; dstw mode 6: SP now 1776 (6) + mov (sp),0(sp) ; dstw mode 6: SP now 1776 (7) +; implied push + jsr pc,1300$ ; implied push: SP now 1176 (8) + mfpi r0 ; implied push: SP now 1774 (9) +; trap instrunctions + emt 100 ; trap push: SP now 1174 (10) + trap 200 ; trap push: SP now 1174 (11) +; dstr mode 1,2,4,6 when rmw + add (sp),(sp) ; dstr mode 1: SP now 1174 (12) + bis (sp),-(sp) ; dstr mode 4: SP now 1172 (13) + incb (sp)+ ; dstr mode 2: SP now 1174 (14) + dec 0(sp) ; dstr mode 6: SP now 1174 (15) +; + br 1500$ +; +1000$: clr cp.err ; HACK: clear CPUERR !!! + htstne sp ; no red stack aborts expected + inc r2 + rti +; +1100$: rti ; dummy emt handler +1200$: rti ; dummy trap handler +1300$: rts pc ; dummy routine +; +1500$: hcmpeq #15.,r2 ; all traps taken ? + mov #v..iit+2,v..iit ; v..iit to catcher + mov #v..emt+2,v..emt ; v..emt to catcher + mov #v..trp+2,v..trp ; v..trp to catcher +; +; part 2: test instructions that should not trap --------------------- +; + mov #stack-2,r2 ; in yellow zone + mov r2,(r2) ; load on stack (not using SP) + mov r2,sp ; SP in yellow zone +; dstw mode 3,5,7 + mov (sp)+,@-(sp) ; dstw mode 5: SP now 1176 + mov @0(sp),@(sp)+ ; dstw mode 3: SP now 1200 + mov -(sp),@0(sp) ; dstw mode 7: SP now 1176 +; dstr mode 3,5,7 when rmw + bis (sp)+,@-(sp) ; dstw mode 5: SP now 1176 + bis @0(sp),@(sp)+ ; dstw mode 3: SP now 1200 + bis -(sp),@0(sp) ; dstw mode 7: SP now 1176 +; dstr mode 1,2,4,6 in read-only + tst (sp) ; dstr mode 1: SP now 1176 + cmp (sp),-(sp) ; dstr mode 4: SP now 1174 + cmp (sp),(sp)+ ; dstr mode 2: SP now 1176 + cmp (sp),0(sp) ; dstr mode 6: SP now 1176 +; dstr mode 3,5,7 in read-only + cmp (sp),@(sp)+ ; dstr mode 3: SP now 1200 + cmp (sp),@-(sp) ; dstr mode 5: SP now 1176 + cmp (sp),@0(sp) ; dstr mode 7: SP now 1176 +; check that EA is compared against STKLIM + clr sp + mov @#2000,2000(sp) ; SP=0, EA=2000 -> no trap +; + clr cp.slr ; STKLIM to default + mov #stack,sp ; SP to default +; +9999$: iot ; end of test A3.3 +; ; Section B: Stress tests ==================================================== ; ; Test B1: address mode torture tests +++++++++++++++++++++++++++++++++++++++ @@ -565,7 +739,7 @@ tc0103: mov #vhugen,v..iit ; set iit handler ; END OF ALL TESTS - loop closure ============================================ ; mov tstno,r0 ; hack, for easy monitoring ... - hcmpeq tstno,#19. ; all tests done ? + hcmpeq tstno,#22. ; all tests done ? ; jmp loop ; diff --git a/tools/tcode/cpu_eis.mac b/tools/tcode/cpu_eis.mac index b75605ff..60f768c4 100644 --- a/tools/tcode/cpu_eis.mac +++ b/tools/tcode/cpu_eis.mac @@ -1,4 +1,4 @@ -; $Id: cpu_eis.mac 1264 2022-07-30 07:42:17Z mueller $ +; $Id: cpu_eis.mac 1314 2022-11-09 10:55:29Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later ; Copyright 2022- by Walter F.J. Mueller ; @@ -688,7 +688,7 @@ te0101: mov #1000$,r4 ; setup data pointer ; 9999$: iot ; end of test E1.1 ; -; Test X1.2 -- xor znvc=1 ++++++++++++++++++++++++++++++++++++++++++++ +; Test E1.2 -- xor znvc=1 ++++++++++++++++++++++++++++++++++++++++++++ ; check xor with all ccs set; register destination ; te0102: mov #1000$,r4 ; setup data pointer diff --git a/tools/tcode/cpu_mmu.mac b/tools/tcode/cpu_mmu.mac index d3871d23..119f870f 100644 --- a/tools/tcode/cpu_mmu.mac +++ b/tools/tcode/cpu_mmu.mac @@ -1,4 +1,4 @@ -; $Id: cpu_mmu.mac 1311 2022-10-29 12:57:38Z mueller $ +; $Id: cpu_mmu.mac 1313 2022-11-04 14:01:08Z mueller $ ; SPDX-License-Identifier: GPL-3.0-or-later ; Copyright 2022- by Walter F.J. Mueller ; @@ -1573,8 +1573,8 @@ te0102: mov #vhmmut,v..mmu ; setup MMU trap handler ; ; case r-abo: read, abort 1200$: mov #vhmmua,v..mmu ; setup MMU abort handler - mov (r5)+,1210$ - mov #1210$,(r2) + mov (r5)+,1210$ + mov #1210$,(r2) tst (r3) ; probe read halt ; expect abort 1210$: .word 0,0 @@ -1593,16 +1593,16 @@ te0102: mov #vhmmut,v..mmu ; setup MMU trap handler ; ; case w-abo: write, abort 1500$: mov #vhmmua,v..mmu ; setup MMU abort handler - mov (r5)+,1510$ - mov #1510$,(r2) - add r0,(r3) ; probe write + mov (r5)+,1510$ + mov #1510$,(r2) + add r0,(r3) ; probe write halt ; expect abort 1510$: .word 0,0 br 1910$ ; to tr-check ; ; case w-trap: write, trap 1600$: mov #vhmmut,v..mmu ; setup MMU trap handler - mov #1900$,(r2) + mov #1900$,(r2) clr (r3) ; probe write halt ; expect trap ; diff --git a/tools/tcode/tcode.ecmd b/tools/tcode/tcode.ecmd index b5dd78d0..ef339f51 100644 --- a/tools/tcode/tcode.ecmd +++ b/tools/tcode/tcode.ecmd @@ -1,25 +1,25 @@ -! $Id: tcode.ecmd 1311 2022-10-29 12:57:38Z mueller $ -! SPDX-License-Identifier: GPL-3.0-or-later -! Copyright 2022- by Walter F.J. Mueller -! -! setup w11 like processor configuration -! set nouwin to disable UNIBUS window (17000000-17757777) to UNIBUS map -! set memory to 3840 -! this way e11 behaves like w11 and SimH, which simplifies tcodes -! +; $Id: tcode.ecmd 1313 2022-11-04 14:01:08Z mueller $ +; SPDX-License-Identifier: GPL-3.0-or-later +; Copyright 2022- by Walter F.J. Mueller +; +; setup w11 like processor configuration +; set nouwin to disable UNIBUS window (17000000-17757777) to UNIBUS map +; set memory to 3840 +; this way e11 behaves like w11 and SimH, which simplifies tcodes +; set cpu 70 set cpu nouwin set memory 3840 set cpu nofpp set idle delay=1 -! set ^E as break character (like in SimH) +; set ^E as break character (like in SimH) set break 005 -! enable PC value logging (inspect with show pclog) +; enable PC value logging (inspect with show pclog) set pclog on -! set sysid, leading '1' indicates simulator, next '2' e11 +; set sysid, leading '1' indicates simulator, next '2' e11 set cpu SYSID=0120345 -! -! create log file, the only way to capture e11 output -! no rediction to stdout possible -! +; +; create log file, the only way to capture e11 output +; no rediction to stdout possible +; log tt0: tmp_e11_tt0