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update ibd_ibtst and ibd_ibmon

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- ibd_ibtst: rename dly[rw]->bsy[rw]; datto for write; add datab
- ibd_ibmon: revise iface, busy 10->8, delay 14->16 bits; track ack properly
This commit is contained in:
wfjm
2019-03-09 09:03:57 +01:00
parent 73adad79e1
commit 374dfe30cc
5 changed files with 139 additions and 100 deletions
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33
rtl/ibus/ibd_ibmon.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibd_ibmon.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: ibd_ibmon.vhd 1116 2019-03-03 08:24:07Z mueller $
--
-- Copyright 2015-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2015-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,7 +20,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 14.7; viv 2014.4-2016.4; ghdl 0.31-0.34
-- Tool versions: xst 14.7; viv 2014.4-2018.3; ghdl 0.31-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -29,6 +29,8 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-03-01 1116 2.1.1 track ack properly
-- 2019-02-23 1115 2.1 revised iface, busy 10->8, delay 14->16 bits
-- 2017-04-16 879 2.0 revised interface, add suspend and repeat collapse
-- 2017-03-04 858 1.0.2 BUGFIX: wrap set when go=0 due to wena=0
-- 2015-05-02 672 1.0.1 use natural for AWIDTH to work around a ghdl issue
@@ -67,12 +69,11 @@
-- 13 : nak (no ack in last non-busy cycle)
-- 12 : ack (ack seen)
-- 11 : busy (busy seen)
-- 10 : -- (reserved in case err is implemented)
-- 10 : -- (reserved)
-- 09 : we (write cycle)
-- 08 : rmw (read-modify-write)
-- 07:00 : delay to prev (msb's)
-- word 2 15:10 : delay to prev (lsb's)
-- 09:00 : number of busy cycles
-- 07:00 : nbusy (number of busy cycles)
-- word 2 : ndly (delay to previous request)
-- word 1 : data
-- word 0 15 : be1 (byte enable low)
-- 14 : be0 (byte enable high)
@@ -143,9 +144,7 @@ architecture syn of ibd_ibmon is
constant dat3_ibf_busy : integer := 11;
constant dat3_ibf_we : integer := 9;
constant dat3_ibf_rmw : integer := 8;
subtype dat3_ibf_ndlymsb is integer range 7 downto 0;
subtype dat2_ibf_ndlylsb is integer range 15 downto 10;
subtype dat2_ibf_nbusy is integer range 9 downto 0;
subtype dat3_ibf_nbusy is integer range 7 downto 0;
constant dat0_ibf_be1 : integer := 15;
constant dat0_ibf_be0 : integer := 14;
constant dat0_ibf_racc : integer := 13;
@@ -194,8 +193,8 @@ architecture syn of ibd_ibmon is
ibtout : slbit; -- ibus trace: tout detected
ibburst : slbit; -- ibus trace: burst detected
ibdata : slv16; -- ibus trace: data
ibnbusy : slv10; -- ibus number of busy cycles
ibndly : slv14; -- ibus delay to prev. access
ibnbusy : slv8; -- ibus number of busy cycles
ibndly : slv16; -- ibus delay to prev. access
end record regs_type;
constant laddrzero : slv(AWIDTH-1 downto 0) := (others=>'0');
@@ -223,8 +222,8 @@ architecture syn of ibd_ibmon is
(others=>'0') -- ibndly
);
constant ibnbusylast : slv10 := (others=>'1');
constant ibndlylast : slv14 := (others=>'1');
constant ibnbusylast : slv8 := (others=>'1');
constant ibndlylast : slv16 := (others=>'1');
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
@@ -487,6 +486,7 @@ begin
n.ibbusy := IB_SRES_SUM.busy;
n.ibnbusy := (others=>'0');
else -- if non-initial cycles
n.iback := r.iback or IB_SRES_SUM.ack;
if r.ibnbusy /= ibnbusylast then -- and count
n.ibnbusy := slv(unsigned(r.ibnbusy) + 1);
end if;
@@ -546,9 +546,8 @@ begin
idat3(dat3_ibf_busy) := r.ibbusy;
idat3(dat3_ibf_we) := r.ibwe;
idat3(dat3_ibf_rmw) := r.ibrmw;
idat3(dat3_ibf_ndlymsb):= r.ibndly(13 downto 6);
idat2(dat2_ibf_ndlylsb):= r.ibndly( 5 downto 0);
idat2(dat2_ibf_nbusy) := r.ibnbusy;
idat3(dat3_ibf_nbusy) := r.ibnbusy;
idat2 := r.ibndly;
idat1 := r.ibdata;
idat0(dat0_ibf_be1) := r.ibbe1;
idat0(dat0_ibf_be0) := r.ibbe0;

111
rtl/ibus/ibd_ibtst.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: ibd_ibtst.vhd 1112 2019-02-17 11:10:04Z mueller $
-- $Id: ibd_ibtst.vhd 1116 2019-03-03 08:24:07Z mueller $
--
-- Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -22,8 +22,9 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-03-01 1116 1.0.1 rnam dly[rw]->bsy[rw]; datto for write; add datab
-- 2019-02-16 1112 1.0 Initial version
-- 2019-02-09 1110 0.1 First draft
-- 2019-02-09 1110 0.1 First draft
------------------------------------------------------------------------------
--
-- ibus registers:
@@ -31,10 +32,11 @@
-- Addr Bits IB RB IR Name Function
-- 00 cntl Control register
-- 15 -- 0W 00 fclr fifo clear
-- 7 -- RW 00 datto ibus timeout for bad loc data access
-- 8 -- RW 00 datab ibus ack while busy for data nak
-- 7 -- RW 00 datto ibus timeout for data nak
-- 6 -- RW 00 nobyt disallow byte writes to data (loc+rem)
-- 5 -- RW 00 dlyw enable loc write delay for fifo/data
-- 4 -- RW 00 dlyr enable loc read delay for fifo/data
-- 5 -- RW 00 bsyw enable loc write busy for fifo/data
-- 4 -- RW 00 bsyr enable loc read busy for fifo/data
-- 3 -- RW 11 remw enable rem write for fifo/data
-- 2 -- RW 11 remr enable rem read for fifo/data
-- 1 -- RW 00 locw enable loc write for fifo/data
@@ -80,10 +82,11 @@ architecture syn of ibd_ibtst is
constant ibaddr_fifo : slv2 := "11"; -- wdat address offset
constant cntl_ibf_fclr : integer := 15;
constant cntl_ibf_datab : integer := 8;
constant cntl_ibf_datto : integer := 7;
constant cntl_ibf_nobyt : integer := 6;
constant cntl_ibf_dlyw : integer := 5;
constant cntl_ibf_dlyr : integer := 4;
constant cntl_ibf_bsyw : integer := 5;
constant cntl_ibf_bsyr : integer := 4;
constant cntl_ibf_remw : integer := 3;
constant cntl_ibf_remr : integer := 2;
constant cntl_ibf_locw : integer := 1;
@@ -100,10 +103,11 @@ architecture syn of ibd_ibtst is
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
datab : slbit; -- cntl: ibus busy for bad loc data
datto : slbit; -- cntl: ibus timeout for bad loc data
nobyt : slbit; -- cntl: disallow byte writes to data
dlyw : slbit; -- cntl: enable loc write delay
dlyr : slbit; -- cntl: enable loc read delay
bsyw : slbit; -- cntl: enable loc write busy
bsyr : slbit; -- cntl: enable loc read busy
remw : slbit; -- cntl: enable rem write
remr : slbit; -- cntl: enable rem read
locw : slbit; -- cntl: enable loc write
@@ -123,7 +127,7 @@ architecture syn of ibd_ibtst is
constant regs_init : regs_type := (
'0', -- ibsel
'0','0','0','0', -- datto,nobyt,dlyw,dlyr
'0','0','0','0','0', -- datab,datto,nobyt,bsyw,bsyr
'1','1','0','0', -- remw,remr,locw,locr
'0','0','0','0', -- racc,cacc,be1,be0
'0','0','0', -- rmw,we,re
@@ -182,8 +186,8 @@ begin
variable ififo_rst : slbit := '0';
variable ififo_ce : slbit := '0';
variable ififo_we : slbit := '0';
variable dlyok : slbit := '0'; -- fifo/data delay ok
variable dodly : slbit := '0'; -- fifo/data do delay
variable bsyok : slbit := '0'; -- fifo/data busy ok
variable dobsy : slbit := '0'; -- fifo/data do busy
variable wrok : slbit := '0'; -- fifo/data write ok
variable rdok : slbit := '0'; -- fifo/data read ok
begin
@@ -199,11 +203,11 @@ begin
ififo_ce := '0';
ififo_we := '0';
dlyok := '0';
bsyok := '0';
if IB_MREQ.racc = '0' then -- loc
dlyok := (r.dlyr and IB_MREQ.re) or (r.dlyw and IB_MREQ.we);
bsyok := (r.bsyr and IB_MREQ.re) or (r.bsyw and IB_MREQ.we);
end if;
dodly := '0';
dobsy := '0';
if IB_MREQ.racc = '1' then -- rem
wrok := r.remw;
@@ -243,14 +247,14 @@ begin
end if;
-- delay counter
if r.ibsel='1' and ibreq='1' and dlyok='1' then -- selected,active,delayed
if r.ibsel='1' and ibreq='1' and bsyok='1' then -- selected,active,busy
if r.req_1 = '0' then -- leading edge
n.dcnt := "111";
dodly := '1';
dobsy := '1';
else -- later
if r.dcnt /= "000" then
n.dcnt := slv(unsigned(r.dcnt) - 1);
dodly := '1';
dobsy := '1';
end if;
end if;
end if;
@@ -262,10 +266,11 @@ begin
if IB_MREQ.racc = '1' then -- rem
if IB_MREQ.we = '1' then -- write
ififo_rst := IB_MREQ.din(cntl_ibf_fclr);
n.datab := IB_MREQ.din(cntl_ibf_datab);
n.datto := IB_MREQ.din(cntl_ibf_datto);
n.nobyt := IB_MREQ.din(cntl_ibf_nobyt);
n.dlyw := IB_MREQ.din(cntl_ibf_dlyw);
n.dlyr := IB_MREQ.din(cntl_ibf_dlyr);
n.bsyw := IB_MREQ.din(cntl_ibf_bsyw);
n.bsyr := IB_MREQ.din(cntl_ibf_bsyr);
n.remw := IB_MREQ.din(cntl_ibf_remw);
n.remr := IB_MREQ.din(cntl_ibf_remr);
n.locw := IB_MREQ.din(cntl_ibf_locw);
@@ -282,76 +287,91 @@ begin
when ibaddr_data => -- DATA
if IB_MREQ.we = '1' then -- write
if wrok = '1' then -- write ok
if wrok = '1' then -- write enabled
if r.nobyt = '1' and -- byte write allowed check
(IB_MREQ.be1='0' or IB_MREQ.be0='0') then
iback := '0'; -- send nak
else -- byte check ok
if dodly = '1' then -- delay active
if dobsy = '1' then -- busy active
iback := '0';
ibbusy := '1';
else -- no delay active
else -- no busy active
if IB_MREQ.be1 = '1' then
n.data(ibf_byte1) := IB_MREQ.din(ibf_byte1);
end if;
if IB_MREQ.be0 = '1' then
n.data(ibf_byte0) := IB_MREQ.din(ibf_byte0);
end if;
end if; -- dodly = '1'
end if; -- dobsy = '1'
end if; -- byte check
else -- write not ok
iback := '0'; -- send nak
else -- write disabled
if dobsy = '1' then -- busy active
iback := r.datab; -- send ack when busy for nak
ibbusy := '1';
else -- no busy active
if r.datto = '1' then -- data time out enabled
iback := '0';
ibbusy := '1'; -- will cause timeout !
else
iback := '0'; -- send nak
end if;
end if; -- dobsy = '1'
end if; -- wrok = '1'
end if; -- IB_MREQ.we = '1'
if IB_MREQ.re = '1' then -- read
if rdok = '1' then -- read enabled
if dodly = '1' then -- delay active
if dobsy = '1' then -- busy active
iback := '0';
ibbusy := '1';
end if;
else -- read disabled
if r.datto = '1' then -- data time out enabled
iback := '0';
ibbusy := '1'; -- will cause timeout !
else
iback := '0'; -- send nak
end if;
if dobsy = '1' then -- busy active
iback := r.datab; -- send ack when busy for nak
ibbusy := '1';
else -- no busy active
if r.datto = '1' then -- data time out enabled
iback := '0';
ibbusy := '1'; -- will cause timeout !
else
iback := '0'; -- send nak
end if;
end if; -- dobsy = '1'
end if; -- rdok = '0'
end if; -- IB_MREQ.re = '1'
when ibaddr_fifo => -- FIFO
if IB_MREQ.we = '1' then -- write
if wrok = '1' then -- write ok
if dodly = '1' then -- delay active
if wrok = '1' then -- write enabled
if dobsy = '1' then -- busy active
iback := '0';
ibbusy := '1';
else -- delay not active
else -- busy not active
if FIFO_FULL = '0' then -- fifo not full
ififo_ce := '1';
ififo_we := '1';
else -- fifo full
iback := '0'; -- send nak
end if; -- FIFO_FULL = '0'
end if; -- dodly = '1'
else -- write not ok
end if; -- dobsy = '1'
else -- write disabled
iback := '0'; -- send nak
end if; -- wrok = '1'
end if; -- IB_MREQ.we = '1'
if IB_MREQ.re = '1' then -- read
if rdok = '1' then -- read ok
if dodly = '1' then -- delay active
if rdok = '1' then -- read enabled
if dobsy = '1' then -- busy active
iback := '0';
ibbusy := '1';
else -- delay not active
else -- busy not active
if FIFO_EMPTY = '0' then -- fifo not empty
ififo_ce := '1';
else -- fifo empty
iback := '0'; -- send nak
end if; -- FIFO_EMPTY = '0'
end if; -- dodly = '1'
else -- read not ok
end if; -- dobsy = '1'
else -- read disabled
iback := '0'; -- send nak
end if; -- rdok = '1'
end if; -- IB_MREQ.re = '1'
@@ -364,10 +384,11 @@ begin
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_cntl => -- CNTL
idout(cntl_ibf_datab) := r.datab;
idout(cntl_ibf_datto) := r.datto;
idout(cntl_ibf_nobyt) := r.nobyt;
idout(cntl_ibf_dlyw) := r.dlyw;
idout(cntl_ibf_dlyr) := r.dlyr;
idout(cntl_ibf_bsyw) := r.bsyw;
idout(cntl_ibf_bsyr) := r.bsyr;
idout(cntl_ibf_remw) := r.remw;
idout(cntl_ibf_remr) := r.remr;
idout(cntl_ibf_locw) := r.locw;