From 3ba4296ddbd2960ea7badb3f44c233a4bb42753a Mon Sep 17 00:00:00 2001 From: wfjm Date: Mon, 15 Aug 2022 09:42:27 +0200 Subject: [PATCH] update known differences [skip ci] --- doc/w11a_known_differences.md | 32 ++++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/doc/w11a_known_differences.md b/doc/w11a_known_differences.md index f4d17531..021fbb3a 100644 --- a/doc/w11a_known_differences.md +++ b/doc/w11a_known_differences.md @@ -7,6 +7,8 @@ The issues of the w11 CPU and systems are listed in a separate document ### Table of content - [Known differences between w11a and KB11-C (11/70)](#user-content-diff) +- [Differences in unspecified behavior cases between w11a and + KB11-C (11/70)](#user-content-unspec) - [Known limitations](#user-content-lim) ### Known differences between w11a and KB11-C (11/70) @@ -27,8 +29,8 @@ The issues of the w11 CPU and systems are listed in a separate document `NOOP`, so traps and interrupts are taken as for all other instructions. **--> The w11a isn't bug compatible with the 11/70.** - A 'red stack violation' loses PSW, a 0 is pushed onto the stack. -- The 'instruction complete flag' in `SSR0` is not implemented, it is - permanently '0', `SSR2` will not record vector addresses in case of a +- The 'instruction complete flag' in `MMR0` is not implemented, it is + permanently '0', `MMR2` will not record vector addresses in case of a vector fetch fault. Recovery of vector fetch faults is therefore not possible, but only 11/45 and 11/70 supported this, no OS used that, and it's even unclear whether it can be practically used. @@ -42,6 +44,32 @@ All four points relate to very 11/70 specific behavior, no operating system depends on them, therefore they are considered acceptable implementation differences. +### Differences in unspecified behavior cases between w11a and KB11-C (11/70) + +- The state of the N and Z condition codes is different after a DIV overflow. + The [1979 processor handbook](http://www.bitsavers.org/pdf/dec/pdp11/handbooks/PDP11_Handbook1979.pdf) + states on page 75 that the state of the N and Z condition codes is unspecified + when V=1 is set after a zero divide or an overflow condition. + After a DIV overflow, the w11 returns Z=0 and N based on the sign of the + full 32-bit result, as can be easily determined by xor'ing of the sign + bits of dividend and divisor. + This is also the most natural result, an overflow is certainly + not zero, and the sign is unambiguously determined by the inputs. + The SimH simulator also behaves like this. A real J11 and a real 11/70 + can have N=0 even when dividend and divisor have opposite signs. And a + real 11/70 can have Z=1. Bottom line is, that the w11 differs from the + behavior of both the real 11/70 and the real J11 behavior. +- the state of the result registers is also unspecified after a DIV with V=1. + SimH and a real J11 never modify a register when V=1 is set. A real 11/70 + and the w11 do, but under different conditions, and leave different values + in the registers. +- for gory details consult the [divtst](../tools/tests/divtst/README.md) code + and the log files for different systems in the + [data](../tools/tests/divtst/data/README.md) directory. + +No software should depend on unspecified behavior of the CPU, therefore +this is considered as acceptable implementation difference. + ### Known limitations - some programs use timing loops based on the execution speed of the