From 3cb0bc69249a07bd7d462cefeb583589e775a6dc Mon Sep 17 00:00:00 2001 From: wfjm Date: Sat, 2 Feb 2019 09:36:23 +0100 Subject: [PATCH] add MIG support for Arty S7 --- doc/CHANGELOG.md | 1 + rtl/bplib/artys7/artys7lib.vhd | 37 +++- rtl/bplib/artys7/mig_artys7.tcl | 58 ++++++ rtl/bplib/artys7/miglib_artys7.vbom | 4 + rtl/bplib/artys7/miglib_artys7.vhd | 121 ++++++++++++ rtl/bplib/artys7/migui_artys7_gsim.vbom | 8 + rtl/bplib/artys7/migui_artys7_gsim.vhd | 136 +++++++++++++ rtl/bplib/artys7/sramif_mig_artys7.vbom | 13 ++ rtl/bplib/artys7/sramif_mig_artys7.vhd | 213 +++++++++++++++++++++ rtl/bplib/artys7/tb/.gitignore | 2 + rtl/bplib/artys7/tb/Makefile | 4 +- rtl/bplib/artys7/tb/artys7_dram_dummy.vbom | 5 + rtl/bplib/artys7/tb/artys7_dram_dummy.vhd | 89 +++++++++ rtl/bplib/artys7/tb/tb_artys7.vhd | 4 +- rtl/bplib/artys7/tb/tb_artys7_dram.vbom | 24 +++ rtl/bplib/artys7/tb/tb_artys7_dram.vhd | 210 ++++++++++++++++++++ 16 files changed, 920 insertions(+), 9 deletions(-) create mode 100644 rtl/bplib/artys7/mig_artys7.tcl create mode 100644 rtl/bplib/artys7/miglib_artys7.vbom create mode 100644 rtl/bplib/artys7/miglib_artys7.vhd create mode 100644 rtl/bplib/artys7/migui_artys7_gsim.vbom create mode 100644 rtl/bplib/artys7/migui_artys7_gsim.vhd create mode 100644 rtl/bplib/artys7/sramif_mig_artys7.vbom create mode 100644 rtl/bplib/artys7/sramif_mig_artys7.vhd create mode 100644 rtl/bplib/artys7/tb/.gitignore create mode 100644 rtl/bplib/artys7/tb/artys7_dram_dummy.vbom create mode 100644 rtl/bplib/artys7/tb/artys7_dram_dummy.vhd create mode 100644 rtl/bplib/artys7/tb/tb_artys7_dram.vbom create mode 100644 rtl/bplib/artys7/tb/tb_artys7_dram.vhd diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index 2068d819..8c814862 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -24,6 +24,7 @@ The full set of tests is only run for tagged releases. - add support for DDR memory via Vivado MIG cores for - Digilent Arty - Digilent Nexys4 DDR + - Digilent Arty S7 - add a low level MIG interface test design ### New features diff --git a/rtl/bplib/artys7/artys7lib.vhd b/rtl/bplib/artys7/artys7lib.vhd index a6702de5..8a9f9a36 100644 --- a/rtl/bplib/artys7/artys7lib.vhd +++ b/rtl/bplib/artys7/artys7lib.vhd @@ -1,6 +1,6 @@ --- $Id: artys7lib.vhd 1038 2018-08-11 12:39:52Z mueller $ +-- $Id: artys7lib.vhd 1105 2019-01-12 19:52:45Z mueller $ -- --- Copyright 2018- by Walter F.J. Mueller +-- Copyright 2018-2019 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -12,14 +12,15 @@ -- for complete details. -- ------------------------------------------------------------------------------ --- Package Name: artylib +-- Package Name: artys7lib -- Description: Digilent Arty S7 components -- -- Dependencies: - --- Tool versions: viv 2017.2-2018.2; ghdl 0.34 +-- Tool versions: viv 2017.2-2018.2; ghdl 0.34-0.35 -- -- Revision History: -- Date Rev Version Comment +-- 2019-01-12 1105 1.1 add artys7_dram_aif -- 2018-08-05 1028 1.0 Initial version ------------------------------------------------------------------------------ @@ -43,4 +44,32 @@ component artys7_aif is -- ARTY S7, abstract iface, base ); end component; +component artys7_dram_aif is -- ARTY S7, abstract iface, base+dram + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv4; -- artys7 switches + I_BTN : in slv4; -- artys7 buttons + O_LED : out slv4; -- artys7 leds + O_RGBLED0 : out slv3; -- artys7 rgb-led 0 + O_RGBLED1 : out slv3; -- artys7 rgb-led 1 + DDR3_DQ : inout slv16; -- dram: data in/out + DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p) + DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n) + DDR3_ADDR : out slv14; -- dram: address + DDR3_BA : out slv3; -- dram: bank address + DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low) + DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low) + DDR3_WE_N : out slbit; -- dram: write enable (act.low) + DDR3_RESET_N : out slbit; -- dram: reset (act.low) + DDR3_CK_P : out slv1; -- dram: clock (diff-p) + DDR3_CK_N : out slv1; -- dram: clock (diff-n) + DDR3_CKE : out slv1; -- dram: clock enable + DDR3_CS_N : out slv1; -- dram: chip select (act.low) + DDR3_DM : out slv2; -- dram: data input mask + DDR3_ODT : out slv1 -- dram: on-die termination + ); +end component; + end package artys7lib; diff --git a/rtl/bplib/artys7/mig_artys7.tcl b/rtl/bplib/artys7/mig_artys7.tcl new file mode 100644 index 00000000..a0a2464e --- /dev/null +++ b/rtl/bplib/artys7/mig_artys7.tcl @@ -0,0 +1,58 @@ +# $Id: mig_artys7.tcl 1105 2019-01-12 19:52:45Z mueller $ +# +# Copyright 2019- by Walter F.J. Mueller +# License disclaimer see License.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2019-01-12 1105 1.0 Initial version +# + +# defined tested MIG versions with project files +set tdsc_list { "4.2" "mig_a.prj" } + +# determine available MIG version (only latest supported !!) +set vlnv [get_ipdefs "xilinx.com:ip:mig_7series:*"] +set vers [lindex [split $vlnv ":"] 3] + +# filter out matching MIG version + +set mprj {} +foreach {tver tprj} $tdsc_list { + lappend tver_list $tver + if {$vers eq $tver} { set mprj $tprj } +} + +puts [format "## tested MIG versions: %s" [join $tver_list " "]] +puts [format "## available MIG version: %s" $vers] + +if {$mprj ne ""} { + puts [format "## selected MIG version: %s with %s" $vers $mprj] +} else { + error "mig_arty: no tested MIG version found" +} + +create_ip -vlnv "xilinx.com:ip:mig_7series:$vers" -module_name migui_artys7 + +set ip_dir [get_property IP_DIR [ get_ips ips migui_artys7]] +##puts "ip_dir: $ip_dir" +puts "## migui: copy $mprj to IP_DIR" +file copy $mprj "$ip_dir/$mprj" + +puts "## migui: set_property" +set_property -dict [list \ + CONFIG.XML_INPUT_FILE $mprj \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.MIG_DONT_TOUCH_PARAM {Custom} \ + CONFIG.BOARD_MIG_PARAM {Custom} \ + ] \ + [get_ips migui_artys7] + +puts "## migui: generate_target" +generate_target {instantiation_template} \ + [get_files "$ip_dir/migui_artys7.xci"] + +puts "## migui: export_ip_user_files" +export_ip_user_files -of_objects \ + [get_files "$ip_dir/migui_artys7.xci"] \ + -no_script -sync -force -quiet diff --git a/rtl/bplib/artys7/miglib_artys7.vbom b/rtl/bplib/artys7/miglib_artys7.vbom new file mode 100644 index 00000000..2f0d29b9 --- /dev/null +++ b/rtl/bplib/artys7/miglib_artys7.vbom @@ -0,0 +1,4 @@ +# libs +../../vlib/slvtypes.vhd +../mig/miglib.vbom +miglib_artys7.vhd diff --git a/rtl/bplib/artys7/miglib_artys7.vhd b/rtl/bplib/artys7/miglib_artys7.vhd new file mode 100644 index 00000000..2ad107a8 --- /dev/null +++ b/rtl/bplib/artys7/miglib_artys7.vhd @@ -0,0 +1,121 @@ +-- $Id: miglib_artys7.vhd 1105 2019-01-12 19:52:45Z mueller $ +-- +-- Copyright 2019- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: miglib_artys7 +-- Description: MIG interface components - for artys7 +-- +-- Dependencies: - +-- Tool versions: viv 2018.3; ghdl 0.35 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2019-01-12 1105 1.0 Initial version (cloned from miglib_arty) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.miglib.all; + +package miglib_artys7 is + +constant mig_bawidth : positive := 4; -- byte addr width +constant mig_mawidth : positive := 28; -- mem addr width +constant mig_mwidth : positive := 2**mig_bawidth; -- mask width ( 16) +constant mig_dwidth : positive := 8*mig_mwidth; -- data width (128) + +component sramif_mig_artys7 is -- SRAM to DDR via MIG for artys7 + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + REQ : in slbit; -- request + WE : in slbit; -- write enable + BUSY : out slbit; -- controller busy + ACK_R : out slbit; -- acknowledge read + ACK_W : out slbit; -- acknowledge write + ACT_R : out slbit; -- signal active read + ACT_W : out slbit; -- signal active write + ADDR : in slv20; -- address (32 bit word address) + BE : in slv4; -- byte enable + DI : in slv32; -- data in (memory view) + DO : out slv32; -- data out (memory view) + CLKMIG : in slbit; -- sys clock for mig core + CLKREF : in slbit; -- ref clock for mig core + TEMP : in slv12; -- die temperature + MONI : out sramif2migui_moni_type;-- monitor signals + DDR3_DQ : inout slv16; -- dram: data in/out + DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p) + DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n) + DDR3_ADDR : out slv14; -- dram: address + DDR3_BA : out slv3; -- dram: bank address + DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low) + DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low) + DDR3_WE_N : out slbit; -- dram: write enable (act.low) + DDR3_RESET_N : out slbit; -- dram: reset (act.low) + DDR3_CK_P : out slv1; -- dram: clock (diff-p) + DDR3_CK_N : out slv1; -- dram: clock (diff-n) + DDR3_CKE : out slv1; -- dram: clock enable + DDR3_CS_N : out slv1; -- dram: chip select (act.low) + DDR3_DM : out slv2; -- dram: data input mask + DDR3_ODT : out slv1 -- dram: on-die termination + ); +end component; + +component migui_artys7 is -- MIG generated for artys7 + port ( + DDR3_DQ : inout slv16; -- dram: data in/out + DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p) + DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n) + DDR3_ADDR : out slv14; -- dram: address + DDR3_BA : out slv3; -- dram: bank address + DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low) + DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low) + DDR3_WE_N : out slbit; -- dram: write enable (act.low) + DDR3_RESET_N : out slbit; -- dram: reset (act.low) + DDR3_CK_P : out slv1; -- dram: clock (diff-p) + DDR3_CK_N : out slv1; -- dram: clock (diff-n) + DDR3_CKE : out slv1; -- dram: clock enable + DDR3_CS_N : out slv1; -- dram: chip select (act.low) + DDR3_DM : out slv2; -- dram: data input mask + DDR3_ODT : out slv1; -- dram: on-die termination + APP_ADDR : in slv(mig_mawidth-1 downto 0); -- MIGUI address + APP_CMD : in slv3; -- MIGUI command + APP_EN : in slbit; -- MIGUI command enable + APP_WDF_DATA : in slv(mig_dwidth-1 downto 0); -- MIGUI write data + APP_WDF_END : in slbit; -- MIGUI write end + APP_WDF_MASK : in slv(mig_mwidth-1 downto 0); -- MIGUI write mask + APP_WDF_WREN : in slbit; -- MIGUI write enable + APP_RD_DATA : out slv(mig_dwidth-1 downto 0); -- MIGUI read data + APP_RD_DATA_END : out slbit; -- MIGUI read end + APP_RD_DATA_VALID : out slbit; -- MIGUI read valid + APP_RDY : out slbit; -- MIGUI ready for cmd + APP_WDF_RDY : out slbit; -- MIGUI ready for data write + APP_SR_REQ : in slbit; -- MIGUI reserved (tie to 0) + APP_REF_REQ : in slbit; -- MIGUI refresh reques + APP_ZQ_REQ : in slbit; -- MIGUI ZQ calibrate request + APP_SR_ACTIVE : out slbit; -- MIGUI reserved (ignore) + APP_REF_ACK : out slbit; -- MIGUI refresh acknowledge + APP_ZQ_ACK : out slbit; -- MIGUI ZQ calibrate acknowledge + UI_CLK : out slbit; -- MIGUI clock + UI_CLK_SYNC_RST : out slbit; -- MIGUI reset + INIT_CALIB_COMPLETE : out slbit; -- MIGUI calibration done + SYS_CLK_I : in slbit; -- MIGUI system clock + CLK_REF_I : in slbit; -- MIGUI reference clock + DEVICE_TEMP_I : in slv12; -- MIGUI xadc temperature + SYS_RST : in slbit -- MIGUI system reset + ); +end component; + +end package miglib_artys7; diff --git a/rtl/bplib/artys7/migui_artys7_gsim.vbom b/rtl/bplib/artys7/migui_artys7_gsim.vbom new file mode 100644 index 00000000..46cf8aab --- /dev/null +++ b/rtl/bplib/artys7/migui_artys7_gsim.vbom @@ -0,0 +1,8 @@ +# libs +../../vlib/slvtypes.vhd +../mig/miglib.vbom +miglib_artys7.vbom +# components +../mig/migui_core_gsim.vbom +# design +migui_artys7_gsim.vhd diff --git a/rtl/bplib/artys7/migui_artys7_gsim.vhd b/rtl/bplib/artys7/migui_artys7_gsim.vhd new file mode 100644 index 00000000..63369905 --- /dev/null +++ b/rtl/bplib/artys7/migui_artys7_gsim.vhd @@ -0,0 +1,136 @@ +-- $Id: migui_artys7_gsim.vhd 1105 2019-01-12 19:52:45Z mueller $ +-- +-- Copyright 2019- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: migui_artys7 - sim +-- Description: MIG generated for artys7 - simple simulator +-- +-- Dependencies: bplib/mig/migui_core_gsim +-- Test bench: tb_tst_sram_artys7 +-- Target Devices: artys7 board +-- Tool versions: viv 2018.3; ghdl 0.35 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2019-01-12 1105 1.0 Initial version (cloned from migui_arty_gsim) +-- +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.miglib.all; +use work.miglib_artys7.all; + +entity migui_artys7 is -- MIG generated for artys7 + port ( + DDR3_DQ : inout slv16; -- dram: data in/out + DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p) + DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n) + DDR3_ADDR : out slv14; -- dram: address + DDR3_BA : out slv3; -- dram: bank address + DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low) + DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low) + DDR3_WE_N : out slbit; -- dram: write enable (act.low) + DDR3_RESET_N : out slbit; -- dram: reset (act.low) + DDR3_CK_P : out slv1; -- dram: clock (diff-p) + DDR3_CK_N : out slv1; -- dram: clock (diff-n) + DDR3_CKE : out slv1; -- dram: clock enable + DDR3_CS_N : out slv1; -- dram: chip select (act.low) + DDR3_DM : out slv2; -- dram: data input mask + DDR3_ODT : out slv1; -- dram: on-die termination + APP_ADDR : in slv(mig_mawidth-1 downto 0); -- MIGUI address + APP_CMD : in slv3; -- MIGUI command + APP_EN : in slbit; -- MIGUI command enable + APP_WDF_DATA : in slv(mig_dwidth-1 downto 0);-- MIGUI write data + APP_WDF_END : in slbit; -- MIGUI write end + APP_WDF_MASK : in slv(mig_mwidth-1 downto 0); -- MIGUI write mask + APP_WDF_WREN : in slbit; -- MIGUI data write enable + APP_RD_DATA : out slv(mig_dwidth-1 downto 0); -- MIGUI read data + APP_RD_DATA_END : out slbit; -- MIGUI read end + APP_RD_DATA_VALID : out slbit; -- MIGUI read valid + APP_RDY : out slbit; -- MIGUI ready for cmd + APP_WDF_RDY : out slbit; -- MIGUI ready for data write + APP_SR_REQ : in slbit; -- MIGUI reserved (tie to 0) + APP_REF_REQ : in slbit; -- MIGUI refresh request + APP_ZQ_REQ : in slbit; -- MIGUI ZQ calibrate request + APP_SR_ACTIVE : out slbit; -- MIGUI reserved (ignore) + APP_REF_ACK : out slbit; -- MIGUI refresh acknowledge + APP_ZQ_ACK : out slbit; -- MIGUI ZQ calibrate acknowledge + UI_CLK : out slbit; -- MIGUI clock + UI_CLK_SYNC_RST : out slbit; -- MIGUI reset + INIT_CALIB_COMPLETE : out slbit; -- MIGUI inital calibration complete + SYS_CLK_I : in slbit; -- MIGUI system clock + CLK_REF_I : in slbit; -- MIGUI reference clock + DEVICE_TEMP_I : in slv12; -- MIGUI xadc temperature + SYS_RST : in slbit -- MIGUI system reset + ); +end migui_artys7; + + +architecture sim of migui_artys7 is + +begin + + MIG_SIM : migui_core_gsim + generic map ( + BAWIDTH => mig_bawidth, + MAWIDTH => mig_mawidth, + SAWIDTH => 24, + CLKMUI_MUL => 7, + CLKMUI_DIV => 14) + port map ( + SYS_CLK => SYS_CLK_I, + SYS_RST => SYS_RST, + UI_CLK => UI_CLK, + UI_CLK_SYNC_RST => UI_CLK_SYNC_RST, + INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE, + APP_RDY => APP_RDY, + APP_EN => APP_EN, + APP_CMD => APP_CMD, + APP_ADDR => APP_ADDR, + APP_WDF_RDY => APP_WDF_RDY, + APP_WDF_WREN => APP_WDF_WREN, + APP_WDF_DATA => APP_WDF_DATA, + APP_WDF_MASK => APP_WDF_MASK, + APP_WDF_END => APP_WDF_END, + APP_RD_DATA_VALID => APP_RD_DATA_VALID, + APP_RD_DATA => APP_RD_DATA, + APP_RD_DATA_END => APP_RD_DATA_END, + APP_REF_REQ => APP_REF_REQ, + APP_ZQ_REQ => APP_ZQ_REQ, + APP_REF_ACK => APP_REF_ACK, + APP_ZQ_ACK => APP_ZQ_ACK + ); + + DDR3_DQ <= (others=>'Z'); + DDR3_DQS_P <= (others=>'Z'); + DDR3_DQS_N <= (others=>'Z'); + DDR3_ADDR <= (others=>'0'); + DDR3_BA <= (others=>'0'); + DDR3_RAS_N <= '1'; + DDR3_CAS_N <= '1'; + DDR3_WE_N <= '1'; + DDR3_RESET_N <= '1'; + DDR3_CK_P <= (others=>'0'); + DDR3_CK_N <= (others=>'1'); + DDR3_CKE <= (others=>'0'); + DDR3_CS_N <= (others=>'1'); + DDR3_DM <= (others=>'0'); + DDR3_ODT <= (others=>'0'); + + APP_SR_ACTIVE <= '0'; + +end sim; diff --git a/rtl/bplib/artys7/sramif_mig_artys7.vbom b/rtl/bplib/artys7/sramif_mig_artys7.vbom new file mode 100644 index 00000000..fcb40d33 --- /dev/null +++ b/rtl/bplib/artys7/sramif_mig_artys7.vbom @@ -0,0 +1,13 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/cdclib/cdclib.vhd +../mig/miglib.vbom +miglib_artys7.vbom +# components +../mig/sramif2migui_core.vbom +../../vlib/cdclib/cdc_pulse.vbom +../../vlib/cdclib/cdc_value.vbom +@tcl:mig_artys7.tcl +[ghdl,vsim]migui_artys7_gsim.vbom +# design +sramif_mig_artys7.vhd diff --git a/rtl/bplib/artys7/sramif_mig_artys7.vhd b/rtl/bplib/artys7/sramif_mig_artys7.vhd new file mode 100644 index 00000000..2284ff35 --- /dev/null +++ b/rtl/bplib/artys7/sramif_mig_artys7.vhd @@ -0,0 +1,213 @@ +-- $Id: sramif_mig_artys7.vhd 1105 2019-01-12 19:52:45Z mueller $ +-- +-- Copyright 2019- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sramif_mig_artys7 - syn +-- Description: SRAM to DDR via MIG for artys7 +-- +-- Dependencies: bplib/mig/sramif2migui_core +-- cdclib/cdc_pulse +-- cdclib/cdc_value +-- migui_artys7 (generated core) +-- Test bench: - +-- Target Devices: artys7 board +-- Tool versions: viv 2018.3; ghdl 0.35 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2019-01-12 1105 1.0 Initial version (cloned from sramif_mig_arty) +-- +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.cdclib.all; +use work.miglib.all; +use work.miglib_artys7.all; + +entity sramif_mig_artys7 is -- SRAM to DDR via MIG for artys7 + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + REQ : in slbit; -- request + WE : in slbit; -- write enable + BUSY : out slbit; -- controller busy + ACK_R : out slbit; -- acknowledge read + ACK_W : out slbit; -- acknowledge write + ACT_R : out slbit; -- signal active read + ACT_W : out slbit; -- signal active write + ADDR : in slv20; -- address (32 bit word address) + BE : in slv4; -- byte enable + DI : in slv32; -- data in (memory view) + DO : out slv32; -- data out (memory view) + CLKMIG : in slbit; -- sys clock for mig core + CLKREF : in slbit; -- ref clock for mig core + TEMP : in slv12; -- xadc die temp for mig core + MONI : out sramif2migui_moni_type;-- monitor signals + DDR3_DQ : inout slv16; -- dram: data in/out + DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p) + DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n) + DDR3_ADDR : out slv14; -- dram: address + DDR3_BA : out slv3; -- dram: bank address + DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low) + DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low) + DDR3_WE_N : out slbit; -- dram: write enable (act.low) + DDR3_RESET_N : out slbit; -- dram: reset (act.low) + DDR3_CK_P : out slv1; -- dram: clock (diff-p) + DDR3_CK_N : out slv1; -- dram: clock (diff-n) + DDR3_CKE : out slv1; -- dram: clock enable + DDR3_CS_N : out slv1; -- dram: chip select (act.low) + DDR3_DM : out slv2; -- dram: data input mask + DDR3_ODT : out slv1 -- dram: on-die termination + ); +end sramif_mig_artys7; + + +architecture syn of sramif_mig_artys7 is + + signal MIG_BUSY : slbit := '0'; + + signal APP_RDY : slbit := '0'; + signal APP_EN : slbit := '0'; + signal APP_CMD : slv3 := (others=>'0'); + signal APP_ADDR : slv(mig_mawidth-1 downto 0) := (others=>'0'); + signal APP_WDF_RDY : slbit := '0'; + signal APP_WDF_WREN : slbit := '0'; + signal APP_WDF_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0'); + signal APP_WDF_MASK : slv(mig_mwidth-1 downto 0) := (others=>'0'); + signal APP_WDF_END : slbit := '0'; + signal APP_RD_DATA_VALID : slbit := '0'; + signal APP_RD_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0'); + signal APP_RD_DATA_END : slbit := '0'; + + signal UI_CLK_SYNC_RST : slbit := '0'; + signal INIT_CALIB_COMPLETE : slbit := '0'; + + signal SYS_RST : slbit := '0'; + signal SYS_RST_BUSY : slbit := '0'; + + signal CLKMUI : slbit := '0'; + signal TEMP_MUI : slv12 := (others=>'0'); -- xadc die temp; on CLKMUI + +begin + + SR2MIG: sramif2migui_core -- SRAM to MIG iface ----------------- + generic map ( + BAWIDTH => mig_bawidth, + MAWIDTH => mig_mawidth) + port map ( + CLK => CLK, + RESET => RESET, + REQ => REQ, + WE => WE, + BUSY => MIG_BUSY, + ACK_R => ACK_R, + ACK_W => ACK_W, + ACT_R => ACT_R, + ACT_W => ACT_W, + ADDR => ADDR, + BE => BE, + DI => DI, + DO => DO, + MONI => MONI, + UI_CLK => CLKMUI, + UI_CLK_SYNC_RST => UI_CLK_SYNC_RST, + INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE, + APP_RDY => APP_RDY, + APP_EN => APP_EN, + APP_CMD => APP_CMD, + APP_ADDR => APP_ADDR, + APP_WDF_RDY => APP_WDF_RDY, + APP_WDF_WREN => APP_WDF_WREN, + APP_WDF_DATA => APP_WDF_DATA, + APP_WDF_MASK => APP_WDF_MASK, + APP_WDF_END => APP_WDF_END, + APP_RD_DATA_VALID => APP_RD_DATA_VALID, + APP_RD_DATA => APP_RD_DATA, + APP_RD_DATA_END => APP_RD_DATA_END + ); + + CDC_SYSRST: cdc_pulse + generic map ( + POUT_SINGLE => false, + BUSY_WACK => true) + port map ( + CLKM => CLK, + RESET => '0', + CLKS => CLKMIG, + PIN => RESET, + BUSY => SYS_RST_BUSY, + POUT => SYS_RST + ); + + CDC_TEMP: cdc_value + generic map ( + DWIDTH => TEMP'length) + port map ( + CLKI => CLK, + CLKO => CLKMUI, + DI => TEMP, + DO => TEMP_MUI, + UPDT => open + ); + + MIG_CTL: migui_artys7 + port map ( + DDR3_DQ => DDR3_DQ, + DDR3_DQS_P => DDR3_DQS_P, + DDR3_DQS_N => DDR3_DQS_N, + DDR3_ADDR => DDR3_ADDR, + DDR3_BA => DDR3_BA, + DDR3_RAS_N => DDR3_RAS_N, + DDR3_CAS_N => DDR3_CAS_N, + DDR3_WE_N => DDR3_WE_N, + DDR3_RESET_N => DDR3_RESET_N, + DDR3_CK_P => DDR3_CK_P, + DDR3_CK_N => DDR3_CK_N, + DDR3_CKE => DDR3_CKE, + DDR3_CS_N => DDR3_CS_N, + DDR3_DM => DDR3_DM, + DDR3_ODT => DDR3_ODT, + APP_ADDR => APP_ADDR, + APP_CMD => APP_CMD, + APP_EN => APP_EN, + APP_WDF_DATA => APP_WDF_DATA, + APP_WDF_END => APP_WDF_END, + APP_WDF_MASK => APP_WDF_MASK, + APP_WDF_WREN => APP_WDF_WREN, + APP_RD_DATA => APP_RD_DATA, + APP_RD_DATA_END => APP_RD_DATA_END, + APP_RD_DATA_VALID => APP_RD_DATA_VALID, + APP_RDY => APP_RDY, + APP_WDF_RDY => APP_WDF_RDY, + APP_SR_REQ => '0', + APP_REF_REQ => '0', + APP_ZQ_REQ => '0', + APP_SR_ACTIVE => open, + APP_REF_ACK => open, + APP_ZQ_ACK => open, + UI_CLK => CLKMUI, + UI_CLK_SYNC_RST => UI_CLK_SYNC_RST, + INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE, + SYS_CLK_I => CLKMIG, + CLK_REF_I => CLKREF, + DEVICE_TEMP_I => TEMP_MUI, + SYS_RST => SYS_RST + ); + + BUSY <= MIG_BUSY or SYS_RST_BUSY; + +end syn; diff --git a/rtl/bplib/artys7/tb/.gitignore b/rtl/bplib/artys7/tb/.gitignore new file mode 100644 index 00000000..c8f234a2 --- /dev/null +++ b/rtl/bplib/artys7/tb/.gitignore @@ -0,0 +1,2 @@ +tb_artys7_dummy +tb_artys7_dram_dummy diff --git a/rtl/bplib/artys7/tb/Makefile b/rtl/bplib/artys7/tb/Makefile index 5a62cc97..a8db5236 100644 --- a/rtl/bplib/artys7/tb/Makefile +++ b/rtl/bplib/artys7/tb/Makefile @@ -1,10 +1,10 @@ -# $Id: Makefile 1038 2018-08-11 12:39:52Z mueller $ +# $Id: Makefile 1105 2019-01-12 19:52:45Z mueller $ # # Revision History: # Date Rev Version Comment # 2018-08-05 1038 1.0 Initial version # -EXE_all = tb_artys7_dummy +EXE_all = tb_artys7_dummy tb_artys7_dram_dummy # include ${RETROBASE}/rtl/make_viv/viv_default_artys7.mk # diff --git a/rtl/bplib/artys7/tb/artys7_dram_dummy.vbom b/rtl/bplib/artys7/tb/artys7_dram_dummy.vbom new file mode 100644 index 00000000..6ca4813d --- /dev/null +++ b/rtl/bplib/artys7/tb/artys7_dram_dummy.vbom @@ -0,0 +1,5 @@ +# libs +../../../vlib/slvtypes.vhd +# components +# design +artys7_dram_dummy.vhd diff --git a/rtl/bplib/artys7/tb/artys7_dram_dummy.vhd b/rtl/bplib/artys7/tb/artys7_dram_dummy.vhd new file mode 100644 index 00000000..e8e1be97 --- /dev/null +++ b/rtl/bplib/artys7/tb/artys7_dram_dummy.vhd @@ -0,0 +1,89 @@ +-- $Id: artys7_dram_dummy.vhd 1105 2019-01-12 19:52:45Z mueller $ +-- +-- Copyright 2019- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: artys7_dram_dummy - syn +-- Description: artys7target (base; serport loopback, dram project) +-- +-- Dependencies: - +-- To test: tb_artys7_dram +-- Target Devices: generic +-- Tool versions: viv 2017.2; ghdl 0.35 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2019-01-12 1105 1.0 Initial version (cloned from artys7) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +entity artys7_dram_dummy is -- ARTY S7 dummy (base+dram) + -- implements artys7_dram_aif + port ( + I_CLK100 : in slbit; -- 100 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv4; -- artys7 switches + I_BTN : in slv4; -- artys7 buttons + O_LED : out slv4; -- artys7 leds + O_RGBLED0 : out slv3; -- artys7 rgb-led 0 + O_RGBLED1 : out slv3; -- artys7 rgb-led 1 + DDR3_DQ : inout slv16; -- dram: data in/out + DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p) + DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n) + DDR3_ADDR : out slv14; -- dram: address + DDR3_BA : out slv3; -- dram: bank address + DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low) + DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low) + DDR3_WE_N : out slbit; -- dram: write enable (act.low) + DDR3_RESET_N : out slbit; -- dram: reset (act.low) + DDR3_CK_P : out slv1; -- dram: clock (diff-p) + DDR3_CK_N : out slv1; -- dram: clock (diff-n) + DDR3_CKE : out slv1; -- dram: clock enable + DDR3_CS_N : out slv1; -- dram: chip select (act.low) + DDR3_DM : out slv2; -- dram: data input mask + DDR3_ODT : out slv1 -- dram: on-die termination + ); +end artys7_dram_dummy; + +architecture syn of artys7_dram_dummy is + +begin + + O_TXD <= I_RXD; -- loop back serport + + O_LED <= I_SWI; -- mirror SWI on LED + + O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED0 + O_RGBLED1 <= (others=>'0'); + + DDR3_DQ <= (others=>'Z'); + DDR3_DQS_P <= (others=>'Z'); + DDR3_DQS_N <= (others=>'Z'); + DDR3_ADDR <= (others=>'0'); + DDR3_BA <= (others=>'0'); + DDR3_RAS_N <= '1'; + DDR3_CAS_N <= '1'; + DDR3_WE_N <= '1'; + DDR3_RESET_N <= '1'; + DDR3_CK_P <= (others=>'0'); + DDR3_CK_N <= (others=>'1'); + DDR3_CKE <= (others=>'0'); + DDR3_CS_N <= (others=>'1'); + DDR3_DM <= (others=>'0'); + DDR3_ODT <= (others=>'0'); + +end syn; diff --git a/rtl/bplib/artys7/tb/tb_artys7.vhd b/rtl/bplib/artys7/tb/tb_artys7.vhd index 9048b670..6a81ba28 100644 --- a/rtl/bplib/artys7/tb/tb_artys7.vhd +++ b/rtl/bplib/artys7/tb/tb_artys7.vhd @@ -1,4 +1,4 @@ --- $Id: tb_artys7.vhd 1064 2018-11-03 09:24:13Z mueller $ +-- $Id: tb_artys7.vhd 1105 2019-01-12 19:52:45Z mueller $ -- -- Copyright 2018- by Walter F.J. Mueller -- @@ -75,8 +75,6 @@ architecture sim of tb_artys7 is signal O_LED : slv4 := (others=>'0'); signal O_RGBLED0 : slv3 := (others=>'0'); signal O_RGBLED1 : slv3 := (others=>'0'); - signal O_RGBLED2 : slv3 := (others=>'0'); - signal O_RGBLED3 : slv3 := (others=>'0'); signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff diff --git a/rtl/bplib/artys7/tb/tb_artys7_dram.vbom b/rtl/bplib/artys7/tb/tb_artys7_dram.vbom new file mode 100644 index 00000000..83f4b950 --- /dev/null +++ b/rtl/bplib/artys7/tb/tb_artys7_dram.vbom @@ -0,0 +1,24 @@ +# Not meant for direct top level usage. Used with +# tb_artys7_dram_(....)[_ssim].vbom and config +# lines to generate the different cases. +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/rlink/rlinklib.vbom +../../../vlib/xlib/xlib.vhd +../artys7lib.vhd +../../../vlib/simlib/simlib.vhd +../../../vlib/simlib/simbus.vhd +${sys_conf := sys_conf_sim.vhd} +# components +${gsr_pulse := ../../../vlib/xlib/gsr_pulse_dummy.vbom} +../../../vlib/simlib/simclk.vbom +../../../vlib/simlib/simclkcnt.vbom +../../../vlib/rlink/tbcore/tbcore_rlink.vbom +../../../vlib/xlib/sfs_gsim_core.vbom +tb_artys7_core.vbom +../../../vlib/serport/tb/serport_master_tb.vbom +${artys7_dram_aif := artys7_dram_dummy.vbom} -UUT +# design +tb_artys7_dram.vhd +@top:tb_artys7_dram diff --git a/rtl/bplib/artys7/tb/tb_artys7_dram.vhd b/rtl/bplib/artys7/tb/tb_artys7_dram.vhd new file mode 100644 index 00000000..55369390 --- /dev/null +++ b/rtl/bplib/artys7/tb/tb_artys7_dram.vhd @@ -0,0 +1,210 @@ +-- $Id: tb_artys7_dram.vhd 1105 2019-01-12 19:52:45Z mueller $ +-- +-- Copyright 2019- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 3, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_artys7_dram - sim +-- Description: Test bench for artys7 (base+dram) +-- +-- Dependencies: simlib/simclk +-- simlib/simclkcnt +-- rlink/tbcore/tbcore_rlink +-- xlib/sfs_gsim_core +-- tb_artys7_core +-- serport/tb/serport_master_tb +-- artys7_dram_aif [UUT] +-- +-- To test: generic, any artys7_dram_aif target +-- +-- Target Devices: generic +-- Tool versions: viv 2017.2; ghdl 0.35 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2019-01-12 1105 1.0 Initial version (derived from tb_artya7) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.rlinklib.all; +use work.xlib.all; +use work.artys7lib.all; +use work.simlib.all; +use work.simbus.all; +use work.sys_conf.all; + +entity tb_artys7_dram is +end tb_artys7_dram; + +architecture sim of tb_artys7_dram is + + signal CLKOSC : slbit := '0'; -- board clock (100 Mhz) + signal CLKCOM : slbit := '0'; -- communication clock + + signal CLKCOM_CYCLE : integer := 0; + + signal RESET : slbit := '0'; + signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !! + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXERR : slbit := '0'; + signal RXACT : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv4 := (others=>'0'); + signal I_BTN : slv4 := (others=>'0'); + signal O_LED : slv4 := (others=>'0'); + signal O_RGBLED0 : slv3 := (others=>'0'); + signal O_RGBLED1 : slv3 := (others=>'0'); + + signal IO_DDR3_DQ : slv16 := (others=>'Z'); + signal IO_DDR3_DQS_P : slv2 := (others=>'Z'); + signal IO_DDR3_DQS_N : slv2 := (others=>'Z'); + + signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff + + constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); + + constant clock_period : Delay_length := 10 ns; + constant clock_offset : Delay_length := 200 ns; + +begin + + GINIT : entity work.gsr_pulse; + + CLKGEN : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLKOSC + ); + + CLKGEN_COM : sfs_gsim_core + generic map ( + VCO_DIVIDE => sys_conf_clkser_vcodivide, + VCO_MULTIPLY => sys_conf_clkser_vcomultiply, + OUT_DIVIDE => sys_conf_clkser_outdivide) + port map ( + CLKIN => CLKOSC, + CLKFX => CLKCOM, + LOCKED => open + ); + + CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); + + TBCORE : entity work.tbcore_rlink + port map ( + CLK => CLKCOM, + RX_DATA => TXDATA, + RX_VAL => TXENA, + RX_HOLD => TXBUSY, + TX_DATA => RXDATA, + TX_ENA => RXVAL + ); + + ARTYS7CORE : entity work.tb_artys7_core + port map ( + I_SWI => I_SWI, + I_BTN => I_BTN + ); + + UUT : artys7_dram_aif + port map ( + I_CLK100 => CLKOSC, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_RGBLED0 => O_RGBLED0, + O_RGBLED1 => O_RGBLED1, + DDR3_DQ => IO_DDR3_DQ, + DDR3_DQS_P => IO_DDR3_DQS_P, + DDR3_DQS_N => IO_DDR3_DQS_N, + DDR3_ADDR => open, + DDR3_BA => open, + DDR3_RAS_N => open, + DDR3_CAS_N => open, + DDR3_WE_N => open, + DDR3_RESET_N => open, + DDR3_CK_P => open, + DDR3_CK_N => open, + DDR3_CKE => open, + DDR3_CS_N => open, + DDR3_DM => open, + DDR3_ODT => open + ); + + SERMSTR : entity work.serport_master_tb + generic map ( + CDWIDTH => CLKDIV'length) + port map ( + CLK => CLKCOM, + RESET => RESET, + CLKDIV => CLKDIV, + ENAXON => R_PORTSEL_XON, + ENAESC => '0', + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXOK => '1', + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + RXSD => O_TXD, + TXSD => I_RXD, + RXRTS_N => open, + TXCTS_N => '0' + ); + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLKCOM); + + if RXERR = '1' then + writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1"); + writeline(output, oline); + end if; + + end loop; + + end process proc_moni; + + -- + -- Notes on portsel and XON control: + -- - most artys7 designs will use hardwired XON=1 + -- - but some (especially basis tests) might not use flow control + -- - that's why XON flow control must be optional and configurable ! + -- + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_portsel then + R_PORTSEL_XON <= to_x01(SB_DATA(1)); + end if; + end if; + end process proc_simbus; + +end sim;