From 3f455d5236ce9323c7f606f839701a07aa16323b Mon Sep 17 00:00:00 2001 From: "Walter F.J. Mueller" Date: Sun, 20 Nov 2011 12:31:43 +0000 Subject: [PATCH] - interim release w11a_V0.532 (untagged) - re-organize modules 'human I/O' interface on Digilent boards - add test designs for 'human I/O' interface for atlys,nexys2, and s3board - small updates in crc8 and dcm areas - with one exception all vhdl sources use now numeric_std --- doc/INSTALL.txt | 2 +- doc/README.txt | 27 +- doc/w11a_os_guide.txt | 4 +- doc/w11a_tb_guide.txt | 22 +- rtl/bplib/atlys/atlys_pins.ucf | 61 +++++ rtl/bplib/atlys/atlys_pins_pma0_rs232.ucf | 23 ++ rtl/bplib/atlys/atlys_pins_pmod.ucf | 25 ++ rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd | 7 +- rtl/bplib/bpgen/bp_rs232_2line_iob.vhd | 3 +- rtl/bplib/bpgen/bp_rs232_4line_iob.vhd | 3 +- rtl/bplib/bpgen/bp_swibtnled.vhd | 3 +- rtl/bplib/bpgen/bpgenlib.vhd | 28 ++- rtl/bplib/bpgen/sn_4x7segctl.vhd | 23 +- rtl/bplib/bpgen/sn_humanio.vbom | 1 - rtl/bplib/bpgen/sn_humanio.vhd | 6 +- rtl/bplib/bpgen/sn_humanio_demu.vbom | 7 + rtl/bplib/bpgen/sn_humanio_demu.vhd | 195 +++++++++++++++ rtl/bplib/bpgen/sn_humanio_rbus.vhd | 11 +- rtl/bplib/issi/is61lv25616al.vhd | 21 +- rtl/bplib/micron/mt45w8mw16b.vhd | 21 +- rtl/bplib/nexys2/n2_cram_dummy.vhd | 3 +- rtl/bplib/nexys2/n2_cram_memctl_as.vhd | 23 +- rtl/bplib/nexys2/tb/tb_nexys2_core.vhd | 13 +- rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd | 13 +- rtl/bplib/s3board/s3_sram_dummy.vhd | 3 +- rtl/bplib/s3board/s3_sram_memctl.vhd | 11 +- rtl/bplib/s3board/s3boardlib.vhd | 3 +- rtl/bplib/s3board/tb/tb_s3board_core.vhd | 13 +- rtl/bplib/s3board/tb/tb_s3board_fusp.vhd | 13 +- rtl/ibus/ib_intmap.vhd | 75 +++--- rtl/ibus/ib_sel.vhd | 4 +- rtl/ibus/ibd_iist.vhd | 25 +- rtl/ibus/ibd_kw11l.vhd | 15 +- rtl/ibus/ibdlib.vhd | 19 +- rtl/ibus/ibdr_dl11.vhd | 15 +- rtl/ibus/ibdr_lp11.vhd | 13 +- rtl/ibus/ibdr_maxisys.vhd | 11 +- rtl/ibus/ibdr_minisys.vhd | 9 +- rtl/ibus/ibdr_pc11.vhd | 13 +- rtl/ibus/ibdr_rk11.vhd | 23 +- rtl/ibus/ibdr_sdreg.vhd | 13 +- rtl/ibus/iblib.vhd | 3 +- rtl/sys_gen/tst_rlink/nexys2/Makefile | 7 +- .../tst_rlink/nexys2/sys_tst_rlink_n2.mfset | 4 +- .../tst_rlink/nexys2/sys_tst_rlink_n2.vbom | 4 +- .../tst_rlink/nexys2/sys_tst_rlink_n2.vhd | 10 +- rtl/sys_gen/tst_rlink/tst_rlink.vhd | 11 +- rtl/sys_gen/tst_snhumanio/Makefile | 23 ++ rtl/sys_gen/tst_snhumanio/atlys/.cvsignore | 4 + rtl/sys_gen/tst_snhumanio/atlys/Makefile | 30 +++ rtl/sys_gen/tst_snhumanio/atlys/sys_conf.vhd | 35 +++ .../atlys/sys_tst_snhumanio_atlys.mfset | 29 +++ .../atlys/sys_tst_snhumanio_atlys.ucf_cpp | 16 ++ .../atlys/sys_tst_snhumanio_atlys.vbom | 12 + .../atlys/sys_tst_snhumanio_atlys.vhd | 130 ++++++++++ rtl/sys_gen/tst_snhumanio/nexys2/.cvsignore | 4 + rtl/sys_gen/tst_snhumanio/nexys2/Makefile | 27 ++ rtl/sys_gen/tst_snhumanio/nexys2/sys_conf.vhd | 35 +++ .../nexys2/sys_tst_snhumanio_n2.mfset | 34 +++ .../nexys2/sys_tst_snhumanio_n2.ucf_cpp | 15 ++ .../nexys2/sys_tst_snhumanio_n2.vbom | 14 ++ .../nexys2/sys_tst_snhumanio_n2.vhd | 159 ++++++++++++ rtl/sys_gen/tst_snhumanio/s3board/.cvsignore | 4 + rtl/sys_gen/tst_snhumanio/s3board/Makefile | 27 ++ .../tst_snhumanio/s3board/sys_conf.vhd | 35 +++ .../s3board/sys_tst_snhumanio_s3.mfset | 27 ++ .../s3board/sys_tst_snhumanio_s3.ucf_cpp | 15 ++ .../s3board/sys_tst_snhumanio_s3.vbom | 14 ++ .../s3board/sys_tst_snhumanio_s3.vhd | 148 +++++++++++ rtl/sys_gen/tst_snhumanio/tst_snhumanio.vbom | 6 + rtl/sys_gen/tst_snhumanio/tst_snhumanio.vhd | 234 ++++++++++++++++++ rtl/sys_gen/w11a/nexys2/sys_conf.vhd | 9 +- rtl/sys_gen/w11a/nexys2/sys_w11a_n2.mfset | 4 +- rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom | 4 +- rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd | 13 +- rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd | 8 +- rtl/vlib/comlib/byte2cdata.vhd | 11 +- rtl/vlib/comlib/cdata2byte.vhd | 11 +- rtl/vlib/comlib/comlib.vhd | 113 ++++----- rtl/vlib/comlib/crc8.vhd | 61 ++--- rtl/vlib/comlib/misc/gen_crc8_tbl.vhd | 17 +- rtl/vlib/comlib/misc/gen_crc8_tbl_check.vhd | 78 +++--- rtl/vlib/genlib/clkdivce.vhd | 23 +- rtl/vlib/genlib/debounce_gen.vhd | 15 +- rtl/vlib/genlib/genlib.vhd | 19 +- rtl/vlib/memlib/fifo_1c_dram.vhd | 3 +- rtl/vlib/memlib/fifo_1c_dram_raw.vhd | 23 +- rtl/vlib/memlib/memlib.vhd | 24 +- rtl/vlib/memlib/ram_1swar_1ar_gen.vhd | 19 +- rtl/vlib/memlib/ram_1swar_gen.vhd | 17 +- rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd | 17 +- rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd | 23 +- rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd | 23 +- rtl/vlib/rbus/rb_mon.vhd | 11 +- rtl/vlib/rbus/rbd_bram.vhd | 17 +- rtl/vlib/rbus/rbd_eyemon.vhd | 19 +- rtl/vlib/rbus/rbd_rbmon.vhd | 19 +- rtl/vlib/rbus/rbd_tester.vhd | 17 +- rtl/vlib/rbus/rbd_timer.vhd | 15 +- rtl/vlib/rbus/rbdlib.vhd | 30 ++- rtl/vlib/rlink/rlink_base.vhd | 9 +- rtl/vlib/rlink/rlink_base_serport.vhd | 9 +- rtl/vlib/rlink/rlink_core.vhd | 17 +- rtl/vlib/rlink/rlink_mon.vhd | 11 +- rtl/vlib/rlink/rlink_mon_sb.vhd | 4 +- rtl/vlib/rlink/rlink_rlb2rl.vhd | 3 +- rtl/vlib/rlink/rlink_serport.vhd | 15 +- rtl/vlib/rlink/rlinklib.vhd | 18 +- rtl/vlib/rlink/tb/tb_rlink.vhd | 17 +- rtl/vlib/rlink/tb/tbcore_rlink.vhd | 23 +- rtl/vlib/rlink/tb/tbcore_rlink_dcm.vhd | 27 +- rtl/vlib/rlink/tb/tbd_rlink_direct.vhd | 3 +- rtl/vlib/rlink/tb/tbd_rlink_serport.vhd | 13 +- rtl/vlib/rlink/tb/tbu_rlink_serport.vhd | 11 +- rtl/vlib/serport/serport.vhd | 134 ++++++++-- rtl/vlib/serport/serport_uart_autobaud.vhd | 19 +- rtl/vlib/serport/serport_uart_rx.vhd | 32 ++- rtl/vlib/serport/serport_uart_rxtx.vhd | 8 +- rtl/vlib/serport/serport_uart_rxtx_ab.vhd | 11 +- rtl/vlib/serport/serport_uart_tx.vhd | 15 +- rtl/vlib/serport/tb/tb_serport_autobaud.vhd | 11 +- rtl/vlib/serport/tb/tb_serport_uart_rx.vhd | 13 +- rtl/vlib/serport/tb/tb_serport_uart_rxtx.vhd | 13 +- rtl/vlib/serport/tb/tbd_serport_autobaud.vhd | 8 +- rtl/vlib/serport/tb/tbd_serport_uart_rx.vhd | 8 +- rtl/vlib/serport/tb/tbd_serport_uart_rxtx.vhd | 8 +- rtl/vlib/simlib/simclk.vhd | 11 +- rtl/vlib/simlib/simclkcnt.vhd | 13 +- rtl/vlib/simlib/simlib.vhd | 32 ++- ...dcm_sp_sfs_gsim.vbom => dcm_sfs_gsim.vbom} | 2 +- .../{dcm_sp_sfs_gsim.vhd => dcm_sfs_gsim.vhd} | 17 +- ...fs_unisim.vbom => dcm_sfs_unisim_s3e.vbom} | 2 +- ..._sfs_unisim.vhd => dcm_sfs_unisim_s3e.vhd} | 20 +- rtl/vlib/xlib/iob_reg_i_gen.vhd | 4 +- rtl/vlib/xlib/iob_reg_io_gen.vhd | 6 +- rtl/vlib/xlib/iob_reg_o_gen.vhd | 4 +- rtl/vlib/xlib/xlib.vhd | 10 +- rtl/w11a/pdp11.vhd | 13 +- rtl/w11a/pdp11_bram.vhd | 11 +- rtl/w11a/pdp11_cache.vhd | 11 +- rtl/w11a/pdp11_core.vhd | 9 +- rtl/w11a/pdp11_core_rbus.vhd | 17 +- rtl/w11a/pdp11_decode.vhd | 9 +- rtl/w11a/pdp11_dpath.vhd | 15 +- rtl/w11a/pdp11_gpr.vhd | 13 +- rtl/w11a/pdp11_irq.vhd | 17 +- rtl/w11a/pdp11_lunit.vhd | 9 +- rtl/w11a/pdp11_mem70.vhd | 29 +-- rtl/w11a/pdp11_mmu.vhd | 19 +- rtl/w11a/pdp11_mmu_sadr.vhd | 17 +- rtl/w11a/pdp11_mmu_ssr12.vhd | 23 +- rtl/w11a/pdp11_munit.vhd | 21 +- rtl/w11a/pdp11_ounit.vhd | 13 +- rtl/w11a/pdp11_psr.vhd | 13 +- rtl/w11a/pdp11_sequencer.vhd | 15 +- rtl/w11a/pdp11_sys70.vhd | 17 +- rtl/w11a/pdp11_tmu.vhd | 13 +- rtl/w11a/pdp11_ubmap.vhd | 14 +- rtl/w11a/pdp11_vmbox.vhd | 17 +- rtl/w11a/tb/tb_pdp11core.vhd | 13 +- rtl/w11a/tb/tbd_pdp11core.vhd | 9 +- tools/bin/pi_rri | 67 ++--- tools/bin/tbw | 19 +- tools/src/Makefile | 4 +- tools/src/librlink/RlinkCrc8.cpp | 69 +++--- tools/tcl/setup_packages | 2 + 166 files changed, 2672 insertions(+), 1029 deletions(-) create mode 100644 rtl/bplib/atlys/atlys_pins.ucf create mode 100644 rtl/bplib/atlys/atlys_pins_pma0_rs232.ucf create mode 100644 rtl/bplib/atlys/atlys_pins_pmod.ucf create mode 100644 rtl/bplib/bpgen/sn_humanio_demu.vbom create mode 100644 rtl/bplib/bpgen/sn_humanio_demu.vhd create mode 100644 rtl/sys_gen/tst_snhumanio/Makefile create mode 100644 rtl/sys_gen/tst_snhumanio/atlys/.cvsignore create mode 100644 rtl/sys_gen/tst_snhumanio/atlys/Makefile create mode 100644 rtl/sys_gen/tst_snhumanio/atlys/sys_conf.vhd create mode 100644 rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.mfset create mode 100644 rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.ucf_cpp create mode 100644 rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vbom create mode 100644 rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vhd create mode 100644 rtl/sys_gen/tst_snhumanio/nexys2/.cvsignore create mode 100644 rtl/sys_gen/tst_snhumanio/nexys2/Makefile create mode 100644 rtl/sys_gen/tst_snhumanio/nexys2/sys_conf.vhd create mode 100644 rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.mfset create mode 100644 rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.ucf_cpp create mode 100644 rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vbom create mode 100644 rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vhd create mode 100644 rtl/sys_gen/tst_snhumanio/s3board/.cvsignore create mode 100644 rtl/sys_gen/tst_snhumanio/s3board/Makefile create mode 100644 rtl/sys_gen/tst_snhumanio/s3board/sys_conf.vhd create mode 100644 rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.mfset create mode 100644 rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.ucf_cpp create mode 100644 rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.vbom create mode 100644 rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.vhd create mode 100644 rtl/sys_gen/tst_snhumanio/tst_snhumanio.vbom create mode 100644 rtl/sys_gen/tst_snhumanio/tst_snhumanio.vhd rename rtl/vlib/xlib/{dcm_sp_sfs_gsim.vbom => dcm_sfs_gsim.vbom} (61%) rename rtl/vlib/xlib/{dcm_sp_sfs_gsim.vhd => dcm_sfs_gsim.vhd} (87%) rename rtl/vlib/xlib/{dcm_sp_sfs_unisim.vbom => dcm_sfs_unisim_s3e.vbom} (65%) rename rtl/vlib/xlib/{dcm_sp_sfs_unisim.vhd => dcm_sfs_unisim_s3e.vhd} (81%) diff --git a/doc/INSTALL.txt b/doc/INSTALL.txt index e93775d2..3d6ce2e8 100644 --- a/doc/INSTALL.txt +++ b/doc/INSTALL.txt @@ -1,4 +1,4 @@ -# $Id: INSTALL.txt 408 2011-09-12 19:48:36Z mueller $ +# $Id: INSTALL.txt 409 2011-09-17 10:40:55Z mueller $ Guide to install and build w11a systems, test benches and support software diff --git a/doc/README.txt b/doc/README.txt index 13ebd36e..1311d539 100644 --- a/doc/README.txt +++ b/doc/README.txt @@ -1,4 +1,4 @@ -# $Id: README.txt 408 2011-09-12 19:48:36Z mueller $ +# $Id: README.txt 428 2011-11-20 12:19:31Z mueller $ Release notes for w11a @@ -60,7 +60,30 @@ Release notes for w11a 3. Change Log ---------------------------------------------------------------- -- trunk (2011-09-11: svn rev 12(oc) 408(wfjm); untagged w11a_V0.531) +++++++++ +- trunk (2011-11-20: svn rev 13(oc) 428(wfjm); untagged w11a_V0.532) +++++++++ + + - Summary + - generalized the 'human I/O' interface for s3board,nexys2/3 and atlys + - added test design for the 'human I/O' interface + - no functional change of w11a CPU core or any existing test systems + + - New features + - new modules + - rtl/sys_gen/tst_snhumanio + - sub-tree with test design for 'human I/O' interface modules + - atlys, nexys2, and s3board directories contain the systems + for the respectice Digilent boards + + - Changes + - functional changes + - use now 'a6' polynomial of Koopman et al for crc8 in rlink + - with one exception all vhdl sources use now numeric_std + - module renames: + vlib/xlib/dcm_sp_sfs_gsim -> vlib/xlib/dcm_sfs_gsim + vlib/xlib/dcm_sp_sfs_unisim -> vlib/xlib/dcm_sfs_unisim_s3e + vlib/xlib/tb/tb_dcm_sp_sfs -> vlib/xlib/tb/tb_dcm_sfs + +- trunk (2011-09-11: svn rev 12(oc) 409(wfjm); untagged w11a_V0.531) +++++++++ - Summary - Many small changes to prepare upcoming support for diff --git a/doc/w11a_os_guide.txt b/doc/w11a_os_guide.txt index f1e1269a..cd101128 100644 --- a/doc/w11a_os_guide.txt +++ b/doc/w11a_os_guide.txt @@ -1,4 +1,4 @@ -# $Id: w11a_os_guide.txt 317 2010-07-22 19:36:56Z mueller $ +# $Id: w11a_os_guide.txt 428 2011-11-20 12:19:31Z mueller $ Guide to run operating system images on w11a systems @@ -82,7 +82,7 @@ Guide to run operating system images on w11a systems 4. 2.11BSD system --------------------------------------------------------- - A disk set is available from - http://www-linux.gsi.de/~mueller/retro/oc_w11/data/211bsd_rkset.tgz + http://www-linux.gsi.de/~mueller/retro/oc_w11/data/211bsd_rkset.tgz Download, unpack and copy the disk images (*.dsk) to $RETROBASE/rtl/sys_gen/w11a/tb diff --git a/doc/w11a_tb_guide.txt b/doc/w11a_tb_guide.txt index 02b9b3e9..9146c687 100644 --- a/doc/w11a_tb_guide.txt +++ b/doc/w11a_tb_guide.txt @@ -1,4 +1,4 @@ -# $Id: w11a_tb_guide.txt 376 2011-04-17 12:24:07Z mueller $ +# $Id: w11a_tb_guide.txt 428 2011-11-20 12:19:31Z mueller $ Guide to running w11a test benches @@ -66,7 +66,7 @@ Guide to running w11a test benches time tbw tb_serport_uart_rx |\ tee tb_serport_uart_rx_dsim.log | egrep "(FAIL|DONE)" -> 1269955.0 ns 63488: DONE - -> real 0m1.178s user 0m1.172s sys 0m0.020s + -> real 0m01.178s user 0m01.172s sys 0m00.020s - serport receiver/transmitter test @@ -74,14 +74,14 @@ Guide to running w11a test benches time tbw tb_serport_uart_rxtx |\ tee tb_serport_uart_rxtx_dsim.log | egrep "(FAIL|DONE)" -> 52335.0 ns 2607: DONE - -> real 0m0.094s user 0m0.092s sys 0m0.008s + -> real 0m00.094s user 0m00.092s sys 0m00.008s - serport autobauder test make tb_serport_autobaud time tbw tb_serport_autobaud |\ tee tb_serport_autobaud_dsim.log | egrep "(FAIL|DONE)" -> 367475.0 ns 18364: DONE - -> real 0m0.610s user 0m0.612s sys 0m0.004s + -> real 0m00.610s user 0m00.612s sys 0m00.004s - rlink core test @@ -90,7 +90,7 @@ Guide to running w11a test benches time tbw tb_rlink_direct |\ tee tb_rlink_direct_dsim.log | egrep "(FAIL|DONE)" -> 142355.0 ns 7108: DONE - -> real 0m0.317s user 0m0.324s sys 0m0.028s + -> real 0m00.317s user 0m00.324s sys 0m00.028s - rlink core test via serial port interface @@ -98,12 +98,12 @@ Guide to running w11a test benches time tbw tb_rlink_serport tb_rlink_serport_stim.dat |\ tee tb_rlink_serport_stim2_dsim.log | egrep "(FAIL|DONE)" -> 72735.0 ns 3627: DONE - -> real 0m0.266s user 0m0.264s sys 0m0.008s + -> real 0m00.266s user 0m00.264s sys 0m00.008s time tbw tb_rlink_serport tb_rlink_stim.dat |\ tee tb_rlink_serport_dsim.log | egrep "(FAIL|DONE)" -> 536155.0 ns 26798: DONE - -> real 0m1.714s user 0m1.704s sys 0m0.044s + -> real 0m01.714s user 0m01.704s sys 0m00.044s - w11a core test (using behavioural model) @@ -112,7 +112,7 @@ Guide to running w11a test benches time tbw tb_pdp11core |\ tee tb_pdp11core_dsim.log | egrep "(FAIL|DONE)" -> 1220255.0 ns 61003: DONE - -> real 0m10.736s user 0m10.713s sys 0m0.060s + -> real 0m10.736s user 0m10.713s sys 0m00.060s - w11a core test (using post-synthesis model) @@ -120,7 +120,7 @@ Guide to running w11a test benches time tbw tb_pdp11core_ssim |\ tee tb_pdp11core_ssim.log | egrep "(FAIL|DONE)" -> 1220255.0 ns 61003: DONE - -> real 1m9.738s user 1m9.588s sys 0m0.096s + -> real 1m09.738s user 1m09.588s sys 0m00.096s 3. System tests benches --------------------------------------------------- @@ -177,7 +177,7 @@ Guide to running w11a test benches @../../../../w11a/tb/tb_pdp11core_stim.dat |\ tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)" -> 7757655.0 ns 387873: DONE - -> real 0m49.835s user 0m50.203s sys 0m0.696s + -> real 0m49.835s user 0m50.203s sys 0m00.696s - sys_w11a_n2 test bench @@ -188,4 +188,4 @@ Guide to running w11a test benches @../../../../w11a/tb/tb_pdp11core_stim.dat |\ tee tb_w11a_n2_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)" -> 6673237.2 ns 387035: DONE - -> real 0m56.173s user 0m56.612s sys 0m0.604s + -> real 0m56.173s user 0m56.612s sys 0m00.604s diff --git a/rtl/bplib/atlys/atlys_pins.ucf b/rtl/bplib/atlys/atlys_pins.ucf new file mode 100644 index 00000000..faa51e69 --- /dev/null +++ b/rtl/bplib/atlys/atlys_pins.ucf @@ -0,0 +1,61 @@ +## $Id: atlys_pins.ucf 414 2011-10-11 19:38:12Z mueller $ +## +## Pin locks for Atlys core functionality +## - USB UART +## - human I/O (switches, buttons, leds) +## +## Revision History: +## Date Rev Version Comment +## 2011-10-10 413 1.0.2 new BTN sequence: clockwise(U-R-D-L) - mid - reset +## 2011-08-05 403 1.0.1 Fix IOSTANDARD typos; rename _GPIO_ to _HIO_ +## 2011-08-04 402 1.0 Initial version +## +## Notes: +## - Bank 0+1 are 3V3; Bank 2 switchable 3V3 or 2V5; Bank 3 is 1V8 (DDR mem) +## - default is DRIVE=12 | SLEW=SLOW +## - pin names from Digilent master AtlysGeneralUCF.zip are given as comments +## +## clocks -------------------------------------------------------------------- +## AtlysGeneralUCF: clk +## +NET "I_CLK100" LOC = "l15" | IOSTANDARD=LVCMOS25; +## +## USB UART interface -------------------------------------------------------- +## AtlysGeneralUCF: UartRx, UartTx (crossed!) +## +NET "I_USB_RXD" LOC = "a16" | IOSTANDARD=LVCMOS33; +NET "O_USB_TXD" LOC = "b16" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW; +## +## SWIs ---------------------------------------------------------------------- +## AtlysGeneralUCF: sw<0:7> +## +NET "I_HIO_SWI<0>" LOC = "a10" | IOSTANDARD=LVCMOS33; +NET "I_HIO_SWI<1>" LOC = "d14" | IOSTANDARD=LVCMOS33; +NET "I_HIO_SWI<2>" LOC = "c14" | IOSTANDARD=LVCMOS33; +NET "I_HIO_SWI<3>" LOC = "p15" | IOSTANDARD=LVCMOS33; +NET "I_HIO_SWI<4>" LOC = "p12" | IOSTANDARD=LVCMOS33; +NET "I_HIO_SWI<5>" LOC = "r5" | IOSTANDARD=LVCMOS33; +NET "I_HIO_SWI<6>" LOC = "t5" | IOSTANDARD=LVCMOS33; +NET "I_HIO_SWI<7>" LOC = "e4" | IOSTANDARD=LVCMOS33; +## +## BTNs ---------------------------------------------------------------------- +## AtlysGeneralUCF: btn<0:5>; clockwise(U-R-D-L) - middle - reset +## +NET "I_HIO_BTN<0>" LOC = "n4" | IOSTANDARD=LVCMOS18; # BTNU +NET "I_HIO_BTN<1>" LOC = "f6" | IOSTANDARD=LVCMOS18; # BTNR +NET "I_HIO_BTN<2>" LOC = "p3" | IOSTANDARD=LVCMOS18; # BTND +NET "I_HIO_BTN<3>" LOC = "p4" | IOSTANDARD=LVCMOS18; # BTNL +NET "I_HIO_BTN<4>" LOC = "f5" | IOSTANDARD=LVCMOS18; # BTNC +NET "I_HIO_BTN<5>" LOC = "t15" | IOSTANDARD=LVCMOS18; # RESET (act.low!!) +## +## LEDs ---------------------------------------------------------------------- +## AtlysGeneralUCF: Led<0:7> +## +NET "O_HIO_LED<0>" LOC = "u18" | IOSTANDARD=LVCMOS33; +NET "O_HIO_LED<1>" LOC = "m14" | IOSTANDARD=LVCMOS33; +NET "O_HIO_LED<2>" LOC = "n14" | IOSTANDARD=LVCMOS33; +NET "O_HIO_LED<3>" LOC = "l14" | IOSTANDARD=LVCMOS33; +NET "O_HIO_LED<4>" LOC = "m13" | IOSTANDARD=LVCMOS33; +NET "O_HIO_LED<5>" LOC = "d4" | IOSTANDARD=LVCMOS33; +NET "O_HIO_LED<6>" LOC = "p16" | IOSTANDARD=LVCMOS33; +NET "O_HIO_LED<7>" LOC = "n12" | IOSTANDARD=LVCMOS33; diff --git a/rtl/bplib/atlys/atlys_pins_pma0_rs232.ucf b/rtl/bplib/atlys/atlys_pins_pma0_rs232.ucf new file mode 100644 index 00000000..46b1b68c --- /dev/null +++ b/rtl/bplib/atlys/atlys_pins_pma0_rs232.ucf @@ -0,0 +1,23 @@ +## $Id: atlys_pins_pma0_rs232.ucf 403 2011-08-06 17:36:22Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-08-06 403 1.0 Initial version +## +## Pmod connector A top / usage RS232 for FTDI USB serport ------------------- +## +## front view (towards PCB edge): +## +## P-6 P-1 +## | | +## +-------------------------+ +## | VCC GND TXD RXD CTS RTS | +## | VCC GND ... ... ... ... | +## ============================= +## < HDMI connector> +## +## +NET "O_FUSP_RTS_N" LOC = "t3" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW; +NET "I_FUSP_CTS_N" LOC = "r3" | IOSTANDARD=LVCMOS33 | PULLDOWN; +NET "I_FUSP_RXD" LOC = "p6" | IOSTANDARD=LVCMOS33 | PULLUP; +NET "O_FUSP_TXD" LOC = "n5" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW; diff --git a/rtl/bplib/atlys/atlys_pins_pmod.ucf b/rtl/bplib/atlys/atlys_pins_pmod.ucf new file mode 100644 index 00000000..9ce7494f --- /dev/null +++ b/rtl/bplib/atlys/atlys_pins_pmod.ucf @@ -0,0 +1,25 @@ +## $Id: atlys_pins_pmod.ucf 403 2011-08-06 17:36:22Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-08-06 403 1.0 Initial version +## +## Pmod connectors ----------------------------------------------------------- +## +## front view (towards PCB edge): +## +## +-------------------------+ +## | VCC GND P-4 P-3 P-2 P-1 | +## | VCC GND P10 P-9 P-8 P-7 | +## ============================= +## < HDMI connector> +## +## Pmod A (top: 0-3; bot: 4-7; all 8 shared with HDMI Type D connector...) +NET "IO_PMODA<0>" LOC = "t3" | IOSTANDARD=LVCMOS33; +NET "IO_PMODA<1>" LOC = "r3" | IOSTANDARD=LVCMOS33; +NET "IO_PMODA<2>" LOC = "p6" | IOSTANDARD=LVCMOS33; +NET "IO_PMODA<3>" LOC = "n5" | IOSTANDARD=LVCMOS33; +NET "IO_PMODA<4>" LOC = "v9" | IOSTANDARD=LVCMOS33; +NET "IO_PMODA<5>" LOC = "t9" | IOSTANDARD=LVCMOS33; +NET "IO_PMODA<6>" LOC = "v4" | IOSTANDARD=LVCMOS33; +NET "IO_PMODA<7>" LOC = "t4" | IOSTANDARD=LVCMOS33; diff --git a/rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd b/rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd index f2a716fd..9abf25ec 100644 --- a/rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd +++ b/rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd @@ -1,4 +1,4 @@ --- $Id: bp_rs232_2l4l_iob.vhd 406 2011-08-14 21:06:44Z mueller $ +-- $Id: bp_rs232_2l4l_iob.vhd 426 2011-11-18 18:14:08Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -36,7 +36,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; use work.slvtypes.all; use work.bpgenlib.all; @@ -123,7 +122,7 @@ begin DORELAY : if RELAY generate proc_regs_pipe: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then RR_RXD0 <= '1'; RR_TXD0 <= '1'; @@ -155,7 +154,7 @@ begin proc_regs_mux: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then R_RXD <= '1'; R_CTS_N <= '0'; diff --git a/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd b/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd index fd45bff1..e50ce691 100644 --- a/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd +++ b/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd @@ -1,4 +1,4 @@ --- $Id: bp_rs232_2line_iob.vhd 387 2011-07-03 17:24:52Z mueller $ +-- $Id: bp_rs232_2line_iob.vhd 426 2011-11-18 18:14:08Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -32,7 +32,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; use work.slvtypes.all; use work.xlib.all; diff --git a/rtl/bplib/bpgen/bp_rs232_4line_iob.vhd b/rtl/bplib/bpgen/bp_rs232_4line_iob.vhd index f1a7ca34..9570c0fe 100644 --- a/rtl/bplib/bpgen/bp_rs232_4line_iob.vhd +++ b/rtl/bplib/bpgen/bp_rs232_4line_iob.vhd @@ -1,4 +1,4 @@ --- $Id: bp_rs232_4line_iob.vhd 391 2011-07-09 17:25:02Z mueller $ +-- $Id: bp_rs232_4line_iob.vhd 426 2011-11-18 18:14:08Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -32,7 +32,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; use work.slvtypes.all; use work.xlib.all; diff --git a/rtl/bplib/bpgen/bp_swibtnled.vhd b/rtl/bplib/bpgen/bp_swibtnled.vhd index 17bc7f40..b5d6e3d8 100644 --- a/rtl/bplib/bpgen/bp_swibtnled.vhd +++ b/rtl/bplib/bpgen/bp_swibtnled.vhd @@ -1,4 +1,4 @@ --- $Id: bp_swibtnled.vhd 403 2011-08-06 17:36:22Z mueller $ +-- $Id: bp_swibtnled.vhd 410 2011-09-18 11:23:09Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -32,7 +32,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; use work.slvtypes.all; use work.xlib.all; diff --git a/rtl/bplib/bpgen/bpgenlib.vhd b/rtl/bplib/bpgen/bpgenlib.vhd index d1099d28..412db1cc 100644 --- a/rtl/bplib/bpgen/bpgenlib.vhd +++ b/rtl/bplib/bpgen/bpgenlib.vhd @@ -1,4 +1,4 @@ --- $Id: bpgenlib.vhd 404 2011-08-07 22:00:25Z mueller $ +-- $Id: bpgenlib.vhd 426 2011-11-18 18:14:08Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller -- @@ -19,6 +19,8 @@ -- Tool versions: 12.1; ghdl 0.26-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-16 426 1.0.6 now numeric_std clean +-- 2011-10-10 413 1.0.5 add sn_humanio_demu -- 2011-08-07 404 1.0.4 add RELAY generic for bp_rs232_2l4l_iob -- 2011-08-06 403 1.0.3 add RESET port for bp_rs232_2l4l_iob -- 2011-07-09 391 1.0.2 move in bp_rs232_2l4l_iob from s3boardlib @@ -28,7 +30,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.rblib.all; @@ -104,7 +106,7 @@ component bp_swibtnled_rbus is -- swi,btn,led handling /w rbus icept BWIDTH : positive := 4; -- BTN port width LWIDTH : positive := 4; -- LED port width DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN - RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8)); + RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8))); port ( CLK : in slbit; -- clock RESET : in slbit := '0'; -- reset @@ -153,11 +155,29 @@ component sn_humanio is -- human i/o handling: swi,btn,led,dsp ); end component; +component sn_humanio_demu is -- human i/o handling: swi,btn,led only + generic ( + DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_MSEC : in slbit; -- 1 ms clock enable + SWI : out slv8; -- switch settings, debounced + BTN : out slv4; -- button settings, debounced + LED : in slv8; -- led data + DSP_DAT : in slv16; -- display data + DSP_DP : in slv4; -- display decimal points + I_SWI : in slv8; -- pad-i: switches + I_BTN : in slv6; -- pad-i: buttons + O_LED : out slv8 -- pad-o: leds + ); +end component; + component sn_humanio_rbus is -- human i/o handling /w rbus intercept generic ( BWIDTH : positive := 4; -- BTN port width DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN - RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8)); + RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8))); port ( CLK : in slbit; -- clock RESET : in slbit := '0'; -- reset diff --git a/rtl/bplib/bpgen/sn_4x7segctl.vhd b/rtl/bplib/bpgen/sn_4x7segctl.vhd index d085af59..9acdd23d 100644 --- a/rtl/bplib/bpgen/sn_4x7segctl.vhd +++ b/rtl/bplib/bpgen/sn_4x7segctl.vhd @@ -1,4 +1,4 @@ --- $Id: sn_4x7segctl.vhd 400 2011-07-31 09:02:16Z mueller $ +-- $Id: sn_4x7segctl.vhd 410 2011-09-18 11:23:09Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -18,9 +18,10 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-09-17 410 1.2.1 now numeric_std clean -- 2011-07-30 400 1.2 digit dark in last quarter (not 16 clocks) -- 2011-07-08 390 1.1.2 renamed from s3_dispdrv -- 2010-04-17 278 1.1.1 renamed from dispdrv @@ -32,7 +33,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; @@ -51,12 +52,12 @@ end sn_4x7segctl; architecture syn of sn_4x7segctl is type regs_type is record - cdiv : std_logic_vector(CDWIDTH-1 downto 0); -- clock divider counter - dcnt : slv2; -- digit counter + cdiv : slv(CDWIDTH-1 downto 0); -- clock divider counter + dcnt : slv2; -- digit counter end record regs_type; constant regs_init : regs_type := ( - conv_std_logic_vector(0,CDWIDTH), + slv(to_unsigned(0,CDWIDTH)), (others=>'0') ); @@ -93,7 +94,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then R_REGS <= N_REGS; end if; @@ -113,9 +114,9 @@ begin r := R_REGS; n := R_REGS; - n.cdiv := unsigned(r.cdiv) - 1; + n.cdiv := slv(unsigned(r.cdiv) - 1); if unsigned(r.cdiv) = 0 then - n.dcnt := unsigned(r.dcnt) + 1; + n.dcnt := slv(unsigned(r.dcnt) + 1); end if; chex := "0000"; @@ -142,13 +143,13 @@ begin cano := "1111"; if r.cdiv(CDWIDTH-1 downto CDWIDTH-2) /= "00" then - cano(conv_integer(unsigned(r.dcnt))) := '0'; + cano(to_integer(unsigned(r.dcnt))) := '0'; end if; N_REGS <= n; ANO_N <= cano; - SEG_N <= not (cdp & hex2segtbl(conv_integer(unsigned(chex)))); + SEG_N <= not (cdp & hex2segtbl(to_integer(unsigned(chex)))); end process proc_next; diff --git a/rtl/bplib/bpgen/sn_humanio.vbom b/rtl/bplib/bpgen/sn_humanio.vbom index 4ff2ba88..56f4fda6 100644 --- a/rtl/bplib/bpgen/sn_humanio.vbom +++ b/rtl/bplib/bpgen/sn_humanio.vbom @@ -2,7 +2,6 @@ ../../vlib/slvtypes.vhd ../../vlib/xlib/xlib.vhd bpgenlib.vbom -## sys_conf : sys_conf.vhd # components ../../vlib/xlib/iob_reg_o_gen.vbom bp_swibtnled.vbom diff --git a/rtl/bplib/bpgen/sn_humanio.vhd b/rtl/bplib/bpgen/sn_humanio.vhd index ce163f18..b67651e6 100644 --- a/rtl/bplib/bpgen/sn_humanio.vhd +++ b/rtl/bplib/bpgen/sn_humanio.vhd @@ -1,4 +1,4 @@ --- $Id: sn_humanio.vhd 403 2011-08-06 17:36:22Z mueller $ +-- $Id: sn_humanio.vhd 410 2011-09-18 11:23:09Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -22,10 +22,11 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 11.4; ghdl 0.26 +-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-09-17 409 13.1 O40d xc3s1000-4 49 86 0 53 s 5.3 ns -- 2011-07-02 387 12.1 M53d xc3s1000-4 48 87 0 53 s 5.1 ns -- 2010-04-10 275 11.4 L68 xc3s1000-4 48 87 0 53 s 5.2 ns -- @@ -42,7 +43,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; use work.slvtypes.all; use work.xlib.all; diff --git a/rtl/bplib/bpgen/sn_humanio_demu.vbom b/rtl/bplib/bpgen/sn_humanio_demu.vbom new file mode 100644 index 00000000..cc277950 --- /dev/null +++ b/rtl/bplib/bpgen/sn_humanio_demu.vbom @@ -0,0 +1,7 @@ +# libs +../../vlib/slvtypes.vhd +bpgenlib.vbom +# components +bp_swibtnled.vbom +# design +sn_humanio_demu.vhd diff --git a/rtl/bplib/bpgen/sn_humanio_demu.vhd b/rtl/bplib/bpgen/sn_humanio_demu.vhd new file mode 100644 index 00000000..0efe8a4b --- /dev/null +++ b/rtl/bplib/bpgen/sn_humanio_demu.vhd @@ -0,0 +1,195 @@ +-- $Id: sn_humanio_demu.vhd 414 2011-10-11 19:38:12Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sn_humanio_demu - syn +-- Description: All BTN, SWI, LED handling for atlys +-- +-- Dependencies: bpgen/bp_swibtnled +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-10-10 413 13.1 O40d xc3s1000-4 67 66 0 55 s 6.1 ns +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-10-11 414 1.0.1 take care of RESET BTN being active low +-- 2011-10-10 413 1.0 Initial version +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.bpgenlib.all; + +-- ---------------------------------------------------------------------------- + +entity sn_humanio_demu is -- human i/o handling: swi,btn,led only + generic ( + DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_MSEC : in slbit; -- 1 ms clock enable + SWI : out slv8; -- switch settings, debounced + BTN : out slv4; -- button settings, debounced + LED : in slv8; -- led data + DSP_DAT : in slv16; -- display data + DSP_DP : in slv4; -- display decimal points + I_SWI : in slv8; -- pad-i: switches + I_BTN : in slv6; -- pad-i: buttons + O_LED : out slv8 -- pad-o: leds + ); +end sn_humanio_demu; + +architecture syn of sn_humanio_demu is + + constant c_mode_led : slv2 := "00"; + constant c_mode_dp : slv2 := "01"; + constant c_mode_datl : slv2 := "10"; + constant c_mode_dath : slv2 := "11"; + + type regs_type is record + mode : slv2; -- current mode + cnt : slv9; -- msec counter + up_1 : slbit; -- btn up last cycle + dn_1 : slbit; -- btn dn last cycle + led : slv8; -- led state + end record regs_type; + + constant regs_init : regs_type := ( + c_mode_led, -- mode + (others=>'0'), -- cnt + '0','0', -- up_1, dn_1 + (others=>'0') -- led + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + signal BTN_HW : slv6 := (others=>'0'); + signal LED_HW : slv8 := (others=>'0'); + +begin + + HIO : bp_swibtnled + generic map ( + SWIDTH => 8, + BWIDTH => 6, + LWIDTH => 8, + DEBOUNCE => DEBOUNCE) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN_HW, + LED => LED_HW, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED + ); + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, CE_MSEC, LED, DSP_DAT, DSP_DP, BTN_HW) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable ibtn : slv4 := (others=>'0'); + variable iup : slbit := '0'; + variable idn : slbit := '0'; + variable ipuls : slbit := '0'; + + begin + r := R_REGS; + n := R_REGS; + + ibtn(0) := not BTN_HW(5); -- RESET button is act. low ! + ibtn(1) := BTN_HW(1); + ibtn(2) := BTN_HW(4); + ibtn(3) := BTN_HW(3); + iup := BTN_HW(0); + idn := BTN_HW(2); + + ipuls := '0'; + + + n.up_1 := iup; + n.dn_1 := idn; + + if iup='0' and idn='0' then + n.cnt := (others=>'0'); + else + if CE_MSEC = '1' then + n.cnt := slv(unsigned(r.cnt) + 1); + if r.cnt = "111111111" then + ipuls := '1'; + end if; + end if; + end if; + + if iup='1' or idn='1' then + n.led := (others=>'0'); + case r.mode is + when c_mode_led => n.led(0) := '1'; + when c_mode_dp => n.led(1) := '1'; + when c_mode_datl => n.led(2) := '1'; + when c_mode_dath => n.led(3) := '1'; + when others => null; + end case; + + if iup='1' and (r.up_1='0' or ipuls='1') then + n.mode := slv(unsigned(r.mode) + 1); + elsif idn='1' and (r.dn_1='0' or ipuls='1') then + n.mode := slv(unsigned(r.mode) - 1); + end if; + + else + case r.mode is + when c_mode_led => n.led := LED; + when c_mode_dp => n.led := "0000" & DSP_DP; + when c_mode_datl => n.led := DSP_DAT( 7 downto 0); + when c_mode_dath => n.led := DSP_DAT(15 downto 8); + when others => null; + end case; + end if; + + N_REGS <= n; + + BTN <= ibtn; + LED_HW <= r.led; + + end process proc_next; + +end syn; diff --git a/rtl/bplib/bpgen/sn_humanio_rbus.vhd b/rtl/bplib/bpgen/sn_humanio_rbus.vhd index a371789f..7c48e4e3 100644 --- a/rtl/bplib/bpgen/sn_humanio_rbus.vhd +++ b/rtl/bplib/bpgen/sn_humanio_rbus.vhd @@ -1,4 +1,4 @@ --- $Id: sn_humanio_rbus.vhd 406 2011-08-14 21:06:44Z mueller $ +-- $Id: sn_humanio_rbus.vhd 427 2011-11-19 21:04:11Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29 +-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -31,6 +31,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.2.1 now numeric_std clean -- 2011-08-14 406 1.2 common register layout with bp_swibtnled_rbus -- 2011-08-07 404 1.3 add pipeline regs ledin,(swi,btn,led,dp,dat)eff -- 2011-07-08 390 1.2 renamed from s3_humanio_rbus, add BWIDTH generic @@ -65,7 +66,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.rblib.all; @@ -77,7 +78,7 @@ entity sn_humanio_rbus is -- human i/o handling /w rbus intercept generic ( BWIDTH : positive := 4; -- BTN port width DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN - RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8)); + RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8))); port ( CLK : in slbit; -- clock RESET : in slbit := '0'; -- reset @@ -183,7 +184,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then R_REGS <= regs_init; else diff --git a/rtl/bplib/issi/is61lv25616al.vhd b/rtl/bplib/issi/is61lv25616al.vhd index 6e2410a4..c56f4778 100644 --- a/rtl/bplib/issi/is61lv25616al.vhd +++ b/rtl/bplib/issi/is61lv25616al.vhd @@ -1,6 +1,6 @@ --- $Id: is61lv25616al.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: is61lv25616al.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2007-2008 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -21,9 +21,10 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.0.2 now numeric_std clean -- 2008-05-12 145 1.0.1 BUGFIX: Output now 'Z' if byte enables deasserted -- 2007-12-14 101 1.0 Initial version (written on warsaw airport) ------------------------------------------------------------------------------ @@ -42,7 +43,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; @@ -108,7 +109,7 @@ end sim; library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; @@ -152,14 +153,14 @@ begin variable ram : ram_type := (others=>datzero); begin - if WE_EFF'event and WE_EFF='0' then -- end of write cycle - -- note: to_x01 used below to prevent - -- that 'z' a written into mem. - ram(conv_integer(unsigned(ADDR))) := to_x01(DATA); + if falling_edge(WE_EFF) then -- end of write cycle + -- note: to_x01 used below to prevent + -- that 'z' a written into mem. + ram(to_integer(unsigned(ADDR))) := to_x01(DATA); end if; if CE='1' and OE='1' and BE='1' and WE='0' then -- output driver - DATA <= ram(conv_integer(unsigned(ADDR))); + DATA <= ram(to_integer(unsigned(ADDR))); else DATA <= (others=>'Z'); end if; diff --git a/rtl/bplib/micron/mt45w8mw16b.vhd b/rtl/bplib/micron/mt45w8mw16b.vhd index 3d86fa8a..1b1467e8 100644 --- a/rtl/bplib/micron/mt45w8mw16b.vhd +++ b/rtl/bplib/micron/mt45w8mw16b.vhd @@ -1,6 +1,6 @@ --- $Id: mt45w8mw16b.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: mt45w8mw16b.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -23,9 +23,10 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 11.4; ghdl 0.26 +-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.3.2 now numeric_std clean -- 2010-06-03 299 1.3.1 improved timing model (WE cycle, robust T_apa) -- 2010-06-03 298 1.3 add timing model again -- 2010-05-28 295 1.2 drop timing (was incorrect), pure functional now @@ -56,7 +57,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; @@ -170,7 +171,7 @@ begin end if; addr_last := L_ADDR; end if; - if OE'event and OE='1' then + if rising_edge(OE) then DOUT_VAL_OE <= '0', '1' after T_oe; end if; end process proc_dout_val; @@ -203,14 +204,14 @@ begin -- end of write cycle -- note: to_x01 used below to prevent that 'z' a written into mem. - if WE_L_EFF'event and WE_L_EFF='0' then - ram(conv_integer(unsigned(L_ADDR)))(f_byte0) := to_x01(DATA(f_byte0)); + if falling_edge(WE_L_EFF) then + ram(to_integer(unsigned(L_ADDR)))(f_byte0) := to_x01(DATA(f_byte0)); end if; - if WE_U_EFF'event and WE_U_EFF='0' then - ram(conv_integer(unsigned(L_ADDR)))(f_byte1) := to_x01(DATA(f_byte1)); + if falling_edge(WE_U_EFF) then + ram(to_integer(unsigned(L_ADDR)))(f_byte1) := to_x01(DATA(f_byte1)); end if; - DOUT <= ram(conv_integer(unsigned(L_ADDR))); + DOUT <= ram(to_integer(unsigned(L_ADDR))); end process proc_cram; diff --git a/rtl/bplib/nexys2/n2_cram_dummy.vhd b/rtl/bplib/nexys2/n2_cram_dummy.vhd index 140c7211..abcefae0 100644 --- a/rtl/bplib/nexys2/n2_cram_dummy.vhd +++ b/rtl/bplib/nexys2/n2_cram_dummy.vhd @@ -1,4 +1,4 @@ --- $Id: n2_cram_dummy.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: n2_cram_dummy.vhd 426 2011-11-18 18:14:08Z mueller $ -- -- Copyright 2010- by Walter F.J. Mueller -- @@ -27,7 +27,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; use work.slvtypes.all; diff --git a/rtl/bplib/nexys2/n2_cram_memctl_as.vhd b/rtl/bplib/nexys2/n2_cram_memctl_as.vhd index 0a8c0bcd..064247c1 100644 --- a/rtl/bplib/nexys2/n2_cram_memctl_as.vhd +++ b/rtl/bplib/nexys2/n2_cram_memctl_as.vhd @@ -1,6 +1,6 @@ --- $Id: n2_cram_memctl_as.vhd 340 2010-11-27 13:00:57Z mueller $ +-- $Id: n2_cram_memctl_as.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -21,7 +21,7 @@ -- Test bench: tb/tb_n2_cram_memctl -- fw_gen/tst_sram/nexys2/tb/tb_tst_sram_n2 -- Target Devices: generic --- Tool versions: xst 11.4; ghdl 0.26 +-- Tool versions: xst 11.4, 13.1; ghdl 0.26 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -31,6 +31,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.0.5 now numeric_std clean -- 2010-11-22 339 1.0.4 cntdly now 3 bit; add assert for DELAY generics -- 2010-06-03 299 1.0.3 add "KEEP" for data iob; MEM_OE='1' on first read -- cycle; @@ -111,7 +112,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.xlib.all; @@ -304,7 +305,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then R_REGS <= regs_init; else @@ -391,7 +392,7 @@ begin idata_oe := '0'; if unsigned(r.cntdly) /= 0 then - n.cntdly := unsigned(r.cntdly) - 1; + n.cntdly := slv(unsigned(r.cntdly) - 1); end if; case r.state is @@ -406,7 +407,7 @@ begin iactr := '1'; -- signal mem read imem_ce := '1'; -- ce CRAM next cycle imem_oe := '1'; -- oe CRAM next cycle - n.cntdly:= conv_std_logic_vector(READ0DELAY-1, n.cntdly'length); + n.cntdly:= slv(to_unsigned(READ0DELAY-1, n.cntdly'length)); n.state := s_rdwait0; -- next: wait when s_rdwait0 => -- s_rdwait0: read wait low word @@ -426,7 +427,7 @@ begin idata_cei := '1'; -- latch input data iaddr0_ce := '1'; -- latch address 0 bit iaddr0 := '1'; -- now go for high word - n.cntdly:= conv_std_logic_vector(READ1DELAY-1, n.cntdly'length); + n.cntdly:= slv(to_unsigned(READ1DELAY-1, n.cntdly'length)); n.state := s_rdwait1; -- next: wait high word when s_rdwait1 => -- s_rdwait1: read wait high word @@ -461,7 +462,7 @@ begin idata_oe := '1'; -- oe FPGA next cycle imem_ce := '1'; -- ce CRAM next cycle imem_we := '1'; -- we CRAM in half cycle - n.cntdly:= conv_std_logic_vector(WRITEDELAY-1, n.cntdly'length); + n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length)); n.state := s_wrwait0; -- next: wait when s_wrwait0 => -- s_rdput0: write wait 1st word @@ -504,7 +505,7 @@ begin idata_oe := '1'; -- oe FPGA next cycle imem_ce := '1'; -- ce CRAM next cycle imem_we := '1'; -- we CRAM in half cycle - n.cntdly:= conv_std_logic_vector(WRITEDELAY-1, n.cntdly'length); + n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length)); n.state := s_wrwait1; -- next: wait when s_wrwait1 => -- s_wrwait1: write wait 2nd word @@ -540,7 +541,7 @@ begin if unsigned(r.cntce) >= 127 then -- if max ce count expired n.fidle := '1'; -- set forced idle flag else -- if max ce count not yet reached - n.cntce := unsigned(r.cntce) + 1; -- increment counter + n.cntce := slv(unsigned(r.cntce) + 1); -- increment counter end if; end if; diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_core.vhd b/rtl/bplib/nexys2/tb/tb_nexys2_core.vhd index c9219594..b77d07de 100644 --- a/rtl/bplib/nexys2/tb/tb_nexys2_core.vhd +++ b/rtl/bplib/nexys2/tb/tb_nexys2_core.vhd @@ -1,6 +1,6 @@ --- $Id: tb_nexys2_core.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: tb_nexys2_core.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,15 +20,16 @@ -- To test: generic, any nexys2 target -- -- Target Devices: generic --- Tool versions: xst 11.4; ghdl 0.26 +-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.0.1 now numeric_std clean -- 2010-05-23 294 1.0 Initial version (derived from tb_s3board_core) ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; @@ -59,8 +60,8 @@ architecture sim of tb_nexys2_core is signal R_SWI : slv8 := (others=>'0'); signal R_BTN : slv4 := (others=>'0'); - constant sbaddr_swi: slv8 := conv_std_logic_vector( 16,8); - constant sbaddr_btn: slv8 := conv_std_logic_vector( 17,8); + constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8)); + constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8)); begin diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd b/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd index 5a65023e..a876e080 100644 --- a/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd +++ b/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd @@ -1,6 +1,6 @@ --- $Id: tb_nexys2_fusp.vhd 351 2010-12-30 21:50:54Z mueller $ +-- $Id: tb_nexys2_fusp.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -23,10 +23,11 @@ -- To test: generic, any nexys2_fusp_aif target -- -- Target Devices: generic --- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29 +-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 3.0.1 now numeric_std clean -- 2010-12-29 351 3.0 use rlink/tb now -- 2010-11-13 338 1.0.2 now dcm aware: add O_CLKSYS, use rritb_core_dcm -- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50 @@ -35,7 +36,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; @@ -100,7 +101,7 @@ architecture sim of tb_nexys2_fusp is signal R_PORTSEL : slbit := '0'; - constant sbaddr_portsel: slv8 := conv_std_logic_vector( 8,8); + constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); constant clockosc_period : time := 20 ns; constant clockosc_offset : time := 200 ns; @@ -215,7 +216,7 @@ begin begin loop - wait until CLKSYS'event and CLKSYS='1'; + wait until rising_edge(CLKSYS); wait for c2out_time; if RXERR = '1' then diff --git a/rtl/bplib/s3board/s3_sram_dummy.vhd b/rtl/bplib/s3board/s3_sram_dummy.vhd index 3389e2ab..0323d887 100644 --- a/rtl/bplib/s3board/s3_sram_dummy.vhd +++ b/rtl/bplib/s3board/s3_sram_dummy.vhd @@ -1,4 +1,4 @@ --- $Id: s3_sram_dummy.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: s3_sram_dummy.vhd 426 2011-11-18 18:14:08Z mueller $ -- -- Copyright 2007-2010 by Walter F.J. Mueller -- @@ -28,7 +28,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; use work.slvtypes.all; diff --git a/rtl/bplib/s3board/s3_sram_memctl.vhd b/rtl/bplib/s3board/s3_sram_memctl.vhd index 4e3208d7..f7d60ce2 100644 --- a/rtl/bplib/s3board/s3_sram_memctl.vhd +++ b/rtl/bplib/s3board/s3_sram_memctl.vhd @@ -1,6 +1,6 @@ --- $Id: s3_sram_memctl.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: s3_sram_memctl.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -21,7 +21,7 @@ -- Test bench: tb/tb_s3_sram_memctl -- fw_gen/tst_sram/s3board/tb/tb_tst_sram_s3 -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -30,6 +30,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.0.6 now numeric_std clean -- 2010-06-03 299 1.0.5 add "KEEP" for data iob; -- 2010-05-16 291 1.0.4 rename memctl_s3sram -> s3_sram_memctl -- 2008-02-17 117 1.0.3 use req,we rather req_r,req_w interface @@ -76,7 +77,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.xlib.all; @@ -213,7 +214,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then R_REGS <= regs_init; else diff --git a/rtl/bplib/s3board/s3boardlib.vhd b/rtl/bplib/s3board/s3boardlib.vhd index 084faa64..b92dbe39 100644 --- a/rtl/bplib/s3board/s3boardlib.vhd +++ b/rtl/bplib/s3board/s3boardlib.vhd @@ -1,4 +1,4 @@ --- $Id: s3boardlib.vhd 391 2011-07-09 17:25:02Z mueller $ +-- $Id: s3boardlib.vhd 426 2011-11-18 18:14:08Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -41,7 +41,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; use work.slvtypes.all; diff --git a/rtl/bplib/s3board/tb/tb_s3board_core.vhd b/rtl/bplib/s3board/tb/tb_s3board_core.vhd index e1f7480c..3644f442 100644 --- a/rtl/bplib/s3board/tb/tb_s3board_core.vhd +++ b/rtl/bplib/s3board/tb/tb_s3board_core.vhd @@ -1,6 +1,6 @@ --- $Id: tb_s3board_core.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: tb_s3board_core.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,16 +20,17 @@ -- To test: generic, any s3board target -- -- Target Devices: generic --- Tool versions: xst 11.4; ghdl 0.26 +-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.0.2 now numeric_std clean -- 2010-05-02 287 1.0.1 add sbaddr_(swi|btn) defs, now sbus addr 16,17 -- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board) ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; @@ -55,8 +56,8 @@ architecture sim of tb_s3board_core is signal R_SWI : slv8 := (others=>'0'); signal R_BTN : slv4 := (others=>'0'); - constant sbaddr_swi: slv8 := conv_std_logic_vector( 16,8); - constant sbaddr_btn: slv8 := conv_std_logic_vector( 17,8); + constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8)); + constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8)); begin diff --git a/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd b/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd index 1cb907ab..48f10648 100644 --- a/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd +++ b/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd @@ -1,6 +1,6 @@ --- $Id: tb_s3board_fusp.vhd 351 2010-12-30 21:50:54Z mueller $ +-- $Id: tb_s3board_fusp.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -23,9 +23,10 @@ -- To test: generic, any s3board_fusp_aif target -- -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 3.0.1 now numeric_std clean -- 2010-12-30 351 3.0 use rlink/tb now -- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50 -- 2010-05-21 292 1.0.3 rename _PM1_ -> _FUSP_ @@ -36,7 +37,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; @@ -95,7 +96,7 @@ architecture sim of tb_s3board_fusp is signal R_PORTSEL : slbit := '0'; - constant sbaddr_portsel: slv8 := conv_std_logic_vector( 8,8); + constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); constant clock_period : time := 20 ns; constant clock_offset : time := 200 ns; @@ -198,7 +199,7 @@ begin begin loop - wait until CLK'event and CLK='1'; + wait until rising_edge(CLK); wait for c2out_time; if RXERR = '1' then diff --git a/rtl/ibus/ib_intmap.vhd b/rtl/ibus/ib_intmap.vhd index f3b2b697..b9d0c16e 100644 --- a/rtl/ibus/ib_intmap.vhd +++ b/rtl/ibus/ib_intmap.vhd @@ -1,6 +1,6 @@ --- $Id: ib_intmap.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: ib_intmap.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2006-2008 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,9 +18,10 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.2.2 now numeric_std clean -- 2008-08-22 161 1.2.1 renamed pdp11_ -> ib_; use iblib -- 2008-01-20 112 1.2 add INTMAP generic to externalize config -- 2008-01-06 111 1.1 add EI_ACK output lines, remove EI_LINE @@ -31,7 +32,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; @@ -58,41 +59,41 @@ architecture syn of ib_intmap is type intv_type is array (15 downto 0) of slv9; constant conf_intp : intp_type := - (conv_std_logic_vector(INTMAP(15).pri,3), -- line 15 - conv_std_logic_vector(INTMAP(14).pri,3), -- line 14 - conv_std_logic_vector(INTMAP(13).pri,3), -- line 13 - conv_std_logic_vector(INTMAP(12).pri,3), -- line 12 - conv_std_logic_vector(INTMAP(11).pri,3), -- line 11 - conv_std_logic_vector(INTMAP(10).pri,3), -- line 10 - conv_std_logic_vector(INTMAP( 9).pri,3), -- line 9 - conv_std_logic_vector(INTMAP( 8).pri,3), -- line 8 - conv_std_logic_vector(INTMAP( 7).pri,3), -- line 7 - conv_std_logic_vector(INTMAP( 6).pri,3), -- line 6 - conv_std_logic_vector(INTMAP( 5).pri,3), -- line 5 - conv_std_logic_vector(INTMAP( 4).pri,3), -- line 4 - conv_std_logic_vector(INTMAP( 3).pri,3), -- line 3 - conv_std_logic_vector(INTMAP( 2).pri,3), -- line 2 - conv_std_logic_vector(INTMAP( 1).pri,3), -- line 1 - conv_std_logic_vector( 0,3) -- line 0 (always 0 !!) + (slv(to_unsigned(INTMAP(15).pri,3)), -- line 15 + slv(to_unsigned(INTMAP(14).pri,3)), -- line 14 + slv(to_unsigned(INTMAP(13).pri,3)), -- line 13 + slv(to_unsigned(INTMAP(12).pri,3)), -- line 12 + slv(to_unsigned(INTMAP(11).pri,3)), -- line 11 + slv(to_unsigned(INTMAP(10).pri,3)), -- line 10 + slv(to_unsigned(INTMAP( 9).pri,3)), -- line 9 + slv(to_unsigned(INTMAP( 8).pri,3)), -- line 8 + slv(to_unsigned(INTMAP( 7).pri,3)), -- line 7 + slv(to_unsigned(INTMAP( 6).pri,3)), -- line 6 + slv(to_unsigned(INTMAP( 5).pri,3)), -- line 5 + slv(to_unsigned(INTMAP( 4).pri,3)), -- line 4 + slv(to_unsigned(INTMAP( 3).pri,3)), -- line 3 + slv(to_unsigned(INTMAP( 2).pri,3)), -- line 2 + slv(to_unsigned(INTMAP( 1).pri,3)), -- line 1 + slv(to_unsigned( 0,3)) -- line 0 (always 0 !!) ); constant conf_intv : intv_type := - (conv_std_logic_vector(INTMAP(15).vec,9), -- line 15 - conv_std_logic_vector(INTMAP(14).vec,9), -- line 14 - conv_std_logic_vector(INTMAP(13).vec,9), -- line 13 - conv_std_logic_vector(INTMAP(12).vec,9), -- line 12 - conv_std_logic_vector(INTMAP(11).vec,9), -- line 11 - conv_std_logic_vector(INTMAP(10).vec,9), -- line 10 - conv_std_logic_vector(INTMAP( 9).vec,9), -- line 9 - conv_std_logic_vector(INTMAP( 8).vec,9), -- line 8 - conv_std_logic_vector(INTMAP( 7).vec,9), -- line 7 - conv_std_logic_vector(INTMAP( 6).vec,9), -- line 6 - conv_std_logic_vector(INTMAP( 5).vec,9), -- line 5 - conv_std_logic_vector(INTMAP( 4).vec,9), -- line 4 - conv_std_logic_vector(INTMAP( 3).vec,9), -- line 3 - conv_std_logic_vector(INTMAP( 2).vec,9), -- line 2 - conv_std_logic_vector(INTMAP( 1).vec,9), -- line 1 - conv_std_logic_vector( 0,9) -- line 0 (always 0 !!) + (slv(to_unsigned(INTMAP(15).vec,9)), -- line 15 + slv(to_unsigned(INTMAP(14).vec,9)), -- line 14 + slv(to_unsigned(INTMAP(13).vec,9)), -- line 13 + slv(to_unsigned(INTMAP(12).vec,9)), -- line 12 + slv(to_unsigned(INTMAP(11).vec,9)), -- line 11 + slv(to_unsigned(INTMAP(10).vec,9)), -- line 10 + slv(to_unsigned(INTMAP( 9).vec,9)), -- line 9 + slv(to_unsigned(INTMAP( 8).vec,9)), -- line 8 + slv(to_unsigned(INTMAP( 7).vec,9)), -- line 7 + slv(to_unsigned(INTMAP( 6).vec,9)), -- line 6 + slv(to_unsigned(INTMAP( 5).vec,9)), -- line 5 + slv(to_unsigned(INTMAP( 4).vec,9)), -- line 4 + slv(to_unsigned(INTMAP( 3).vec,9)), -- line 3 + slv(to_unsigned(INTMAP( 2).vec,9)), -- line 2 + slv(to_unsigned(INTMAP( 1).vec,9)), -- line 1 + slv(to_unsigned( 0,9)) -- line 0 (always 0 !!) ); -- attribute PRIORITY_EXTRACT : string; @@ -122,7 +123,7 @@ begin variable iei_ack : slv16 := (others=>'0'); begin - iline := conv_integer(unsigned(EI_LINE)); + iline := to_integer(unsigned(EI_LINE)); iei_ack := (others=>'0'); if EI_ACKM = '1' then diff --git a/rtl/ibus/ib_sel.vhd b/rtl/ibus/ib_sel.vhd index 4f331835..a5baabff 100644 --- a/rtl/ibus/ib_sel.vhd +++ b/rtl/ibus/ib_sel.vhd @@ -1,4 +1,4 @@ --- $Id: ib_sel.vhd 335 2010-10-24 22:24:23Z mueller $ +-- $Id: ib_sel.vhd 427 2011-11-19 21:04:11Z mueller $ -- -- Copyright 2010- by Walter F.J. Mueller -- @@ -54,7 +54,7 @@ begin proc_regs: process (CLK) variable isel : slbit := '0'; begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then isel := '0'; if IB_MREQ.aval='1' and IB_MREQ.addr(12 downto SAWIDTH+1)=IB_ADDR(12 downto SAWIDTH+1) then diff --git a/rtl/ibus/ibd_iist.vhd b/rtl/ibus/ibd_iist.vhd index 0454570f..4c8ff781 100644 --- a/rtl/ibus/ibd_iist.vhd +++ b/rtl/ibus/ibd_iist.vhd @@ -1,6 +1,6 @@ --- $Id: ibd_iist.vhd 350 2010-12-28 16:40:11Z mueller $ +-- $Id: ibd_iist.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2009-2010 by Walter F.J. Mueller +-- Copyright 2009-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -29,6 +29,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 0.8.1 now numeric_std clean -- 2010-10-17 333 0.8 use ibus V2 interface -- 2009-06-07 224 0.7 send inverted stc_stp; remove pgc_err; honor msk_im -- also for dcf_dcf and exc_rte; add iist_mreq and @@ -40,7 +41,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; @@ -69,7 +70,7 @@ end ibd_iist; architecture syn of ibd_iist is - constant ibaddr_iist : slv16 := conv_std_logic_vector(8#177500#,16); + constant ibaddr_iist : slv16 := slv(to_unsigned(8#177500#,16)); constant tdlysnd : natural := 150; -- send delay timer @@ -223,7 +224,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if BRESET = '1' or -- BRESET is 1 for system and ibus reset R_REGS.req_clear='1' then R_REGS <= regs_init; -- @@ -280,14 +281,14 @@ begin tcnt256_end := '0'; if CE_USEC='1' and r.stc_enb='1'then -- if st enabled on every usec - n.tcnt256 := unsigned(r.tcnt256) + 1; -- advance 8 bit counter + n.tcnt256 := slv(unsigned(r.tcnt256) + 1); -- advance 8 bit counter if unsigned(r.tcnt256) = 255 then -- if wrap tcnt256_end := '1'; -- signal 256 usec passed end if; end if; tcntsnd_end := '0'; - n.tcntsnd := unsigned(r.tcntsnd) + 1; -- advance send timer counter + n.tcntsnd := slv(unsigned(r.tcntsnd) + 1); -- advance send timer counter if unsigned(r.tcntsnd) = tdlysnd-1 then -- if delay time reached tcntsnd_end := '1'; -- signal end end if; @@ -559,7 +560,7 @@ begin if unsigned(r.acr_ac) <= unsigned(ac_exc) then -- if ac 0,..,10 if IB_MREQ.rmw = '0' then -- if not 1st part of rmw - n.acr_ac := unsigned(r.acr_ac) + 1; -- autoincrement + n.acr_ac := slv(unsigned(r.acr_ac) + 1); -- autoincrement end if; end if; @@ -570,7 +571,7 @@ begin -- sanity timer if tcnt256_end = '1' then -- if 256 usec expired (and enabled) - n.stc_count := unsigned(r.stc_count) - 1; + n.stc_count := slv(unsigned(r.stc_count) - 1); if unsigned(r.stc_count) = 0 then -- if sanity timer expired n.stc_tmo := '1'; -- set timeout flag n.req_stsnd := '1'; -- request st transmit @@ -598,8 +599,8 @@ begin eff_bus(i).bmask(2) xor eff_bus(i).bmask(3) xor not eff_bus(i).par; - act_ibit := eff_bus(i).imask(conv_integer(unsigned(eff_id))); - act_bbit := eff_bus(i).bmask(conv_integer(unsigned(eff_id))); + act_ibit := eff_bus(i).imask(to_integer(unsigned(eff_id))); + act_bbit := eff_bus(i).bmask(to_integer(unsigned(eff_id))); n.dcf_brk(i) := eff_bus(i).dcf; -- trace dcf state in brk diff --git a/rtl/ibus/ibd_kw11l.vhd b/rtl/ibus/ibd_kw11l.vhd index ffbaae64..e663752f 100644 --- a/rtl/ibus/ibd_kw11l.vhd +++ b/rtl/ibus/ibd_kw11l.vhd @@ -1,6 +1,6 @@ --- $Id: ibd_kw11l.vhd 350 2010-12-28 16:40:11Z mueller $ +-- $Id: ibd_kw11l.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2008-2010 by Walter F.J. Mueller +-- Copyright 2008-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -27,6 +27,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.1.1 now numeric_std clean -- 2010-10-17 333 1.1 use ibus V2 interface -- 2009-06-01 221 1.0.5 BUGFIX: add RESET; don't clear tcnt on ibus reset -- 2008-08-22 161 1.0.4 use iblib; add EI_ACK to proc_next sens. list @@ -38,7 +39,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; @@ -60,7 +61,7 @@ end ibd_kw11l; architecture syn of ibd_kw11l is - constant ibaddr_kw11l : slv16 := conv_std_logic_vector(8#177546#,16); + constant ibaddr_kw11l : slv16 := slv(to_unsigned(8#177546#,16)); constant lks_ibf_ie : integer := 6; constant lks_ibf_moni : integer := 7; @@ -91,7 +92,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if BRESET = '1' then -- BRESET is 1 for system and ibus reset R_REGS <= regs_init; if RESET = '0' then -- if RESET=0 we do just an ibus reset @@ -142,7 +143,7 @@ begin -- other state changes if CE_MSEC = '1' then - n.tcnt := unsigned(r.tcnt) + 1; + n.tcnt := slv(unsigned(r.tcnt) + 1); if unsigned(r.tcnt) = tdivide-1 then n.tcnt := (others=>'0'); n.moni := '1'; diff --git a/rtl/ibus/ibdlib.vhd b/rtl/ibus/ibdlib.vhd index 2c614daa..9126ee73 100644 --- a/rtl/ibus/ibdlib.vhd +++ b/rtl/ibus/ibdlib.vhd @@ -1,6 +1,6 @@ --- $Id: ibdlib.vhd 335 2010-10-24 22:24:23Z mueller $ +-- $Id: ibdlib.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2008-2010 by Walter F.J. Mueller +-- Copyright 2008-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Definitions for ibus devices -- -- Dependencies: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.1.2 now numeric_std clean -- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM; -- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ -- 2009-07-12 233 1.0.5 add RESET, CE_USEC to _dl11, CE_USEC to _minisys @@ -31,7 +32,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; @@ -67,6 +68,12 @@ end record iist_sres_type; constant iist_sres_init : iist_sres_type := ('0','0'); +-- ise 13.1 xst can bug check if generic defaults in a package are defined via +-- 'slv(to_unsigned())'. The conv_ construct prior to numeric_std was ok. +-- As workaround the ibus default addresses are defined here as constant. +constant ibaddr_dz11 : slv16 := slv(to_unsigned(8#160100#,16)); +constant ibaddr_dl11 : slv16 := slv(to_unsigned(8#177560#,16)); + component ibd_iist is -- ibus dev(loc): IIST -- fixed address: 177500 generic ( @@ -158,7 +165,7 @@ end component; component ibdr_dz11 is -- ibus dev(rem): DZ11 generic ( - IB_ADDR : slv16 := conv_std_logic_vector(8#160100#,16)); + IB_ADDR : slv16 := ibaddr_dz11); port ( CLK : in slbit; -- clock RESET : in slbit; -- system reset @@ -175,7 +182,7 @@ end component; component ibdr_dl11 is -- ibus dev(rem): DL11-A/B generic ( - IB_ADDR : slv16 := conv_std_logic_vector(8#177560#,16)); + IB_ADDR : slv16 := ibaddr_dl11); port ( CLK : in slbit; -- clock CE_USEC : in slbit; -- usec pulse diff --git a/rtl/ibus/ibdr_dl11.vhd b/rtl/ibus/ibdr_dl11.vhd index bb4a07ee..77b96eec 100644 --- a/rtl/ibus/ibdr_dl11.vhd +++ b/rtl/ibus/ibdr_dl11.vhd @@ -1,6 +1,6 @@ --- $Id: ibdr_dl11.vhd 350 2010-12-28 16:40:11Z mueller $ +-- $Id: ibdr_dl11.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2008-2010 by Walter F.J. Mueller +-- Copyright 2008-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -28,6 +28,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.2.2 now numeric_std clean -- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM; -- 2010-10-17 333 1.2 use ibus V2 interface -- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ @@ -44,7 +45,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; @@ -52,7 +53,7 @@ use work.iblib.all; -- ---------------------------------------------------------------------------- entity ibdr_dl11 is -- ibus dev(rem): DL11-A/B generic ( - IB_ADDR : slv16 := conv_std_logic_vector(8#177560#,16)); + IB_ADDR : slv16 := slv(to_unsigned(8#177560#,16))); port ( CLK : in slbit; -- clock CE_USEC : in slbit; -- usec pulse @@ -123,7 +124,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if BRESET = '1' then R_REGS <= regs_init; if RESET = '0' then -- if RESET=0 we do just an ibus reset @@ -311,7 +312,7 @@ begin n.rdlybsy := '1'; -- set busy end if; elsif CE_USEC = '1' then -- if end-of-usec - n.rdlycnt := unsigned(r.rdlycnt) - 1; -- decrement + n.rdlycnt := slv(unsigned(r.rdlycnt) - 1); -- decrement if r.rdlybsy='1' and -- if delay busy unsigned(r.rdlycnt) = 0 then -- and counter at zero n.rdlybsy := '0'; -- clear busy diff --git a/rtl/ibus/ibdr_lp11.vhd b/rtl/ibus/ibdr_lp11.vhd index 7aadfbd8..5393d52f 100644 --- a/rtl/ibus/ibdr_lp11.vhd +++ b/rtl/ibus/ibdr_lp11.vhd @@ -1,6 +1,6 @@ --- $Id: ibdr_lp11.vhd 350 2010-12-28 16:40:11Z mueller $ +-- $Id: ibdr_lp11.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2009-2010 by Walter F.J. Mueller +-- Copyright 2009-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -27,6 +27,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.2.2 now numeric_std clean -- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM; -- 2010-10-17 333 1.2 use ibus V2 interface -- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ @@ -42,7 +43,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; @@ -64,7 +65,7 @@ end ibdr_lp11; architecture syn of ibdr_lp11 is - constant ibaddr_lp11 : slv16 := conv_std_logic_vector(8#177514#,16); + constant ibaddr_lp11 : slv16 := slv(to_unsigned(8#177514#,16)); constant ibaddr_csr : slv1 := "0"; -- csr address offset constant ibaddr_buf : slv1 := "1"; -- buf address offset @@ -99,7 +100,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if BRESET = '1' then -- BRESET is 1 for system and ibus reset R_REGS <= regs_init; if RESET = '0' then -- if RESET=0 we do just an ibus reset diff --git a/rtl/ibus/ibdr_maxisys.vhd b/rtl/ibus/ibdr_maxisys.vhd index 846d3c4f..c33da1cf 100644 --- a/rtl/ibus/ibdr_maxisys.vhd +++ b/rtl/ibus/ibdr_maxisys.vhd @@ -1,6 +1,6 @@ --- $Id: ibdr_maxisys.vhd 350 2010-12-28 16:40:11Z mueller $ +-- $Id: ibdr_maxisys.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2009-2010 by Walter F.J. Mueller +-- Copyright 2009-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -27,7 +27,7 @@ -- ib_intmap -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -36,6 +36,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.1.2 now numeric_std clean -- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM; -- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ -- 2009-07-12 233 1.0.4 reorder ports; add RESET, CE_USEC to _dl11 @@ -72,7 +73,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; @@ -265,7 +266,7 @@ begin begin I0 : ibdr_dl11 generic map ( - IB_ADDR => conv_std_logic_vector(8#176500#,16)) + IB_ADDR => slv(to_unsigned(8#176500#,16))) port map ( CLK => CLK, CE_USEC => CE_USEC, diff --git a/rtl/ibus/ibdr_minisys.vhd b/rtl/ibus/ibdr_minisys.vhd index 43169ccb..1c8a2570 100644 --- a/rtl/ibus/ibdr_minisys.vhd +++ b/rtl/ibus/ibdr_minisys.vhd @@ -1,6 +1,6 @@ --- $Id: ibdr_minisys.vhd 350 2010-12-28 16:40:11Z mueller $ +-- $Id: ibdr_minisys.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2008-2010 by Walter F.J. Mueller +-- Copyright 2008-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -23,7 +23,7 @@ -- ib_intmap -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -32,6 +32,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.1.2 now numeric_std clean -- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM; -- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ -- 2009-07-12 233 1.0.7 reorder ports, add CE_USEC; add RESET and CE_USEC @@ -58,7 +59,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; diff --git a/rtl/ibus/ibdr_pc11.vhd b/rtl/ibus/ibdr_pc11.vhd index 0d6ad75a..228c8a4a 100644 --- a/rtl/ibus/ibdr_pc11.vhd +++ b/rtl/ibus/ibdr_pc11.vhd @@ -1,6 +1,6 @@ --- $Id: ibdr_pc11.vhd 350 2010-12-28 16:40:11Z mueller $ +-- $Id: ibdr_pc11.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2009-2010 by Walter F.J. Mueller +-- Copyright 2009-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: xxdp: zpcae0 -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -27,6 +27,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.2.2 now numeric_std clean -- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM; -- 2010-10-17 333 1.2 use ibus V2 interface -- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ @@ -37,7 +38,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; @@ -61,7 +62,7 @@ end ibdr_pc11; architecture syn of ibdr_pc11 is - constant ibaddr_pc11 : slv16 := conv_std_logic_vector(8#177550#,16); + constant ibaddr_pc11 : slv16 := slv(to_unsigned(8#177550#,16)); constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset @@ -116,7 +117,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if BRESET = '1' then -- BRESET is 1 for system and ibus reset R_REGS <= regs_init; -- if RESET = '0' then -- if RESET=0 we do just an ibus reset diff --git a/rtl/ibus/ibdr_rk11.vhd b/rtl/ibus/ibdr_rk11.vhd index 4b147a4e..97a06287 100644 --- a/rtl/ibus/ibdr_rk11.vhd +++ b/rtl/ibus/ibdr_rk11.vhd @@ -1,6 +1,6 @@ --- $Id: ibdr_rk11.vhd 350 2010-12-28 16:40:11Z mueller $ +-- $Id: ibdr_rk11.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2008-2010 by Walter F.J. Mueller +-- Copyright 2008-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,7 +18,7 @@ -- Dependencies: ram_1swar_gen -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -28,6 +28,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.2.2 now numeric_std clean -- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM; -- 2010-10-17 333 1.2 use ibus V2 interface -- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ @@ -48,7 +49,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.memlib.all; @@ -71,7 +72,7 @@ end ibdr_rk11; architecture syn of ibdr_rk11 is - constant ibaddr_rk11 : slv16 := conv_std_logic_vector(8#177400#,16); + constant ibaddr_rk11 : slv16 := slv(to_unsigned(8#177400#,16)); constant ibaddr_rkds : slv3 := "000"; -- rkds address offset constant ibaddr_rker : slv3 := "001"; -- rker address offset @@ -190,7 +191,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if BRESET='1' or R_REGS.creset='1' then R_REGS <= regs_init; if R_REGS.creset = '1' then @@ -262,7 +263,7 @@ begin when s_init => ibhold := r.ibsel; -- hold ibus when controller busy icrip := '1'; - n.icnt := unsigned(r.icnt) + 1; + n.icnt := slv(unsigned(r.icnt) + 1); if unsigned(r.icnt) = 7 then n.state := s_idle; end if; @@ -296,7 +297,7 @@ begin idout(rkds_ibf_sc) := r.sc; end if; - if r.sbusy(conv_integer(unsigned(imem_addr(2 downto 0))))='1' then + if r.sbusy(to_integer(unsigned(imem_addr(2 downto 0))))='1' then idout(rkds_ibf_adry) := '0'; -- clear drive access rdy end if; @@ -359,7 +360,7 @@ begin if unsigned(IB_MREQ.din(rkcs_ibf_func))=4 or -- if seek unsigned(IB_MREQ.din(rkcs_ibf_func))=6 then -- or drive reset - n.sbusy(conv_integer(unsigned(r.drsel))) := '1'; -- set busy + n.sbusy(to_integer(unsigned(r.drsel))) := '1'; -- set busy end if; end if; @@ -441,7 +442,7 @@ begin elsif iscval = '1' then -- was a seek done n.scp := '1'; -- signal seek complete interrupt n.id := iscid; -- load id - n.sireq(conv_integer(unsigned(iscid))) := '0'; -- reset sireq bit + n.sireq(to_integer(unsigned(iscid))) := '0'; -- reset sireq bit end if; end if; @@ -456,7 +457,7 @@ begin if unsigned(r.sc) = 8#13# then -- sector counter (count to 8#13#) n.sc := (others=>'0'); else - n.sc := unsigned(r.sc) + 1; + n.sc := slv(unsigned(r.sc) + 1); end if; end if; diff --git a/rtl/ibus/ibdr_sdreg.vhd b/rtl/ibus/ibdr_sdreg.vhd index 92d8eb7c..f4b1c677 100644 --- a/rtl/ibus/ibdr_sdreg.vhd +++ b/rtl/ibus/ibdr_sdreg.vhd @@ -1,6 +1,6 @@ --- $Id: ibdr_sdreg.vhd 350 2010-12-28 16:40:11Z mueller $ +-- $Id: ibdr_sdreg.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,7 +18,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -27,6 +27,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.2.1 now numeric_std clean -- 2010-10-17 333 1.2 use ibus V2 interface -- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ -- 2008-08-22 161 1.0.4 use iblib @@ -40,7 +41,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; @@ -59,7 +60,7 @@ end ibdr_sdreg; architecture syn of ibdr_sdreg is - constant ibaddr_sdreg : slv16 := conv_std_logic_vector(8#177570#,16); + constant ibaddr_sdreg : slv16 := slv(to_unsigned(8#177570#,16)); type regs_type is record -- state registers ibsel : slbit; -- ibus select @@ -80,7 +81,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then R_REGS <= regs_init; else diff --git a/rtl/ibus/iblib.vhd b/rtl/ibus/iblib.vhd index 5aedde2d..0176c9c4 100644 --- a/rtl/ibus/iblib.vhd +++ b/rtl/ibus/iblib.vhd @@ -1,4 +1,4 @@ --- $Id: iblib.vhd 346 2010-12-22 22:59:26Z mueller $ +-- $Id: iblib.vhd 427 2011-11-19 21:04:11Z mueller $ -- -- Copyright 2008-2010 by Walter F.J. Mueller -- @@ -28,7 +28,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; use work.slvtypes.all; diff --git a/rtl/sys_gen/tst_rlink/nexys2/Makefile b/rtl/sys_gen/tst_rlink/nexys2/Makefile index 3a55ee26..ef83b6f7 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/Makefile +++ b/rtl/sys_gen/tst_rlink/nexys2/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 405 2011-08-14 08:16:28Z mueller $ +# $Id: Makefile 410 2011-09-18 11:23:09Z mueller $ # # Revision History: # Date Rev Version Comment @@ -18,11 +18,6 @@ all : $(BIT_all) clean : ise_clean rm -f sys_tst_rlink_n2.ucf # -sys_tst_rlink_n2.mcs : sys_tst_rlink_n2.bit - promgen -w -x xcf04s -p mcs -u 0 sys_tst_rlink_n2 - mv sys_tst_rlink_n2.prm sys_tst_rlink_n2_prm.log - mv sys_tst_rlink_n2.cfi sys_tst_rlink_n2_cfi.log -# #---- # include $(RETROBASE)/rtl/make/generic_xflow.mk diff --git a/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.mfset b/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.mfset index aa3ece0b..87efa7ab 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.mfset +++ b/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.mfset @@ -1,4 +1,4 @@ -# $Id: sys_tst_rlink_n2.mfset 406 2011-08-14 21:06:44Z mueller $ +# $Id: sys_tst_rlink_n2.mfset 427 2011-11-19 21:04:11Z mueller $ # # ---------------------------------------------------------------------------- [xst] @@ -9,7 +9,7 @@ Node of sequential type is unconnected Node of sequential type is unconnected Node of sequential type is unconnected -Unconnected output port 'LOCKED' of component 'dcm_sp_sfs' +Unconnected output port 'LOCKED' of component 'dcm_sfs' Unconnected output port 'OFIFO_SIZE' of component 'rlink_base' Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen' diff --git a/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom b/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom index 2c69524d..8592b15c 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom +++ b/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vbom @@ -8,8 +8,8 @@ ../../../bplib/nexys2/nexys2lib.vhd sys_conf : sys_conf.vhd # components -[xst,isim]../../../vlib/xlib/dcm_sp_sfs_unisim.vbom -[ghdl]../../../vlib/xlib/dcm_sp_sfs_gsim.vbom +[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom ../../../bplib/bpgen/sn_humanio_rbus.vbom diff --git a/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd b/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd index 56b6306f..d2e4e21b 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd +++ b/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_rlink_n2.vhd 406 2011-08-14 21:06:44Z mueller $ +-- $Id: sys_tst_rlink_n2.vhd 427 2011-11-19 21:04:11Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -15,7 +15,7 @@ -- Module Name: sys_tst_rlink_n2 - syn -- Description: rlink tester design for nexys2 -- --- Dependencies: vlib/xlib/dcm_sp_sfs +-- Dependencies: vlib/xlib/dcm_sfs -- vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_2l4l_iob -- bplib/bpgen/sn_humanio_rbus @@ -25,7 +25,7 @@ -- Test bench: tb/tb_tst_rlink_n2 -- -- Target Devices: generic --- Tool versions: xst 12.1; ghdl 0.29 +-- Tool versions: xst 12.1, 13.1; ghdl 0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -35,6 +35,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-17 426 1.1.3 use dcm_sfs now -- 2011-07-09 391 1.1.2 use now bp_rs232_2l4l_iob -- 2011-07-08 390 1.1.1 use now sn_humanio -- 2011-06-26 385 1.1 move s3_humanio_rbus from tst_rlink to top level @@ -60,7 +61,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; use work.slvtypes.all; use work.xlib.all; @@ -137,7 +137,7 @@ begin RESET <= '0'; -- so far not used - DCM : dcm_sp_sfs + DCM : dcm_sfs generic map ( CLKFX_DIVIDE => sys_conf_clkfx_divide, CLKFX_MULTIPLY => sys_conf_clkfx_multiply, diff --git a/rtl/sys_gen/tst_rlink/tst_rlink.vhd b/rtl/sys_gen/tst_rlink/tst_rlink.vhd index 54e807ed..dddfc5f5 100644 --- a/rtl/sys_gen/tst_rlink/tst_rlink.vhd +++ b/rtl/sys_gen/tst_rlink/tst_rlink.vhd @@ -1,4 +1,4 @@ --- $Id: tst_rlink.vhd 385 2011-06-26 22:10:57Z mueller $ +-- $Id: tst_rlink.vhd 427 2011-11-19 21:04:11Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -26,10 +26,11 @@ -- Test bench: nexys2/tb/tb_tst_rlink_n2 -- -- Target Devices: generic --- Tool versions: xst 12.1; ghdl 0.29 +-- Tool versions: xst 12.1, 13.1; ghdl 0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.1.1 now numeric_std clean -- 2011-06-26 385 1.1 remove s3_humanio_rbus (will be in board design); -- remove hio interface ports, add rbus ports -- 2011-04-02 375 1.0.1 add rbd_eyemon and two timer @@ -42,7 +43,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.rblib.all; @@ -113,7 +114,7 @@ begin OFAWIDTH => 0, ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, - RB_ADDR => conv_std_logic_vector(2#11111110#,8), + RB_ADDR => slv(to_unsigned(2#11111110#,8)), CDWIDTH => 13, CDINIT => CDINIT) port map ( @@ -175,7 +176,7 @@ begin EMON : rbd_eyemon generic map ( RB_ADDR => rbaddr_emon, - RDIV => conv_std_logic_vector(0,8)) + RDIV => slv(to_unsigned(0,8))) port map ( CLK => CLK, RESET => RESET, diff --git a/rtl/sys_gen/tst_snhumanio/Makefile b/rtl/sys_gen/tst_snhumanio/Makefile new file mode 100644 index 00000000..5fa96b75 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/Makefile @@ -0,0 +1,23 @@ +# $Id: Makefile 410 2011-09-18 11:23:09Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-09-17 410 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +ISE_PATH = xc3s1000-ft256-4 +# +.PHONY : all clean +# +all : $(NGC_all) +# +clean : ise_clean +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +include $(VBOM_all:.vbom=.dep_xst) +# diff --git a/rtl/sys_gen/tst_snhumanio/atlys/.cvsignore b/rtl/sys_gen/tst_snhumanio/atlys/.cvsignore new file mode 100644 index 00000000..2249f17e --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/atlys/.cvsignore @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_snhumanio_atlys.ucf +*.dep_ucf_cpp +*.svf diff --git a/rtl/sys_gen/tst_snhumanio/atlys/Makefile b/rtl/sys_gen/tst_snhumanio/atlys/Makefile new file mode 100644 index 00000000..9c03c38d --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/atlys/Makefile @@ -0,0 +1,30 @@ +# $Id: Makefile 414 2011-10-11 19:38:12Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-10-11 414 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +ISE_BOARD = atlys +ISE_PATH = xc6slx45-csg324-2 +# +XFLOWOPT_SYN = syn_s6_speed.opt +XFLOWOPT_IMP = imp_s6_speed.opt +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f sys_tst_snhumanio_atlys.ucf +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +# diff --git a/rtl/sys_gen/tst_snhumanio/atlys/sys_conf.vhd b/rtl/sys_gen/tst_snhumanio/atlys/sys_conf.vhd new file mode 100644 index 00000000..a71ea8e6 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/atlys/sys_conf.vhd @@ -0,0 +1,35 @@ +-- $Id: sys_conf.vhd 414 2011-10-11 19:38:12Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_snhumanio_atlys (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-10-11 414 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + +end package sys_conf; + diff --git a/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.mfset b/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.mfset new file mode 100644 index 00000000..4106309d --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.mfset @@ -0,0 +1,29 @@ +# $Id: sys_tst_snhumanio_atlys.mfset 416 2011-10-15 13:32:57Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Case statement is complete. others clause is never selected + +sys_tst_snhumanio_atlys\..*Output port of the instance is unconnected + +Node of sequential type is unconnected + +The FF/Latch in Unit <.*> is equivalent +The small RAM <.*> will be implemented on LUTs + +# +# ---------------------------------------------------------------------------- +[tra] + +# +# ---------------------------------------------------------------------------- +[map] +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] + +# +# ---------------------------------------------------------------------------- +[bgn] diff --git a/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.ucf_cpp b/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.ucf_cpp new file mode 100644 index 00000000..e9b2f98e --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.ucf_cpp @@ -0,0 +1,16 @@ +## $Id: sys_tst_snhumanio_atlys.ucf_cpp 414 2011-10-11 19:38:12Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-10-11 414 1.0 Initial version +## + +NET "I_CLK100" TNM_NET = "I_CLK100"; +TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK100"; +OFFSET = OUT 20 ns AFTER "I_CLK100"; + +## std board +## +#include "bplib/atlys/atlys_pins.ucf" +#include "bplib/atlys/atlys_pins_pma0_rs232.ucf" diff --git a/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vbom b/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vbom new file mode 100644 index 00000000..4467154e --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vbom @@ -0,0 +1,12 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +sys_conf : sys_conf.vhd +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/sn_humanio_demu.vbom +../tst_snhumanio.vbom +# design +sys_tst_snhumanio_atlys.vhd +@ucf_cpp: sys_tst_snhumanio_atlys.ucf diff --git a/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vhd b/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vhd new file mode 100644 index 00000000..0eff65de --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vhd @@ -0,0 +1,130 @@ +-- $Id: sys_tst_snhumanio_atlys.vhd 414 2011-10-11 19:38:12Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_snhumanio_atlys - syn +-- Description: snhumanio tester design for atlys +-- +-- Dependencies: vlib/genlib/clkdivce +-- bplib/bpgen/sn_humanio_demu +-- tst_snhumanio +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-10-11 414 13.1 O40d xc6slx45 166 196 - 60 t 4.9 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-10-11 414 1.0 Initial version +------------------------------------------------------------------------------ +-- Usage of Atlys Switches, Buttons, LEDs: +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_snhumanio_atlys is -- top level + -- implements xxx_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock +-- O_CLKSYS : out slbit; -- DCM derived system clock + I_USB_RXD : in slbit; -- USB UART receive data (board view) + O_USB_TXD : out slbit; -- USB UART transmit data (board view) + I_HIO_SWI : in slv8; -- atlys hio switches + I_HIO_BTN : in slv6; -- atlys hio buttons + O_HIO_LED: out slv8; -- atlys hio leds + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end sys_tst_snhumanio_atlys; + +architecture syn of sys_tst_snhumanio_atlys is + + signal CLK : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_MSEC : slbit := '0'; + +begin + + RESET <= '0'; -- so far not used + + CLK <= I_CLK100; + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => 100, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio_demu + generic map ( + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_HIO_SWI, + I_BTN => I_HIO_BTN, + O_LED => O_HIO_LED + ); + + HIOTEST : entity work.tst_snhumanio + generic map ( + BWIDTH => 4) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + O_USB_TXD <= I_USB_RXD; + O_FUSP_TXD <= I_FUSP_RXD; + O_FUSP_RTS_N <= I_FUSP_CTS_N; + +end syn; diff --git a/rtl/sys_gen/tst_snhumanio/nexys2/.cvsignore b/rtl/sys_gen/tst_snhumanio/nexys2/.cvsignore new file mode 100644 index 00000000..827dbbf7 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/nexys2/.cvsignore @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_snhumanio_n2.ucf +*.dep_ucf_cpp +*.svf diff --git a/rtl/sys_gen/tst_snhumanio/nexys2/Makefile b/rtl/sys_gen/tst_snhumanio/nexys2/Makefile new file mode 100644 index 00000000..52376364 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/nexys2/Makefile @@ -0,0 +1,27 @@ +# $Id: Makefile 410 2011-09-18 11:23:09Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-09-17 410 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +ISE_BOARD = nexys2 +ISE_PATH = xc3s1200e-fg320-4 +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f sys_tst_snhumanio_n2.ucf +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +# diff --git a/rtl/sys_gen/tst_snhumanio/nexys2/sys_conf.vhd b/rtl/sys_gen/tst_snhumanio/nexys2/sys_conf.vhd new file mode 100644 index 00000000..e3a2b939 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/nexys2/sys_conf.vhd @@ -0,0 +1,35 @@ +-- $Id: sys_conf.vhd 410 2011-09-18 11:23:09Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_snhumanio_n2 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-09-17 410 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + +end package sys_conf; + diff --git a/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.mfset b/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.mfset new file mode 100644 index 00000000..11ad9657 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.mfset @@ -0,0 +1,34 @@ +# $Id: sys_tst_snhumanio_n2.mfset 412 2011-10-08 15:15:20Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Mux is complete : default of case is discarded + +Unconnected output port 'CE_USEC' of component 'clkdivce' + +Input is never used + +FF/Latch has a constant value of 0 +Node of sequential type is unconnected + +# +# ---------------------------------------------------------------------------- +[tra] + +# +# ---------------------------------------------------------------------------- +[map] +The signal is incomplete +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] +The signal I_MEM_WAIT_IBUF has no load +There are 1 loadless signals in this design + +# +# ---------------------------------------------------------------------------- +[bgn] +Spartan-3 1200E and 1600E devices do not support bitstream +The signal is incomplete diff --git a/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.ucf_cpp b/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.ucf_cpp new file mode 100644 index 00000000..13d09c12 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.ucf_cpp @@ -0,0 +1,15 @@ +## $Id: sys_tst_snhumanio_n2.ucf_cpp 410 2011-09-18 11:23:09Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-09-17 410 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +## std board +## +#include "bplib/nexys2/nexys2_pins.ucf" diff --git a/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vbom b/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vbom new file mode 100644 index 00000000..70dde87b --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vbom @@ -0,0 +1,14 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/nexys2/nexys2lib.vhd +sys_conf : sys_conf.vhd +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_snhumanio.vbom +../../../bplib/nexys2/n2_cram_dummy.vbom +# design +sys_tst_snhumanio_n2.vhd +@ucf_cpp: sys_tst_snhumanio_n2.ucf diff --git a/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vhd b/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vhd new file mode 100644 index 00000000..72f2f131 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vhd @@ -0,0 +1,159 @@ +-- $Id: sys_tst_snhumanio_n2.vhd 419 2011-11-01 19:42:30Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_snhumanio_n2 - syn +-- Description: snhumanio tester design for nexys2 +-- +-- Dependencies: vlib/genlib/clkdivce +-- bplib/bpgen/sn_humanio +-- tst_snhumanio +-- vlib/nexys2/n2_cram_dummy +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-09-17 410 13.1 O40d xc3s1200e-4 149 207 - 144 t 10.2 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-10-25 419 1.0.2 get entity name right... +-- 2011-09-17 410 1.0 Initial version +------------------------------------------------------------------------------ +-- Usage of Nexys 2 Switches, Buttons, LEDs: +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.nexys2lib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_snhumanio_n2 is -- top level + -- implements nexys2_aif + port ( + I_CLK50 : in slbit; -- 50 MHz clock + O_CLKSYS : out slbit; -- DCM derived system clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- s3 switches + I_BTN : in slv4; -- s3 buttons + O_LED : out slv8; -- s3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16 -- cram: data lines + ); +end sys_tst_snhumanio_n2; + +architecture syn of sys_tst_snhumanio_n2 is + + signal CLK : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_MSEC : slbit := '0'; + +begin + + RESET <= '0'; -- so far not used + + CLK <= I_CLK50; + O_CLKSYS <= CLK; + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => 50, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio + generic map ( + BWIDTH => 4, + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + HIOTEST : entity work.tst_snhumanio + generic map ( + BWIDTH => 4) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + O_TXD <= I_RXD; + + SRAM_PROT : n2_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_FLA_CE_N => O_FLA_CE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + +end syn; diff --git a/rtl/sys_gen/tst_snhumanio/s3board/.cvsignore b/rtl/sys_gen/tst_snhumanio/s3board/.cvsignore new file mode 100644 index 00000000..4a12f23d --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/s3board/.cvsignore @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_snhumanio_s3.ucf +*.dep_ucf_cpp +*.svf diff --git a/rtl/sys_gen/tst_snhumanio/s3board/Makefile b/rtl/sys_gen/tst_snhumanio/s3board/Makefile new file mode 100644 index 00000000..a5f40bc4 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/s3board/Makefile @@ -0,0 +1,27 @@ +# $Id: Makefile 410 2011-09-18 11:23:09Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-09-18 410 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +ISE_BOARD = s3board +ISE_PATH = xc3s1000-ft256-4 +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f sys_tst_snhumanio_s3.ucf +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +# diff --git a/rtl/sys_gen/tst_snhumanio/s3board/sys_conf.vhd b/rtl/sys_gen/tst_snhumanio/s3board/sys_conf.vhd new file mode 100644 index 00000000..9bf198e5 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/s3board/sys_conf.vhd @@ -0,0 +1,35 @@ +-- $Id: sys_conf.vhd 410 2011-09-18 11:23:09Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_snhumanio_n2 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-09-18 410 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + +end package sys_conf; + diff --git a/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.mfset b/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.mfset new file mode 100644 index 00000000..f5179443 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.mfset @@ -0,0 +1,27 @@ +# $Id: sys_tst_snhumanio_s3.mfset 417 2011-10-22 10:30:29Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Mux is complete : default of case is discarded + +Unconnected output port 'CE_USEC' of component 'clkdivce' + +FF/Latch has a constant value of 0 +Node of sequential type is unconnected + +# +# ---------------------------------------------------------------------------- +[tra] + +# +# ---------------------------------------------------------------------------- +[map] +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] + +# +# ---------------------------------------------------------------------------- +[bgn] diff --git a/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.ucf_cpp b/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.ucf_cpp new file mode 100644 index 00000000..a257e892 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.ucf_cpp @@ -0,0 +1,15 @@ +## $Id: sys_tst_snhumanio_s3.ucf_cpp 410 2011-09-18 11:23:09Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-09-18 410 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +## std board +## +#include "bplib/s3board/s3board_pins.ucf" diff --git a/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.vbom b/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.vbom new file mode 100644 index 00000000..6040beb5 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.vbom @@ -0,0 +1,14 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/s3board/s3boardlib.vhd +sys_conf : sys_conf.vhd +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_snhumanio.vbom +../../../bplib/s3board/s3_sram_dummy.vbom +# design +sys_tst_snhumanio_s3.vhd +@ucf_cpp: sys_tst_snhumanio_s3.ucf diff --git a/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.vhd b/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.vhd new file mode 100644 index 00000000..b45efa24 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.vhd @@ -0,0 +1,148 @@ +-- $Id: sys_tst_snhumanio_s3.vhd 419 2011-11-01 19:42:30Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_snhumanio_s3 - syn +-- Description: snhumanio tester design for s3board +-- +-- Dependencies: vlib/genlib/clkdivce +-- bplib/bpgen/sn_humanio +-- tst_snhumanio +-- s3board/s3_sram_dummy +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-09-18 410 13.1 O40d xc3s1000-4 149 211 - 143 t 11.4 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-10-25 419 1.0.2 get entity name right... +-- 2011-10-15 416 1.0.1 remove O_CLKSYS top level port +-- 2011-09-18 410 1.0 Initial version +------------------------------------------------------------------------------ +-- Usage of S3BOARD Switches, Buttons, LEDs: +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.s3boardlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_snhumanio_s3 is -- top level + -- implements s3board_aif + port ( + I_CLK50 : in slbit; -- 50 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- s3 switches + I_BTN : in slv4; -- s3 buttons + O_LED : out slv8; -- s3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32 -- sram: data lines + ); +end sys_tst_snhumanio_s3; + +architecture syn of sys_tst_snhumanio_s3 is + + signal CLK : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_MSEC : slbit := '0'; + +begin + + RESET <= '0'; -- so far not used + + CLK <= I_CLK50; + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => 50, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio + generic map ( + BWIDTH => 4, + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + HIOTEST : entity work.tst_snhumanio + generic map ( + BWIDTH => 4) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + O_TXD <= I_RXD; + + SRAM_PROT : s3_sram_dummy -- connect SRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + +end syn; diff --git a/rtl/sys_gen/tst_snhumanio/tst_snhumanio.vbom b/rtl/sys_gen/tst_snhumanio/tst_snhumanio.vbom new file mode 100644 index 00000000..14115e42 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/tst_snhumanio.vbom @@ -0,0 +1,6 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/comlib/comlib.vhd +# components +# design +tst_snhumanio.vhd diff --git a/rtl/sys_gen/tst_snhumanio/tst_snhumanio.vhd b/rtl/sys_gen/tst_snhumanio/tst_snhumanio.vhd new file mode 100644 index 00000000..2331ab78 --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/tst_snhumanio.vhd @@ -0,0 +1,234 @@ +-- $Id: tst_snhumanio.vhd 416 2011-10-15 13:32:57Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tst_snhumanio - syn +-- Description: simple stand-alone tester for sn_humanio +-- +-- Dependencies: - +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-10-15 416 1.0.2 fix sensitivity list of proc_next +-- 2011-10-08 412 1.0.1 use better rndm init (so that swi=0 is non-const) +-- 2011-09-17 410 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.comlib.all; + +-- ---------------------------------------------------------------------------- + +entity tst_snhumanio is -- tester for rlink + generic ( + BWIDTH : positive := 4); -- BTN port width + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CE_MSEC : in slbit; -- msec pulse + SWI : in slv8; -- switch settings + BTN : in slv(BWIDTH-1 downto 0); -- button settings + LED : out slv8; -- led data + DSP_DAT : out slv16; -- display data + DSP_DP : out slv4 -- display decimal points + ); +end tst_snhumanio; + +architecture syn of tst_snhumanio is + + constant c_mode_rndm : slv2 := "00"; + constant c_mode_cnt : slv2 := "01"; + constant c_mode_swi : slv2 := "10"; + constant c_mode_btst : slv2 := "11"; + + type regs_type is record + mode : slv2; -- current mode + allon : slbit; -- all LEDs on if set + cnt : slv16; -- counter + tcnt : slv16; -- swi/btn toggle counter + rndm : slv8; -- random number + swi_1 : slv8; -- last SWI state + btn_1 : slv(BWIDTH-1 downto 0); -- last BTN state + led : slv8; -- LED output state + dsp : slv16; -- display data + dp : slv4; -- display decimal points + end record regs_type; + + -- the rndm start value is /= 0 because a seed of 0 with a SWI setting of 0 + -- will result in a 0-0-0 sequence. The 01010101 start will get trapped in a + -- constant sequence with a 01100011 switch setting, which is rather unlikely. + constant rndminit : slv8 := "01010101"; + + constant btnzero : slv(BWIDTH-1 downto 0) := (others=>'0'); + + constant regs_init : regs_type := ( + c_mode_rndm, -- mode + '0', -- allon + (others=>'0'), -- cnt + (others=>'0'), -- tcnt + rndminit, -- rndm + (others=>'0'), -- swi_1 + btnzero, -- btn_1 + (others=>'0'), -- led + (others=>'0'), -- dsp + (others=>'0') -- dp + + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + signal BTN4 : slbit := '0'; + +begin + + assert BWIDTH>=4 + report "assert(BWIDTH>=4): at least 4 BTNs available" + severity failure; + + B4YES: if BWIDTH > 4 generate + BTN4 <= BTN(4); + end generate B4YES; + B4NO: if BWIDTH = 4 generate + BTN4 <= '0'; + end generate B4NO; + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, CE_MSEC, SWI, BTN, BTN4) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + variable btn03 : slv4 := (others=>'0'); + + begin + r := R_REGS; + n := R_REGS; + + n.swi_1 := SWI; + n.btn_1 := BTN; + + if SWI/=r.swi_1 or BTN/=r.btn_1 then + n.tcnt := slv(unsigned(r.tcnt) + 1); + end if; + + btn03 := BTN(3 downto 0); + n.allon := BTN4; + + if unsigned(BTN) /= 0 then -- is a button being pressed ? + if r.mode /= c_mode_btst then -- not in btst mode + case btn03 is + when "0001" => -- 0001 single button -> rndm mode + n.mode := c_mode_rndm; + n.rndm := rndminit; + + when "0010" => -- 0010 single button -> cnt mode + n.mode := c_mode_cnt; + + when "0100" => -- 0100 single button -> swi mode + n.mode := c_mode_swi; + + when "1000" => -- 1001 single button -> btst mode + n.mode := c_mode_btst; + n.tcnt := (others=>'0'); + + when others => -- any 2+ button combo -> led test + n.allon := '1'; + end case; + + else -- button press in btst mode + + case btn03 is + when "1001" => -- 1001 double btn -> rndm mode + n.mode := c_mode_rndm; + when "1010" => -- 1010 double btn -> rndm cnt + n.mode := c_mode_cnt; + when "1100" => -- 1100 double btn -> rndm swi + n.mode := c_mode_swi; + when others => null; + end case; + + end if; + + else -- no button being pressed + + if CE_MSEC = '1' then -- on every usec + n.cnt := slv(unsigned(r.cnt) + 1); -- inc counter + if unsigned(r.cnt(8 downto 0)) = 0 then -- every 1/2 sec (approx.) + n.rndm := crc8_update(r.rndm, SWI); -- update rndm state + end if; + end if; + end if; + + if r.allon = '1' then -- if led test selected + n.led := (others=>'1'); -- all led,dsp,dp on + n.dsp := (others=>'1'); + n.dp := (others=>'1'); + + else -- no led test, normal output + + case r.mode is + when c_mode_rndm => + n.led := r.rndm; + n.dsp(7 downto 0) := r.rndm; + n.dsp(15 downto 8) := not r.rndm; + + when c_mode_cnt => + n.led := r.cnt(14 downto 7); + n.dsp := r.cnt; + + when c_mode_swi => + n.led := SWI; + n.dsp(7 downto 0) := SWI; + n.dsp(15 downto 8) := not SWI; + + when c_mode_btst => + n.led := SWI; + n.dsp := r.tcnt; + + when others => null; + end case; + + n.dp := BTN(3 downto 0); + + end if; + + N_REGS <= n; + + LED <= r.led; + DSP_DAT <= r.dsp; + DSP_DP <= r.dp; + + end process proc_next; + + +end syn; diff --git a/rtl/sys_gen/w11a/nexys2/sys_conf.vhd b/rtl/sys_gen/w11a/nexys2/sys_conf.vhd index 749057bb..ee50df42 100644 --- a/rtl/sys_gen/w11a/nexys2/sys_conf.vhd +++ b/rtl/sys_gen/w11a/nexys2/sys_conf.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf.vhd 341 2010-11-27 23:05:43Z mueller $ +-- $Id: sys_conf.vhd 428 2011-11-20 12:19:31Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Definitions for sys_w11a_n2 (for synthesis) -- -- Dependencies: - --- Tool versions: xst 11.4; ghdl 0.26 +-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 428 1.1.1 use clksys=56 (58 no closure after numeric_std...) -- 2010-11-27 341 1.1 add dcm and memctl related constants (clksys=58) -- 2010-05-05 295 1.0 Initial version (derived from _s3 version) ------------------------------------------------------------------------------ @@ -37,7 +38,7 @@ use work.slvtypes.all; package sys_conf is constant sys_conf_clkfx_divide : positive := 25; - constant sys_conf_clkfx_multiply : positive := 29; -- ==> 58 MHz + constant sys_conf_clkfx_multiply : positive := 28; -- ==> 56 MHz constant sys_conf_memctl_read0delay : positive := 3; constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; diff --git a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.mfset b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.mfset index 96688af9..382591d5 100644 --- a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.mfset +++ b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.mfset @@ -1,4 +1,4 @@ -# $Id: sys_w11a_n2.mfset 406 2011-08-14 21:06:44Z mueller $ +# $Id: sys_w11a_n2.mfset 427 2011-11-19 21:04:11Z mueller $ # # ---------------------------------------------------------------------------- [xst] @@ -14,7 +14,7 @@ Node of sequential type is unconnected Node of sequential type is unconnected Node of sequential type is unconnected -Unconnected output port 'LOCKED' of component 'dcm_sp_sfs' +Unconnected output port 'LOCKED' of component 'dcm_sfs' Unconnected output port 'RL_MONI' of component 'rlink_base_serport' Unconnected output port 'RL_SER_MONI' of component 'rlink_base_serport' Unconnected output port 'ACK_W' of component 'n2_cram_memctl_as' diff --git a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom index 9a4f8c1f..5e91494a 100644 --- a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom +++ b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom @@ -11,8 +11,8 @@ ../../../w11a/pdp11.vhd sys_conf = sys_conf.vhd # components -[xst,isim]../../../vlib/xlib/dcm_sp_sfs_unisim.vbom -[ghdl]../../../vlib/xlib/dcm_sp_sfs_gsim.vbom +[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom ../../../bplib/bpgen/sn_humanio_rbus.vbom diff --git a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd index 82967ec1..423ab880 100644 --- a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd +++ b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_n2.vhd 404 2011-08-07 22:00:25Z mueller $ +-- $Id: sys_w11a_n2.vhd 427 2011-11-19 21:04:11Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -15,7 +15,7 @@ -- Module Name: sys_w11a_n2 - syn -- Description: w11a test design for nexys2 -- --- Dependencies: vlib/xlib/dcm_sp_sfs +-- Dependencies: vlib/xlib/dcm_sfs -- vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_2l4l_iob -- bplib/bpgen/sn_humanio_rbus @@ -36,10 +36,11 @@ -- Test bench: tb/tb_sys_w11a_n2 -- -- Target Devices: generic --- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1; ghdl 0.26-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1, 13.1; ghdl 0.26-0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-11-18 427 13.1 O40d xc3s1200e-4 1433 4374 242 2680 ok: LP+PC+DL+II -- 2010-12-30 351 12.1 M53d xc3s1200e-4 1389 4368 242 2674 ok: LP+PC+DL+II -- 2010-11-06 336 12.1 M53d xc3s1200e-4 1357 4304* 242 2618 ok: LP+PC+DL+II -- 2010-10-24 335 12.1 M53d xc3s1200e-4 1357 4546 242 2618 ok: LP+PC+DL+II @@ -62,6 +63,8 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.2.4 now numeric_std clean +-- 2011-11-17 426 1.2.3 use dcm_sfs now -- 2011-07-09 391 1.2.2 use now bp_rs232_2l4l_iob -- 2011-07-08 390 1.2.1 use now sn_humanio -- 2010-12-30 351 1.2 ported to rbv3 @@ -111,7 +114,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.xlib.all; @@ -241,7 +244,7 @@ begin report "assert sys_conf_clksys on MHz grid" severity failure; - DCM : dcm_sp_sfs + DCM : dcm_sfs generic map ( CLKFX_DIVIDE => sys_conf_clkfx_divide, CLKFX_MULTIPLY => sys_conf_clkfx_multiply, diff --git a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd index 4fa069bb..f793d615 100644 --- a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd +++ b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_s3.vhd 404 2011-08-07 22:00:25Z mueller $ +-- $Id: sys_w11a_s3.vhd 427 2011-11-19 21:04:11Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -35,10 +35,11 @@ -- Test bench: tb/tb_sys_w11a_s3 -- -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 11.4, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1, 13.1; ghdl 0.18-0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-11-19 427 13.1 O40d xc3s1000-4 1322 4298 242 2616 OK: LP+PC+DL+II -- 2010-12-30 351 12.1 M53d xc3s1000-4 1316 4291 242 2609 OK: LP+PC+DL+II -- 2010-11-06 336 12.1 M53d xc3s1000-4 1284 4253* 242 2575 OK: LP+PC+DL+II -- 2010-10-24 335 12.1 M53d xc3s1000-4 1284 4495 242 2575 OK: LP+PC+DL+II @@ -71,6 +72,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.4.3 now numeric_std clean -- 2011-07-09 391 1.4.2 use now bp_rs232_2l4l_iob -- 2011-07-08 390 1.4.1 use now sn_humanio -- 2010-12-30 351 1.4 ported to rbv3 @@ -129,7 +131,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.genlib.all; diff --git a/rtl/vlib/comlib/byte2cdata.vhd b/rtl/vlib/comlib/byte2cdata.vhd index 2fc334aa..b97eb4f5 100644 --- a/rtl/vlib/comlib/byte2cdata.vhd +++ b/rtl/vlib/comlib/byte2cdata.vhd @@ -1,6 +1,6 @@ --- $Id: byte2cdata.vhd 348 2010-12-26 15:23:44Z mueller $ +-- $Id: byte2cdata.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2007- by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,17 +18,18 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.0.2 now numeric_std clean -- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned -- 2007-08-27 76 1.0 Initial version ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; @@ -79,7 +80,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then R_REGS <= regs_init; else diff --git a/rtl/vlib/comlib/cdata2byte.vhd b/rtl/vlib/comlib/cdata2byte.vhd index 8ae9fa9b..73cb265b 100644 --- a/rtl/vlib/comlib/cdata2byte.vhd +++ b/rtl/vlib/comlib/cdata2byte.vhd @@ -1,6 +1,6 @@ --- $Id: cdata2byte.vhd 348 2010-12-26 15:23:44Z mueller $ +-- $Id: cdata2byte.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2007- by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,17 +18,18 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.0.2 now numeric_std clean -- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned -- 2007-06-30 62 1.0 Initial version ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; @@ -81,7 +82,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then R_REGS <= regs_init; else diff --git a/rtl/vlib/comlib/comlib.vhd b/rtl/vlib/comlib/comlib.vhd index 5aeca1f0..006078af 100644 --- a/rtl/vlib/comlib/comlib.vhd +++ b/rtl/vlib/comlib/comlib.vhd @@ -1,4 +1,4 @@ --- $Id: comlib.vhd 400 2011-07-31 09:02:16Z mueller $ +-- $Id: comlib.vhd 427 2011-11-19 21:04:11Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -16,9 +16,11 @@ -- Description: communication components -- -- Dependencies: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-09-17 410 1.4 now numeric_std clean; use for crc8 'A6' polynomial +-- of Koopman et al.; crc8_update(_tbl) now function -- 2011-07-30 400 1.3 added byte2word, word2byte -- 2007-10-12 88 1.2.1 avoid ieee.std_logic_unsigned, use cast to unsigned -- 2007-07-08 65 1.2 added procedure crc8_update_tbl @@ -29,7 +31,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; @@ -107,10 +109,8 @@ component crc8 is -- crc-8 generator, checker ); end component; - procedure crc8_update (crc : inout slv8; - data : in slv8); - procedure crc8_update_tbl (crc : inout slv8; - data : in slv8); + function crc8_update (crc : in slv8; data : in slv8) return slv8; + function crc8_update_tbl (crc : in slv8; data : in slv8) return slv8; end package comlib; @@ -118,67 +118,68 @@ end package comlib; package body comlib is - procedure crc8_update (crc : inout slv8; - data : in slv8) is + function crc8_update (crc: in slv8; data: in slv8) return slv8 is variable t : slv8 := (others=>'0'); + variable n : slv8 := (others=>'0'); begin t := data xor crc; - crc(0) := t(0) xor t(4) xor t(5) xor t(6); - crc(1) := t(1) xor t(5) xor t(6) xor t(7); - crc(2) := t(0) xor t(2) xor t(4) xor t(5) xor t(7); - crc(3) := t(0) xor t(1) xor t(3) xor t(4); - crc(4) := t(0) xor t(1) xor t(2) xor t(6); - crc(5) := t(1) xor t(2) xor t(3) xor t(7); - crc(6) := t(2) xor t(3) xor t(4); - crc(7) := t(3) xor t(4) xor t(5); + + n(0) := t(5) xor t(4) xor t(2) xor t(0); + n(1) := t(6) xor t(5) xor t(3) xor t(1); + n(2) := t(7) xor t(6) xor t(5) xor t(0); + n(3) := t(7) xor t(6) xor t(5) xor t(4) xor t(2) xor t(1) xor t(0); + n(4) := t(7) xor t(6) xor t(5) xor t(3) xor t(2) xor t(1); + n(5) := t(7) xor t(6) xor t(4) xor t(3) xor t(2); + n(6) := t(7) xor t(3) xor t(2) xor t(0); + n(7) := t(4) xor t(3) xor t(1); + + return n; - end procedure crc8_update; + end function crc8_update; - procedure crc8_update_tbl (crc : inout slv8; - data : in slv8) is + function crc8_update_tbl (crc: in slv8; data: in slv8) return slv8 is type crc8_tbl_type is array (0 to 255) of integer; variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl - ( 0, 29, 58, 39, 116, 105, 78, 83, - 232, 245, 210, 207, 156, 129, 166, 187, - 205, 208, 247, 234, 185, 164, 131, 158, - 37, 56, 31, 2, 81, 76, 107, 118, - 135, 154, 189, 160, 243, 238, 201, 212, - 111, 114, 85, 72, 27, 6, 33, 60, - 74, 87, 112, 109, 62, 35, 4, 25, - 162, 191, 152, 133, 214, 203, 236, 241, - 19, 14, 41, 52, 103, 122, 93, 64, - 251, 230, 193, 220, 143, 146, 181, 168, - 222, 195, 228, 249, 170, 183, 144, 141, - 54, 43, 12, 17, 66, 95, 120, 101, - 148, 137, 174, 179, 224, 253, 218, 199, - 124, 97, 70, 91, 8, 21, 50, 47, - 89, 68, 99, 126, 45, 48, 23, 10, - 177, 172, 139, 150, 197, 216, 255, 226, - 38, 59, 28, 1, 82, 79, 104, 117, - 206, 211, 244, 233, 186, 167, 128, 157, - 235, 246, 209, 204, 159, 130, 165, 184, - 3, 30, 57, 36, 119, 106, 77, 80, - 161, 188, 155, 134, 213, 200, 239, 242, - 73, 84, 115, 110, 61, 32, 7, 26, - 108, 113, 86, 75, 24, 5, 34, 63, - 132, 153, 190, 163, 240, 237, 202, 215, - 53, 40, 15, 18, 65, 92, 123, 102, - 221, 192, 231, 250, 169, 180, 147, 142, - 248, 229, 194, 223, 140, 145, 182, 171, - 16, 13, 42, 55, 100, 121, 94, 67, - 178, 175, 136, 149, 198, 219, 252, 225, - 90, 71, 96, 125, 46, 51, 20, 9, - 127, 98, 69, 88, 11, 22, 49, 44, - 151, 138, 173, 176, 227, 254, 217, 196 - ); + ( 0, 77, 154, 215, 121, 52, 227, 174, -- 00-07 + 242, 191, 104, 37, 139, 198, 17, 92, -- 00-0f + 169, 228, 51, 126, 208, 157, 74, 7, -- 10-17 + 91, 22, 193, 140, 34, 111, 184, 245, -- 10-1f + 31, 82, 133, 200, 102, 43, 252, 177, -- 20-27 + 237, 160, 119, 58, 148, 217, 14, 67, -- 20-2f + 182, 251, 44, 97, 207, 130, 85, 24, -- 30-37 + 68, 9, 222, 147, 61, 112, 167, 234, -- 30-3f + 62, 115, 164, 233, 71, 10, 221, 144, -- 40-47 + 204, 129, 86, 27, 181, 248, 47, 98, -- 40-4f + 151, 218, 13, 64, 238, 163, 116, 57, -- 50-57 + 101, 40, 255, 178, 28, 81, 134, 203, -- 50-5f + 33, 108, 187, 246, 88, 21, 194, 143, -- 60-67 + 211, 158, 73, 4, 170, 231, 48, 125, -- 60-6f + 136, 197, 18, 95, 241, 188, 107, 38, -- 70-70 + 122, 55, 224, 173, 3, 78, 153, 212, -- 70-7f + 124, 49, 230, 171, 5, 72, 159, 210, -- 80-87 + 142, 195, 20, 89, 247, 186, 109, 32, -- 80-8f + 213, 152, 79, 2, 172, 225, 54, 123, -- 90-97 + 39, 106, 189, 240, 94, 19, 196, 137, -- 90-9f + 99, 46, 249, 180, 26, 87, 128, 205, -- a0-a7 + 145, 220, 11, 70, 232, 165, 114, 63, -- a0-af + 202, 135, 80, 29, 179, 254, 41, 100, -- b0-b7 + 56, 117, 162, 239, 65, 12, 219, 150, -- b0-bf + 66, 15, 216, 149, 59, 118, 161, 236, -- c0-c7 + 176, 253, 42, 103, 201, 132, 83, 30, -- c0-cf + 235, 166, 113, 60, 146, 223, 8, 69, -- d0-d7 + 25, 84, 131, 206, 96, 45, 250, 183, -- d0-df + 93, 16, 199, 138, 36, 105, 190, 243, -- e0-e7 + 175, 226, 53, 120, 214, 155, 76, 1, -- e0-ef + 244, 185, 110, 35, 141, 192, 23, 90, -- f0-f7 + 6, 75, 156, 209, 127, 50, 229, 168 -- f0-ff + ); begin - crc := conv_std_logic_vector( - crc8_tbl(conv_integer(unsigned(data xor crc))), 8); + return slv(to_unsigned(crc8_tbl(to_integer(unsigned(data xor crc))), 8)); - end procedure crc8_update_tbl; + end function crc8_update_tbl; end package body comlib; diff --git a/rtl/vlib/comlib/crc8.vhd b/rtl/vlib/comlib/crc8.vhd index 0d96438c..e04e5d9d 100644 --- a/rtl/vlib/comlib/crc8.vhd +++ b/rtl/vlib/comlib/crc8.vhd @@ -1,4 +1,4 @@ --- $Id: crc8.vhd 406 2011-08-14 21:06:44Z mueller $ +-- $Id: crc8.vhd 410 2011-09-18 11:23:09Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -13,34 +13,35 @@ -- ------------------------------------------------------------------------------ -- Module Name: crc8 - syn --- Description: 8bit CRC generator, use CRC-8-SAE J1850 polynomial. --- Based on CRC-8-SAE J1850 polynomial: --- x^8 + x^4 + x^3 + x^2 + 1 (0x1d) --- It is irreducible, and can be implemented with <= 54 xor's +-- Description: 8bit CRC generator, use 'A6' polynomial of Koopman and +-- Chakravarty. Has HD=3 for up to 247 bits and optimal HD=2 +-- error detection for longer messages: -- --- Notes: # XST synthesis for a Spartan-3 gives: --- 1-bit xor2 : 11 --- 1-bit xor4 : 5 --- 1-bit xor5 : 1 --- Number of 4 input LUTs: 20 --- # Synthesis with crc8_update_tbl gives a lut-rom based table --- design. Even though a 256x8 bit ROM is behind, the optimizer --- gets it into 12 slices with 22 4 input LUTs, thus only --- little larger than with xor's. +-- x^8 + x^6 + x^3 + x^2 + 1 (0xa6) +-- +-- It is irreducible, and can be implemented with <= 37 xor's +-- This polynomial is described in +-- http://dx.doi.org/10.1109%2FDSN.2004.1311885 -- -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-09-17 410 13.1 O40d xc3s1200e-4 8 25 - 13 (A6 polynom) +-- 2011-09-17 409 13.1 O40d xc3s1200e-4 8 18 - 10 (SAE J1850) +-- -- Revision History: -- Date Rev Version Comment +-- 2011-09-17 409 1.1 use now 'A6' polynomial of Koopman et al. -- 2011-08-14 406 1.0.1 remove superfluous variable r -- 2007-07-08 65 1.0 Initial version ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; use work.slvtypes.all; use work.comlib.all; @@ -59,40 +60,24 @@ end crc8; architecture syn of crc8 is - signal R_CRC : slv8 := INIT; -- state registers - signal N_CRC : slv8 := INIT; -- next value state regs - begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then R_CRC <= INIT; else - R_CRC <= N_CRC; + if ENA = '1' then + R_CRC <= crc8_update(R_CRC, DI); + end if; end if; end if; end process proc_regs; - proc_next: process (R_CRC, DI, ENA) - variable n : slv8 := INIT; - begin - - n := R_CRC; - - if ENA = '1' then - crc8_update(n, DI); - end if; - - N_CRC <= n; - - CRC <= R_CRC; - - end process proc_next; - - + CRC <= R_CRC; + end syn; diff --git a/rtl/vlib/comlib/misc/gen_crc8_tbl.vhd b/rtl/vlib/comlib/misc/gen_crc8_tbl.vhd index fc333f2f..a1eaeac5 100644 --- a/rtl/vlib/comlib/misc/gen_crc8_tbl.vhd +++ b/rtl/vlib/comlib/misc/gen_crc8_tbl.vhd @@ -1,6 +1,6 @@ --- $Id: gen_crc8_tbl.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: gen_crc8_tbl.vhd 410 2011-09-18 11:23:09Z mueller $ -- --- Copyright 2007- by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -15,18 +15,18 @@ -- Module Name: gen_crc8_tbl - sim -- Description: stand-alone program to print crc8 transition table -- --- Dependencies: comlib/crc8_update (procedure) +-- Dependencies: comlib/crc8_update (function) -- -- Revision History: -- Date Rev Version Comment +-- 2011-09-17 410 1.1 now numeric_std clean; use function crc8_update -- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned -- 2007-07-08 65 1.0 Initial version ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_textio.all; +use ieee.numeric_std.all; use std.textio.all; use work.slvtypes.all; @@ -41,13 +41,14 @@ begin process variable crc : slv8 := (others=>'0'); variable dat : slv8 := (others=>'0'); + variable nxt : slv8 := (others=>'0'); variable oline : line; begin for i in 0 to 255 loop crc := (others=>'0'); - dat := conv_std_logic_vector(i,8); - crc8_update(crc, dat); - write(oline, conv_integer(unsigned(crc)), right, 4); + dat := slv(to_unsigned(i,8)); + nxt := crc8_update(crc, dat); + write(oline, to_integer(unsigned(nxt)), right, 4); if i /= 255 then write(oline, string'(",")); end if; diff --git a/rtl/vlib/comlib/misc/gen_crc8_tbl_check.vhd b/rtl/vlib/comlib/misc/gen_crc8_tbl_check.vhd index 6935d886..4f04dec2 100644 --- a/rtl/vlib/comlib/misc/gen_crc8_tbl_check.vhd +++ b/rtl/vlib/comlib/misc/gen_crc8_tbl_check.vhd @@ -1,6 +1,6 @@ --- $Id: gen_crc8_tbl_check.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: gen_crc8_tbl_check.vhd 410 2011-09-18 11:23:09Z mueller $ -- --- Copyright 2007- by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,19 +19,15 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-09-17 410 1.1 use now 'A6' polynomial of Koopman et al. -- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned -- 2007-07-08 65 1.0 Initial version ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_textio.all; use std.textio.all; ---use work.slvtypes.all; ---use work.comlib.all; - entity gen_crc8_tbl_check is end gen_crc8_tbl_check; @@ -42,40 +38,40 @@ begin type crc8_tbl_type is array (0 to 255) of integer; variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl - ( 0, 29, 58, 39, 116, 105, 78, 83, - 232, 245, 210, 207, 156, 129, 166, 187, - 205, 208, 247, 234, 185, 164, 131, 158, - 37, 56, 31, 2, 81, 76, 107, 118, - 135, 154, 189, 160, 243, 238, 201, 212, - 111, 114, 85, 72, 27, 6, 33, 60, - 74, 87, 112, 109, 62, 35, 4, 25, - 162, 191, 152, 133, 214, 203, 236, 241, - 19, 14, 41, 52, 103, 122, 93, 64, - 251, 230, 193, 220, 143, 146, 181, 168, - 222, 195, 228, 249, 170, 183, 144, 141, - 54, 43, 12, 17, 66, 95, 120, 101, - 148, 137, 174, 179, 224, 253, 218, 199, - 124, 97, 70, 91, 8, 21, 50, 47, - 89, 68, 99, 126, 45, 48, 23, 10, - 177, 172, 139, 150, 197, 216, 255, 226, - 38, 59, 28, 1, 82, 79, 104, 117, - 206, 211, 244, 233, 186, 167, 128, 157, - 235, 246, 209, 204, 159, 130, 165, 184, - 3, 30, 57, 36, 119, 106, 77, 80, - 161, 188, 155, 134, 213, 200, 239, 242, - 73, 84, 115, 110, 61, 32, 7, 26, - 108, 113, 86, 75, 24, 5, 34, 63, - 132, 153, 190, 163, 240, 237, 202, 215, - 53, 40, 15, 18, 65, 92, 123, 102, - 221, 192, 231, 250, 169, 180, 147, 142, - 248, 229, 194, 223, 140, 145, 182, 171, - 16, 13, 42, 55, 100, 121, 94, 67, - 178, 175, 136, 149, 198, 219, 252, 225, - 90, 71, 96, 125, 46, 51, 20, 9, - 127, 98, 69, 88, 11, 22, 49, 44, - 151, 138, 173, 176, 227, 254, 217, 196 - ); - + ( 0, 77, 154, 215, 121, 52, 227, 174, + 242, 191, 104, 37, 139, 198, 17, 92, + 169, 228, 51, 126, 208, 157, 74, 7, + 91, 22, 193, 140, 34, 111, 184, 245, + 31, 82, 133, 200, 102, 43, 252, 177, + 237, 160, 119, 58, 148, 217, 14, 67, + 182, 251, 44, 97, 207, 130, 85, 24, + 68, 9, 222, 147, 61, 112, 167, 234, + 62, 115, 164, 233, 71, 10, 221, 144, + 204, 129, 86, 27, 181, 248, 47, 98, + 151, 218, 13, 64, 238, 163, 116, 57, + 101, 40, 255, 178, 28, 81, 134, 203, + 33, 108, 187, 246, 88, 21, 194, 143, + 211, 158, 73, 4, 170, 231, 48, 125, + 136, 197, 18, 95, 241, 188, 107, 38, + 122, 55, 224, 173, 3, 78, 153, 212, + 124, 49, 230, 171, 5, 72, 159, 210, + 142, 195, 20, 89, 247, 186, 109, 32, + 213, 152, 79, 2, 172, 225, 54, 123, + 39, 106, 189, 240, 94, 19, 196, 137, + 99, 46, 249, 180, 26, 87, 128, 205, + 145, 220, 11, 70, 232, 165, 114, 63, + 202, 135, 80, 29, 179, 254, 41, 100, + 56, 117, 162, 239, 65, 12, 219, 150, + 66, 15, 216, 149, 59, 118, 161, 236, + 176, 253, 42, 103, 201, 132, 83, 30, + 235, 166, 113, 60, 146, 223, 8, 69, + 25, 84, 131, 206, 96, 45, 250, 183, + 93, 16, 199, 138, 36, 105, 190, 243, + 175, 226, 53, 120, 214, 155, 76, 1, + 244, 185, 110, 35, 141, 192, 23, 90, + 6, 75, 156, 209, 127, 50, 229, 168 + ); + variable crc : integer := 0; variable oline : line; diff --git a/rtl/vlib/genlib/clkdivce.vhd b/rtl/vlib/genlib/clkdivce.vhd index fbee166b..75e9fed9 100644 --- a/rtl/vlib/genlib/clkdivce.vhd +++ b/rtl/vlib/genlib/clkdivce.vhd @@ -1,6 +1,6 @@ --- $Id: clkdivce.vhd 341 2010-11-27 23:05:43Z mueller $ +-- $Id: clkdivce.vhd 418 2011-10-23 20:11:40Z mueller $ -- --- Copyright 2007-2008 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,9 +18,10 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-10-22 418 1.0.3 now numeric_std clean -- 2008-01-20 112 1.0.2 rename clkgen->clkdivce; remove SYS_CLK port -- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned -- 2007-06-30 62 1.0 Initial version @@ -28,7 +29,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; @@ -55,8 +56,8 @@ architecture syn of clkdivce is end record regs_type; constant regs_init : regs_type := ( - conv_std_logic_vector(USECDIV-1,CDUWIDTH), - conv_std_logic_vector(MSECDIV-1,10), + slv(to_unsigned(USECDIV-1,CDUWIDTH)), + slv(to_unsigned(MSECDIV-1,10)), '0','0' ); @@ -73,7 +74,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then R_REGS <= N_REGS; end if; @@ -92,14 +93,14 @@ begin n.usec := '0'; n.msec := '0'; - n.ucnt := unsigned(r.ucnt) - 1; + n.ucnt := slv(unsigned(r.ucnt) - 1); if unsigned(r.ucnt) = 0 then n.usec := '1'; - n.ucnt := conv_std_logic_vector(USECDIV-1,CDUWIDTH); - n.mcnt := unsigned(r.mcnt) - 1; + n.ucnt := slv(to_unsigned(USECDIV-1,CDUWIDTH)); + n.mcnt := slv(unsigned(r.mcnt) - 1); if unsigned(r.mcnt) = 0 then n.msec := '1'; - n.mcnt := conv_std_logic_vector(MSECDIV-1,10); + n.mcnt := slv(to_unsigned(MSECDIV-1,10)); end if; end if; diff --git a/rtl/vlib/genlib/debounce_gen.vhd b/rtl/vlib/genlib/debounce_gen.vhd index e3129750..fb86d190 100644 --- a/rtl/vlib/genlib/debounce_gen.vhd +++ b/rtl/vlib/genlib/debounce_gen.vhd @@ -1,6 +1,6 @@ --- $Id: debounce_gen.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: debounce_gen.vhd 418 2011-10-23 20:11:40Z mueller $ -- --- Copyright 2007- by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,9 +18,10 @@ -- Dependencies: - -- Test bench: tb/tb_debounce_gen -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-10-22 418 1.0.3 now numeric_std clean -- 2007-12-26 105 1.0.2 add default for RESET -- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned -- 2007-06-29 61 1.0 Initial version @@ -28,7 +29,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; @@ -76,7 +77,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then R_REGS.cecnt <= cntzero; R_REGS.dref <= DI; @@ -107,7 +108,7 @@ begin if CE_INT = '1' then if unsigned(r.cecnt) = 0 then - n.cecnt := conv_std_logic_vector(CEDIV-1,CWIDTH); + n.cecnt := slv(to_unsigned(CEDIV-1,CWIDTH)); n.dref := DI; n.dchange := datazero; for i in DI'range loop @@ -117,7 +118,7 @@ begin end loop; else - n.cecnt := unsigned(r.cecnt) - 1; + n.cecnt := slv(unsigned(r.cecnt) - 1); end if; end if; diff --git a/rtl/vlib/genlib/genlib.vhd b/rtl/vlib/genlib/genlib.vhd index 7526c01f..16ba7cfd 100644 --- a/rtl/vlib/genlib/genlib.vhd +++ b/rtl/vlib/genlib/genlib.vhd @@ -1,6 +1,6 @@ --- $Id: genlib.vhd 389 2011-07-07 21:59:00Z mueller $ +-- $Id: genlib.vhd 422 2011-11-10 18:44:06Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,6 +19,7 @@ -- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 -- Revision History: -- Date Rev Version Comment +-- 2011-11-09 421 1.0.8 add cdc_pulse -- 2010-04-17 277 1.0.7 timer: no default for START,DONE,BUSY; drop STOP -- 2010-04-02 273 1.0.6 add timer -- 2008-01-20 112 1.0.5 rename clkgen->clkdivce @@ -153,4 +154,18 @@ component timer is -- retriggerable timer ); end component; +component cdc_pulse is -- clock domain cross for pulse + generic ( + POUT_SINGLE : boolean := false; -- if true: single cycle pout + BUSY_WACK : boolean := false); -- if true: busy waits for ack + port ( + CLKM : in slbit; -- clock master + RESET : in slbit := '0'; -- M|reset + CLKS : in slbit; -- clock slave + PIN : in slbit; -- M|pulse in + BUSY : out slbit; -- M|busy + POUT : out slbit -- S|pulse out + ); +end component; + end package genlib; diff --git a/rtl/vlib/memlib/fifo_1c_dram.vhd b/rtl/vlib/memlib/fifo_1c_dram.vhd index 286564ff..70c86b49 100644 --- a/rtl/vlib/memlib/fifo_1c_dram.vhd +++ b/rtl/vlib/memlib/fifo_1c_dram.vhd @@ -1,4 +1,4 @@ --- $Id: fifo_1c_dram.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: fifo_1c_dram.vhd 421 2011-11-07 21:23:50Z mueller $ -- -- Copyright 2007- by Walter F.J. Mueller -- @@ -36,7 +36,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; use work.slvtypes.all; use work.memlib.all; diff --git a/rtl/vlib/memlib/fifo_1c_dram_raw.vhd b/rtl/vlib/memlib/fifo_1c_dram_raw.vhd index 68a2373e..de5ec030 100644 --- a/rtl/vlib/memlib/fifo_1c_dram_raw.vhd +++ b/rtl/vlib/memlib/fifo_1c_dram_raw.vhd @@ -1,6 +1,6 @@ --- $Id: fifo_1c_dram_raw.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: fifo_1c_dram_raw.vhd 421 2011-11-07 21:23:50Z mueller $ -- --- Copyright 2007- by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,16 +20,17 @@ -- -- Test bench: tb/tb_fifo_1c_dram -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-07 421 1.0.2 now numeric_std clean -- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned -- 2007-06-03 47 1.0 Initial version ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.memlib.all; @@ -63,9 +64,9 @@ architecture syn of fifo_1c_dram_raw is constant memsize : positive := 2**AWIDTH; constant regs_init : regs_type := ( - conv_std_logic_vector(0,AWIDTH), - conv_std_logic_vector(0,AWIDTH), - '1','0' + slv(to_unsigned(0,AWIDTH)), -- waddr + slv(to_unsigned(0,AWIDTH)), -- raddr + '1','0' -- empty,full ); signal R_REGS : regs_type := regs_init; -- state registers @@ -92,7 +93,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then R_REGS <= N_REGS; end if; @@ -116,7 +117,7 @@ begin re_val := RE and not r.empty; we_val := WE and ((not r.full) or RE); - isize := unsigned(r.waddr) - unsigned(r.raddr); + isize := slv(unsigned(r.waddr) - unsigned(r.raddr)); iram_we := '0'; if RESET = '1' then @@ -125,7 +126,7 @@ begin else if we_val = '1' then - n.waddr := unsigned(r.waddr) + 1; + n.waddr := slv(unsigned(r.waddr) + 1); iram_we := '1'; if re_val = '0' then n.empty := '0'; @@ -136,7 +137,7 @@ begin end if; if re_val = '1' then - n.raddr := unsigned(r.raddr) + 1; + n.raddr := slv(unsigned(r.raddr) + 1); if we_val = '0' then n.full := '0'; if unsigned(isize) = 1 then diff --git a/rtl/vlib/memlib/memlib.vhd b/rtl/vlib/memlib/memlib.vhd index 2a7bdb9c..c05c0428 100644 --- a/rtl/vlib/memlib/memlib.vhd +++ b/rtl/vlib/memlib/memlib.vhd @@ -1,4 +1,4 @@ --- $Id: memlib.vhd 389 2011-07-07 21:59:00Z mueller $ +-- $Id: memlib.vhd 424 2011-11-13 16:38:23Z mueller $ -- -- Copyright 2006-2007 by Walter F.J. Mueller -- @@ -17,7 +17,7 @@ -- asynchronus rams; Fifo's. -- -- Dependencies: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment -- 2008-03-08 123 1.0.3 add ram_2swsr_xfirst_gen_unisim @@ -222,16 +222,16 @@ component fifo_2c_dram is -- fifo, 2 clock, dram based port ( CLKW : in slbit; -- clock (write side) CLKR : in slbit; -- clock (read side) - RESETW : in slbit; -- reset (synchronous with CLKW) - RESETR : in slbit; -- reset (synchronous with CLKR) - DI : in slv(DWIDTH-1 downto 0); -- input data - ENA : in slbit; -- write enable - BUSY : out slbit; -- write port hold - DO : out slv(DWIDTH-1 downto 0); -- output data - VAL : out slbit; -- read valid - HOLD : in slbit; -- read hold - SIZEW : out slv(AWIDTH-1 downto 0); -- number slots to write (synch w/ CLKW) - SIZER : out slv(AWIDTH-1 downto 0) -- number slots to read (synch w/ CLKR) + RESETW : in slbit; -- W|reset from write side + RESETR : in slbit; -- R|reset from read side + DI : in slv(DWIDTH-1 downto 0); -- W|input data + ENA : in slbit; -- W|write enable + BUSY : out slbit; -- W|write port hold + DO : out slv(DWIDTH-1 downto 0); -- R|output data + VAL : out slbit; -- R|read valid + HOLD : in slbit; -- R|read hold + SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write + SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read ); end component; diff --git a/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd b/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd index ae7458f2..110cf1cc 100644 --- a/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd +++ b/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd @@ -1,6 +1,6 @@ --- $Id: ram_1swar_1ar_gen.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: ram_1swar_1ar_gen.vhd 422 2011-11-10 18:44:06Z mueller $ -- --- Copyright 2006-2008 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -22,10 +22,11 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment --- 2008-03-08 123 1.0.1 use std_logic_arith, not _unsigned; use unsigned() +-- 2011-11-08 422 1.0.2 now numeric_std clean +-- 2008-03-08 123 1.0.1 use std_..._arith, not _unsigned; use unsigned() -- 2007-06-03 45 1.0 Initial version -- -- Some synthesis results: @@ -42,7 +43,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; @@ -75,14 +76,14 @@ begin proc_clk: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if WE = '1' then - RAM(conv_integer(unsigned(ADDRA))) <= DI; + RAM(to_integer(unsigned(ADDRA))) <= DI; end if; end if; end process proc_clk; - DOA <= RAM(conv_integer(unsigned(ADDRA))); - DOB <= RAM(conv_integer(unsigned(ADDRB))); + DOA <= RAM(to_integer(unsigned(ADDRA))); + DOB <= RAM(to_integer(unsigned(ADDRB))); end syn; diff --git a/rtl/vlib/memlib/ram_1swar_gen.vhd b/rtl/vlib/memlib/ram_1swar_gen.vhd index 6db9eeb1..ac1459f4 100644 --- a/rtl/vlib/memlib/ram_1swar_gen.vhd +++ b/rtl/vlib/memlib/ram_1swar_gen.vhd @@ -1,6 +1,6 @@ --- $Id: ram_1swar_gen.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: ram_1swar_gen.vhd 422 2011-11-10 18:44:06Z mueller $ -- --- Copyright 2006-2008 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -22,10 +22,11 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment --- 2008-03-08 123 1.0.1 use std_logic_arith, not _unsigned; use unsigned() +-- 2011-11-08 422 1.0.2 now numeric_std clean +-- 2008-03-08 123 1.0.1 use std_..._arith, not _unsigned; use unsigned() -- 2007-06-03 45 1.0 Initial version -- -- Some synthesis results: @@ -38,7 +39,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; @@ -69,13 +70,13 @@ begin proc_clk: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if WE = '1' then - RAM(conv_integer(unsigned(ADDR))) <= DI; + RAM(to_integer(unsigned(ADDR))) <= DI; end if; end if; end process proc_clk; - DO <= RAM(conv_integer(unsigned(ADDR))); + DO <= RAM(to_integer(unsigned(ADDR))); end syn; diff --git a/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd b/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd index b469762e..7bae823d 100644 --- a/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd +++ b/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd @@ -1,6 +1,6 @@ --- $Id: ram_1swsr_wfirst_gen.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: ram_1swsr_wfirst_gen.vhd 422 2011-11-10 18:44:06Z mueller $ -- --- Copyright 2006-2010 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -27,18 +27,19 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-08 422 1.0.4 now numeric_std clean -- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables --- 2008-03-08 123 1.0.2 use std_logic_arith, not _unsigned; use unsigned(); +-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned(); -- 2008-03-02 122 1.0.1 change generic default for BRAM models -- 2007-06-03 45 1.0 Initial version ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; @@ -73,12 +74,12 @@ begin proc_clk: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if EN = '1' then if WE = '1' then - sv_ram(conv_integer(unsigned(ADDR))) := DI; + sv_ram(to_integer(unsigned(ADDR))) := DI; end if; - R_DO <= sv_ram(conv_integer(unsigned(ADDR))); + R_DO <= sv_ram(to_integer(unsigned(ADDR))); end if; end if; end process proc_clk; diff --git a/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd b/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd index 2ed3244f..59e43e1a 100644 --- a/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd +++ b/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd @@ -1,6 +1,6 @@ --- $Id: ram_2swsr_rfirst_gen.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: ram_2swsr_rfirst_gen.vhd 422 2011-11-10 18:44:06Z mueller $ -- --- Copyright 2006-2010 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -22,11 +22,12 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-08 422 1.0.4 now numeric_std clean -- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables --- 2008-03-08 123 1.0.2 use std_logic_arith, not _unsigned; use unsigned(); +-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned(); -- now initialize DO to all '0' at start -- 2008-03-02 122 1.0.1 change generic default for BRAM models -- 2007-06-03 45 1.0 Initial version @@ -34,7 +35,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; @@ -75,11 +76,11 @@ begin proc_clka: process (CLKA) begin - if CLKA'event and CLKA='1' then + if rising_edge(CLKA) then if ENA = '1' then - R_DOA <= sv_ram(conv_integer(unsigned(ADDRA))); + R_DOA <= sv_ram(to_integer(unsigned(ADDRA))); if WEA = '1' then - sv_ram(conv_integer(unsigned(ADDRA))) := DIA; + sv_ram(to_integer(unsigned(ADDRA))) := DIA; end if; end if; end if; @@ -87,11 +88,11 @@ begin proc_clkb: process (CLKB) begin - if CLKB'event and CLKB='1' then + if rising_edge(CLKB) then if ENB = '1' then - R_DOB <= sv_ram(conv_integer(unsigned(ADDRB))); + R_DOB <= sv_ram(to_integer(unsigned(ADDRB))); if WEB = '1' then - sv_ram(conv_integer(unsigned(ADDRB))) := DIB; + sv_ram(to_integer(unsigned(ADDRB))) := DIB; end if; end if; end if; diff --git a/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd b/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd index fc2010b1..c4e0e035 100644 --- a/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd +++ b/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd @@ -1,6 +1,6 @@ --- $Id: ram_2swsr_wfirst_gen.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: ram_2swsr_wfirst_gen.vhd 422 2011-11-10 18:44:06Z mueller $ -- --- Copyright 2006-2010 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -22,18 +22,19 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-08 422 1.0.4 now numeric_std clean -- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables --- 2008-03-08 123 1.0.2 use std_logic_arith, not _unsigned; use unsigned(); +-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned(); -- 2008-03-02 122 1.0.1 change generic default for BRAM models -- 2007-06-03 45 1.0 Initial version ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; @@ -73,24 +74,24 @@ begin proc_clka: process (CLKA) begin - if CLKA'event and CLKA='1' then + if rising_edge(CLKA) then if ENA = '1' then if WEA = '1' then - sv_ram(conv_integer(unsigned(ADDRA))) := DIA; + sv_ram(to_integer(unsigned(ADDRA))) := DIA; end if; - R_DOA <= sv_ram(conv_integer(unsigned(ADDRA))); + R_DOA <= sv_ram(to_integer(unsigned(ADDRA))); end if; end if; end process proc_clka; proc_clkb: process (CLKB) begin - if CLKB'event and CLKB='1' then + if rising_edge(CLKB) then if ENB = '1' then if WEB = '1' then - sv_ram(conv_integer(unsigned(ADDRB))) := DIB; + sv_ram(to_integer(unsigned(ADDRB))) := DIB; end if; - R_DOB <= sv_ram(conv_integer(unsigned(ADDRB))); + R_DOB <= sv_ram(to_integer(unsigned(ADDRB))); end if; end if; end process proc_clkb; diff --git a/rtl/vlib/rbus/rb_mon.vhd b/rtl/vlib/rbus/rb_mon.vhd index 56babf31..103a045b 100644 --- a/rtl/vlib/rbus/rb_mon.vhd +++ b/rtl/vlib/rbus/rb_mon.vhd @@ -1,6 +1,6 @@ --- $Id: rb_mon.vhd 346 2010-12-22 22:59:26Z mueller $ +-- $Id: rb_mon.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -17,10 +17,11 @@ -- -- Dependencies: - -- Test bench: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 3.0.1 now numeric_std clean -- 2010-12-22 346 3.0 renamed rritb_rbmon -> rb_mon -- 2010-06-05 301 2.1.1 renamed _rpmon -> _rbmon -- 2010-06-03 299 2.1 new init encoding (WE=0/1 int/ext) @@ -35,7 +36,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; @@ -99,7 +100,7 @@ begin wait until ENA='1'; -- stall process till enabled end if; - wait until CLK'event and CLK='1'; -- check at end of clock cycle + wait until rising_edge(CLK); -- check at end of clock cycle if RB_MREQ.aval='1' and (RB_MREQ.re='1' or RB_MREQ.we='1') then if RB_SRES.err = '1' then diff --git a/rtl/vlib/rbus/rbd_bram.vhd b/rtl/vlib/rbus/rbd_bram.vhd index ab1fa05f..3675d116 100644 --- a/rtl/vlib/rbus/rbd_bram.vhd +++ b/rtl/vlib/rbus/rbd_bram.vhd @@ -1,6 +1,6 @@ --- $Id: rbd_bram.vhd 372 2011-03-20 22:48:11Z mueller $ +-- $Id: rbd_bram.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,7 +20,7 @@ -- Test bench: rlink/tb/tb_rlink_tba_ttcombo -- -- Target Devices: generic --- Tool versions: xst 12.1; ghdl 0.29 +-- Tool versions: xst 12.1, 13.1; ghdl 0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -28,6 +28,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.0.3 now numeric_std clean -- 2010-12-31 352 1.0.2 simplify irb_ack logic -- 2010-12-29 351 1.0.1 default addr 1111001x->1111010x -- 2010-12-26 349 1.0 Initial version @@ -44,7 +45,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.memlib.all; @@ -53,7 +54,7 @@ use work.rblib.all; entity rbd_bram is -- rbus dev: rbus bram test target -- complete rrirp_aif interface generic ( - RB_ADDR : slv8 := conv_std_logic_vector(2#11110100#,8)); + RB_ADDR : slv8 := slv(to_unsigned(2#11110100#,8))); port ( CLK : in slbit; -- clock RESET : in slbit; -- reset @@ -109,7 +110,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then R_REGS <= regs_init; else @@ -165,7 +166,7 @@ begin if irbena = '1' then -- if request active if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0 - n.cntbusy := unsigned(r.cntbusy) - 1; -- decrement busy timer + n.cntbusy := slv(unsigned(r.cntbusy) - 1); -- decrement busy timer end if; end if; @@ -186,7 +187,7 @@ begin ibramwe := '1'; end if; if irbena = '1' then - n.addr := unsigned(r.addr) + 1; + n.addr := slv(unsigned(r.addr) + 1); end if; end if; diff --git a/rtl/vlib/rbus/rbd_eyemon.vhd b/rtl/vlib/rbus/rbd_eyemon.vhd index 0c639c18..572a20d7 100644 --- a/rtl/vlib/rbus/rbd_eyemon.vhd +++ b/rtl/vlib/rbus/rbd_eyemon.vhd @@ -1,4 +1,4 @@ --- $Id: rbd_eyemon.vhd 406 2011-08-14 21:06:44Z mueller $ +-- $Id: rbd_eyemon.vhd 427 2011-11-19 21:04:11Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 12.1; ghdl 0.29 +-- Tool versions: xst 12.1, 13.1; ghdl 0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -29,6 +29,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.0.3 now numeric_std clean -- 2011-04-02 375 1.0.2 handle back-to-back chars properly (in sim..) -- 2010-12-31 352 1.0.1 simplify irb_ack logic -- 2010-12-27 349 1.0 Initial version @@ -56,7 +57,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.memlib.all; @@ -64,8 +65,8 @@ use work.rblib.all; entity rbd_eyemon is -- rbus dev: eye monitor for serport's generic ( - RB_ADDR : slv8 := conv_std_logic_vector(2#11111000#,8); - RDIV : slv8 := conv_std_logic_vector(0,8)); + RB_ADDR : slv8 := slv(to_unsigned(2#11111000#,8)); + RDIV : slv8 := slv(to_unsigned(0,8))); port ( CLK : in slbit; -- clock RESET : in slbit; -- reset @@ -160,7 +161,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then R_REGS <= regs_init; else @@ -313,7 +314,7 @@ begin laddr_inc := '1'; end if; else - n.rdivcnt := unsigned(r.rdivcnt) - 1; + n.rdivcnt := slv(unsigned(r.rdivcnt) - 1); end if; when s_clr => -- s_clr: clear memory --------------- @@ -333,7 +334,7 @@ begin elsif laddr_clr = '1' then n.laddr := (others=>'0'); elsif laddr_inc = '1' then - n.laddr := unsigned(r.laddr) + 1; + n.laddr := slv(unsigned(r.laddr) + 1); end if; n.laddr_1 := r.laddr; @@ -341,7 +342,7 @@ begin ibramdi := (others=>'0'); if r.memclr = '0' then - ibramdi := unsigned(BRAM_DOA) + 1; + ibramdi := slv(unsigned(BRAM_DOA) + 1); end if; N_REGS <= n; diff --git a/rtl/vlib/rbus/rbd_rbmon.vhd b/rtl/vlib/rbus/rbd_rbmon.vhd index 6e9b0623..e2fe6582 100644 --- a/rtl/vlib/rbus/rbd_rbmon.vhd +++ b/rtl/vlib/rbus/rbd_rbmon.vhd @@ -1,4 +1,4 @@ --- $Id: rbd_rbmon.vhd 387 2011-07-03 17:24:52Z mueller $ +-- $Id: rbd_rbmon.vhd 427 2011-11-19 21:04:11Z mueller $ -- -- Copyright 2010-2011 by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- Test bench: rlink/tb/tb_rlink_tba_ttcombo -- -- Target Devices: generic --- Tool versions: xst 12.1; ghdl 0.29 +-- Tool versions: xst 12.1, 13.1; ghdl 0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -28,6 +28,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.0.3 now numeric_std clean -- 2011-03-27 374 1.0.2 rename ncyc -> nbusy because it counts busy cycles -- 2010-12-31 352 1.0.1 simplify irb_ack logic -- 2010-12-27 349 1.0 Initial version @@ -63,7 +64,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.memlib.all; @@ -71,7 +72,7 @@ use work.rblib.all; entity rbd_rbmon is -- rbus dev: rbus monitor generic ( - RB_ADDR : slv8 := conv_std_logic_vector(2#11111100#,8); + RB_ADDR : slv8 := slv(to_unsigned(2#11111100#,8)); AWIDTH : positive := 9); port ( CLK : in slbit; -- clock @@ -197,7 +198,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then R_REGS <= regs_init; else @@ -282,7 +283,7 @@ begin irb_err := '1'; end if; if RB_MREQ.re = '1' then - n.waddr := unsigned(r.waddr) + 1; + n.waddr := slv(unsigned(r.waddr) + 1); if r.waddr = "11" then laddr_inc := '1'; end if; @@ -352,7 +353,7 @@ begin n.rberr := '1'; end if; if r.rbnbusy /= rbnbusylast then -- and count - n.rbnbusy := unsigned(r.rbnbusy) + 1; + n.rbnbusy := slv(unsigned(r.rbnbusy) + 1); end if; end if; n.rbnak := not RB_SRES_SUM.ack; @@ -368,13 +369,13 @@ begin n.rbndly := (others=>'0'); -- clear delay counter else -- just idle if r.rbndly /= rbndlylast then -- count cycles - n.rbndly := unsigned(r.rbndly) + 1; + n.rbndly := slv(unsigned(r.rbndly) + 1); end if; end if; end if; if laddr_inc = '1' then - n.laddr := unsigned(r.laddr) + 1; + n.laddr := slv(unsigned(r.laddr) + 1); if r.go='1' and r.laddr=laddrlast then n.wrap := '1'; end if; diff --git a/rtl/vlib/rbus/rbd_tester.vhd b/rtl/vlib/rbus/rbd_tester.vhd index 631a3624..1f8f1afd 100644 --- a/rtl/vlib/rbus/rbd_tester.vhd +++ b/rtl/vlib/rbus/rbd_tester.vhd @@ -1,6 +1,6 @@ --- $Id: rbd_tester.vhd 369 2011-03-13 22:39:26Z mueller $ +-- $Id: rbd_tester.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,7 +20,7 @@ -- Test bench: rlink/tb/tb_rlink (used as test target) -- -- Target Devices: generic --- Tool versions: xst 12.1; ghdl 0.29 +-- Tool versions: xst 12.1, 13.1; ghdl 0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -29,6 +29,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.0.4 now numeric_std clean -- 2010-12-31 352 1.0.3 simplify irb_ack logic -- 2010-12-29 351 1.0.2 default addr 111101xx->111100xx -- 2010-12-12 344 1.0.1 send 0101.. on busy or err; fix init and busy logic @@ -51,7 +52,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.memlib.all; @@ -60,7 +61,7 @@ use work.rblib.all; entity rbd_tester is -- rbus dev: rbus tester -- complete rrirp_aif interface generic ( - RB_ADDR : slv8 := conv_std_logic_vector(2#11110000#,8)); + RB_ADDR : slv8 := slv(to_unsigned(2#11110000#,8))); port ( CLK : in slbit; -- clock RESET : in slbit; -- reset @@ -146,7 +147,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then R_REGS <= regs_init; else @@ -208,10 +209,10 @@ begin if irbena = '1' then -- if request active if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0 - n.cntbusy := unsigned(r.cntbusy) - 1; -- decrement busy timer + n.cntbusy := slv(unsigned(r.cntbusy) - 1); -- decrement busy timer end if; if r.cntcyc /= cntcyc_max then -- if cycle counter < max - n.cntcyc := unsigned(r.cntcyc) + 1; -- increment cycle counter + n.cntcyc := slv(unsigned(r.cntcyc) + 1); -- increment cycle counter end if; end if; diff --git a/rtl/vlib/rbus/rbd_timer.vhd b/rtl/vlib/rbus/rbd_timer.vhd index e849b71d..65c5702a 100644 --- a/rtl/vlib/rbus/rbd_timer.vhd +++ b/rtl/vlib/rbus/rbd_timer.vhd @@ -1,6 +1,6 @@ --- $Id: rbd_timer.vhd 351 2010-12-30 21:50:54Z mueller $ +-- $Id: rbd_timer.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,7 +20,7 @@ -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 12.1; ghdl 0.29 +-- Tool versions: xst 12.1, 13.1; ghdl 0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -28,6 +28,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.0.1 now numeric_std clean -- 2010-12-29 351 1.0 Initial version ------------------------------------------------------------------------------ -- @@ -40,14 +41,14 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.rblib.all; entity rbd_timer is -- rbus dev: usec precision timer generic ( - RB_ADDR : slv8 := conv_std_logic_vector(2#00000000#,8)); + RB_ADDR : slv8 := slv(to_unsigned(2#00000000#,8))); port ( CLK : in slbit; -- clock CE_USEC : in slbit; -- usec pulse @@ -82,7 +83,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then R_REGS <= regs_init; else @@ -132,7 +133,7 @@ begin n.timer_act := '0'; -- mark unactive n.timer_end := '1'; -- send end marker else -- else: timer not at end - n.timer := unsigned(r.timer) - 1; -- decrement + n.timer := slv(unsigned(r.timer) - 1); -- decrement end if; end if; end if; diff --git a/rtl/vlib/rbus/rbdlib.vhd b/rtl/vlib/rbus/rbdlib.vhd index cd8631b6..9281c9c1 100644 --- a/rtl/vlib/rbus/rbdlib.vhd +++ b/rtl/vlib/rbus/rbdlib.vhd @@ -1,6 +1,6 @@ --- $Id: rbdlib.vhd 351 2010-12-30 21:50:54Z mueller $ +-- $Id: rbdlib.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,10 +16,11 @@ -- Description: Definitions for rbus devices -- -- Dependencies: - --- Tool versions: xst 12.1; ghdl 0.29 +-- Tool versions: xst 12.1, 13.1; ghdl 0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.2.1 now numeric_std clean -- 2010-12-29 351 1.2 new address layout; add rbd_timer -- 2010-12-27 349 1.1 now correct defs for _rbmon and _eyemon -- 2010-12-04 343 1.0 Initial version @@ -37,17 +38,26 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.rblib.all; package rbdlib is + +-- ise 13.1 xst can bug check if generic defaults in a package are defined via +-- 'slv(to_unsigned())'. The conv_ construct prior to numeric_std was ok. +-- As workaround the ibus default addresses are defined here as constant. +constant rbaddr_tester : slv8 := slv(to_unsigned(2#11110000#,8)); +constant rbaddr_bram : slv8 := slv(to_unsigned(2#11110100#,8)); +constant rbaddr_rbmon : slv8 := slv(to_unsigned(2#11111100#,8)); +constant rbaddr_eyemon : slv8 := slv(to_unsigned(2#11111000#,8)); +constant rbaddr_timer : slv8 := slv(to_unsigned(2#00000000#,8)); component rbd_tester is -- rbus dev: rbus tester -- complete rbus_aif interface generic ( - RB_ADDR : slv8 := conv_std_logic_vector(2#11110000#,8)); + RB_ADDR : slv8 := rbaddr_tester); port ( CLK : in slbit; -- clock RESET : in slbit; -- reset @@ -61,7 +71,7 @@ end component; component rbd_bram is -- rbus dev: bram test target -- incomplete rbus_aif interface generic ( - RB_ADDR : slv8 := conv_std_logic_vector(2#11110100#,8)); + RB_ADDR : slv8 := rbaddr_bram); port ( CLK : in slbit; -- clock RESET : in slbit; -- reset @@ -72,7 +82,7 @@ end component; component rbd_rbmon is -- rbus dev: rbus monitor generic ( - RB_ADDR : slv8 := conv_std_logic_vector(2#11111100#,8); + RB_ADDR : slv8 := rbaddr_rbmon; AWIDTH : positive := 9); port ( CLK : in slbit; -- clock @@ -85,8 +95,8 @@ end component; component rbd_eyemon is -- rbus dev: eye monitor for serport's generic ( - RB_ADDR : slv8 := conv_std_logic_vector(2#11111000#,8); - RDIV : slv8 := conv_std_logic_vector(0,8)); + RB_ADDR : slv8 := rbaddr_eyemon; + RDIV : slv8 := (others=>'0')); port ( CLK : in slbit; -- clock RESET : in slbit; -- reset @@ -99,7 +109,7 @@ end component; component rbd_timer is -- rbus dev: usec precision timer generic ( - RB_ADDR : slv8 := conv_std_logic_vector(2#00000000#,8)); + RB_ADDR : slv8 := rbaddr_timer); port ( CLK : in slbit; -- clock CE_USEC : in slbit; -- usec pulse diff --git a/rtl/vlib/rlink/rlink_base.vhd b/rtl/vlib/rlink/rlink_base.vhd index a08130f6..0e0d9be2 100644 --- a/rtl/vlib/rlink/rlink_base.vhd +++ b/rtl/vlib/rlink/rlink_base.vhd @@ -1,6 +1,6 @@ --- $Id: rlink_base.vhd 350 2010-12-28 16:40:11Z mueller $ +-- $Id: rlink_base.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -24,7 +24,7 @@ -- tb/tb_rlink_tba_ttcombo -- -- Target Devices: generic --- Tool versions: xst 12.1; ghdl 0.29 +-- Tool versions: xst 12.1, 13.1; ghdl 0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri ifa ofa @@ -33,12 +33,13 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 1.0.1 now numeric_std clean -- 2010-12-25 348 1.0 Initial version ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.rblib.all; diff --git a/rtl/vlib/rlink/rlink_base_serport.vhd b/rtl/vlib/rlink/rlink_base_serport.vhd index 917f0bc6..8c0d5590 100644 --- a/rtl/vlib/rlink/rlink_base_serport.vhd +++ b/rtl/vlib/rlink/rlink_base_serport.vhd @@ -1,6 +1,6 @@ --- $Id: rlink_base_serport.vhd 350 2010-12-28 16:40:11Z mueller $ +-- $Id: rlink_base_serport.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -32,6 +32,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 3.1.1 now numeric_std clean -- 2010-12-26 348 3.1 rename from rlink_core_serport, use now rlink_base -- 2010-12-24 347 3.0.1 rename: CP_*->RL->* -- 2010-12-04 343 3.0 renamed rri_ -> rlink_ @@ -45,7 +46,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.rblib.all; @@ -60,7 +61,7 @@ entity rlink_base_serport is -- rlink base+serport combo OFAWIDTH : natural := 5; -- output fifo address width (0=none) ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none) ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none) - RB_ADDR : slv8 := conv_std_logic_vector(2#11111110#,8); + RB_ADDR : slv8 := slv(to_unsigned(2#11111110#,8)); CDWIDTH : positive := 13; -- clk divider width CDINIT : natural := 15); -- clk divider initial/reset setting port ( diff --git a/rtl/vlib/rlink/rlink_core.vhd b/rtl/vlib/rlink/rlink_core.vhd index 0fd792cc..2c304b73 100644 --- a/rtl/vlib/rlink/rlink_core.vhd +++ b/rtl/vlib/rlink/rlink_core.vhd @@ -1,6 +1,6 @@ --- $Id: rlink_core.vhd 350 2010-12-28 16:40:11Z mueller $ +-- $Id: rlink_core.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -22,7 +22,7 @@ -- tb/tb_rlink_tba_ttcombo -- -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -33,6 +33,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 3.1.3 now numeric_std clean -- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core; -- 2010-12-24 347 3.1.1 rename: CP_*->RL->* -- 2010-12-22 346 3.1 wblk dcrc error: send nak, transit to s_error now; @@ -162,7 +163,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.comlib.all; @@ -326,7 +327,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then R_REGS <= regs_init; else @@ -773,7 +774,7 @@ begin end if; when s_blk => -- s_blk: block count handling ------- - n.cnt := unsigned(r.cnt) - 1; -- decrement transfer count + n.cnt := slv(unsigned(r.cnt) - 1);-- decrement transfer count if unsigned(r.cnt) = 0 then -- if last transfer if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk n.state := s_txstat; -- next: send stat @@ -852,14 +853,14 @@ begin if ato_go = '0' then -- handle access timeout counter n.atocnt := atocnt_init; -- if ato_go=0, keep in reset else - n.atocnt := unsigned(r.atocnt) - 1;-- otherwise count down + n.atocnt := slv(unsigned(r.atocnt) - 1);-- otherwise count down end if; if ito_go = '0' then -- handle idle timeout counter n.itocnt := r.itoval; -- if ito_go=0, keep at start value else if CE_INT = '1' then - n.itocnt := unsigned(r.itocnt) - 1;-- otherwise count down every CE_INT + n.itocnt := slv(unsigned(r.itocnt) - 1);-- otherwise cnt dn every CE_INT end if; end if; diff --git a/rtl/vlib/rlink/rlink_mon.vhd b/rtl/vlib/rlink/rlink_mon.vhd index a994c70f..64b922f6 100644 --- a/rtl/vlib/rlink/rlink_mon.vhd +++ b/rtl/vlib/rlink/rlink_mon.vhd @@ -1,6 +1,6 @@ --- $Id: rlink_mon.vhd 348 2010-12-26 15:23:44Z mueller $ +-- $Id: rlink_mon.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -17,10 +17,11 @@ -- -- Dependencies: - -- Test bench: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 3.0.2 now numeric_std clean -- 2010-12-24 347 3.0.1 rename: CP_*->RL->* -- 2010-12-22 346 3.0 renamed rritb_cpmon -> rlink_mon -- 2010-06-11 303 2.5.1 fix data9 assignment, always proper width now @@ -31,7 +32,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; @@ -117,7 +118,7 @@ begin wait until ENA='1'; -- stall process till enabled end if; - wait until CLK'event and CLK='1'; -- check at end of clock cycle + wait until rising_edge(CLK); -- check at end of clock cycle if RL_ENA = '1' then if RL_BUSY = '1' then diff --git a/rtl/vlib/rlink/rlink_mon_sb.vhd b/rtl/vlib/rlink/rlink_mon_sb.vhd index 53f083fb..0feb56ee 100644 --- a/rtl/vlib/rlink/rlink_mon_sb.vhd +++ b/rtl/vlib/rlink/rlink_mon_sb.vhd @@ -1,4 +1,4 @@ --- $Id: rlink_mon_sb.vhd 347 2010-12-24 12:10:42Z mueller $ +-- $Id: rlink_mon_sb.vhd 427 2011-11-19 21:04:11Z mueller $ -- -- Copyright 2007-2010 by Walter F.J. Mueller -- @@ -17,7 +17,7 @@ -- -- Dependencies: simbus -- Test bench: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/vlib/rlink/rlink_rlb2rl.vhd b/rtl/vlib/rlink/rlink_rlb2rl.vhd index b589243a..e0d710b6 100644 --- a/rtl/vlib/rlink/rlink_rlb2rl.vhd +++ b/rtl/vlib/rlink/rlink_rlb2rl.vhd @@ -1,4 +1,4 @@ --- $Id: rlink_rlb2rl.vhd 350 2010-12-28 16:40:11Z mueller $ +-- $Id: rlink_rlb2rl.vhd 427 2011-11-19 21:04:11Z mueller $ -- -- Copyright 2010- by Walter F.J. Mueller -- @@ -70,7 +70,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; use work.slvtypes.all; use work.comlib.all; diff --git a/rtl/vlib/rlink/rlink_serport.vhd b/rtl/vlib/rlink/rlink_serport.vhd index a7a99bdc..7665de34 100644 --- a/rtl/vlib/rlink/rlink_serport.vhd +++ b/rtl/vlib/rlink/rlink_serport.vhd @@ -1,4 +1,4 @@ --- $Id: rlink_serport.vhd 406 2011-08-14 21:06:44Z mueller $ +-- $Id: rlink_serport.vhd 427 2011-11-19 21:04:11Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- Test bench: tb/tb_rlink_serport -- -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -28,6 +28,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 3.1.2 now numeric_std clean -- 2011-08-14 406 3.1.1 cleaner code for RL_SER_MONI.clkdiv assignment -- 2010-12-25 348 3.1 re-written, is now a serial to rlink_base adapter -- 2010-12-24 347 3.0.1 rename: CP_*->RL->* @@ -42,7 +43,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.serport.all; @@ -51,7 +52,7 @@ use work.rlinklib.all; entity rlink_serport is -- rlink serport adapter generic ( - RB_ADDR : slv8 := conv_std_logic_vector(2#11111110#,8); + RB_ADDR : slv8 := slv(to_unsigned(2#11111110#,8)); CDWIDTH : positive := 13; -- clk divider width CDINIT : natural := 15); -- clk divider initial/reset setting port ( @@ -144,7 +145,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then R_REGS <= regs_init; else @@ -204,7 +205,7 @@ begin n.flpbusy := '1'; n.flpcnt := r.fwidth; else - n.fldcnt := unsigned(r.fldcnt) - 1; + n.fldcnt := slv(unsigned(r.fldcnt) - 1); end if; end if; @@ -212,7 +213,7 @@ begin if unsigned(r.flpcnt) = 0 then n.flpbusy := '0'; else - n.flpcnt := unsigned(r.flpcnt) - 1; + n.flpcnt := slv(unsigned(r.flpcnt) - 1); end if; end if; diff --git a/rtl/vlib/rlink/rlinklib.vhd b/rtl/vlib/rlink/rlinklib.vhd index ad52a806..64efcf73 100644 --- a/rtl/vlib/rlink/rlinklib.vhd +++ b/rtl/vlib/rlink/rlinklib.vhd @@ -1,6 +1,6 @@ --- $Id: rlinklib.vhd 389 2011-07-07 21:59:00Z mueller $ +-- $Id: rlinklib.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,10 +16,11 @@ -- Description: Definitions for rlink interface and bus entities -- -- Dependencies: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 3.1.3 now numeric_std clean -- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core; -- new rlink_serport interface; -- rename rlink_core_serport->rlink_base_serport @@ -47,7 +48,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.rblib.all; @@ -94,6 +95,11 @@ end record rl_moni_type; constant rl_moni_init : rl_moni_type := ('0','0','0'); -- eop,attn,lamp +-- ise 13.1 xst can bug check if generic defaults in a package are defined via +-- 'slv(to_unsigned())'. The conv_ construct prior to numeric_std was ok. +-- As workaround the ibus default addresses are defined here as constant. +constant rbaddr_rlink_serport : slv8 := slv(to_unsigned(2#11111110#,8)); + component rlink_core is -- rlink core with 9bit iface generic ( ATOWIDTH : positive := 5; -- access timeout counter width @@ -214,7 +220,7 @@ subtype c_rlink_serport_rbf_rtson is integer range 2 downto 0; -- component rlink_serport is -- rlink serport adapter generic ( - RB_ADDR : slv8 := conv_std_logic_vector(2#11111110#,8); + RB_ADDR : slv8 := rbaddr_rlink_serport; CDWIDTH : positive := 13; -- clk divider width CDINIT : natural := 15); -- clk divider initial/reset setting port ( @@ -248,7 +254,7 @@ component rlink_base_serport is -- rlink base+serport combo OFAWIDTH : natural := 5; -- output fifo address width (0=none) ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none) ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none) - RB_ADDR : slv8 := conv_std_logic_vector(2#11111110#,8); + RB_ADDR : slv8 := rbaddr_rlink_serport; CDWIDTH : positive := 13; -- clk divider width CDINIT : natural := 15); -- clk divider initial/reset setting port ( diff --git a/rtl/vlib/rlink/tb/tb_rlink.vhd b/rtl/vlib/rlink/tb/tb_rlink.vhd index c3da5fc7..f3710a3e 100644 --- a/rtl/vlib/rlink/tb/tb_rlink.vhd +++ b/rtl/vlib/rlink/tb/tb_rlink.vhd @@ -1,6 +1,6 @@ --- $Id: tb_rlink.vhd 351 2010-12-30 21:50:54Z mueller $ +-- $Id: tb_rlink.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -27,10 +27,11 @@ -- rlink_serport (via tbd_rlink_serport) -- -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 3.0.7 fix crc8_update_tbl usage; now numeric_std clean -- 2010-12-29 351 3.0.6 use new rbd_tester addr 111100xx (from 111101xx) -- 2010-12-26 348 3.0.5 use simbus to export clkcycle (for tbd_..serport) -- 2010-12-23 347 3.0.4 use rb_mon, rlink_mon directly; rename CP_*->RL_* @@ -94,7 +95,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; @@ -227,7 +228,7 @@ begin RBTEST : rbd_tester generic map ( - RB_ADDR => conv_std_logic_vector(2#11110000#,8)) + RB_ADDR => slv(to_unsigned(2#11110000#,8))) port map ( CLK => CLK, RESET => '0', @@ -318,7 +319,7 @@ begin begin txlist(ntxlist) := '0' & data; ntxlist := ntxlist + 1; - crc8_update_tbl(txcrc, data); + txcrc := crc8_update_tbl(txcrc, data); end procedure do_tx8; procedure do_tx16 (data : inout slv16) is @@ -331,7 +332,7 @@ begin begin sv_rxlist(sv_nrxlist) := '0' & data; sv_nrxlist := sv_nrxlist + 1; - crc8_update_tbl(rxcrc, data); + rxcrc := crc8_update_tbl(rxcrc, data); end procedure do_rx8; procedure do_rx16 (data : inout slv16) is @@ -626,7 +627,7 @@ begin begin loop - wait until CLK'event and CLK='1'; + wait until rising_edge(CLK); wait for c2out_time; if RL_VAL = '1' then diff --git a/rtl/vlib/rlink/tb/tbcore_rlink.vhd b/rtl/vlib/rlink/tb/tbcore_rlink.vhd index 32195a77..fea57637 100644 --- a/rtl/vlib/rlink/tb/tbcore_rlink.vhd +++ b/rtl/vlib/rlink/tb/tbcore_rlink.vhd @@ -1,6 +1,6 @@ --- $Id: tbcore_rlink.vhd 351 2010-12-30 21:50:54Z mueller $ +-- $Id: tbcore_rlink.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,9 +20,10 @@ -- To test: generic, any rlink_cext based target -- -- Target Devices: generic --- Tool versions: xst 11.4; ghdl 0.26 +-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 3.0.1 now numeric_std clean -- 2010-12-29 351 3.0 rename rritb_core->tbcore_rlink; use rbv3 naming -- 2010-06-05 301 1.1.2 rename .rpmon -> .rbmon -- 2010-05-02 287 1.1.1 rename config command .sdata -> .sinit; @@ -33,7 +34,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; @@ -181,23 +182,23 @@ begin stim_loop: loop - wait until CLK_L'event and CLK_L='1'; + wait until rising_edge(CLK_L); wait for CLK_PERIOD-SETUP_TIME; SB_ADDR <= (others=>'Z'); SB_DATA <= (others=>'Z'); - icycle := conv_integer(unsigned(SB_CLKCYCLE)); + icycle := to_integer(unsigned(SB_CLKCYCLE)); RX_VAL <= '0'; if RX_HOLD = '0' then irxint := rlink_cext_getbyte(icycle); if irxint >= 0 then if irxint <= 16#ff# then -- normal data byte - RX_DATA <= conv_std_logic_vector(irxint, 8); + RX_DATA <= slv(to_unsigned(irxint, 8)); RX_VAL <= '1'; elsif irxint >= 16#1000000# then -- out-of-band message - irxslv := conv_std_logic_vector(irxint, 24); + irxslv := slv(to_unsigned(irxint mod 16#1000000#, 24)); iaddr := irxslv(23 downto 16); idata := irxslv(15 downto 0); writetimestamp(oline, SB_CLKCYCLE, ": OOB-MSG"); @@ -209,7 +210,7 @@ begin writeoct(oline, idata, right, 7); writeline(output, oline); if unsigned(iaddr) = 0 then - ibit := conv_integer(unsigned(idata(15 downto 8))); + ibit := to_integer(unsigned(idata(15 downto 8))); r_sb_cntl(ibit) := idata(0); else SB_ADDR <= iaddr; @@ -250,10 +251,10 @@ begin begin loop - wait until CLK_L'event and CLK_L='1'; + wait until rising_edge(CLK_L); wait for C2OUT_TIME; if TX_ENA = '1' then - itxdata := conv_integer(unsigned(TX_DATA)); + itxdata := to_integer(unsigned(TX_DATA)); itxrc := rlink_cext_putbyte(itxdata); assert itxrc=0 report "rlink_cext_putbyte error: " & integer'image(itxrc) diff --git a/rtl/vlib/rlink/tb/tbcore_rlink_dcm.vhd b/rtl/vlib/rlink/tb/tbcore_rlink_dcm.vhd index fb40ad86..88837099 100644 --- a/rtl/vlib/rlink/tb/tbcore_rlink_dcm.vhd +++ b/rtl/vlib/rlink/tb/tbcore_rlink_dcm.vhd @@ -1,6 +1,6 @@ --- $Id: tbcore_rlink_dcm.vhd 351 2010-12-30 21:50:54Z mueller $ +-- $Id: tbcore_rlink_dcm.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -21,10 +21,11 @@ -- To test: generic, any rlink_cext based target -- -- Target Devices: generic --- Tool versions: 11.4-12.1; ghdl 0.26-0.29 +-- Tool versions: 11.4, 12.1, 13.1; ghdl 0.26-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 3.0.1 now numeric_std clean -- 2010-12-29 351 3.0 rename rritb_core_dcm->tbcore_rlink_dcm; rbv3 names -- 2010-11-13 338 1.1 First DCM aware version, cloned from rritb_core -- 2010-06-05 301 1.1.2 renamed .rpmon -> .rbmon @@ -36,7 +37,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; @@ -187,14 +188,14 @@ begin -- just wait for 10 CLKSYS cycles for i in 1 to 10 loop - wait until CLKSYS'event and CLKSYS='1'; + wait until rising_edge(CLKSYS); clksys_period := now - t_lastclksys; t_lastclksys := now; end loop; -- i stim_loop: loop - wait until CLKSYS'event and CLKSYS='1'; + wait until rising_edge(CLKSYS); clksys_period := now - t_lastclksys; t_lastclksys := now; @@ -203,17 +204,17 @@ begin SB_ADDR <= (others=>'Z'); SB_DATA <= (others=>'Z'); - icycle := conv_integer(unsigned(SB_CLKCYCLE)); + icycle := to_integer(unsigned(SB_CLKCYCLE)); RX_VAL <= '0'; if RX_HOLD = '0' then irxint := rlink_cext_getbyte(icycle); if irxint >= 0 then if irxint <= 16#ff# then -- normal data byte - RX_DATA <= conv_std_logic_vector(irxint, 8); + RX_DATA <= slv(to_unsigned(irxint, 8)); RX_VAL <= '1'; elsif irxint >= 16#1000000# then -- out-of-band message - irxslv := conv_std_logic_vector(irxint, 24); + irxslv := slv(to_unsigned(irxint mod 16#1000000#, 24)); iaddr := irxslv(23 downto 16); idata := irxslv(15 downto 0); writetimestamp(oline, SB_CLKCYCLE, ": OOB-MSG"); @@ -225,7 +226,7 @@ begin writeoct(oline, idata, right, 7); writeline(output, oline); if unsigned(iaddr) = 0 then - ibit := conv_integer(unsigned(idata(15 downto 8))); + ibit := to_integer(unsigned(idata(15 downto 8))); r_sb_cntl(ibit) := idata(0); else SB_ADDR <= iaddr; @@ -250,7 +251,7 @@ begin -- just wait for 50 CLKSYS cycles for i in 1 to 50 loop - wait until CLKSYS'event and CLKSYS='1'; + wait until rising_edge(CLKSYS); end loop; -- i CLK_STOP <= '1'; @@ -269,10 +270,10 @@ begin begin loop - wait until CLKSYS'event and CLKSYS='1'; + wait until rising_edge(CLKSYS); wait for C2OUT_TIME; if TX_ENA = '1' then - itxdata := conv_integer(unsigned(TX_DATA)); + itxdata := to_integer(unsigned(TX_DATA)); itxrc := rlink_cext_putbyte(itxdata); assert itxrc=0 report "rlink_cext_putbyte error: " & integer'image(itxrc) diff --git a/rtl/vlib/rlink/tb/tbd_rlink_direct.vhd b/rtl/vlib/rlink/tb/tbd_rlink_direct.vhd index 114e40fd..50f36f30 100644 --- a/rtl/vlib/rlink/tb/tbd_rlink_direct.vhd +++ b/rtl/vlib/rlink/tb/tbd_rlink_direct.vhd @@ -1,4 +1,4 @@ --- $Id: tbd_rlink_direct.vhd 348 2010-12-26 15:23:44Z mueller $ +-- $Id: tbd_rlink_direct.vhd 427 2011-11-19 21:04:11Z mueller $ -- -- Copyright 2007-2010 by Walter F.J. Mueller -- @@ -50,7 +50,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; use work.slvtypes.all; use work.rblib.all; diff --git a/rtl/vlib/rlink/tb/tbd_rlink_serport.vhd b/rtl/vlib/rlink/tb/tbd_rlink_serport.vhd index 86898bc2..6d8f812a 100644 --- a/rtl/vlib/rlink/tb/tbd_rlink_serport.vhd +++ b/rtl/vlib/rlink/tb/tbd_rlink_serport.vhd @@ -1,6 +1,6 @@ --- $Id: tbd_rlink_serport.vhd 350 2010-12-28 16:40:11Z mueller $ +-- $Id: tbd_rlink_serport.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -27,10 +27,11 @@ -- To test: rlink_serport -- -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 3.0.5 now numeric_std clean -- 2010-12-28 350 3.0.4 use CLKDIV/CDINIT=0; -- 2010-12-26 348 3.0.3 add RTS/CTS ports for tbu_; -- 2010-12-24 347 3.0.2 rename: CP_*->RL->* @@ -52,7 +53,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; @@ -107,7 +108,7 @@ architecture syn of tbd_rlink_serport is signal TXDATA : slv8 := (others=>'0'); signal TXENA : slbit := '0'; signal TXBUSY : slbit := '0'; - signal CLKDIV : slv13 := conv_std_logic_vector(c_cdinit,CDWIDTH); + signal CLKDIV : slv13 := slv(to_unsigned(c_cdinit,CDWIDTH)); component tbu_rlink_serport is -- rlink core+serport combo port ( @@ -227,7 +228,7 @@ begin variable ncycle : integer := 0; begin loop - wait until CLK'event and CLK='1'; -- check at end of clock cycle + wait until rising_edge(CLK); -- check at end of clock cycle if RTS_N /= rts_last then writetimestamp(oline, SB_CLKCYCLE, ": rts "); write(oline, string'(" RTS_N ")); diff --git a/rtl/vlib/rlink/tb/tbu_rlink_serport.vhd b/rtl/vlib/rlink/tb/tbu_rlink_serport.vhd index 2867e381..859b0e5e 100644 --- a/rtl/vlib/rlink/tb/tbu_rlink_serport.vhd +++ b/rtl/vlib/rlink/tb/tbu_rlink_serport.vhd @@ -1,6 +1,6 @@ --- $Id: tbu_rlink_serport.vhd 350 2010-12-28 16:40:11Z mueller $ +-- $Id: tbu_rlink_serport.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -32,10 +32,11 @@ -- 2007-10-27 92 8.2.03 I34 xc3s1000-4 283 594 18 323 s 10.3 -- 2007-10-27 92 8.1.03 I27 xc3s1000-4 285 596 18 - s 9.32 -- --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-19 427 3.1.2 now numeric_std clean -- 2010-12-28 350 3.1.1 use CLKDIV/CDINIT=0; -- 2010-12-26 348 3.1 use rlink_base now; add RTS/CTS ports -- 2010-12-24 347 3.0.1 rename: CP_*->RL->* @@ -53,7 +54,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.rblib.all; @@ -147,7 +148,7 @@ begin SERPORT : rlink_serport generic map ( - RB_ADDR => conv_std_logic_vector(2#11111110#,8), + RB_ADDR => slv(to_unsigned(2#11111110#,8)), CDWIDTH => CDWIDTH, CDINIT => c_cdinit) port map ( diff --git a/rtl/vlib/serport/serport.vhd b/rtl/vlib/serport/serport.vhd index 117597e6..699a8a84 100644 --- a/rtl/vlib/serport/serport.vhd +++ b/rtl/vlib/serport/serport.vhd @@ -1,6 +1,6 @@ --- $Id: serport.vhd 389 2011-07-07 21:59:00Z mueller $ +-- $Id: serport.vhd 424 2011-11-13 16:38:23Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,10 +16,13 @@ -- Description: serial port interface components -- -- Dependencies: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-10-23 419 1.2.4 remove serport_clkdiv_ consts; +-- 2011-10-22 417 1.2.3 add serport_xon(rx|tx) defs +-- 2011-10-14 416 1.2.2 add c_serport defs -- 2010-12-26 348 1.2.1 add ABCLKDIV to serport_uart_rxtx_ab -- 2010-04-10 276 1.2 add clock divider constant defs -- 2007-10-22 88 1.1 renames (in prev revs); remove std_logic_unsigned @@ -33,21 +36,10 @@ use work.slvtypes.all; package serport is --- clock divider constants assume 50 MHz clock - - constant serport_clkdiv_009600 : integer := 5208-1; -- 50000000/ 9600=5208.33 - constant serport_clkdiv_019200 : integer := 2604-1; -- 50000000/ 19200=2604.16 - constant serport_clkdiv_038400 : integer := 1302-1; -- 50000000/ 38400=1302.08 - constant serport_clkdiv_057600 : integer := 868-1; -- 50000000/ 57600= 868.05 - constant serport_clkdiv_115200 : integer := 434-1; -- 50000000/115200= 434.02 - constant serport_clkdiv_230400 : integer := 217-1; -- 50000000/230400= 217.01 - constant serport_clkdiv_460800 : integer := 109-1; -- 50000000/460800= 108.51 - constant serport_clkdiv_500000 : integer := 100-1; -- 50000000/500000= 100 - constant serport_clkdiv_576000 : integer := 87-1; -- 50000000/576000= 86.80 - constant serport_clkdiv_921600 : integer := 54-1; -- 50000000/921600= 54.25 - constant serport_clkdiv_1M : integer := 50-1; -- 50000000/1M = 50 - constant serport_clkdiv_2M : integer := 24-1; -- 50000000/2M = 25 - + constant c_serport_xon : slv8 := "00010001"; -- char xon: ^Q = hex 11 + constant c_serport_xoff : slv8 := "00010011"; -- char xoff ^S = hex 13 + constant c_serport_xesc : slv8 := "00011011"; -- char xesc ^[ = ESC = hex 1B + component serport_uart_rxtx is -- serial port uart: rx+tx combo generic ( CDWIDTH : positive := 13); -- clk divider width @@ -134,4 +126,110 @@ component serport_uart_autobaud is -- serial port uart: autobauder ); end component; +component serport_xonrx is -- serial port: xon/xoff logic rx path + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + ENAXON : in slbit; -- enable xon/xoff handling + ENAESC : in slbit; -- enable xon/xoff escaping + UART_RXDATA : in slv8; -- uart data out + UART_RXVAL : in slbit; -- uart data valid + RXDATA : out slv8; -- user data out + RXVAL : out slbit; -- user data valid + RXHOLD : in slbit; -- user data hold + RXOVR : out slbit; -- user data overrun + TXOK : out slbit -- tx channel ok + ); +end component; + +component serport_xontx is -- serial port: xon/xoff logic tx path + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + ENAXON : in slbit; -- enable xon/xoff handling + ENAESC : in slbit; -- enable xon/xoff escaping + UART_TXDATA : out slv8; -- uart data in + UART_TXENA : out slbit; -- uart data enable + UART_TXBUSY : in slbit; -- uart data busy + TXDATA : in slv8; -- user data in + TXENA : in slbit; -- user data enable + TXBUSY : out slbit; -- user data busy + RXOK : in slbit; -- rx channel ok + TXOK : in slbit -- tx channel ok + ); +end component; + +type serport_stat_type is record -- serial port module status + rxerr : slbit; -- receiver data error (frame error) + rxovr : slbit; -- receiver data overrun + rxact : slbit; -- receiver active + txact : slbit; -- transceiver active + abact : slbit; -- autobauder active;if 1 clkdiv invalid + abdone : slbit; -- autobauder resync done + abclkdiv : slv16; -- autobauder clock divider + rxok : slbit; -- rx channel ok + txok : slbit; -- tx channel ok +end record serport_stat_type; + +constant serport_stat_init : serport_stat_type := ( + '0','0', -- rxerr,rxovr + '0','0', -- rxact,txact + '0','0', -- abact,abdone + (others=>'0'), -- abclkdiv + '0','0' -- rxok,txok +); + +component serport_1clock is -- serial port module, 1 clock domain + generic ( + CDWIDTH : positive := 13; -- clk divider width + CDINIT : natural := 15; -- clk divider initial/reset setting + RXFAWIDTH : natural := 5; -- rx fifo address width + TXFAWIDTH : natural := 5); -- tx fifo address width + port ( + CLK : in slbit; -- clock + CE_MSEC : in slbit; -- 1 msec clock enable + RESET : in slbit; -- reset + ENAXON : in slbit; -- enable xon/xoff handling + ENAESC : in slbit; -- enable xon/xoff escaping + RXDATA : out slv8; -- receiver data out + RXVAL : out slbit; -- receiver data valid + RXHOLD : in slbit; -- receiver data hold + TXDATA : in slv8; -- transmit data in + TXENA : in slbit; -- transmit data enable + TXBUSY : out slbit; -- transmit busy + STAT : out serport_stat_type; -- serport module status + RXSD : in slbit; -- receive serial data (uart view) + TXSD : out slbit; -- transmit serial data (uart view) + RXRTS_N : out slbit; -- receive rts (uart view, act.low) + TXCTS_N : in slbit -- transmit cts (uart view, act.low) + ); +end component; + +component serport_2clock is -- serial port module, 2 clock domain + generic ( + CDWIDTH : positive := 13; -- clk divider width + CDINIT : natural := 15; -- clk divider initial/reset setting + RXFAWIDTH : natural := 5; -- rx fifo address width + TXFAWIDTH : natural := 5); -- tx fifo address width + port ( + CLKU : in slbit; -- clock (backend:user) + RESET : in slbit; -- reset + CLKS : in slbit; -- clock (frontend:serial) + CES_MSEC : in slbit; -- S|1 msec clock enable + ENAXON : in slbit; -- U|enable xon/xoff handling + ENAESC : in slbit; -- U|enable xon/xoff escaping + RXDATA : out slv8; -- U|receiver data out + RXVAL : out slbit; -- U|receiver data valid + RXHOLD : in slbit; -- U|receiver data hold + TXDATA : in slv8; -- U|transmit data in + TXENA : in slbit; -- U|transmit data enable + TXBUSY : out slbit; -- U|transmit busy + STAT : out serport_stat_type; -- U|serport module status + RXSD : in slbit; -- S|receive serial data (uart view) + TXSD : out slbit; -- S|transmit serial data (uart view) + RXRTS_N : out slbit; -- S|receive rts (uart view, act.low) + TXCTS_N : in slbit -- S|transmit cts (uart view, act.low) + ); +end component; + end package serport; diff --git a/rtl/vlib/serport/serport_uart_autobaud.vhd b/rtl/vlib/serport/serport_uart_autobaud.vhd index 545eccf9..6098a65f 100644 --- a/rtl/vlib/serport/serport_uart_autobaud.vhd +++ b/rtl/vlib/serport/serport_uart_autobaud.vhd @@ -1,6 +1,6 @@ --- $Id: serport_uart_autobaud.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: serport_uart_autobaud.vhd 417 2011-10-22 10:30:29Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,9 +18,10 @@ -- Dependencies: - -- Test bench: tb/tb_serport_autobaud -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 +-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-10-22 417 1.0.4 now numeric_std clean -- 2010-04-18 279 1.0.3 change ccnt start value to -3, better rounding -- 2007-10-14 89 1.0.2 all instantiation with CDINIT=0 -- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned @@ -29,7 +30,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; @@ -75,11 +76,11 @@ architecture syn of serport_uart_autobaud is -- --> ccntinit = -3 constant ccntinit : slv(CDWIDTH-1+3 downto 0) := - conv_std_logic_vector(2**(CDWIDTH+3)-3, CDWIDTH+3); + slv(to_unsigned(2**(CDWIDTH+3)-3, CDWIDTH+3)); constant mcntzero : slv7 := (others=>'0'); constant mcntlast : slv7 := (others=>'1'); constant regs_init : regs_type := ( - conv_std_logic_vector(CDINIT,CDWIDTH)&"000", + slv(to_unsigned(CDINIT,CDWIDTH))&"000", (others=>'0'), '0', s_idle @@ -97,7 +98,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then R_REGS <= regs_init; else @@ -128,7 +129,7 @@ begin iact := '0'; if CE_MSEC = '1' then -- if end of msec if r.seen1 = '0' then -- if no '1' seen on RXD - n.mcnt := unsigned(r.mcnt) + 1; -- up break timer counter + n.mcnt := slv(unsigned(r.mcnt) + 1); -- up break timer counter if r.mcnt = mcntlast then -- after 127 msec n.state := s_break; -- break detected ! end if; @@ -156,7 +157,7 @@ begin n.state := s_idle; -- to s_idle, autobauding done idone := '1'; -- emit done pulse else -- otherwise still in '0' of sync - n.ccnt := unsigned(n.ccnt) + 1; -- increment ccnt + n.ccnt := slv(unsigned(n.ccnt) + 1); -- increment ccnt end if; when others => null; -- ----------------------------------- diff --git a/rtl/vlib/serport/serport_uart_rx.vhd b/rtl/vlib/serport/serport_uart_rx.vhd index c1f38dd0..71e4a2da 100644 --- a/rtl/vlib/serport/serport_uart_rx.vhd +++ b/rtl/vlib/serport/serport_uart_rx.vhd @@ -1,6 +1,6 @@ --- $Id: serport_uart_rx.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: serport_uart_rx.vhd 421 2011-11-07 21:23:50Z mueller $ -- --- Copyright 2007-2009 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -24,9 +24,10 @@ -- Dependencies: - -- Test bench: tb/tb_serport_uart_rxtx -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-10-22 417 2.0.3 now numeric_std clean -- 2009-07-12 233 2.0.2 remove snoopers -- 2008-03-02 121 2.0.1 comment out snoopers -- 2007-10-21 91 2.0 re-designed and -implemented with state machine. @@ -43,12 +44,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; - --- synthesis translate_off -use ieee.std_logic_textio.all; -use std.textio.all; --- synthesis translate_on +use ieee.numeric_std.all; use work.slvtypes.all; @@ -91,11 +87,11 @@ architecture syn of serport_uart_rx is constant ccntzero : slv(CDWIDTH-1 downto 0) := (others=>'0'); constant dcntzero : slv(CDWIDTH downto 0) := (others=>'0'); constant regs_init : regs_type := ( - s_idle, - ccntzero, - dcntzero, - (others=>'0'), - (others=>'0') + s_idle, -- state + ccntzero, -- ccnt + dcntzero, -- dcnt + (others=>'0'), -- bcnt + (others=>'0') -- sreg ); signal R_REGS : regs_type := regs_init; -- state registers @@ -106,7 +102,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then R_REGS <= N_REGS; end if; @@ -280,7 +276,7 @@ begin if ld_ccnt = '1' then -- implement ccnt n.ccnt := CLKDIV; else - n.ccnt := unsigned(r.ccnt) - 1; + n.ccnt := slv(unsigned(r.ccnt) - 1); end if; if ld_dcnt = '1' then -- implement dcnt @@ -288,7 +284,7 @@ begin n.dcnt(0) := RXSD; else if RXSD = '1' then - n.dcnt := unsigned(r.dcnt) + 1; + n.dcnt := slv(unsigned(r.dcnt) + 1); end if; end if; @@ -296,7 +292,7 @@ begin n.bcnt := (others=>'0'); else if ce_bcnt = '1' then - n.bcnt := unsigned(r.bcnt) + 1; + n.bcnt := slv(unsigned(r.bcnt) + 1); end if; end if; diff --git a/rtl/vlib/serport/serport_uart_rxtx.vhd b/rtl/vlib/serport/serport_uart_rxtx.vhd index 0cdb7038..586d87bc 100644 --- a/rtl/vlib/serport/serport_uart_rxtx.vhd +++ b/rtl/vlib/serport/serport_uart_rxtx.vhd @@ -1,6 +1,6 @@ --- $Id: serport_uart_rxtx.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: serport_uart_rxtx.vhd 417 2011-10-22 10:30:29Z mueller $ -- --- Copyright 2007- by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,7 +19,7 @@ -- serport_uart_tx -- Test bench: tb/tb_serport_uart_rxtx -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 +-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment -- 2007-06-24 60 1.0 Initial version @@ -27,7 +27,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.serport.all; diff --git a/rtl/vlib/serport/serport_uart_rxtx_ab.vhd b/rtl/vlib/serport/serport_uart_rxtx_ab.vhd index 0c8f95a0..fe6523f0 100644 --- a/rtl/vlib/serport/serport_uart_rxtx_ab.vhd +++ b/rtl/vlib/serport/serport_uart_rxtx_ab.vhd @@ -1,6 +1,6 @@ --- $Id: serport_uart_rxtx_ab.vhd 350 2010-12-28 16:40:11Z mueller $ +-- $Id: serport_uart_rxtx_ab.vhd 417 2011-10-22 10:30:29Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,7 +19,7 @@ -- serport_uart_rxtx -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -27,13 +27,14 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-10-22 417 1.1.1 now numeric_std clean -- 2010-12-26 348 1.1 add ABCLKDIV port for clock divider setting -- 2007-06-24 60 1.0 Initial version ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.serport.all; @@ -63,7 +64,7 @@ end serport_uart_rxtx_ab; architecture syn of serport_uart_rxtx_ab is - signal CLKDIV : slv(CDWIDTH-1 downto 0) := conv_std_logic_vector(0, CDWIDTH); + signal CLKDIV : slv(CDWIDTH-1 downto 0) := slv(to_unsigned(0, CDWIDTH)); signal ABACT_L : slbit := '0'; -- local readable copy of ABACT signal UART_RESET : slbit := '0'; diff --git a/rtl/vlib/serport/serport_uart_tx.vhd b/rtl/vlib/serport/serport_uart_tx.vhd index 99e1ee06..ae43906e 100644 --- a/rtl/vlib/serport/serport_uart_tx.vhd +++ b/rtl/vlib/serport/serport_uart_tx.vhd @@ -1,6 +1,6 @@ --- $Id: serport_uart_tx.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: serport_uart_tx.vhd 417 2011-10-22 10:30:29Z mueller $ -- --- Copyright 2007- by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,9 +18,10 @@ -- Dependencies: - -- Test bench: tb/tb_serport_uart_rxtx -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-10-22 417 1.0.4 now numeric_std clean -- 2007-10-21 91 1.0.3 use 1 stop bits (redesigned _rx allows this) -- 2007-10-19 90 1.0.2 use 2 stop bits (allow CLKDIV=0 operation in sim) -- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned @@ -29,7 +30,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; @@ -73,7 +74,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then R_REGS <= N_REGS; end if; @@ -104,7 +105,7 @@ begin if unsigned(r.ccnt) = 0 then ld_ccnt := '1'; n.sreg := '1' & r.sreg(8 downto 1); - n.bcnt := unsigned(r.bcnt) + 1; + n.bcnt := slv(unsigned(r.bcnt) + 1); if unsigned(r.bcnt) = 9 then -- if 10 bits send n.busy := '0'; -- declare all done end if; @@ -119,7 +120,7 @@ begin if ld_ccnt = '1' then n.ccnt := CLKDIV; else - n.ccnt := unsigned(r.ccnt) - 1; + n.ccnt := slv(unsigned(r.ccnt) - 1); end if; N_REGS <= n; diff --git a/rtl/vlib/serport/tb/tb_serport_autobaud.vhd b/rtl/vlib/serport/tb/tb_serport_autobaud.vhd index 996ebe57..cb3f2b91 100644 --- a/rtl/vlib/serport/tb/tb_serport_autobaud.vhd +++ b/rtl/vlib/serport/tb/tb_serport_autobaud.vhd @@ -1,6 +1,6 @@ --- $Id: tb_serport_autobaud.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: tb_serport_autobaud.vhd 417 2011-10-22 10:30:29Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -33,6 +33,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-10-22 417 1.1.3 now numeric_std clean -- 2010-04-24 281 1.1.2 use direct instatiation for tbd_ -- 2008-03-24 129 1.1.1 CLK_CYCLE now 31 bits -- 2007-10-21 91 1.1 now use 'send' command, self-checking (FAIL's) @@ -44,7 +45,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; @@ -231,7 +232,7 @@ begin begin loop - wait until CLK'event and CLK='1'; + wait until rising_edge(CLK); if R_MON_VAL_1 = '1' then if R_MON_VAL_2 = '1' then @@ -256,7 +257,7 @@ begin if ABDONE = '1' then writetimestamp(oline, CLK_CYCLE, ": auto CLKDIV ="); - write(oline, conv_integer(unsigned(CLKDIV)), right, 3); + write(oline, to_integer(unsigned(CLKDIV)), right, 3); writeline(output, oline); end if; diff --git a/rtl/vlib/serport/tb/tb_serport_uart_rx.vhd b/rtl/vlib/serport/tb/tb_serport_uart_rx.vhd index 803f20f0..dd3bd842 100644 --- a/rtl/vlib/serport/tb/tb_serport_uart_rx.vhd +++ b/rtl/vlib/serport/tb/tb_serport_uart_rx.vhd @@ -1,6 +1,6 @@ --- $Id: tb_serport_uart_rx.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: tb_serport_uart_rx.vhd 417 2011-10-22 10:30:29Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -30,6 +30,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-10-22 417 1.0.3 now numeric_std clean -- 2010-04-24 281 1.0.2 use direct instatiation for tbd_ -- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits -- 2007-10-21 91 1.0 Initial version @@ -37,7 +38,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; @@ -52,7 +53,7 @@ architecture sim of tb_serport_uart_rx is signal CLK : slbit := '0'; signal RESET : slbit := '0'; - signal CLKDIV : slv5 := conv_std_logic_vector(15, 5); + signal CLKDIV : slv5 := slv(to_unsigned(15, 5)); signal RXSD : slbit := '1'; signal RXDATA : slv8 := (others=>'0'); signal RXVAL : slbit := '0'; @@ -156,7 +157,7 @@ begin end loop; read_ea(iline, irate); wait for 2*clock_period; - CLKDIV <= conv_std_logic_vector(irate-1, CLKDIV'length); + CLKDIV <= slv(to_unsigned(irate-1, CLKDIV'length)); wait for 2*clock_period; when ".xrate" => -- .xrate @@ -266,7 +267,7 @@ begin begin loop - wait until CLK'event and CLK='1'; + wait until rising_edge(CLK); if R_MON_VAL_1 = '1' then if R_MON_VAL_2 = '1' then diff --git a/rtl/vlib/serport/tb/tb_serport_uart_rxtx.vhd b/rtl/vlib/serport/tb/tb_serport_uart_rxtx.vhd index fd07e16e..d0c07d29 100644 --- a/rtl/vlib/serport/tb/tb_serport_uart_rxtx.vhd +++ b/rtl/vlib/serport/tb/tb_serport_uart_rxtx.vhd @@ -1,6 +1,6 @@ --- $Id: tb_serport_uart_rxtx.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: tb_serport_uart_rxtx.vhd 417 2011-10-22 10:30:29Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -33,6 +33,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-10-22 417 1.1.3 now numeric_std clean -- 2010-04-24 281 1.1.2 use direct instatiation for tbd_ -- 2008-03-24 129 1.1.1 CLK_CYCLE now 31 bits -- 2007-10-21 91 1.1 now use 'send' command, self-checking (FAIL's) @@ -42,7 +43,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; @@ -57,7 +58,7 @@ architecture sim of tb_serport_uart_rxtx is signal CLK : slbit := '0'; signal RESET : slbit := '0'; - signal CLKDIV : slv13 := conv_std_logic_vector(15, 13); + signal CLKDIV : slv13 := slv(to_unsigned(15, 13)); signal RXDATA : slv8 := (others=>'0'); signal RXVAL : slbit := '0'; signal RXERR : slbit := '0'; @@ -149,7 +150,7 @@ begin when ".rate " => -- .rate read_ea(iline, irate); - CLKDIV <= conv_std_logic_vector(irate-1, 13); + CLKDIV <= slv(to_unsigned(irate-1, 13)); when "send " => -- send read_ea(iline, idelta); @@ -214,7 +215,7 @@ begin begin loop - wait until CLK'event and CLK='1'; + wait until rising_edge(CLK); if R_MON_VAL_1 = '1' then if R_MON_VAL_2 = '1' then diff --git a/rtl/vlib/serport/tb/tbd_serport_autobaud.vhd b/rtl/vlib/serport/tb/tbd_serport_autobaud.vhd index 36bdd61c..1ef82849 100644 --- a/rtl/vlib/serport/tb/tbd_serport_autobaud.vhd +++ b/rtl/vlib/serport/tb/tbd_serport_autobaud.vhd @@ -1,6 +1,6 @@ --- $Id: tbd_serport_autobaud.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: tbd_serport_autobaud.vhd 417 2011-10-22 10:30:29Z mueller $ -- --- Copyright 2007- by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -34,7 +34,7 @@ -- 2007-10-27 92 8.2.03 I34 xc3s1000-4 153 338 0 178 s 9.45 -- 2007-10-27 92 8.1.03 I27 xc3s1000-4 152 293 0 - s 9.40 -- --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment -- 2008-01-20 112 1.0.1 rename clkgen->clkdivce @@ -43,7 +43,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.genlib.all; diff --git a/rtl/vlib/serport/tb/tbd_serport_uart_rx.vhd b/rtl/vlib/serport/tb/tbd_serport_uart_rx.vhd index bca2626c..1098699c 100644 --- a/rtl/vlib/serport/tb/tbd_serport_uart_rx.vhd +++ b/rtl/vlib/serport/tb/tbd_serport_uart_rx.vhd @@ -1,6 +1,6 @@ --- $Id: tbd_serport_uart_rx.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: tbd_serport_uart_rx.vhd 417 2011-10-22 10:30:29Z mueller $ -- --- Copyright 2007- by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -30,7 +30,7 @@ -- 2007-10-27 92 8.2.03 I34 xc3s1000-4 29 90 0 47 s 8.45 -- 2007-10-27 92 8.1.03 I27 xc3s1000-4 31 92 0 - s 8.25 -- --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment -- 2007-10-21 91 1.0 Initial version @@ -38,7 +38,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.serport.all; diff --git a/rtl/vlib/serport/tb/tbd_serport_uart_rxtx.vhd b/rtl/vlib/serport/tb/tbd_serport_uart_rxtx.vhd index b4e00b88..88190737 100644 --- a/rtl/vlib/serport/tb/tbd_serport_uart_rxtx.vhd +++ b/rtl/vlib/serport/tb/tbd_serport_uart_rxtx.vhd @@ -1,6 +1,6 @@ --- $Id: tbd_serport_uart_rxtx.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: tbd_serport_uart_rxtx.vhd 417 2011-10-22 10:30:29Z mueller $ -- --- Copyright 2007- by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -30,7 +30,7 @@ -- 2007-10-27 92 8.2.03 I34 xc3s1000-4 73 152 0 81 s 9.30 -- 2007-10-27 92 8.1.03 I27 xc3s1000-4 73 125 0 - s 9.30 -- --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment -- 2007-10-21 91 1.0 Initial version @@ -38,7 +38,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.serport.all; diff --git a/rtl/vlib/simlib/simclk.vhd b/rtl/vlib/simlib/simclk.vhd index d1e6a223..f7082b48 100644 --- a/rtl/vlib/simlib/simclk.vhd +++ b/rtl/vlib/simlib/simclk.vhd @@ -1,6 +1,6 @@ --- $Id: simclk.vhd 338 2010-11-13 22:19:25Z mueller $ +-- $Id: simclk.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2007-2008 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,10 +18,11 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.0.3 now numeric_std clean -- 2008-03-24 129 1.0.2 CLK_CYCLE now 31 bits -- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned -- 2007-08-10 72 1.0 Initial version @@ -29,7 +30,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; entity simclk is -- test bench clock generator @@ -58,7 +59,7 @@ begin clk_loop: loop CLK <= '1'; wait for 0 ns; -- make a delta cycle so that clock - icycle := unsigned(icycle) + 1; -- cycle number is updated after the + icycle := slv(unsigned(icycle) + 1); -- cycle number is updated after the CLK_CYCLE <= icycle; -- clock transition. all edge triggered -- proc's will thus read old value. wait for clock_halfperiod; diff --git a/rtl/vlib/simlib/simclkcnt.vhd b/rtl/vlib/simlib/simclkcnt.vhd index 50a214f7..4c507075 100644 --- a/rtl/vlib/simlib/simclkcnt.vhd +++ b/rtl/vlib/simlib/simclkcnt.vhd @@ -1,6 +1,6 @@ --- $Id: simclkcnt.vhd 338 2010-11-13 22:19:25Z mueller $ +-- $Id: simclkcnt.vhd 423 2011-11-12 22:22:25Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2011- by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,16 +18,17 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 12.1; ghdl 0.29 +-- Tool versions: xst 12.1, 13.1; ghdl 0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-12 423 1.0.1 now numeric_std clean -- 2010-11-13 72 1.0 Initial version ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; entity simclkcnt is -- test bench system clock cycle counter @@ -44,8 +45,8 @@ begin proc_clk: process (CLK) begin - if CLK'event and CLK='1' then - R_CLKCNT <= unsigned(R_CLKCNT) + 1; + if rising_edge(CLK) then + R_CLKCNT <= slv(unsigned(R_CLKCNT) + 1); end if; end process proc_clk; diff --git a/rtl/vlib/simlib/simlib.vhd b/rtl/vlib/simlib/simlib.vhd index 2febf934..84444fd3 100644 --- a/rtl/vlib/simlib/simlib.vhd +++ b/rtl/vlib/simlib/simlib.vhd @@ -1,6 +1,6 @@ --- $Id: simlib.vhd 346 2010-12-22 22:59:26Z mueller $ +-- $Id: simlib.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2006-2010 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,10 +18,11 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.3.8 now numeric_std clean -- 2010-12-22 346 1.3.7 rename readcommand -> readdotcomm -- 2010-11-13 338 1.3.6 add simclkcnt; xx.x ns time in writetimestamp() -- 2008-03-24 129 1.3.5 CLK_CYCLE now 31 bits @@ -43,7 +44,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; @@ -375,10 +376,10 @@ end procedure readhex; -- ------------------------------------- procedure readgen( -- read slv generic base - L: inout line; -- line - value: out std_logic_vector; -- value to be read - good: out boolean; -- success flag - base: in integer := 2) is -- default base + L: inout line; -- line + value: out std_logic_vector; -- value to be read + good: out boolean; -- success flag + base: in integer := 2) is -- default base variable nibble : std_logic_vector(3 downto 0); variable sum : std_logic_vector(31 downto 0); @@ -387,7 +388,7 @@ procedure readgen( -- read slv generic base variable ok : boolean; variable ivalue : integer; variable ichar : character; - + begin assert not value'ascending(1) @@ -430,7 +431,12 @@ begin when 16 => readhex(L, value, ok); when 10 => read(L, ivalue, ok); - value := conv_std_logic_vector(ivalue, value'length); + -- the following if allows to enter negative integers, e.g. -1 for all-1 + if ivalue >= 0 then + value := slv(to_unsigned(ivalue, value'length)); + else + value := slv(to_signed(ivalue, value'length)); + end if; when others => null; end case; end if; @@ -955,7 +961,7 @@ begin end case; end loop; -- i if ochar = ' ' then - write(L,conv_integer(unsigned(nibble))); + write(L,to_integer(unsigned(nibble))); else write(L,ochar); end if; @@ -1017,7 +1023,7 @@ begin end case; end loop; -- i if ochar = ' ' then - write(L,hextab(conv_integer(unsigned(nibble))+1)); + write(L,hextab(to_integer(unsigned(nibble))+1)); else write(L,ochar); end if; @@ -1075,7 +1081,7 @@ begin write(L, t_dnsec, right, 1); write(L, string'(" ns")); - write(L, conv_integer(unsigned(clkcyc)), right, 7); + write(L, to_integer(unsigned(clkcyc)), right, 7); if str /= null_string then write(L, str); end if; diff --git a/rtl/vlib/xlib/dcm_sp_sfs_gsim.vbom b/rtl/vlib/xlib/dcm_sfs_gsim.vbom similarity index 61% rename from rtl/vlib/xlib/dcm_sp_sfs_gsim.vbom rename to rtl/vlib/xlib/dcm_sfs_gsim.vbom index 25bac812..19ce55c2 100644 --- a/rtl/vlib/xlib/dcm_sp_sfs_gsim.vbom +++ b/rtl/vlib/xlib/dcm_sfs_gsim.vbom @@ -1,4 +1,4 @@ # libs ../slvtypes.vhd # design -dcm_sp_sfs_gsim.vhd +dcm_sfs_gsim.vhd diff --git a/rtl/vlib/xlib/dcm_sp_sfs_gsim.vhd b/rtl/vlib/xlib/dcm_sfs_gsim.vhd similarity index 87% rename from rtl/vlib/xlib/dcm_sp_sfs_gsim.vhd rename to rtl/vlib/xlib/dcm_sfs_gsim.vhd index fefaf981..75f341fb 100644 --- a/rtl/vlib/xlib/dcm_sp_sfs_gsim.vhd +++ b/rtl/vlib/xlib/dcm_sfs_gsim.vhd @@ -1,6 +1,6 @@ --- $Id: dcm_sp_sfs_gsim.vhd 338 2010-11-13 22:19:25Z mueller $ +-- $Id: dcm_sfs_gsim.vhd 426 2011-11-18 18:14:08Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -12,17 +12,18 @@ -- for complete details. -- ------------------------------------------------------------------------------ --- Module Name: dcm_sp_sfs - sim --- Description: DCM_SP as 'simple freq. synthesis' +-- Module Name: dcm_sfs - sim +-- Description: DCM for simple frequency synthesis -- simple vhdl model, without Xilinx UNISIM primitives -- -- Dependencies: - -- Test bench: - -- Target Devices: generic Spartan-3A,-3E --- Tool versions: xst 12.1; ghdl 0.29 +-- Tool versions: xst 12.1, 13.1; ghdl 0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-17 426 1.0.1 rename dcm_sp_sfs -> dcm_sfs -- 2010-11-12 338 1.0 Initial version ------------------------------------------------------------------------------ @@ -31,7 +32,7 @@ use ieee.std_logic_1164.all; use work.slvtypes.all; -entity dcm_sp_sfs is -- DCM_SP as 'simple freq. synthesis' +entity dcm_sfs is -- DCM for simple frequency synthesis generic ( CLKFX_DIVIDE : positive := 1; -- FX clock divide (1-32) CLKFX_MULTIPLY : positive := 1; -- FX clock multiply (2-32) (1->no DCM) @@ -41,10 +42,10 @@ entity dcm_sp_sfs is -- DCM_SP as 'simple freq. synthesis' CLKFX : out slbit; -- clock output (synthesized freq.) LOCKED : out slbit -- dcm locked ); -end dcm_sp_sfs; +end dcm_sfs; -architecture sim of dcm_sp_sfs is +architecture sim of dcm_sfs is signal CLK_DIVPULSE : slbit := '0'; signal CLKOUT_PERIOD : time := 0 ns; diff --git a/rtl/vlib/xlib/dcm_sp_sfs_unisim.vbom b/rtl/vlib/xlib/dcm_sfs_unisim_s3e.vbom similarity index 65% rename from rtl/vlib/xlib/dcm_sp_sfs_unisim.vbom rename to rtl/vlib/xlib/dcm_sfs_unisim_s3e.vbom index a86fe3f8..f25c78fa 100644 --- a/rtl/vlib/xlib/dcm_sp_sfs_unisim.vbom +++ b/rtl/vlib/xlib/dcm_sfs_unisim_s3e.vbom @@ -2,4 +2,4 @@ ../slvtypes.vhd @lib:unisim # design -dcm_sp_sfs_unisim.vhd +dcm_sfs_unisim_s3e.vhd diff --git a/rtl/vlib/xlib/dcm_sp_sfs_unisim.vhd b/rtl/vlib/xlib/dcm_sfs_unisim_s3e.vhd similarity index 81% rename from rtl/vlib/xlib/dcm_sp_sfs_unisim.vhd rename to rtl/vlib/xlib/dcm_sfs_unisim_s3e.vhd index 4ed6ebd1..3a7bd900 100644 --- a/rtl/vlib/xlib/dcm_sp_sfs_unisim.vhd +++ b/rtl/vlib/xlib/dcm_sfs_unisim_s3e.vhd @@ -1,6 +1,6 @@ --- $Id: dcm_sp_sfs_unisim.vhd 338 2010-11-13 22:19:25Z mueller $ +-- $Id: dcm_sfs_unisim_s3e.vhd 426 2011-11-18 18:14:08Z mueller $ -- --- Copyright 2010- by Walter F.J. Mueller +-- Copyright 2010-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -12,8 +12,8 @@ -- for complete details. -- ------------------------------------------------------------------------------ --- Module Name: dcm_sp_sfs - syn --- Description: DCM_SP as 'simple freq. synthesis' +-- Module Name: dcm_sfs - syn +-- Description: DCM for simple frequency synthesis; SPARTAN-3E version -- Direct instantiation of Xilinx UNISIM primitives -- -- Dependencies: - @@ -23,6 +23,8 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-17 426 1.0.3 rename dcm_sp_sfs -> dcm_sfs, SPARTAN-3E version +-- 2011-11-10 423 1.0.2 add FAMILY generic, SPARTAN-3 support -- 2010-11-12 338 1.0.1 drop SB_CLK generic; allow DIV=1,MUL=1 without DCM -- 2010-11-07 337 1.0 Initial version ------------------------------------------------------------------------------ @@ -35,7 +37,7 @@ use unisim.vcomponents.ALL; use work.slvtypes.all; -entity dcm_sp_sfs is -- DCM_SP as 'simple freq. synthesis' +entity dcm_sfs is -- DCM for simple frequency synthesis generic ( CLKFX_DIVIDE : positive := 1; -- FX clock divide (1-32) CLKFX_MULTIPLY : positive := 1; -- FX clock multiply (2-32) (1->no DCM) @@ -45,10 +47,10 @@ entity dcm_sp_sfs is -- DCM_SP as 'simple freq. synthesis' CLKFX : out slbit; -- clock output (synthesized freq.) LOCKED : out slbit -- dcm locked ); -end dcm_sp_sfs; +end dcm_sfs; -architecture syn of dcm_sp_sfs is +architecture syn of dcm_sfs is begin @@ -60,8 +62,8 @@ begin CLKFX <= CLKIN; LOCKED <= '1'; end generate DCM0; - - DCM1: if CLKFX_MULTIPLY >= 2 generate + + DCM1: if CLKFX_MULTIPLY>=2 generate DCM : dcm_sp generic map ( diff --git a/rtl/vlib/xlib/iob_reg_i_gen.vhd b/rtl/vlib/xlib/iob_reg_i_gen.vhd index 4c3d014e..8024d39a 100644 --- a/rtl/vlib/xlib/iob_reg_i_gen.vhd +++ b/rtl/vlib/xlib/iob_reg_i_gen.vhd @@ -1,4 +1,4 @@ --- $Id: iob_reg_i_gen.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: iob_reg_i_gen.vhd 426 2011-11-18 18:14:08Z mueller $ -- -- Copyright 2007- by Walter F.J. Mueller -- @@ -55,7 +55,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if CE = '1' then R_DI <= PAD; end if; diff --git a/rtl/vlib/xlib/iob_reg_io_gen.vhd b/rtl/vlib/xlib/iob_reg_io_gen.vhd index 8a0427c1..43166565 100644 --- a/rtl/vlib/xlib/iob_reg_io_gen.vhd +++ b/rtl/vlib/xlib/iob_reg_io_gen.vhd @@ -1,4 +1,4 @@ --- $Id: iob_reg_io_gen.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: iob_reg_io_gen.vhd 427 2011-11-19 21:04:11Z mueller $ -- -- Copyright 2007-2008 by Walter F.J. Mueller -- @@ -18,7 +18,7 @@ -- Dependencies: iob_keeper_gen [sim only] -- Test bench: - -- Target Devices: generic Spartan, Virtex --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment -- 2008-05-22 149 1.0.4 use internally TE to match OBUFT T polarity @@ -76,7 +76,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then R_TE <= not OE; if CEI = '1' then R_DI <= to_x01(PAD); diff --git a/rtl/vlib/xlib/iob_reg_o_gen.vhd b/rtl/vlib/xlib/iob_reg_o_gen.vhd index f93ff424..941d17ad 100644 --- a/rtl/vlib/xlib/iob_reg_o_gen.vhd +++ b/rtl/vlib/xlib/iob_reg_o_gen.vhd @@ -1,4 +1,4 @@ --- $Id: iob_reg_o_gen.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: iob_reg_o_gen.vhd 426 2011-11-18 18:14:08Z mueller $ -- -- Copyright 2007- by Walter F.J. Mueller -- @@ -55,7 +55,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if CE = '1' then R_DO <= DO; end if; diff --git a/rtl/vlib/xlib/xlib.vhd b/rtl/vlib/xlib/xlib.vhd index 4bc85564..4e65ad10 100644 --- a/rtl/vlib/xlib/xlib.vhd +++ b/rtl/vlib/xlib/xlib.vhd @@ -1,6 +1,6 @@ --- $Id: xlib.vhd 389 2011-07-07 21:59:00Z mueller $ +-- $Id: xlib.vhd 426 2011-11-18 18:14:08Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,11 @@ -- Description: Xilinx specific components -- -- Dependencies: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-17 426 1.0.7 rename dcm_sp_sfs -> dcm_sfs; remove family generic +-- 2011-11-10 423 1.0.6 add family generic for dcm_sp_sfs -- 2010-11-07 337 1.0.5 add dcm_sp_sfs -- 2008-05-23 149 1.0.4 add iob_io(_gen) -- 2008-05-22 148 1.0.3 add iob_keeper(_gen); @@ -152,7 +154,7 @@ component iob_keeper_gen is -- keeper for IOB, vector ); end component; -component dcm_sp_sfs is -- DCM_SP as 'simple freq. synthesis' +component dcm_sfs is -- DCM for simple frequency synthesis generic ( CLKFX_DIVIDE : positive := 2; -- FX clock divide (1-32) CLKFX_MULTIPLY : positive := 2; -- FX clock divide (2-32) diff --git a/rtl/w11a/pdp11.vhd b/rtl/w11a/pdp11.vhd index 93a80d86..04e09a44 100644 --- a/rtl/w11a/pdp11.vhd +++ b/rtl/w11a/pdp11.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11.vhd 351 2010-12-30 21:50:54Z mueller $ +-- $Id: pdp11.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2006-2010 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -16,9 +16,10 @@ -- Description: Definitions for pdp11 components -- -- Dependencies: - --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.4.8 now numeric_std clean -- 2010-12-30 351 1.4.7 rename pdp11_core_rri->pdp11_core_rbus; use rblib -- 2010-10-23 335 1.4.6 rename RRI_LAM->RB_LAM; -- 2010-10-16 332 1.4.5 renames of pdp11_du_drv port names @@ -81,7 +82,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; @@ -1070,8 +1071,8 @@ end component; component pdp11_core_rbus is -- core to rbus interface generic ( - RB_ADDR_CORE : slv8 := conv_std_logic_vector(2#00000000#,8); - RB_ADDR_IBUS : slv8 := conv_std_logic_vector(2#10000000#,8)); + RB_ADDR_CORE : slv8 := slv(to_unsigned(2#00000000#,8)); + RB_ADDR_IBUS : slv8 := slv(to_unsigned(2#10000000#,8))); port ( CLK : in slbit; -- clock RESET : in slbit; -- reset diff --git a/rtl/w11a/pdp11_bram.vhd b/rtl/w11a/pdp11_bram.vhd index 19cdfee5..a8144a53 100644 --- a/rtl/w11a/pdp11_bram.vhd +++ b/rtl/w11a/pdp11_bram.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_bram.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: pdp11_bram.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2008- by Walter F.J. Mueller +-- Copyright 2008-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,9 +18,10 @@ -- Dependencies: memlib/ram_2swsr_rfirst_gen -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.0.3 now numeric_std clean -- 2008-03-01 120 1.0.2 add addrzero constant to avoid XST errors -- 2008-02-23 118 1.0.1 AWIDTH now a generic port -- 2008-02-17 117 1.0 Initial version @@ -28,7 +29,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.memlib.all; @@ -112,7 +113,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if GRESET = '1' then R_REGS <= regs_init; else diff --git a/rtl/w11a/pdp11_cache.vhd b/rtl/w11a/pdp11_cache.vhd index bfe17a1f..7e62d1a5 100644 --- a/rtl/w11a/pdp11_cache.vhd +++ b/rtl/w11a/pdp11_cache.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_cache.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: pdp11_cache.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2008- by Walter F.J. Mueller +-- Copyright 2008-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,9 +18,10 @@ -- Dependencies: memlib/ram_2swsr_rfirst_gen -- Test bench: - -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.0.3 now numeric_std clean -- 2008-02-23 118 1.0.2 ce cache in s_idle to avoid U's in sim -- factor invariants out of if's; fix tag rmiss logic -- 2008-02-17 117 1.0.1 use em_(mreq|sres) interface; use req,we for mem @@ -30,7 +31,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.memlib.all; @@ -209,7 +210,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if GRESET = '1' then R_REGS <= regs_init; else diff --git a/rtl/w11a/pdp11_core.vhd b/rtl/w11a/pdp11_core.vhd index cc3b8a64..5e9ffa45 100644 --- a/rtl/w11a/pdp11_core.vhd +++ b/rtl/w11a/pdp11_core.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_core.vhd 351 2010-12-30 21:50:54Z mueller $ +-- $Id: pdp11_core.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2006-2010 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -27,9 +27,10 @@ -- tb/tb_rlink_tba_pdp11core -- -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.3.1 now numeric_std clean -- 2010-06-13 305 1.3 add CP_ADDR in port; drop R_CPDIN, R_CPOUT; _vmbox -- CP_ADDR now from in port; dpath CP_DIN now from in -- port; out port CP_DOUT now from _dpath @@ -51,7 +52,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; diff --git a/rtl/w11a/pdp11_core_rbus.vhd b/rtl/w11a/pdp11_core_rbus.vhd index aca5d5e5..c986af52 100644 --- a/rtl/w11a/pdp11_core_rbus.vhd +++ b/rtl/w11a/pdp11_core_rbus.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_core_rbus.vhd 352 2011-01-02 13:01:37Z mueller $ +-- $Id: pdp11_core_rbus.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,9 +19,10 @@ -- Test bench: tb/tb_rlink_tba_pdp11core -- -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.26 +-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29 -- Revision History: - -- Date Rev Version Comment +-- 2011-11-18 427 1.1.1 now numeric_std clean -- 2010-12-29 351 1.1 renamed from pdp11_core_rri; ported to rbv3 -- 2010-10-23 335 1.2.3 rename RRI_LAM->RB_LAM; -- 2010-06-20 308 1.2.2 use c_ibrb_ibf_ def's @@ -78,7 +79,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.rblib.all; @@ -88,8 +89,8 @@ use work.pdp11.all; entity pdp11_core_rbus is -- core to rbus interface generic ( - RB_ADDR_CORE : slv8 := conv_std_logic_vector(2#00000000#,8); - RB_ADDR_IBUS : slv8 := conv_std_logic_vector(2#10000000#,8)); + RB_ADDR_CORE : slv8 := slv(to_unsigned(2#00000000#,8)); + RB_ADDR_IBUS : slv8 := slv(to_unsigned(2#10000000#,8))); port ( CLK : in slbit; -- clock RESET : in slbit; -- reset @@ -152,7 +153,7 @@ architecture syn of pdp11_core_rbus is proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if RESET = '1' then R_REGS <= regs_init; else @@ -341,7 +342,7 @@ architecture syn of pdp11_core_rbus is irb_err := CP_STAT.cmderr or CP_STAT.cmdmerr; if CP_STAT.cmdack = '1' then -- normal cycle end if r.doinc = '1' then - n.addr := unsigned(r.addr) + 1; + n.addr := slv(unsigned(r.addr) + 1); end if; if r.waitstep = '1' then irb_busy := '1'; diff --git a/rtl/w11a/pdp11_decode.vhd b/rtl/w11a/pdp11_decode.vhd index ec1b08df..02d8f039 100644 --- a/rtl/w11a/pdp11_decode.vhd +++ b/rtl/w11a/pdp11_decode.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_decode.vhd 330 2010-09-19 17:43:53Z mueller $ +-- $Id: pdp11_decode.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2006-2008 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,9 +18,10 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.0.6 now numeric_std clean -- 2010-09-18 300 1.0.5 rename (adlm)box->(oalm)unit -- 2008-11-30 174 1.0.4 BUGFIX: add updt_dstadsrc; set for MFP(I/D) -- 2008-05-03 143 1.0.3 get fork_srcr,fork_dstr,fork_dsta assign out of if @@ -31,7 +32,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.pdp11.all; diff --git a/rtl/w11a/pdp11_dpath.vhd b/rtl/w11a/pdp11_dpath.vhd index 1539607a..417907c5 100644 --- a/rtl/w11a/pdp11_dpath.vhd +++ b/rtl/w11a/pdp11_dpath.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_dpath.vhd 330 2010-09-19 17:43:53Z mueller $ +-- $Id: pdp11_dpath.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2006-2010 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -24,9 +24,10 @@ -- -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.2.2 now numeric_std clean -- 2010-09-18 300 1.2.1 rename (adlm)box->(oalm)unit -- 2010-06-13 305 1.2 rename CPDIN -> CP_DIN; add CP_DOUT out port; -- remove CPADDR out port; drop R_CPADDR, proc_cpaddr; @@ -44,7 +45,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; @@ -242,7 +243,7 @@ begin proc_dregs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if CNTL.dsrc_we = '1' then if CNTL.dsrc_sel = '0' then @@ -284,7 +285,7 @@ begin proc_mregs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if CNTL.ireg_we = '1' then R_IREG <= VM_DOUT; @@ -295,7 +296,7 @@ begin proc_cpdout: process (CLK) begin - if CLK'event and CLK='1'then + if rising_edge(CLK) then if CRESET = '1' then R_CPDOUT <= (others=>'0'); else diff --git a/rtl/w11a/pdp11_gpr.vhd b/rtl/w11a/pdp11_gpr.vhd index 4b6856c4..e3d089bb 100644 --- a/rtl/w11a/pdp11_gpr.vhd +++ b/rtl/w11a/pdp11_gpr.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_gpr.vhd 314 2010-07-09 17:38:41Z mueller $ +-- $Id: pdp11_gpr.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2006-2007 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,9 +19,10 @@ -- -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.0.4 now numeric_std clean -- 2008-08-22 161 1.0.3 rename ubf_ -> ibf_; use iblib -- 2007-12-30 108 1.0.2 use ubf_byte[01] -- 2007-06-14 56 1.0.1 Use slvtypes.all @@ -30,7 +31,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.memlib.all; @@ -140,14 +141,14 @@ begin proc_pc : process (CLK) alias R_PC15 : slv15 is R_PC(15 downto 1); -- upper 15 bit of PC begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if WE='1' and ADST=c_gpr_pc then R_PC(ibf_byte0) <= DIN(ibf_byte0); if BYTOP = '0' then R_PC(ibf_byte1) <= DIN(ibf_byte1); end if; elsif PCINC = '1' then - R_PC15 <= unsigned(R_PC15) + 1; + R_PC15 <= slv(unsigned(R_PC15) + 1); end if; end if; end process proc_pc; diff --git a/rtl/w11a/pdp11_irq.vhd b/rtl/w11a/pdp11_irq.vhd index e9c18a90..a743566c 100644 --- a/rtl/w11a/pdp11_irq.vhd +++ b/rtl/w11a/pdp11_irq.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_irq.vhd 335 2010-10-24 22:24:23Z mueller $ +-- $Id: pdp11_irq.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,10 +18,11 @@ -- Dependencies: ib_sel -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.2.2 now numeric_std clean -- 2010-10-23 335 1.2.1 use ib_sel -- 2010-10-17 333 1.2 use ibus V2 interface -- 2008-08-22 161 1.1.4 use iblib @@ -36,7 +37,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; @@ -61,7 +62,7 @@ end pdp11_irq; architecture syn of pdp11_irq is - constant ibaddr_pirq : slv16 := conv_std_logic_vector(8#177772#,16); + constant ibaddr_pirq : slv16 := slv(to_unsigned(8#177772#,16)); subtype pirq_ubf_pir is integer range 15 downto 9; subtype pirq_ubf_pia_h is integer range 7 downto 5; @@ -101,7 +102,7 @@ begin proc_pirq : process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if BRESET = '1' then R_PIRQ <= (others => '0'); elsif IBSEL_PIRQ='1' and IB_MREQ.we='1'and IB_MREQ.be1='1' then @@ -120,7 +121,7 @@ begin "000"; proc_irq : process (PI_PRI, EI_PRI, EI_VECT, INT_ACK) - + constant vect_default : slv9 := slv(to_unsigned(8#240#,9)); begin EI_ACKM <= '0'; @@ -131,7 +132,7 @@ begin EI_ACKM <= INT_ACK; else PRI <= PI_PRI; - VECT <= conv_std_logic_vector(8#240#,9)(8 downto 2); + VECT <= vect_default(8 downto 2); end if; end process proc_irq; diff --git a/rtl/w11a/pdp11_lunit.vhd b/rtl/w11a/pdp11_lunit.vhd index e3139f69..93bc614d 100644 --- a/rtl/w11a/pdp11_lunit.vhd +++ b/rtl/w11a/pdp11_lunit.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_lunit.vhd 330 2010-09-19 17:43:53Z mueller $ +-- $Id: pdp11_lunit.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2006-2008 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,9 +18,10 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.26 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.1.1 now numeric_std clean -- 2010-09-18 300 1.1 renamed from lbox -- 2008-03-30 131 1.0.2 BUGFIX: SXT clears V condition code -- 2007-06-14 56 1.0.1 Use slvtypes.all @@ -29,7 +30,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.pdp11.all; diff --git a/rtl/w11a/pdp11_mem70.vhd b/rtl/w11a/pdp11_mem70.vhd index 20caad31..5d3aa02c 100644 --- a/rtl/w11a/pdp11_mem70.vhd +++ b/rtl/w11a/pdp11_mem70.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_mem70.vhd 333 2010-10-17 21:18:33Z mueller $ +-- $Id: pdp11_mem70.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2008-2010 by Walter F.J. Mueller +-- Copyright 2008-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,10 +18,11 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.1.1 now numeric_std clean -- 2010-10-17 333 1.1 use ibus V2 interface -- 2008-08-22 161 1.0.2 rename ubf_ -> ibf_; use iblib -- 2008-02-23 118 1.0.1 use sys_conf_mem_losize; rename CACHE_ENA->_FMISS @@ -30,7 +31,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; @@ -53,14 +54,14 @@ end pdp11_mem70; architecture syn of pdp11_mem70 is - constant ibaddr_loaddr : slv16 := conv_std_logic_vector(8#177740#,16); - constant ibaddr_hiaddr : slv16 := conv_std_logic_vector(8#177742#,16); - constant ibaddr_syserr : slv16 := conv_std_logic_vector(8#177744#,16); - constant ibaddr_cntl : slv16 := conv_std_logic_vector(8#177746#,16); - constant ibaddr_maint : slv16 := conv_std_logic_vector(8#177750#,16); - constant ibaddr_hm : slv16 := conv_std_logic_vector(8#177752#,16); - constant ibaddr_losize : slv16 := conv_std_logic_vector(8#177760#,16); - constant ibaddr_hisize : slv16 := conv_std_logic_vector(8#177762#,16); + constant ibaddr_loaddr : slv16 := slv(to_unsigned(8#177740#,16)); + constant ibaddr_hiaddr : slv16 := slv(to_unsigned(8#177742#,16)); + constant ibaddr_syserr : slv16 := slv(to_unsigned(8#177744#,16)); + constant ibaddr_cntl : slv16 := slv(to_unsigned(8#177746#,16)); + constant ibaddr_maint : slv16 := slv(to_unsigned(8#177750#,16)); + constant ibaddr_hm : slv16 := slv(to_unsigned(8#177752#,16)); + constant ibaddr_losize : slv16 := slv(to_unsigned(8#177760#,16)); + constant ibaddr_hisize : slv16 := slv(to_unsigned(8#177762#,16)); subtype cntl_ibf_frep is integer range 5 downto 4; subtype cntl_ibf_fmiss is integer range 3 downto 2; @@ -93,7 +94,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if CRESET = '1' then R_REGS <= regs_init; else @@ -152,7 +153,7 @@ begin idout(r.hm_data'range) := r.hm_data; end if; if r.ibsel_ls = '1' then - idout := conv_std_logic_vector(sys_conf_mem_losize,16); + idout := slv(to_unsigned(sys_conf_mem_losize,16)); end if; if r.ibsel_cr='1' and ibw0='1' then diff --git a/rtl/w11a/pdp11_mmu.vhd b/rtl/w11a/pdp11_mmu.vhd index dedf782b..941d8320 100644 --- a/rtl/w11a/pdp11_mmu.vhd +++ b/rtl/w11a/pdp11_mmu.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_mmu.vhd 335 2010-10-24 22:24:23Z mueller $ +-- $Id: pdp11_mmu.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2006-2010 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -22,10 +22,11 @@ -- -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.4.2 now numeric_std clean -- 2010-10-23 335 1.4.1 use ib_sel -- 2010-10-17 333 1.4 use ibus V2 interface -- 2010-06-20 307 1.3.7 rename cpacc to cacc in mmu_cntl_type @@ -49,7 +50,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; @@ -74,8 +75,8 @@ end pdp11_mmu; architecture syn of pdp11_mmu is - constant ibaddr_ssr0 : slv16 := conv_std_logic_vector(8#177572#,16); - constant ibaddr_ssr3 : slv16 := conv_std_logic_vector(8#172516#,16); + constant ibaddr_ssr0 : slv16 := slv(to_unsigned(8#177572#,16)); + constant ibaddr_ssr3 : slv16 := slv(to_unsigned(8#172516#,16)); constant ssr0_ibf_abo_nonres : integer := 15; constant ssr0_ibf_abo_length : integer := 14; @@ -200,7 +201,7 @@ begin proc_ssr0 : process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if BRESET = '1' then R_SSR0 <= mmu_ssr0_init; else @@ -211,7 +212,7 @@ begin proc_ssr3 : process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if BRESET = '1' then R_SSR3 <= mmu_ssr3_init; elsif IBSEL_SSR3='1' and IB_MREQ.we='1' then @@ -252,7 +253,7 @@ begin iasn(3) := dspace_ok; iasn(2 downto 0) := asf; - ipaddrh := unsigned("000000000"&bn) + unsigned(SARSDR.saf); + ipaddrh := slv(unsigned("000000000"&bn) + unsigned(SARSDR.saf)); DSPACE <= dspace_ok; ASN <= iasn; diff --git a/rtl/w11a/pdp11_mmu_sadr.vhd b/rtl/w11a/pdp11_mmu_sadr.vhd index 459839b2..d7b18e12 100644 --- a/rtl/w11a/pdp11_mmu_sadr.vhd +++ b/rtl/w11a/pdp11_mmu_sadr.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_mmu_sadr.vhd 351 2010-12-30 21:50:54Z mueller $ +-- $Id: pdp11_mmu_sadr.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2006-2010 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,10 +19,11 @@ -- -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.3.3 now numeric_std clean -- 2010-12-30 351 1.3.2 BUGFIX: fix sensitivity list of proc_eaddr -- 2010-10-23 335 1.3.1 change proc_eaddr logic, shorten logic path -- 2010-10-17 333 1.3 use ibus V2 interface @@ -40,7 +41,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.memlib.all; @@ -77,9 +78,9 @@ architecture syn of pdp11_mmu_sadr is -- -- mode => (addr(8), not addr(6)) [Note: km "00" sm "01" um "11"] - constant ibaddr_kmdar : slv16 := conv_std_logic_vector(8#172300#,16); - constant ibaddr_smdar : slv16 := conv_std_logic_vector(8#172200#,16); - constant ibaddr_umdar : slv16 := conv_std_logic_vector(8#177600#,16); + constant ibaddr_kmdar : slv16 := slv(to_unsigned(8#172300#,16)); + constant ibaddr_smdar : slv16 := slv(to_unsigned(8#172200#,16)); + constant ibaddr_umdar : slv16 := slv(to_unsigned(8#177600#,16)); subtype sdr_ibf_slf is integer range 14 downto 8; subtype sdr_ibf_aib is integer range 7 downto 6; @@ -165,7 +166,7 @@ begin variable ibsel_dr : slbit := '0'; variable ibsel_ar : slbit := '0'; begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then ibsel_dr := '0'; ibsel_ar := '0'; if IB_MREQ.aval = '1' then diff --git a/rtl/w11a/pdp11_mmu_ssr12.vhd b/rtl/w11a/pdp11_mmu_ssr12.vhd index e254d7e6..ca93abd8 100644 --- a/rtl/w11a/pdp11_mmu_ssr12.vhd +++ b/rtl/w11a/pdp11_mmu_ssr12.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_mmu_ssr12.vhd 335 2010-10-24 22:24:23Z mueller $ +-- $Id: pdp11_mmu_ssr12.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2006-2010 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,10 +18,11 @@ -- Dependencies: ib_sel -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.2.2 now numeric_std clean -- 2010-10-23 335 1.2.1 use ib_sel -- 2010-10-17 333 1.2 use ibus V2 interface -- 2009-05-30 220 1.1.4 final removal of snoopers (were already commented) @@ -35,7 +36,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; @@ -56,8 +57,8 @@ end pdp11_mmu_ssr12; architecture syn of pdp11_mmu_ssr12 is - constant ibaddr_ssr1 : slv16 := conv_std_logic_vector(8#177574#,16); - constant ibaddr_ssr2 : slv16 := conv_std_logic_vector(8#177576#,16); + constant ibaddr_ssr1 : slv16 := slv(to_unsigned(8#177574#,16)); + constant ibaddr_ssr2 : slv16 := slv(to_unsigned(8#177576#,16)); subtype ssr1_ibf_rb_delta is integer range 15 downto 11; subtype ssr1_ibf_rb_num is integer range 10 downto 8; @@ -117,7 +118,7 @@ begin proc_regs : process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then R_SSR1 <= N_SSR1; R_SSR2 <= N_SSR2; end if; @@ -167,16 +168,16 @@ begin if use_rb = '0' then nssr1.ra_num := MONI.regnum; if MONI.isdec = '0' then - nssr1.ra_delta := signed(nssr1.ra_delta) + signed(delta); + nssr1.ra_delta := slv(signed(nssr1.ra_delta) + signed(delta)); else - nssr1.ra_delta := signed(nssr1.ra_delta) - signed(delta); + nssr1.ra_delta := slv(signed(nssr1.ra_delta) - signed(delta)); end if; else nssr1.rb_num := MONI.regnum; if MONI.isdec = '0' then - nssr1.rb_delta := signed(nssr1.rb_delta) + signed(delta); + nssr1.rb_delta := slv(signed(nssr1.rb_delta) + signed(delta)); else - nssr1.rb_delta := signed(nssr1.rb_delta) - signed(delta); + nssr1.rb_delta := slv(signed(nssr1.rb_delta) - signed(delta)); end if; end if; end if; diff --git a/rtl/w11a/pdp11_munit.vhd b/rtl/w11a/pdp11_munit.vhd index eb0a1bda..669f35a4 100644 --- a/rtl/w11a/pdp11_munit.vhd +++ b/rtl/w11a/pdp11_munit.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_munit.vhd 330 2010-09-19 17:43:53Z mueller $ +-- $Id: pdp11_munit.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2006-2007 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,9 +18,10 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.1.1 now numeric_std clean -- 2010-09-18 300 1.1 renamed from mbox -- 2007-06-14 56 1.0.1 Use slvtypes.all -- 2007-05-12 26 1.0 Initial version @@ -28,7 +29,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.pdp11.all; @@ -99,7 +100,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then R_DD_L <= NEXT_DD_L; R_DDO_LT <= NEXT_DDO_LT; R_DIV_V <= NEXT_DIV_V; @@ -152,9 +153,9 @@ begin if S_DIV_CN='1' or S_ASH_CN='1' or S_ASHC_CN='1' then if R_SHC(5) = '0' then - NEXT_SHC <= unsigned(R_SHC) - 1; + NEXT_SHC <= slv(unsigned(R_SHC) - 1); else - NEXT_SHC <= unsigned(R_SHC) + 1; + NEXT_SHC <= slv(unsigned(R_SHC) + 1); end if; NEXT_C1 <= '0'; end if; @@ -210,9 +211,9 @@ begin end if; if subadd = '0' then - dd_h_new := signed(dd_h_old) + signed(DR); + dd_h_new := slv(signed(dd_h_old) + signed(DR)); else - dd_h_new := signed(dd_h_old) - signed(DR); + dd_h_new := slv(signed(dd_h_old) - signed(DR)); end if; dd_gt := '0'; @@ -304,7 +305,7 @@ begin begin - prod := signed(DSRC) * signed(DDST); + prod := slv(signed(DSRC) * signed(DDST)); case FUNC is when c_munit_func_mul => diff --git a/rtl/w11a/pdp11_ounit.vhd b/rtl/w11a/pdp11_ounit.vhd index bfab5a59..45fece37 100644 --- a/rtl/w11a/pdp11_ounit.vhd +++ b/rtl/w11a/pdp11_ounit.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_ounit.vhd 330 2010-09-19 17:43:53Z mueller $ +-- $Id: pdp11_ounit.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2006-2007 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,9 +18,10 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.1.1 now numeric_std clean -- 2010-09-18 300 1.1 renamed from abox -- 2007-06-14 56 1.0.1 Use slvtypes.all -- 2007-05-12 26 1.0 Initial version @@ -28,7 +29,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.pdp11.all; @@ -92,9 +93,9 @@ begin end case; if OPSUB = '0' then - sum := unsigned(ma) + unsigned(mb); + sum := slv(unsigned(ma) + unsigned(mb)); else - sum := unsigned(ma) - unsigned(mb); + sum := slv(unsigned(ma) - unsigned(mb)); end if; nzo := '0'; diff --git a/rtl/w11a/pdp11_psr.vhd b/rtl/w11a/pdp11_psr.vhd index 1fd955e0..28bb5825 100644 --- a/rtl/w11a/pdp11_psr.vhd +++ b/rtl/w11a/pdp11_psr.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_psr.vhd 335 2010-10-24 22:24:23Z mueller $ +-- $Id: pdp11_psr.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2006-2010 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,10 +18,11 @@ -- Dependencies: ib_sel -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.2.2 now numeric_std clean -- 2010-10-23 335 1.2.1 use ib_sel -- 2010-10-17 333 1.2 use ibus V2 interface -- 2009-05-30 220 1.1.4 final removal of snoopers (were already commented) @@ -35,7 +36,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; @@ -60,7 +61,7 @@ end pdp11_psr; architecture syn of pdp11_psr is - constant ibaddr_psr : slv16 := conv_std_logic_vector(8#177776#,16); + constant ibaddr_psr : slv16 := slv(to_unsigned(8#177776#,16)); signal IBSEL_PSR : slbit := '0'; signal R_PSW : psw_type := psw_init; -- ps register @@ -96,7 +97,7 @@ begin proc_psw : process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if CRESET = '1' then R_PSW <= psw_init; diff --git a/rtl/w11a/pdp11_sequencer.vhd b/rtl/w11a/pdp11_sequencer.vhd index 57b73063..6528c260 100644 --- a/rtl/w11a/pdp11_sequencer.vhd +++ b/rtl/w11a/pdp11_sequencer.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_sequencer.vhd 335 2010-10-24 22:24:23Z mueller $ +-- $Id: pdp11_sequencer.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2006-2010 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,10 +18,11 @@ -- Dependencies: ib_sel -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.4.2 now numeric_std clean -- 2010-10-23 335 1.4.1 use ib_sel -- 2010-10-17 333 1.4 use ibus V2 interface -- 2010-09-18 300 1.3.2 rename (adlm)box->(oalm)unit @@ -59,7 +60,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; @@ -94,7 +95,7 @@ end pdp11_sequencer; architecture syn of pdp11_sequencer is - constant ibaddr_cpuerr : slv16 := conv_std_logic_vector(8#177766#,16); + constant ibaddr_cpuerr : slv16 := slv(to_unsigned(8#177766#,16)); constant cpuerr_ibf_illhlt : integer := 7; constant cpuerr_ibf_adderr : integer := 6; @@ -276,7 +277,7 @@ begin proc_status: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if GRESET = '1' then R_STATUS <= cpustat_init; R_CPUERR <= cpuerr_init; @@ -293,7 +294,7 @@ begin proc_state: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if GRESET = '1' then R_STATE <= s_idle; else diff --git a/rtl/w11a/pdp11_sys70.vhd b/rtl/w11a/pdp11_sys70.vhd index 384376c6..75e2f723 100644 --- a/rtl/w11a/pdp11_sys70.vhd +++ b/rtl/w11a/pdp11_sys70.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_sys70.vhd 333 2010-10-17 21:18:33Z mueller $ +-- $Id: pdp11_sys70.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2008-2010 by Walter F.J. Mueller +-- Copyright 2008-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -18,10 +18,11 @@ -- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.1.1 now numeric_std clean -- 2010-10-17 333 1.1 use ibus V2 interface -- 2008-08-22 161 1.0.1 use iblib -- 2008-04-20 137 1.0 Initial version @@ -29,7 +30,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.pdp11.all; @@ -49,8 +50,8 @@ end pdp11_sys70; architecture syn of pdp11_sys70 is - constant ibaddr_mbrk : slv16 := conv_std_logic_vector(8#177770#,16); - constant ibaddr_sysid : slv16 := conv_std_logic_vector(8#177764#,16); + constant ibaddr_mbrk : slv16 := slv(to_unsigned(8#177770#,16)); + constant ibaddr_sysid : slv16 := slv(to_unsigned(8#177764#,16)); type regs_type is record -- state registers ibsel_mbrk : slbit; -- ibus select mbrk @@ -70,7 +71,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if CRESET = '1' then R_REGS <= regs_init; else @@ -111,7 +112,7 @@ begin idout(r.mbrk'range) := r.mbrk; end if; if r.ibsel_sysid = '1' then - idout := conv_std_logic_vector(8#123456#,16); + idout := slv(to_unsigned(8#123456#,16)); end if; if r.ibsel_mbrk='1' and ibw0='1' then diff --git a/rtl/w11a/pdp11_tmu.vhd b/rtl/w11a/pdp11_tmu.vhd index e8c2f658..f7da0342 100644 --- a/rtl/w11a/pdp11_tmu.vhd +++ b/rtl/w11a/pdp11_tmu.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_tmu.vhd 333 2010-10-17 21:18:33Z mueller $ +-- $Id: pdp11_tmu.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2008-2010 by Walter F.J. Mueller +-- Copyright 2008-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,10 +19,11 @@ -- -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: ghdl 0.18-0.25 +-- Tool versions: ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.0.7 now numeric_std clean -- 2010-10-17 333 1.0.6 use ibus V2 interface -- 2010-06-26 309 1.0.5 add ibmreq.dip,.cacc,.racc to trace -- 2009-05-10 214 1.0.4 add ENA signal (trace enable) @@ -34,7 +35,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; @@ -76,7 +77,7 @@ begin begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if R_FIRST = '1' then R_FIRST <= '0'; @@ -167,7 +168,7 @@ begin end if; if wcycle then - write(oline, conv_integer(unsigned(SB_CLKCYCLE)), right, 9); + write(oline, to_integer(unsigned(SB_CLKCYCLE)), right, 9); write(oline, string'(" 0")); writeoct(oline, DM_STAT_DP.pc, right, 7); writeoct(oline, ipsw, right, 7); diff --git a/rtl/w11a/pdp11_ubmap.vhd b/rtl/w11a/pdp11_ubmap.vhd index c6596b4a..d1e64565 100644 --- a/rtl/w11a/pdp11_ubmap.vhd +++ b/rtl/w11a/pdp11_ubmap.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_ubmap.vhd 335 2010-10-24 22:24:23Z mueller $ +-- $Id: pdp11_ubmap.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2008-2010 by Walter F.J. Mueller +-- Copyright 2008-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,10 +19,11 @@ -- ib_sel -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.1.2 now numeric_std clean -- 2010-10-23 335 1.1.1 use ib_sel -- 2010-10-17 333 1.1 use ibus V2 interface -- 2008-08-22 161 1.0.1 use iblib @@ -31,7 +32,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.memlib.all; @@ -53,7 +54,7 @@ end pdp11_ubmap; architecture syn of pdp11_ubmap is - constant ibaddr_ubmap : slv16 := conv_std_logic_vector(8#170200#,16); + constant ibaddr_ubmap : slv16 := slv(to_unsigned(8#170200#,16)); signal IBSEL_UBMAP : slbit := '0'; @@ -161,7 +162,8 @@ begin MAP_1_WE <= iwe1; MAP_0_WE <= iwe0; - ADDR_PM <= unsigned(MAP_DOUT) + unsigned("000000000"&ADDR_UB(12 downto 1)); + ADDR_PM <= slv(unsigned(MAP_DOUT) + + unsigned("000000000"&ADDR_UB(12 downto 1))); IB_SRES.ack <= IBSEL_UBMAP and (IB_MREQ.re or IB_MREQ.we); IB_SRES.busy <= ibusy; diff --git a/rtl/w11a/pdp11_vmbox.vhd b/rtl/w11a/pdp11_vmbox.vhd index 56f74af9..20b860df 100644 --- a/rtl/w11a/pdp11_vmbox.vhd +++ b/rtl/w11a/pdp11_vmbox.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_vmbox.vhd 335 2010-10-24 22:24:23Z mueller $ +-- $Id: pdp11_vmbox.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2006-2010 by Walter F.J. Mueller +-- Copyright 2006-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -23,10 +23,11 @@ -- -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 +-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.6.3 now numeric_std clean -- 2010-10-23 335 1.6.2 add r.paddr_iopage, use ib_sel -- 2010-10-22 334 1.6.1 deassert ibus be's at end-cycle; fix rmw logic -- 2010-10-17 333 1.6 implement ibus V2 interface @@ -61,7 +62,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; @@ -94,7 +95,7 @@ end pdp11_vmbox; architecture syn of pdp11_vmbox is - constant ibaddr_slim : slv16 := conv_std_logic_vector(8#177774#,16); + constant ibaddr_slim : slv16 := slv(to_unsigned(8#177774#,16)); constant atowidth : natural := 5; -- size of access timeout counter type state_type is ( @@ -234,7 +235,7 @@ begin proc_slim: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if BRESET = '1' then R_SLIM <= (others=>'0'); elsif IBSEL_SLIM='1' and IB_MREQ.we='1' then @@ -247,7 +248,7 @@ begin proc_regs: process (CLK) begin - if CLK'event and CLK='1' then + if rising_edge(CLK) then if GRESET = '1' then R_REGS <= regs_init; else @@ -617,7 +618,7 @@ begin if ato_go = '0' then -- handle access timeout counter n.atocnt := atocnt_init; -- if ato_go=0, keep in reset else - n.atocnt := unsigned(r.atocnt) - 1;-- otherwise count down + n.atocnt := slv(unsigned(r.atocnt) - 1);-- otherwise count down end if; ipaddr := (others=>'0'); diff --git a/rtl/w11a/tb/tb_pdp11core.vhd b/rtl/w11a/tb/tb_pdp11core.vhd index b0477d8b..63b99d02 100644 --- a/rtl/w11a/tb/tb_pdp11core.vhd +++ b/rtl/w11a/tb/tb_pdp11core.vhd @@ -1,4 +1,4 @@ --- $Id: tb_pdp11core.vhd 352 2011-01-02 13:01:37Z mueller $ +-- $Id: tb_pdp11core.vhd 427 2011-11-19 21:04:11Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -46,6 +46,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.3.2 now numeric_std clean -- 2011-01-02 352 1.3.1 rename .cpmon->.rlmon -- 2010-12-30 351 1.3 rename tb_pdp11_core -> tb_pdp11core -- 2010-06-20 308 1.2.2 add wibrb, ribr, wibr commands for ibr accesses @@ -77,7 +78,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; @@ -353,12 +354,12 @@ begin when "rr| " => -- rr[0-7] ifunc := c_cpfunc_rreg; - irnum := conv_std_logic_vector(rind, 3); + irnum := slv(to_unsigned(rind, 3)); readtagval2_ea(iline, "d", ichk, idin, imsk, 8); when "wr| " => -- wr[0-7] ifunc := c_cpfunc_wreg; - irnum := conv_std_logic_vector(rind, 3); + irnum := slv(to_unsigned(rind, 3)); readoct_ea(iline, idin); -- Note: there are no field definitions for wal, wah, wibrb because @@ -524,7 +525,7 @@ begin end loop; if imemi then -- rmi or wmi seen ? then inc ar - r_addr := unsigned(r_addr) + 1; + r_addr := slv(unsigned(r_addr) + 1); end if; write(oline, dcycle, right, 4); @@ -637,7 +638,7 @@ begin begin loop - wait until CLK'event and CLK='1'; + wait until rising_edge(CLK); wait for c2out_time; R_WAITOK <= '0'; diff --git a/rtl/w11a/tb/tbd_pdp11core.vhd b/rtl/w11a/tb/tbd_pdp11core.vhd index 1ee0ad3a..e9ea74dd 100644 --- a/rtl/w11a/tb/tbd_pdp11core.vhd +++ b/rtl/w11a/tb/tbd_pdp11core.vhd @@ -1,6 +1,6 @@ --- $Id: tbd_pdp11core.vhd 351 2010-12-30 21:50:54Z mueller $ +-- $Id: tbd_pdp11core.vhd 427 2011-11-19 21:04:11Z mueller $ -- --- Copyright 2007-2010 by Walter F.J. Mueller +-- Copyright 2007-2011 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -26,7 +26,7 @@ -- To test: pdp11_core -- -- Target Devices: generic --- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -41,6 +41,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2011-11-18 427 1.5.1 now numeric_std clean -- 2010-12-30 351 1.5 rename tbd_pdp11_core -> tbd_pdp11core -- 2010-10-23 335 1.4.2 rename RRI_LAM->RB_LAM; -- 2010-06-20 307 1.4.1 add CP_ADDR_racc, CP_ADDR_be port @@ -63,7 +64,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; use work.slvtypes.all; use work.genlib.all; diff --git a/tools/bin/pi_rri b/tools/bin/pi_rri index d67d199b..0ac9a7f6 100755 --- a/tools/bin/pi_rri +++ b/tools/bin/pi_rri @@ -1,5 +1,5 @@ #!/usr/bin/perl -w -# $Id: pi_rri 374 2011-03-27 17:02:47Z mueller $ +# $Id: pi_rri 410 2011-09-18 11:23:09Z mueller $ # # Copyright 2007-2010 by Walter F.J. Mueller # @@ -14,6 +14,7 @@ # # Revision History: # Date Rev Version Comment +# 2011-09-17 410 1.6.4 use for crc8 now a6 polynomial # 2010-12-29 351 1.6.3 rename rriext->cext and cpmon->rlmon # 2010-06-27 310 1.6.2 fix autoflush for fh_log; duplicate exec err to log # 2010-06-18 306 1.6.1 PDPCP_ADDR_IBRB now 020, PDPCP_ADDR_IBR now 0200; @@ -511,38 +512,38 @@ my %rri_cname2cmd = (rreg => 0, # c_rri_cmd_rreg : slv3 := "000"; attn => 5, # c_rri_cmd_attn : slv3 := "101"; init => 6); # c_rri_cmd_init : slv3 := "110"; -my @crc8_tbl = ( 0, 29, 58, 39, 116, 105, 78, 83, # from gen_crc8_tbl - 232, 245, 210, 207, 156, 129, 166, 187, - 205, 208, 247, 234, 185, 164, 131, 158, - 37, 56, 31, 2, 81, 76, 107, 118, - 135, 154, 189, 160, 243, 238, 201, 212, - 111, 114, 85, 72, 27, 6, 33, 60, - 74, 87, 112, 109, 62, 35, 4, 25, - 162, 191, 152, 133, 214, 203, 236, 241, - 19, 14, 41, 52, 103, 122, 93, 64, - 251, 230, 193, 220, 143, 146, 181, 168, - 222, 195, 228, 249, 170, 183, 144, 141, - 54, 43, 12, 17, 66, 95, 120, 101, - 148, 137, 174, 179, 224, 253, 218, 199, - 124, 97, 70, 91, 8, 21, 50, 47, - 89, 68, 99, 126, 45, 48, 23, 10, - 177, 172, 139, 150, 197, 216, 255, 226, - 38, 59, 28, 1, 82, 79, 104, 117, - 206, 211, 244, 233, 186, 167, 128, 157, - 235, 246, 209, 204, 159, 130, 165, 184, - 3, 30, 57, 36, 119, 106, 77, 80, - 161, 188, 155, 134, 213, 200, 239, 242, - 73, 84, 115, 110, 61, 32, 7, 26, - 108, 113, 86, 75, 24, 5, 34, 63, - 132, 153, 190, 163, 240, 237, 202, 215, - 53, 40, 15, 18, 65, 92, 123, 102, - 221, 192, 231, 250, 169, 180, 147, 142, - 248, 229, 194, 223, 140, 145, 182, 171, - 16, 13, 42, 55, 100, 121, 94, 67, - 178, 175, 136, 149, 198, 219, 252, 225, - 90, 71, 96, 125, 46, 51, 20, 9, - 127, 98, 69, 88, 11, 22, 49, 44, - 151, 138, 173, 176, 227, 254, 217, 196); +my @crc8_tbl = ( 0, 77, 154, 215, 121, 52, 227, 174, # from gen_crc8_tbl + 242, 191, 104, 37, 139, 198, 17, 92, + 169, 228, 51, 126, 208, 157, 74, 7, + 91, 22, 193, 140, 34, 111, 184, 245, + 31, 82, 133, 200, 102, 43, 252, 177, + 237, 160, 119, 58, 148, 217, 14, 67, + 182, 251, 44, 97, 207, 130, 85, 24, + 68, 9, 222, 147, 61, 112, 167, 234, + 62, 115, 164, 233, 71, 10, 221, 144, + 204, 129, 86, 27, 181, 248, 47, 98, + 151, 218, 13, 64, 238, 163, 116, 57, + 101, 40, 255, 178, 28, 81, 134, 203, + 33, 108, 187, 246, 88, 21, 194, 143, + 211, 158, 73, 4, 170, 231, 48, 125, + 136, 197, 18, 95, 241, 188, 107, 38, + 122, 55, 224, 173, 3, 78, 153, 212, + 124, 49, 230, 171, 5, 72, 159, 210, + 142, 195, 20, 89, 247, 186, 109, 32, + 213, 152, 79, 2, 172, 225, 54, 123, + 39, 106, 189, 240, 94, 19, 196, 137, + 99, 46, 249, 180, 26, 87, 128, 205, + 145, 220, 11, 70, 232, 165, 114, 63, + 202, 135, 80, 29, 179, 254, 41, 100, + 56, 117, 162, 239, 65, 12, 219, 150, + 66, 15, 216, 149, 59, 118, 161, 236, + 176, 253, 42, 103, 201, 132, 83, 30, + 235, 166, 113, 60, 146, 223, 8, 69, + 25, 84, 131, 206, 96, 45, 250, 183, + 93, 16, 199, 138, 36, 105, 190, 243, + 175, 226, 53, 120, 214, 155, 76, 1, + 244, 185, 110, 35, 141, 192, 23, 90, + 6, 75, 156, 209, 127, 50, 229, 168); my $ocrc = 0; my $icrc = 0; diff --git a/tools/bin/tbw b/tools/bin/tbw index c2321a34..8979517d 100755 --- a/tools/bin/tbw +++ b/tools/bin/tbw @@ -1,7 +1,7 @@ #!/usr/bin/perl -w -# $Id: tbw 314 2010-07-09 17:38:41Z mueller $ +# $Id: tbw 420 2011-11-06 21:25:54Z mueller $ # -# Copyright 2007-2010 by Walter F.J. Mueller +# Copyright 2007-2011 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -14,6 +14,7 @@ # # Revision History: # Date Rev Version Comment +# 2011-11-06 420 1.2.3 fix tbw.dat parsing (allow / in file names) # 2010-05-23 294 1.2.2 handle tb_code's in non-local directories # 2010-04-18 279 1.2.1 add -help and more text to print_usage() # 2009-11-22 252 1.2 add ISim support @@ -103,15 +104,17 @@ if (-r $tbwdat_file) { while () { chomp; next if /^#/; - if (/^\s*\[([\.\/a-zA-Z0-9_]*)\]\s*$/) { + if ( m{^\s*\[([\.\/a-zA-Z0-9_]*)\]\s*$} ) { last if $done; $ok = 0; $ok = 1 if ($1 eq $tb_code || $1 eq $tb_code_stem); - } elsif (/^\s*([a-zA-Z0-9_]*)\s*=\s*([a-zA-Z0-9_.<>]*)\s*$/) { + } elsif ( m{^\s*([a-zA-Z0-9_]*)\s*=\s*([a-zA-Z0-9_./<>]*)\s*$} ) { if ($ok) { push @file_dsc, {tag=>$1, val=>$2}; $done = 1; } + } else { + print "tbw-E: bad line in tbw.dat:\n $_\n"; } } } @@ -125,6 +128,14 @@ unless (scalar (@file_dsc)) { val=>$tb_code_stem . "_stim.dat"}; } +if (0) { + foreach my $dsc (@file_dsc) { + my $tag = $dsc->{tag}; + my $val = $dsc->{val}; + printf " %s = %s\n", $tag, $val; + } +} + # # now process argument list # diff --git a/tools/src/Makefile b/tools/src/Makefile index 8954a101..31522fa7 100644 --- a/tools/src/Makefile +++ b/tools/src/Makefile @@ -5,7 +5,7 @@ # # Revision History: # Date Rev Version Comment -# 2011-07-31 401 1.2 rename realclean->distclean +# 2011-07-31 401 1.2 rename realclean->distclean; add librusbtpp # 2011-03-20 372 1.1.1 renamed ..tcl -> ..tpp # 2011-03-14 370 1.1.0 rename librtoolstcl -> librtcltools # 2011-02-13 361 1.1 add realclean rule; add dirs and dependencies @@ -16,6 +16,7 @@ DIRS += librlink DIRS += librtcltools DIRS += librutiltpp DIRS += librlinktpp +DIRS += librusbtpp # BUILDDIRS = $(DIRS:%=build-%) CLEANDIRS = $(DIRS:%=clean-%) @@ -35,6 +36,7 @@ build-librlink : build-librtools build-librtcltools : build-librtools build-librutiltpp : build-librtcltools build-librlinktpp : build-librlink build-librtcltools +build-librusbtpp : build-librtcltools # $(BUILDDIRS): $(MAKE) -C $(@:build-%=%) diff --git a/tools/src/librlink/RlinkCrc8.cpp b/tools/src/librlink/RlinkCrc8.cpp index 12073eba..9f20b2ca 100644 --- a/tools/src/librlink/RlinkCrc8.cpp +++ b/tools/src/librlink/RlinkCrc8.cpp @@ -1,4 +1,4 @@ -// $Id: RlinkCrc8.cpp 365 2011-02-28 07:28:26Z mueller $ +// $Id: RlinkCrc8.cpp 410 2011-09-18 11:23:09Z mueller $ // // Copyright 2011- by Walter F.J. Mueller // @@ -13,13 +13,14 @@ // // Revision History: // Date Rev Version Comment +// 2011-09-17 410 1.1 use now a6 polynomial for crc8 // 2011-02-27 365 1.0 Initial version // 2011-01-15 355 0.1 First draft // --------------------------------------------------------------------------- /*! \file - \version $Id: RlinkCrc8.cpp 365 2011-02-28 07:28:26Z mueller $ + \version $Id: RlinkCrc8.cpp 410 2011-09-18 11:23:09Z mueller $ \brief Implemenation of class RlinkCrc8. */ @@ -39,38 +40,38 @@ using namespace Retro; const uint8_t RlinkCrc8::fCrc8Table[256] = { - 0, 29, 58, 39, 116, 105, 78, 83, - 232, 245, 210, 207, 156, 129, 166, 187, - 205, 208, 247, 234, 185, 164, 131, 158, - 37, 56, 31, 2, 81, 76, 107, 118, - 135, 154, 189, 160, 243, 238, 201, 212, - 111, 114, 85, 72, 27, 6, 33, 60, - 74, 87, 112, 109, 62, 35, 4, 25, - 162, 191, 152, 133, 214, 203, 236, 241, - 19, 14, 41, 52, 103, 122, 93, 64, - 251, 230, 193, 220, 143, 146, 181, 168, - 222, 195, 228, 249, 170, 183, 144, 141, - 54, 43, 12, 17, 66, 95, 120, 101, - 148, 137, 174, 179, 224, 253, 218, 199, - 124, 97, 70, 91, 8, 21, 50, 47, - 89, 68, 99, 126, 45, 48, 23, 10, - 177, 172, 139, 150, 197, 216, 255, 226, - 38, 59, 28, 1, 82, 79, 104, 117, - 206, 211, 244, 233, 186, 167, 128, 157, - 235, 246, 209, 204, 159, 130, 165, 184, - 3, 30, 57, 36, 119, 106, 77, 80, - 161, 188, 155, 134, 213, 200, 239, 242, - 73, 84, 115, 110, 61, 32, 7, 26, - 108, 113, 86, 75, 24, 5, 34, 63, - 132, 153, 190, 163, 240, 237, 202, 215, - 53, 40, 15, 18, 65, 92, 123, 102, - 221, 192, 231, 250, 169, 180, 147, 142, - 248, 229, 194, 223, 140, 145, 182, 171, - 16, 13, 42, 55, 100, 121, 94, 67, - 178, 175, 136, 149, 198, 219, 252, 225, - 90, 71, 96, 125, 46, 51, 20, 9, - 127, 98, 69, 88, 11, 22, 49, 44, - 151, 138, 173, 176, 227, 254, 217, 196 + 0, 77, 154, 215, 121, 52, 227, 174, // from gen_crc8_tbl + 242, 191, 104, 37, 139, 198, 17, 92, + 169, 228, 51, 126, 208, 157, 74, 7, + 91, 22, 193, 140, 34, 111, 184, 245, + 31, 82, 133, 200, 102, 43, 252, 177, + 237, 160, 119, 58, 148, 217, 14, 67, + 182, 251, 44, 97, 207, 130, 85, 24, + 68, 9, 222, 147, 61, 112, 167, 234, + 62, 115, 164, 233, 71, 10, 221, 144, + 204, 129, 86, 27, 181, 248, 47, 98, + 151, 218, 13, 64, 238, 163, 116, 57, + 101, 40, 255, 178, 28, 81, 134, 203, + 33, 108, 187, 246, 88, 21, 194, 143, + 211, 158, 73, 4, 170, 231, 48, 125, + 136, 197, 18, 95, 241, 188, 107, 38, + 122, 55, 224, 173, 3, 78, 153, 212, + 124, 49, 230, 171, 5, 72, 159, 210, + 142, 195, 20, 89, 247, 186, 109, 32, + 213, 152, 79, 2, 172, 225, 54, 123, + 39, 106, 189, 240, 94, 19, 196, 137, + 99, 46, 249, 180, 26, 87, 128, 205, + 145, 220, 11, 70, 232, 165, 114, 63, + 202, 135, 80, 29, 179, 254, 41, 100, + 56, 117, 162, 239, 65, 12, 219, 150, + 66, 15, 216, 149, 59, 118, 161, 236, + 176, 253, 42, 103, 201, 132, 83, 30, + 235, 166, 113, 60, 146, 223, 8, 69, + 25, 84, 131, 206, 96, 45, 250, 183, + 93, 16, 199, 138, 36, 105, 190, 243, + 175, 226, 53, 120, 214, 155, 76, 1, + 244, 185, 110, 35, 141, 192, 23, 90, + 6, 75, 156, 209, 127, 50, 229, 168 }; //------------------------------------------+----------------------------------- diff --git a/tools/tcl/setup_packages b/tools/tcl/setup_packages index 78179ea5..a56158dd 100755 --- a/tools/tcl/setup_packages +++ b/tools/tcl/setup_packages @@ -11,4 +11,6 @@ pkg_mkIndex -verbose rbbram *.tcl pkg_mkIndex -verbose rbs3hio *.tcl pkg_mkIndex -verbose rbemon *.tcl # +pkg_mkIndex -verbose tstsram *.tcl +# pkg_mkIndex -verbose tst_rlink *.tcl