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pdp11_sequencer: BUGFIX: correct ysv flow implementation
- rtl/w11a - pdp11.vhd: rename, eg srv->ser; drop trap_done; add in_vecysv - pdp11_sequencer: renames; BUGFIX: correct ysv flow implementation - pdp11_vmbox.vhd: rename some rsv->ser; remove obsolete trap_done - tools/tbench/w11a/test_w11a_cpuerr.tcl: removed, all in cpu_details.mac - tools/tcl/rw11/defs.tcl: renames - tools/tcode/cpu_details.mac: expand A3.3, add A3.4
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wfjm
@@ -1,10 +1,10 @@
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; $Id: cpu_details.mac 1317 2022-11-19 15:33:42Z mueller $
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; $Id: cpu_details.mac 1320 2022-11-22 18:52:59Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; Revision History:
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; Date Rev Version Comment
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; 2022-11-18 1316 1.0 Initial version
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; 2022-11-22 1320 1.0 Initial version
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; 2022-07-18 1259 0.1 First draft
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;
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; Test CPU details
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@@ -76,7 +76,7 @@
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pi.n06=6*042 ; lsb for pir 6 next
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pi.n07=7*042 ; lsb for pir 7 next
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;
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ta0101: mov #1000$,v..pir ; setup handler
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ta0101: mov #1000$,v..pir ; set up handler
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mov #cp.pr7,v..pir+2 ; which runs at pr7
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mov #cp.pir,r3 ; ptr to PIRQ
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mov #cp.psw,r4 ; ptr to PSW
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@@ -444,8 +444,7 @@ ta0302:
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200$: halt
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halt
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;
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1000$: clr cp.err ; HACK: clear CPUERR !!!
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tst sp ; red abort seen ?
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1000$: tst sp ; red abort seen ?
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beq 1010$ ; if yes, check status
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inc r2 ; if no, got for next push
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rti
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@@ -525,10 +524,13 @@ ta0302:
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;
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9999$: iot ; end of test A3.2
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;
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; Test A3.3 -- stack trap address modes ++++++++++++++++++++++++++++++
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; Test A3.3 -- stack trap conditions +++++++++++++++++++++++++++++++++
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; Verifies that mode 1,2,4,6 trap for dstw flows and dstr when rmw
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; Verifies that mode 3,5,7 writes do not trap
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; Verifies that mode 1-7 reads do not trap
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; Verifies that implict pushes (JSR,MFPI) trap
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; Verifies that vector push of trap instructions (EMT,TRAP tested) traps
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; Verifies that vector push of an interrupt (PIRQ tested) traps
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; Notes:
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; - dstw (mov,clr,..) and dstr (add,bis,...) flows write to stack -> test both
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; - inspired by eqkce0 test 041 that verifies do/dont trap instruction cases
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@@ -538,17 +540,18 @@ ta0303: tstb systyp ; skip if not on w11
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bge 100$
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jmp 9999$
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;
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100$: mov #1000$,v..iit ; set up iit handler
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100$: mov #1400,cp.slr ; set yellow limit to 1776
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;
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; part 1: test instructions that should trap -------------------------
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;
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mov #1000$,v..iit ; set up iit handler
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clr v..iit+2
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mov #1100$,v..emt ; set up emt handler
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clr v..emt+2
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mov #1200$,v..trp ; set up trap handler
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clr v..trp+2
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mov #1400,cp.slr ; set yellow limit to 1776
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clr r2 ; clear trap counter
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;
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; part 1: test instructions that should trap -------------------------
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;
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; dstw mode 1,2,4,6
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mov #1000,-(sp) ; dstw mode 4: SP now 1776 (1)
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clr -(sp) ; dstw mode 4: SP now 1774 (2)
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@@ -571,8 +574,7 @@ ta0303: tstb systyp ; skip if not on w11
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;
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br 1500$
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;
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1000$: clr cp.err ; HACK: clear CPUERR !!!
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htstne sp ; no red stack aborts expected
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1000$: htstne sp ; no red stack aborts expected
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inc r2
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rti
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;
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@@ -587,7 +589,7 @@ ta0303: tstb systyp ; skip if not on w11
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;
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; part 2: test instructions that should not trap ---------------------
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;
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mov #stack-2,r2 ; in yellow zone
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2000$: mov #stack-2,r2 ; in yellow zone
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mov r2,(r2) ; load on stack (not using SP)
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mov r2,sp ; SP in yellow zone
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; dstw mode 3,5,7
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@@ -611,11 +613,130 @@ ta0303: tstb systyp ; skip if not on w11
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clr sp
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mov @#2000,2000(sp) ; SP=0, EA=2000 -> no trap
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;
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; part 3: test that interrupt (from PIRQ) vector push traps ----------
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; Triggers 3 PIRQ interrupts at PR1, PR3, and PR6.
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; The PIRQ interrupt vector push will issue a ysv trap.
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; That trap executes before the first instruction of the pir handler.
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; The iit handler must therefore execute at PR7 to lockout interrupts.
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; When the iit handler returns, the pir hander will execute.
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;
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3000$: mov #3100$,v..iit ; set up iit handler
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mov #cp.pr7,v..iit+2 ; lockout interrupts !
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mov #3200$,v..pir ; set up pir handler
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mov #cp.pr7,v..pir+2 ; lockout interrupts
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mov #stack,sp ; SP to default (STKLIM still 1400)
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clr r2 ; clear trap counter
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mov #cp.pir,r3 ; ptr to cp.pir
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mov #3500$,r5 ; ptr to probe data
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;
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spl 0
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movb #bit06!bit03!bit01,1(r3) ; request PIRQ 6+3+1
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nop
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br 3900$
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;
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; iit handler
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3100$: htstne sp ; no red stack aborts expected
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hcmpeq #177777,(r5)+ ; check state
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inc r2
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rti
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;
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; pir handler
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3200$: mov (r3),r0 ; get PIRQ
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bic #177761,r0 ; mask out index bits (is pri*2)
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asr r0 ; now pri*1
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hcmpeq r0,(r5)+ ; check state
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mov #pi.r00,r1
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ash r0,r1 ; pi.r00 <<(pri)
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bic r1,(r3) ; clear PIRQ request
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rti
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;
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; state check data
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3500$: .word 177777,6. ; iit marker + pr6 pirq
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.word 177777,3. ; iit marker + pr3 pirq
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.word 177777,1. ; iit marker + pr1 pirq
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;
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3900$: hcmpeq #3.,r2 ; all traps taken ?
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mov #v..iit+2,v..iit ; v..iit to catcher
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clr v..iit+2
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mov #v..pir+2,v..pir ; v..pir to catcher
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clr v..pir+2
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;
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; final cleanup
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clr cp.slr ; STKLIM to default
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mov #stack,sp ; SP to default
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;
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9999$: iot ; end of test A3.3
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;
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; Test A3.4 -- red stack abort conditions ++++++++++++++++++++++++++++
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; Verifies that instruction writes abort
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; Verifies that implict pushes (JSR,MFPI) abort
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; Verifies that vector push after trap instructions and interrupts abort
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; Abort on 1st and 2nd push is tested.
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;
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ta0304:
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mov #1000$,v..iit ; set up iit handler
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mov #cp.pr7,v..iit+2 ; lockout interrupts !
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mov #1400,cp.slr ; yellow <=1776 and red <= 1736
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clr @#1736 ; ensure top red word zero
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clr cp.err ; clear CPUERR
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;
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; dstw flow
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mov #1740,sp ; SP at red border
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mov #100$,r5
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mov #123456,-(sp)
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halt
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;
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; dstr flow (rmw)
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100$: mov #200$,r5
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add (sp),-(sp)
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halt
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;
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; implicit push instructions
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200$: mov #300$,r5
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jsr pc,210$
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halt
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210$: halt
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;
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300$: mov #400$,r5
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mfpi r0
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halt
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;
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; vector flow abort in 2nd push, 1st push in yellow (use EMT for test)
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; Note: SimH scribbles into red zone, therefore test skipped for SimH
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400$: cmpb systyp,#sy.sih ; skip section on SimH
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beq 500$
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mov sp,r0
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mov #123456,(r0)+ ; write marker to 1740, r0 to avoid ysv
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mov r0,sp ; SP now 1402 -> abort on 2nd push
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mov #cp.pr3,cp.psw ; set pr3 as marker
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mov #420$,r5 ; leaves NZVC = 0000
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emt 100
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410$: halt
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420$: hcmpeq #cp.pr3,@#1740 ; check that PS written
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;
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; vector flow abort in 1st push (use PIRQ for test)
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500$: spl 0
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mov #600$,r5
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mov #pi.r04,cp.pir ; request PIRQ 4
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halt
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600$: clr cp.pir
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br 9000$
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;
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1000$: htsteq sp ; check SP=0
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htsteq @#1736 ; check stack clean
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hcmpeq #cp.rsv,cp.err ; check CPUERR.rsv (and no ysv)
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clr cp.err ; clear CPUERR
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mov #1740,sp ; restore SP
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jmp (r5) ; continue
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;
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9000$: clr cp.slr ; STKLIM to default
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mov #v..iit+2,v..iit ; v..iit to catcher
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clr v..iit+2
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mov #stack,sp ; SP to default
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spl 0 ; back to PR0
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;
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9999$: iot ; end of test A3.4
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;
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; Section B: Stress tests ====================================================
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;
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; Test B1: address mode torture tests +++++++++++++++++++++++++++++++++++++++
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@@ -826,21 +947,22 @@ tc0103: mov #vhugen,v..iit ; set iit handler
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; END OF ALL TESTS - loop closure ============================================
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;
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mov tstno,r0 ; hack, for easy monitoring ...
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hcmpeq tstno,#22. ; all tests done ?
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hcmpeq tstno,#23. ; all tests done ?
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;
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jmp loop
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;
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; kernel handlers ============================================================
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;
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; vhugen - generic handler for expected traps/abort ++++++++++++++++++++++++++
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; the kernel continution address must be written to vhustp
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; the continution address must be written to vhustp
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; execution will reset vhustp to a catcher value
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; --> vhustp must be set for each execution
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;
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vhugen: tst (sp)+ ; discard one word of vector push
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mov vhustp,(sp) ; set up kernel return address
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vhugen: add #4,sp ; discard vector frame
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mov vhustp,100$ ; set up return address
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mov #vhuhlt,vhustp ; reset stop address by catcher
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rts pc ; end return to continuation address
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jmp @100$ ; end return to continuation address
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100$: .word 0
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vhustp: .word vhuhlt
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vhuhlt: halt
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;
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