diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index dff0923e..26281b18 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -28,8 +28,9 @@ The full set of tests is only run for tagged releases. ### Summary - cleanup tbrun setup, drop nexys4 and add nexys4d ([see blog](https://wfjm.github.io/blogs/w11/2019-07-27-nexys4-obituary.html)) - add ostest support for rsx11m-31_rk, rsx11m-40_rk and rsx11mp-30_rp oskits -- Doxygen support now for V1.9.4 and without discontinued Tcl - all actively used commands have now a man page +- Doxygen support now for V1.9.4; remove discontinued Tcl support +- build flow Vivado 2022.1 ready; handle synth 8-3331 -> 8-7129 transition) ### New features ### Changes - tools changes diff --git a/doc/INSTALL_simh.md b/doc/INSTALL_simh.md index a88a8705..467783e2 100644 --- a/doc/INSTALL_simh.md +++ b/doc/INSTALL_simh.md @@ -32,7 +32,7 @@ The maintainer of the [simh/simh](https://github.com/simh/simh) GitHub project, [Mark Pizzolato](https://github.com/markpizz), decided on May 15th, 2022 with commit [ce2adce6](https://github.com/simh/simh/commit/ce2adce6) to change the license of the repository. The bottom line of the change is, that some files -are declared proprietary and this repository is not longer a +are declared proprietary and this repository is no longer a [FOSS](https://en.wikipedia.org/wiki/Free_and_open-source_software) project, see also issue [#1163](https://github.com/simh/simh/issues/1163). This triggered massive reactions, see issue @@ -40,7 +40,7 @@ This triggered massive reactions, see issue SimH mailing list [simh@groups.io](https://groups.io/g/simh), starting with post [New license?](https://groups.io/g/simh/topic/new_license/91108560). See especially Bob Supnik's post -[SimH licensing and the state of the project](https://groups.io/g/simh/topic/simh_licensing_and_the_state/91173868) +[SimH licensing and the state of the project](https://groups.io/g/simh/topic/simh_licensing_and_the_state/91173868). Given that situation using version `v3.11-1` as described above is the only prudent option for the time being. diff --git a/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vmfset b/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vmfset index 16f3e783..7a6ca6c7 100644 --- a/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vmfset +++ b/rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_tst_mig_arty.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_tst_mig_arty.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2019-02-02 1108 2018.3 # 2019-02-02 1108 2017.2 # @@ -10,7 +11,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # false_path -hold ignored by synth ---------------------------- @@ -23,6 +27,7 @@ I [Designutils 20-1567] # generic i [Synth 8-3295] RLINK:RB_LAM[\d*] # unconnected ports -------------------------------------------- +{:2019.2} I [Synth 8-3331] RB_MREQ # generic # --> I_SWI not used # OK 2018-12-23 i [Synth 8-3331] I_SWI[\d] @@ -32,6 +37,18 @@ i [Synth 8-3331] O_LED[(2|3)] i [Synth 8-3331] rlink_sp2c.*CE_(USEC|MSEC) # --> APP_SR_ACTIVE is unused (reserved port) # OK 2018-12-23 i [Synth 8-3331] APP_SR_ACTIVE +# ------------------ +{2022.1:} +I [Synth 8-7129] RB_MREQ # generic +# --> I_SWI not used # OK 2022-05-26 +i [Synth 8-7129] I_SWI[\d] +# --> O_LED only partially used # OK 2022-05-26 +i [Synth 8-7129] O_LED[(2|3)] +# --> rlink_sp2c doesn't use CE_USEC and CE_MSEC # OK 2022-05-26 +i [Synth 8-7129] CE_(USEC|MSEC) .* rlink_sp2c +# --> APP_SR_ACTIVE is unused (reserved port) # OK 2022-06-26 +i [Synth 8-7129] APP_SR_ACTIVE +{:} # sequential element removed (2017.1 nonsense) ----------------- I [Synth 8-6014] _reg # generic diff --git a/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vmfset b/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vmfset index 82286898..2b4b621e 100644 --- a/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vmfset +++ b/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_tst_mig_n4d.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_tst_mig_n4d.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2019-08-10 1201 2019.1 # 2019-02-02 1108 2018.3 # 2019-02-02 1108 2017.2 @@ -11,7 +12,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # false_path -hold ignored by synth ---------------------------- @@ -30,6 +34,7 @@ i [Synth 8-3917] O_SEG_N[\d] i [Synth 8-3295] RLINK:RB_LAM[\d*] # unconnected ports -------------------------------------------- +{:2019.2} I [Synth 8-3331] RB_MREQ # generic # --> I_SWI not used # OK 2018-12-30 i [Synth 8-3331] I_SWI[\d+] @@ -40,6 +45,19 @@ i [Synth 8-3331] I_BTNRST_N i [Synth 8-3331] rlink_sp2c.*CE_(USEC|MSEC) # --> APP_SR_ACTIVE is unused (reserved port) # OK 2018-12-30 i [Synth 8-3331] APP_SR_ACTIVE +# ------------------ +{2022.1:} +I [Synth 8-7129] RB_MREQ # generic +# --> I_SWI not used # OK 2022-05-26 +i [Synth 8-7129] I_SWI[\d+] +# --> I_BTN partially, I_BTNRST_N not used # OK 2022-05-26 +i [Synth 8-7129] I_BTN[4] +i [Synth 8-7129] I_BTNRST_N +# --> rlink_sp2c doesn't use CE_USEC and CE_MSEC # OK 2022-05-26 +i [Synth 8-7129] CE_(USEC|MSEC) .* rlink_sp2c +# --> APP_SR_ACTIVE is unused (reserved port) # OK 2022-06-26 +i [Synth 8-7129] APP_SR_ACTIVE +{:} # sequential element removed (2017.1 nonsense) ----------------- I [Synth 8-6014] _reg # generic diff --git a/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vmfset b/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vmfset index 20f4e21b..1f0ad91e 100644 --- a/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vmfset +++ b/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_tst_rlink_arty.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_tst_rlink_arty.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2022-04-23 1225 2020.1 # 2019-02-02 1108 2018.3 # 2019-02-02 1108 2017.2 @@ -11,7 +12,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # unconnected ports -------------------------------------------- @@ -19,6 +23,11 @@ i [Constraints 18-5210] # generic I [Synth 8-3331] RB_MREQ # generic # --> rlink_sp1c doesn't use CE_USEC # OK 2016-06-05 i [Synth 8-3331] rlink_sp1c.*CE_USEC +# ------------------ +{2022.1:} +I [Synth 8-7129] RB_MREQ # generic +# --> rlink_sp1c doesn't use CE_USEC # OK 2022-05-26 +i [Synth 8-7129] CE_USEC .* rlink_sp1c {:} # sequential element removed (2017.1 nonsense) ----------------- diff --git a/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vmfset b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vmfset index 5ea46cc4..fc6ed8a4 100644 --- a/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vmfset +++ b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_tst_rlink_b3.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_tst_rlink_b3.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2022-04-23 1225 2020.1 # 2019-02-02 1108 2018.3 # 2019-02-02 1108 2017.2 @@ -11,7 +12,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # unconnected ports -------------------------------------------- @@ -19,6 +23,11 @@ i [Constraints 18-5210] # generic I [Synth 8-3331] RB_MREQ # generic # --> rlink_sp1c doesn't use CE_USEC # OK 2016-06-05 i [Synth 8-3331] rlink_sp1c.*CE_USEC +# ------------------ +{2022.1:} +I [Synth 8-7129] RB_MREQ # generic +# --> rlink_sp1c doesn't use CE_USEC # OK 2022-05-26 +i [Synth 8-7129] CE_USEC .* rlink_sp1c {:} # sequential element removed (2017.1 nonsense) ----------------- diff --git a/rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vmfset b/rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vmfset index 9d249c09..91f27b3f 100644 --- a/rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vmfset +++ b/rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_tst_rlink_c7.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_tst_rlink_c7.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2022-04-23 1225 2020.1 # 2019-02-02 1108 2018.3 # 2019-02-02 1108 2017.2 @@ -11,7 +12,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # unconnected ports -------------------------------------------- @@ -21,6 +25,13 @@ I [Synth 8-3331] RB_MREQ # generic i [Synth 8-3331] rlink_sp1c.*CE_USEC # --> I_BTN unused # OK 2017-06-05 i [Synth 8-3331] I_BTN[\d+] +# ------------------ +{2022.1:} +I [Synth 8-7129] RB_MREQ # generic +# --> rlink_sp1c doesn't use CE_USEC # OK 2022-05-26 +i [Synth 8-7129] CE_USEC .* rlink_sp1c +# --> I_BTN unused # OK 2022-05-26 +i [Synth 8-7129] I_BTN[\d+] {:} # sequential element removed (2017.1 nonsense) ----------------- diff --git a/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vmfset b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vmfset index 34d595f7..b7bf8530 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vmfset +++ b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_tst_rlink_n4.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_tst_rlink_n4.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2019-02-02 1108 2018.3 # 2019-02-02 1108 2017.2 # @@ -10,15 +11,27 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # unconnected ports -------------------------------------------- +{:2019.2} I [Synth 8-3331] RB_MREQ # generic # --> I_BTNRST_N unused in design # OK 2016-06-05 -I [Synth 8-3331] I_BTNRST_N +i [Synth 8-3331] I_BTNRST_N # --> rlink_sp1c doesn't use CE_USEC # OK 2016-06-05 i [Synth 8-3331] rlink_sp1c.*CE_USEC +# ------------------ +{2022.1:} +I [Synth 8-7129] RB_MREQ # generic +# --> I_BTNRST_N unused in design # OK 2022-05-26 +i [Synth 8-7129] I_BTNRST_N +# --> rlink_sp1c doesn't use CE_USEC # OK 2022-05-26 +i [Synth 8-7129] CE_USEC .* rlink_sp1c +{:} # sequential element removed (2017.1 nonsense) ----------------- I [Synth 8-6014] _reg # generic diff --git a/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vmfset b/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vmfset new file mode 100644 index 00000000..9e5d85b9 --- /dev/null +++ b/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vmfset @@ -0,0 +1,55 @@ +# $Id: sys_tst_rlink_n4d.vmfset 1242 2022-05-27 17:08:43Z mueller $ +# +# Validated code/tool version combinations +# Date rev viv +# 2022-05-26 1242 2022.1 +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# general issues ----------------------------------------------- +{2018.2:} +# stupid new warning, Xilinx suggests to safely ingnore +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] +{:} + +# unconnected ports -------------------------------------------- +{:2019.2} +I [Synth 8-3331] RB_MREQ # generic +# --> I_BTNRST_N unused in design # OK 2016-06-05 +i [Synth 8-3331] I_BTNRST_N +# --> rlink_sp1c doesn't use CE_USEC # OK 2016-06-05 +i [Synth 8-3331] rlink_sp1c.*CE_USEC +# ------------------ +{2022.1:} +I [Synth 8-7129] RB_MREQ # generic +# --> I_BTNRST_N unused in design # OK 2022-05-26 +i [Synth 8-7129] I_BTNRST_N +# --> rlink_sp1c doesn't use CE_USEC # OK 2022-05-26 +i [Synth 8-7129] CE_USEC .* rlink_sp1c +{:} + +# sequential element removed (2017.1 nonsense) ----------------- +I [Synth 8-6014] _reg # generic + +# unused sequential element ------------------------------------ +{2017.2:2018.2} +I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic +# --> monitor outputs moneop,monattn currently not used # OK 2016-06-05 +i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop] +i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn] +# --> LED(6:2) currently not driven # OK 2016-06-05 +i [Synth 8-3332] R_REGS_reg[ledin][\d].*sn_humanio_rbus +# ENAESC=0, therefore esc logic inactive # OK 2016-06-05 +i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[escseen] +i [Synth 8-3332] SERPORT/XONTX/R_REGS_reg[escpend] +# --> SER_MONI.rxovr indeed unused # OK 2016-06-05 +i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[rxovr] +{:} + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization diff --git a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vmfset b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vmfset index cb0bca0e..a964c800 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vmfset +++ b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_tst_serloop1_n4.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_tst_serloop1_n4.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2019-02-02 1108 2018.3 # 2019-02-02 1108 2017.2 # @@ -11,7 +12,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # +++# port driven by constant -------------------------------------- @@ -26,6 +30,7 @@ i [Synth 8-3917] O_LED[1\d] i [Synth 8-3295] HIO:LED[\d*] # unconnected ports -------------------------------------------- +{:2019.2} # --> unused SWI and BTN # OK 2016-06-05 i [Synth 8-3331] tst_serloop_hiomap.*SWI[\d] i [Synth 8-3331] tst_serloop_hiomap.*BTN[\d] @@ -34,6 +39,16 @@ i [Synth 8-3331] SER_MONI[abclkdiv.*][\d*] # --> other unused fields which aren't visualized # OK 2016-06-05 i [Synth 8-3331] SER_MONI[(rxact|txact|abdone|rxerr|rxovr)] i [Synth 8-3331] HIO_CNTL[enaftdi] +{2022.1:} +# --> unused SWI and BTN # OK 2022-05-26 +i [Synth 8-7129] SWI[\d] .* tst_serloop_hiomap +i [Synth 8-7129] BTN[\d] .* tst_serloop_hiomap +# --> clkdiv isn't displayed # OK 2022-05-26 +i [Synth 8-7129] SER_MONI[abclkdiv.*][\d*] +# --> other unused fields which aren't visualized # OK 2022-05-26 +i [Synth 8-7129] SER_MONI[(rxact|txact|abdone|rxerr|rxovr)] +i [Synth 8-7129] HIO_CNTL[enaftdi] +{:} # sequential element removed (2017.1 nonsense) ----------------- I [Synth 8-6014] _reg # generic diff --git a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vmfset b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vmfset index 706c1fe6..836016c1 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vmfset +++ b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_tst_serloop2_n4.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_tst_serloop2_n4.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2019-02-02 1108 2018.3 # 2019-02-02 1108 2017.2 # @@ -10,7 +11,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # false_path -hold ignored by synth ---------------------------- @@ -28,6 +32,7 @@ i [Synth 8-3917] O_LED[1\d] i [Synth 8-3295] HIO:LED[\d*] # unconnected ports -------------------------------------------- +{:2019.2} # --> unused SWI and BTN # OK 2016-06-05 i [Synth 8-3331] tst_serloop_hiomap.*SWI[\d] i [Synth 8-3331] tst_serloop_hiomap.*BTN[\d] @@ -36,6 +41,16 @@ i [Synth 8-3331] SER_MONI[abclkdiv.*][\d*] # --> other unused fields which aren't visualized # OK 2016-06-05 i [Synth 8-3331] SER_MONI[(rxact|txact|abdone|rxerr|rxovr)] i [Synth 8-3331] HIO_CNTL[enaftdi] +{2022.1:} +# --> unused SWI and BTN # OK 2022-05-26 +i [Synth 8-7129] SWI[\d] .* tst_serloop_hiomap +i [Synth 8-7129] BTN[\d] .* tst_serloop_hiomap +# --> clkdiv isn't displayed # OK 2022-05-26 +i [Synth 8-7129] SER_MONI[abclkdiv.*][\d*] +# --> other unused fields which aren't visualized # OK 2022-05-26 +i [Synth 8-7129] SER_MONI[(rxact|txact|abdone|rxerr|rxovr)] +i [Synth 8-7129] HIO_CNTL[enaftdi] +{:} # sequential element removed (2017.1 nonsense) ----------------- I [Synth 8-6014] _reg # generic diff --git a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop1_n4d.vmfset b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop1_n4d.vmfset new file mode 100644 index 00000000..76c194a5 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop1_n4d.vmfset @@ -0,0 +1,64 @@ +# $Id: sys_tst_serloop1_n4d.vmfset 1242 2022-05-27 17:08:43Z mueller $ +# +# Validated code/tool version combinations +# Date rev viv +# 2022-05-26 1242 2022.1 +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] + +# general issues ----------------------------------------------- +{2018.2:} +# stupid new warning, Xilinx suggests to safely ingnore +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] +{:} + +# +++# port driven by constant -------------------------------------- +# --> RGBLED0 unused # OK 2016-06-05 +i [Synth 8-3917] O_RGBLED0[\d] +# --> upper 8 LEDs unused +i [Synth 8-3917] O_LED[(8|9)] +i [Synth 8-3917] O_LED[1\d] + +# tying undriven pin to constant ------------------------------- +# upper 8 LEDs unused # OK 2016-06-05 +i [Synth 8-3295] HIO:LED[\d*] + +# unconnected ports -------------------------------------------- +{:2019.2} +# --> unused SWI and BTN # OK 2016-06-05 +i [Synth 8-3331] tst_serloop_hiomap.*SWI[\d] +i [Synth 8-3331] tst_serloop_hiomap.*BTN[\d] +# --> clkdiv isn't displayed # OK 2016-06-05 +i [Synth 8-3331] SER_MONI[abclkdiv.*][\d*] +# --> other unused fields which aren't visualized # OK 2016-06-05 +i [Synth 8-3331] SER_MONI[(rxact|txact|abdone|rxerr|rxovr)] +i [Synth 8-3331] HIO_CNTL[enaftdi] +{2022.1:} +# --> unused SWI and BTN # OK 2022-05-26 +i [Synth 8-7129] SWI[\d] .* tst_serloop_hiomap +i [Synth 8-7129] BTN[\d] .* tst_serloop_hiomap +# --> clkdiv isn't displayed # OK 2022-05-26 +i [Synth 8-7129] SER_MONI[abclkdiv.*][\d*] +# --> other unused fields which aren't visualized # OK 2022-05-26 +i [Synth 8-7129] SER_MONI[(rxact|txact|abdone|rxerr|rxovr)] +i [Synth 8-7129] HIO_CNTL[enaftdi] +{:} + +# sequential element removed (2017.1 nonsense) ----------------- +I [Synth 8-6014] _reg # generic + +# unused sequential element ------------------------------------ +{2017.2:2018.2} +# --> many HIO pins not used # OK 2016-06-05 +i [Synth 8-3332] HIO/IOB_(SWI|BTN)/R_DI_reg[\d*] +i [Synth 8-3332] HIO/DEB.DEB_(SWI|BTN)/R_REGS_reg[(dref|dout|dchange)][\d*] +{:} + +# +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization diff --git a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vmfset b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vmfset new file mode 100644 index 00000000..933044d8 --- /dev/null +++ b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vmfset @@ -0,0 +1,69 @@ +# $Id: sys_tst_serloop2_n4d.vmfset 1242 2022-05-27 17:08:43Z mueller $ +# +# Validated code/tool version combinations +# Date rev viv +# 2022-05-26 1242 2022.1 +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# general issues ----------------------------------------------- +{2018.2:} +# stupid new warning, Xilinx suggests to safely ingnore +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] +{:} + +# false_path -hold ignored by synth ---------------------------- +I [Designutils 20-1567] # generic + +# port driven by constant -------------------------------------- +# --> RGBLED0 unused # OK 2016-06-05 +i [Synth 8-3917] O_RGBLED0[\d] +# --> upper 8 LEDs unused +i [Synth 8-3917] O_LED[(8|9)] +i [Synth 8-3917] O_LED[1\d] + +# tying undriven pin to constant ------------------------------- +# upper 8 LEDs unused # OK 2016-06-05 +i [Synth 8-3295] HIO:LED[\d*] + +# unconnected ports -------------------------------------------- +{:2019.2} +# --> unused SWI and BTN # OK 2016-06-05 +i [Synth 8-3331] tst_serloop_hiomap.*SWI[\d] +i [Synth 8-3331] tst_serloop_hiomap.*BTN[\d] +# --> clkdiv isn't displayed # OK 2016-06-05 +i [Synth 8-3331] SER_MONI[abclkdiv.*][\d*] +# --> other unused fields which aren't visualized # OK 2016-06-05 +i [Synth 8-3331] SER_MONI[(rxact|txact|abdone|rxerr|rxovr)] +i [Synth 8-3331] HIO_CNTL[enaftdi] +{2022.1:} +# --> unused SWI and BTN # OK 2022-05-26 +i [Synth 8-7129] SWI[\d] .* tst_serloop_hiomap +i [Synth 8-7129] BTN[\d] .* tst_serloop_hiomap +# --> clkdiv isn't displayed # OK 2022-05-26 +i [Synth 8-7129] SER_MONI[abclkdiv.*][\d*] +# --> other unused fields which aren't visualized # OK 2022-05-26 +i [Synth 8-7129] SER_MONI[(rxact|txact|abdone|rxerr|rxovr)] +i [Synth 8-7129] HIO_CNTL[enaftdi] +{:} + +# sequential element removed (2017.1 nonsense) ----------------- +I [Synth 8-6014] _reg # generic + +# unused sequential element ------------------------------------ +{2017.2:2018.2} +I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic +# --> currently CDUWIDTH=8, but clock below 127 MHz # OK 2018-12-29 +i [Synth 8-3332] GEN_CLKALL/DIV_CLK0/R_REGS_reg[ucnt][7] +# --> many HIO pins not used # OK 2016-06-05 +i [Synth 8-3332] HIO/IOB_(SWI|BTN)/R_DI_reg[\d*] +i [Synth 8-3332] HIO/DEB.DEB_(SWI|BTN)/R_REGS_reg[(dref|dout|dchange)][\d*] +{:} + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization diff --git a/rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vmfset b/rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vmfset index 33e0df8b..ffaf47b5 100644 --- a/rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vmfset +++ b/rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_tst_snhumanio_b3.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_tst_snhumanio_b3.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2019-02-02 1108 2018.3 # 2019-02-02 1108 2017.2 # @@ -10,7 +11,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # sequential element removed (2017.1 nonsense) ----------------- diff --git a/rtl/sys_gen/tst_snhumanio/nexys4/sys_tst_snhumanio_n4.vmfset b/rtl/sys_gen/tst_snhumanio/nexys4/sys_tst_snhumanio_n4.vmfset index e0f18d98..56fa147e 100644 --- a/rtl/sys_gen/tst_snhumanio/nexys4/sys_tst_snhumanio_n4.vmfset +++ b/rtl/sys_gen/tst_snhumanio/nexys4/sys_tst_snhumanio_n4.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_tst_snhumanio_n4.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_tst_snhumanio_n4.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2019-02-02 1108 2018.3 # 2019-02-02 1108 2017.2 # @@ -10,7 +11,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # sequential element removed (2017.1 nonsense) ----------------- diff --git a/rtl/sys_gen/tst_snhumanio/nexys4d/sys_tst_snhumanio_n4d.vmfset b/rtl/sys_gen/tst_snhumanio/nexys4d/sys_tst_snhumanio_n4d.vmfset new file mode 100644 index 00000000..bca8025b --- /dev/null +++ b/rtl/sys_gen/tst_snhumanio/nexys4d/sys_tst_snhumanio_n4d.vmfset @@ -0,0 +1,32 @@ +# $Id: sys_tst_snhumanio_n4d.vmfset 1242 2022-05-27 17:08:43Z mueller $ +# +# Validated code/tool version combinations +# Date rev viv +# 2022-05-26 1242 2022.1 +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# general issues ----------------------------------------------- +{2018.2:} +# stupid new warning, Xilinx suggests to safely ingnore +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] +{:} + +# sequential element removed (2017.1 nonsense) ----------------- +I [Synth 8-6014] _reg # generic + +# port driven by constant -------------------------------------- +# --> RGBLED0 and upper 4 DSP digits unused # OK 2016-06-05 +i [Synth 8-3917] O_RGBLED0[\d] +i [Synth 8-3917] O_ANO_N[4] +i [Synth 8-3917] O_ANO_N[5] +i [Synth 8-3917] O_ANO_N[6] +i [Synth 8-3917] O_ANO_N[7] + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization diff --git a/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vmfset b/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vmfset index 97fd0f75..9118668d 100644 --- a/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vmfset +++ b/rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_tst_sram_arty.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_tst_sram_arty.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2022-04-23 1225 2020.1 # 2019-02-02 1108 2018.3 # 2019-02-02 1108 2017.2 @@ -11,7 +12,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # false_path -hold ignored by synth ---------------------------- @@ -40,6 +44,19 @@ i [Synth 8-3331] tst_sram.*MEM_ACK_W i [Synth 8-3331] rlink_sp2c.*CE_(USEC|MSEC) # --> data end marker not used # OK 2018-12-20 i [Synth 8-3331] sramif2migui_core .*APP_RD_DATA_END +# ------------------ +{2022.1:} +I [Synth 8-7129] RB_MREQ # generic +# --> I_SWI not used # OK 2022-05-26 +i [Synth 8-7129] I_SWI[\d] +# --> O_LED only partially used # OK 2022-05-26 +i [Synth 8-7129] O_LED[(2|3)] +# --> MEM_ACK_W not used by current tst_sram # OK 2022-05-26 +i [Synth 8-7129] MEM_ACK_W .* tst_sram +# --> rlink_sp2c doesn't use CE_USEC and CE_MSEC # OK 2022-05-26 +i [Synth 8-7129] CE_(USEC|MSEC) .* rlink_sp2c +# --> data end marker not used # OK 2022-05-26 +i [Synth 8-7129] APP_RD_DATA_END .* sramif2migui_core {:} # sequential element removed (2017.1 nonsense) ----------------- diff --git a/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vmfset b/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vmfset index 314314a4..43116ab1 100644 --- a/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vmfset +++ b/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_tst_sram_c7.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_tst_sram_c7.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2022-04-23 1225 2020.1 # 2019-02-02 1108 2018.3 # 2019-02-02 1108 2017.2 @@ -11,7 +12,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # false_path -hold ignored by synth ---------------------------- @@ -39,6 +43,15 @@ i [Synth 8-3331] I_BTN[\d] i [Synth 8-3331] tst_sram.*MEM_ACK_W # --> rlink_sp2c doesn't use CE_USEC and CE_MSEC # OK 2017-06-11 i [Synth 8-3331] rlink_sp2c.*CE_(USEC|MSEC) +# ------------------ +{2022.1:} +I [Synth 8-7129] RB_MREQ # generic +# --> I_BTN not used # OK 2022-05-26 +i [Synth 8-7129] I_BTN[\d] .* sys_tst_sram_c7 +# --> MEM_ACK_W not used by current tst_sram # OK 2022-05-26 +i [Synth 8-7129] MEM_ACK_W .* tst_sram +# --> rlink_sp2c doesn't use CE_USEC and CE_MSEC # OK 2022-05-26 +i [Synth 8-7129] CE_(USEC|MSEC) .* rlink_sp2c {:} # sequential element removed (2017.1 nonsense) ----------------- diff --git a/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vmfset b/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vmfset index 7b3320aa..ba960cef 100644 --- a/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vmfset +++ b/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_tst_sram_n4.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_tst_sram_n4.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2019-02-02 1108 2018.3 # 2019-02-02 1108 2017.2 # @@ -10,7 +11,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # false_path -hold ignored by synth ---------------------------- @@ -26,6 +30,7 @@ i [Synth 8-3295] HIO:LED[\d*] i [Synth 8-3295] RLINK:RB_LAM[\d*] # unconnected ports -------------------------------------------- +{:2019.2} I [Synth 8-3331] RB_MREQ # generic # --> I_MEM_WAIT not used by current nx_cram_memctl_as # OK 2016-06-05 i [Synth 8-3331] nx_cram_memctl_as.*I_MEM_WAIT @@ -33,6 +38,16 @@ i [Synth 8-3331] nx_cram_memctl_as.*I_MEM_WAIT i [Synth 8-3331] tst_sram.*MEM_ACK_W # --> rlink_sp2c doesn't use CE_USEC and CE_MSEC # OK 2016-06-05 i [Synth 8-3331] rlink_sp2c.*CE_(USEC|MSEC) +# ------------------ +{2022.1:} +I [Synth 8-7129] RB_MREQ # generic +# --> I_MEM_WAIT not used by current nx_cram_memctl_as # OK 2022-05-26 +i [Synth 8-7129] I_MEM_WAIT .* nx_cram_memctl_as +# --> MEM_ACK_W not used by current tst_sram # OK 2022-05-26 +i [Synth 8-7129] MEM_ACK_W .* tst_sram +# --> rlink_sp2c doesn't use CE_USEC and CE_MSEC # OK 2022-05-26 +i [Synth 8-7129] CE_(USEC|MSEC) .* rlink_sp2c +{:} # sequential element removed (2017.1 nonsense) ----------------- I [Synth 8-6014] _reg # generic diff --git a/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vmfset b/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vmfset index a93d6258..e99090ee 100644 --- a/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vmfset +++ b/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_tst_sram_n4d.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_tst_sram_n4d.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2022-04-23 1225 2020.1 # 2019-02-02 1108 2018.3 # 2019-02-02 1108 2017.2 @@ -11,7 +12,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # false_path -hold ignored by synth ---------------------------- @@ -39,6 +43,15 @@ i [Synth 8-3331] tst_sram.*MEM_ACK_W i [Synth 8-3331] rlink_sp2c.*CE_(USEC|MSEC) # --> data end marker not used # OK 2019-01-02 i [Synth 8-3331] sramif2migui_core .*APP_RD_DATA_END +# ------------------ +{2022.1:} +I [Synth 8-7129] RB_MREQ # generic +# --> MEM_ACK_W not used by current tst_sram # OK 2022-05-26 +i [Synth 8-7129] MEM_ACK_W .* tst_sram +# --> rlink_sp2c doesn't use CE_USEC and CE_MSEC # OK 2022-05-26 +i [Synth 8-7129] CE_(USEC|MSEC) .* rlink_sp2c +# --> data end marker not used # OK 2019-01-02 +i [Synth 8-7129] APP_RD_DATA_END .* sramif2migui_core {:} # sequential element removed (2017.1 nonsense) ----------------- diff --git a/rtl/sys_gen/w11a/arty/sys_w11a_arty.vmfset b/rtl/sys_gen/w11a/arty/sys_w11a_arty.vmfset index 7043ff0e..ee25a43c 100644 --- a/rtl/sys_gen/w11a/arty/sys_w11a_arty.vmfset +++ b/rtl/sys_gen/w11a/arty/sys_w11a_arty.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_w11a_arty.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_w11a_arty.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2022-04-23 1225 2020.1 # 2019-06-05 1159 2019.1 # 2019-02-02 1108 2018.3 @@ -12,7 +13,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # binding instance .. which has no pins ------------------------ @@ -38,7 +42,7 @@ I [Synth 8-3331] SER_MONI # generic i [Synth 8-3331] pdp11_sequencer .* IREG[1(1|2|3|4)] # --> ccin indedd not fully used # OK 2018-12-28 i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)] -# --> some psr bits are used # OK 2018-12-28 +# --> some psr bits are unused # OK 2018-12-28 i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)] # --> not all moni fields used # OK 2018-12-28 i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)] @@ -54,6 +58,37 @@ i [Synth 8-3331] ibdr_deuna .* EI_ACK i [Synth 8-3331] ibd_iist .* EI_ACK # --> data end marker not used # OK 2019-01-02 i [Synth 8-3331] sramif2migui_core .*APP_RD_DATA_END +# ------------------ +{2022.1:} +I [Synth 8-7129] IB_MREQ # generic +I [Synth 8-7129] RB_MREQ # generic +I [Synth 8-7129] DM_STAT_CO # generic +I [Synth 8-7129] DM_STAT_DP # generic +I [Synth 8-7129] DM_STAT_EXP # generic +I [Synth 8-7129] DM_STAT_SE # generic +I [Synth 8-7129] DM_STAT_VM # generic +I [Synth 8-7129] CP_STAT # generic +I [Synth 8-7129] SER_MONI # generic +# --> ireg indeed not fully used # OK 2022-05-26 +i [Synth 8-7129] IREG[1(1|2|3|4)] .* pdp11_sequencer +# --> ccin indedd not fully used # OK 2022-05-26 +i [Synth 8-7129] CCIN[(1|2)] .* pdp11_lunit +# --> some psr bits are unused # OK 2022-05-26 +i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr +# --> not all moni fields used # OK 2022-05-26 +i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12 +# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26 +i [Synth 8-7129] CNTL[trap_done] .* pdp11_mmu +i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu +# --> so far no usage of usec and msec pulse # OK 2022-05-26 +i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c +# --> msec indeed not used # OK 2022-05-26 +i [Synth 8-7129] CE_MSEC .* ibdr_rl11 +# --> ei_ack not used, interrupt request cleared via register # OK 2022-05-26 +i [Synth 8-7129] EI_ACK .* ibdr_deuna +i [Synth 8-7129] EI_ACK .* ibd_iist +# --> data end marker not used # OK 2019-01-02 +i [Synth 8-7129] APP_RD_DATA_END .* sramif2migui_core {:} # sequential element removed (2017.1 nonsense) ----------------- diff --git a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vmfset b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vmfset index 310052ef..6eb53de9 100644 --- a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vmfset +++ b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_w11a_br_arty.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_w11a_br_arty.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2019-06-05 1159 2019.1 # 2019-02-02 1108 2018.3 # 2019-02-02 1108 2017.2 @@ -11,7 +12,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # binding instance .. which has no pins ------------------------ @@ -23,6 +27,7 @@ I [Designutils 20-1567] # generic # net without driver ------------------------------------------- # unconnected ports -------------------------------------------- +{:2019.2} I [Synth 8-3331] IB_MREQ # generic I [Synth 8-3331] RB_MREQ # generic I [Synth 8-3331] DM_STAT_CO # generic @@ -36,7 +41,7 @@ I [Synth 8-3331] SER_MONI # generic i [Synth 8-3331] pdp11_sequencer .* IREG[1(1|2|3|4)] # --> ccin indedd not fully used # OK 2018-11-18 i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)] -# --> some psr bits are used # OK 2018-11-18 +# --> some psr bits are unused # OK 2018-11-18 i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)] # --> not all moni fields used # OK 2018-11-18 i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)] @@ -52,6 +57,38 @@ i [Synth 8-3331] ibdr_rl11 .* CE_MSEC # --> ei_ack not used, interrupt request cleared via register # OK 2018-11-23 i [Synth 8-3331] ibdr_deuna .* EI_ACK i [Synth 8-3331] ibd_iist .* EI_ACK +# ------------------ +{2022.1:} +I [Synth 8-7129] IB_MREQ # generic +I [Synth 8-7129] RB_MREQ # generic +I [Synth 8-7129] DM_STAT_CO # generic +I [Synth 8-7129] DM_STAT_DP # generic +I [Synth 8-7129] DM_STAT_EXP # generic +I [Synth 8-7129] DM_STAT_SE # generic +I [Synth 8-7129] DM_STAT_VM # generic +I [Synth 8-7129] CP_STAT # generic +I [Synth 8-7129] SER_MONI # generic +# --> ireg indeed not fully used # OK 2022-05-26 +i [Synth 8-7129] IREG[1(1|2|3|4)] .* pdp11_sequencer +# --> ccin indedd not fully used # OK 2022-05-26 +i [Synth 8-7129] CCIN[(1|2)] .* pdp11_lunit +# --> some psr bits are unused # OK 2022-05-26 +i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr +# --> not all moni fields used # OK 2022-05-26 +i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12 +# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26 +i [Synth 8-7129] CNTL[trap_done] .* pdp11_mmu +i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu +# --> so far no usage of usec and msec pulse # OK 2022-05-26 +i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c +# --> only small memory available # OK 2022-05-26 +i [Synth 8-7129] ADDR[1(6|7|8|9)] .* pdp11_bram_memctl +# --> msec indeed not used # OK 2022-05-26 +i [Synth 8-7129] CE_MSEC .* ibdr_rl11 +# --> ei_ack not used, interrupt request cleared via register # OK 2022-05-26 +i [Synth 8-7129] EI_ACK .* ibdr_deuna +i [Synth 8-7129] EI_ACK .* ibd_iist +{:} # sequential element removed (2017.1 nonsense) ----------------- I [Synth 8-6014] _reg # generic diff --git a/rtl/sys_gen/w11a/artys7/sys_w11a_as7.vmfset b/rtl/sys_gen/w11a/artys7/sys_w11a_as7.vmfset index 07e2166b..f08e497b 100644 --- a/rtl/sys_gen/w11a/artys7/sys_w11a_as7.vmfset +++ b/rtl/sys_gen/w11a/artys7/sys_w11a_as7.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_w11a_as7.vmfset 1159 2019-06-06 19:15:50Z mueller $ +# $Id: sys_w11a_as7.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2019-02-02 1108 2018.3 # # ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ @@ -9,7 +10,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # binding instance .. which has no pins ------------------------ @@ -21,6 +25,7 @@ I [Designutils 20-1567] # generic # net without driver ------------------------------------------- # unconnected ports -------------------------------------------- +{:2019.2} I [Synth 8-3331] IB_MREQ # generic I [Synth 8-3331] RB_MREQ # generic I [Synth 8-3331] DM_STAT_CO # generic @@ -34,7 +39,7 @@ I [Synth 8-3331] SER_MONI # generic i [Synth 8-3331] pdp11_sequencer .* IREG[1(1|2|3|4)] # --> ccin indedd not fully used # OK 2019-01-12 i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)] -# --> some psr bits are used # OK 2019-01-12 +# --> some psr bits are unused # OK 2019-01-12 i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)] # --> not all moni fields used # OK 2019-01-12 i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)] @@ -52,6 +57,40 @@ i [Synth 8-3331] ibdr_deuna .* EI_ACK i [Synth 8-3331] ibd_iist .* EI_ACK # --> data end marker not used # OK 2019-01-12 i [Synth 8-3331] sramif2migui_core .*APP_RD_DATA_END +# ------------------ +{2022.1:} +I [Synth 8-7129] IB_MREQ # generic +I [Synth 8-7129] RB_MREQ # generic +I [Synth 8-7129] DM_STAT_CO # generic +I [Synth 8-7129] DM_STAT_DP # generic +I [Synth 8-7129] DM_STAT_EXP # generic +I [Synth 8-7129] DM_STAT_SE # generic +I [Synth 8-7129] DM_STAT_VM # generic +I [Synth 8-7129] CP_STAT # generic +I [Synth 8-7129] SER_MONI # generic +# --> ireg indeed not fully used # OK 2022-05-26 +i [Synth 8-7129] IREG[1(1|2|3|4)] .* pdp11_sequencer +# --> ccin indedd not fully used # OK 2022-05-26 +i [Synth 8-7129] CCIN[(1|2)] .* pdp11_lunit +# --> some psr bits are unused # OK 2022-05-26 +i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr +# --> not all moni fields used # OK 2022-05-26 +i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12 +# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26 +i [Synth 8-7129] CNTL[trap_done] .* pdp11_mmu +i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu +# --> pdp11_hio70_arty doesn't use MEM_ACT # OK 2022-05-26 +i [Synth 8-7129] MEM_ACT_(R|W) .* pdp11_hio70_artys7 +# --> so far no usage of usec and msec pulse # OK 2022-05-26 +i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c +# --> msec indeed not used # OK 2022-05-26 +i [Synth 8-7129] CE_MSEC .* ibdr_rl11 +# --> ei_ack not used, interrupt request cleared via register # OK 2022-05-26 +i [Synth 8-7129] EI_ACK .* ibdr_deuna +i [Synth 8-7129] EI_ACK .* ibd_iist +# --> data end marker not used # OK 2019-01-02 +i [Synth 8-7129] APP_RD_DATA_END .* sramif2migui_core +{:} # sequential element removed (2017.1 nonsense) ----------------- I [Synth 8-6014] _reg # generic diff --git a/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vmfset b/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vmfset index ad90c115..d4dbf7f8 100644 --- a/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vmfset +++ b/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_w11a_br_as7.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_w11a_br_as7.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2019-06-05 1159 2019.1 # 2019-02-02 1108 2018.3 # 2019-02-02 1108 2017.2 @@ -11,7 +12,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # binding instance .. which has no pins ------------------------ @@ -23,6 +27,7 @@ I [Designutils 20-1567] # generic # net without driver ------------------------------------------- # unconnected ports -------------------------------------------- +{:2019.2} I [Synth 8-3331] IB_MREQ # generic I [Synth 8-3331] RB_MREQ # generic I [Synth 8-3331] DM_STAT_CO # generic @@ -36,7 +41,7 @@ I [Synth 8-3331] SER_MONI # generic i [Synth 8-3331] pdp11_sequencer .* IREG[1(1|2|3|4)] # --> ccin indedd not fully used # OK 2018-11-18 i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)] -# --> some psr bits are used # OK 2018-11-18 +# --> some psr bits are unused # OK 2018-11-18 i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)] # --> not all moni fields used # OK 2018-11-18 i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)] @@ -54,6 +59,40 @@ i [Synth 8-3331] ibdr_deuna .* EI_ACK i [Synth 8-3331] ibd_iist .* EI_ACK # --> rl11 doesn't use MSEC # OK 2019-02-02 i [Synth 8-3331] ibdr_rl11 .* CE_MSEC +# ------------------ +{2022.1:} +I [Synth 8-7129] IB_MREQ # generic +I [Synth 8-7129] RB_MREQ # generic +I [Synth 8-7129] DM_STAT_CO # generic +I [Synth 8-7129] DM_STAT_DP # generic +I [Synth 8-7129] DM_STAT_EXP # generic +I [Synth 8-7129] DM_STAT_SE # generic +I [Synth 8-7129] DM_STAT_VM # generic +I [Synth 8-7129] CP_STAT # generic +I [Synth 8-7129] SER_MONI # generic +# --> ireg indeed not fully used # OK 2022-05-26 +i [Synth 8-7129] IREG[1(1|2|3|4)] .* pdp11_sequencer +# --> ccin indedd not fully used # OK 2022-05-26 +i [Synth 8-7129] CCIN[(1|2)] .* pdp11_lunit +# --> some psr bits are unused # OK 2022-05-26 +i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr +# --> not all moni fields used # OK 2022-05-26 +i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12 +# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26 +i [Synth 8-7129] CNTL[trap_done] .* pdp11_mmu +i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu +# --> so far no usage of usec and msec pulse # OK 2022-05-26 +i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c +# --> pdp11_hio70_arty doesn't use MEM_ACT # OK 2022-05-26 +i [Synth 8-7129] MEM_ACT_(R|W) .* pdp11_hio70_artys7 +# --> only small memory available # OK 2022-05-26 +i [Synth 8-7129] ADDR[1(6|7|8|9)] .* pdp11_bram_memctl +# --> ei_ack not used, interrupt request cleared via register # OK 2022-05-26 +i [Synth 8-7129] EI_ACK .* ibdr_deuna +i [Synth 8-7129] EI_ACK .* ibd_iist +# --> msec indeed not used # OK 2022-05-26 +i [Synth 8-7129] CE_MSEC .* ibdr_rl11 +{:} # sequential element removed (2017.1 nonsense) ----------------- I [Synth 8-6014] _reg # generic diff --git a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset index 93c1e7a6..5dffef70 100644 --- a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset +++ b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_w11a_b3.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_w11a_b3.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2022-04-23 1225 2020.1 # 2019-06-05 1159 2019.1 # 2019-02-02 1108 2018.3 @@ -12,7 +13,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # binding instance .. which has no pins ------------------------ @@ -38,7 +42,7 @@ I [Synth 8-3331] SER_MONI # generic i [Synth 8-3331] pdp11_sequencer .* IREG[1(1|2|3|4)] # --> ccin indedd not fully used # OK 2018-11-18 i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)] -# --> some psr bits are used # OK 2018-11-18 +# --> some psr bits are unused # OK 2018-11-18 i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)] # --> not all moni fields used # OK 2018-11-18 i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)] @@ -54,6 +58,37 @@ i [Synth 8-3331] ibdr_rl11 .* CE_MSEC # --> ei_ack not used, interrupt request cleared via register # OK 2018-11-23 i [Synth 8-3331] ibdr_deuna .* EI_ACK i [Synth 8-3331] ibd_iist .* EI_ACK +# ------------------ +{2022.1:} +I [Synth 8-7129] IB_MREQ # generic +I [Synth 8-7129] RB_MREQ # generic +I [Synth 8-7129] DM_STAT_CO # generic +I [Synth 8-7129] DM_STAT_DP # generic +I [Synth 8-7129] DM_STAT_EXP # generic +I [Synth 8-7129] DM_STAT_SE # generic +I [Synth 8-7129] DM_STAT_VM # generic +I [Synth 8-7129] CP_STAT # generic +I [Synth 8-7129] SER_MONI # generic +# --> ireg indeed not fully used # OK 2022-05-26 +i [Synth 8-7129] IREG[1(1|2|3|4)] .* pdp11_sequencer +# --> ccin indedd not fully used # OK 2022-05-26 +i [Synth 8-7129] CCIN[(1|2)] .* pdp11_lunit +# --> some psr bits are unused # OK 2022-05-26 +i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr +# --> not all moni fields used # OK 2022-05-26 +i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12 +# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26 +i [Synth 8-7129] CNTL[trap_done] .* pdp11_mmu +i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu +# --> so far no usage of usec and msec pulse # OK 2022-05-26 +i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c +# --> small memory, not all addr lines connected # OK 2022-05-26 +i [Synth 8-7129] ADDR[1(6|7|8|9)] .* pdp11_bram_memctl +# --> msec indeed not used # OK 2022-05-26 +i [Synth 8-7129] CE_MSEC .* ibdr_rl11 +# --> ei_ack not used, interrupt request cleared via register # OK 2022-05-26 +i [Synth 8-7129] EI_ACK .* ibdr_deuna +i [Synth 8-7129] EI_ACK .* ibd_iist {:} # sequential element removed (2017.1 nonsense) ----------------- diff --git a/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vmfset b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vmfset index d4858a4e..05a5b48d 100644 --- a/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vmfset +++ b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_w11a_c7.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_w11a_c7.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2022-04-23 1225 2020.1 # 2019-06-05 1159 2019.1 # 2019-02-02 1108 2018.3 @@ -12,7 +13,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # binding instance .. which has no pins ------------------------ @@ -46,7 +50,7 @@ i [Synth 8-3331] I_BTN[\d] i [Synth 8-3331] pdp11_sequencer .* IREG[1(1|2|3|4)] # --> ccin indedd not fully used # OK 2018-11-18 i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)] -# --> some psr bits are used # OK 2018-11-18 +# --> some psr bits are unused # OK 2018-11-18 i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)] # --> not all moni fields used # OK 2018-11-18 i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)] @@ -62,6 +66,39 @@ i [Synth 8-3331] ibdr_rl11 .* CE_MSEC # --> ei_ack not used, interrupt request cleared via register # OK 2018-11-23 i [Synth 8-3331] ibdr_deuna .* EI_ACK i [Synth 8-3331] ibd_iist .* EI_ACK +# ------------------ +{2022.1:} +I [Synth 8-7129] IB_MREQ # generic +I [Synth 8-7129] RB_MREQ # generic +I [Synth 8-7129] DM_STAT_CO # generic +I [Synth 8-7129] DM_STAT_DP # generic +I [Synth 8-7129] DM_STAT_EXP # generic +I [Synth 8-7129] DM_STAT_SE # generic +I [Synth 8-7129] DM_STAT_VM # generic +I [Synth 8-7129] CP_STAT # generic +I [Synth 8-7129] SER_MONI # generic +# --> I_BTN not used # OK 2022-05-26 +i [Synth 8-7129] I_BTN[\d] +# --> ireg indeed not fully used # OK 2022-05-26 +i [Synth 8-7129] IREG[1(1|2|3|4)] .* pdp11_sequencer +# --> ccin indedd not fully used # OK 2022-05-26 +i [Synth 8-7129] CCIN[(1|2)] .* pdp11_lunit +# --> some psr bits are unused # OK 2022-05-26 +i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr +# --> not all moni fields used # OK 2022-05-26 +i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12 +# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26 +i [Synth 8-7129] CNTL[trap_done] .* pdp11_mmu +i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu +# --> so far no usage of usec and msec pulse # OK 2022-05-26 +i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c +# --> small memory, not all addr lines connected # OK 2022-05-26 +i [Synth 8-7129] ADDR[1(6|7|8|9)] .* pdp11_bram_memctl +# --> msec indeed not used # OK 2022-05-26 +i [Synth 8-7129] CE_MSEC .* ibdr_rl11 +# --> ei_ack not used, interrupt request cleared via register # OK 2022-05-26 +i [Synth 8-7129] EI_ACK .* ibdr_deuna +i [Synth 8-7129] EI_ACK .* ibd_iist {:} # sequential element removed (2017.1 nonsense) ----------------- diff --git a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vmfset b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vmfset index 8abe5b9f..97b6ae50 100644 --- a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vmfset +++ b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_w11a_n4.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_w11a_n4.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2019-06-05 1159 2019.1 # 2019-02-02 1108 2018.3 # 2019-02-02 1108 2017.2 @@ -11,7 +12,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # binding instance .. which has no pins ------------------------ @@ -25,6 +29,7 @@ I [Designutils 20-1567] i [Synth 8-3917] O_RGBLED0[\d] # unconnected ports -------------------------------------------- +{:2019.2} I [Synth 8-3331] IB_MREQ # generic I [Synth 8-3331] RB_MREQ # generic I [Synth 8-3331] DM_STAT_CO # generic @@ -38,7 +43,7 @@ I [Synth 8-3331] SER_MONI # generic i [Synth 8-3331] pdp11_sequencer .* IREG[1(1|2|3|4)] # --> ccin indedd not fully used # OK 2018-11-18 i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)] -# --> some psr bits are used # OK 2018-11-18 +# --> some psr bits are unused # OK 2018-11-18 i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)] # --> not all moni fields used # OK 2018-11-18 i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)] @@ -54,6 +59,37 @@ i [Synth 8-3331] ibdr_deuna .* EI_ACK i [Synth 8-3331] ibd_iist .* EI_ACK # --> i_mem_wait not used in as driver # OK 2018-11-23 i [Synth 8-3331] nx_cram_memctl_as .* I_MEM_WAIT +{2022.1:} +I [Synth 8-7129] IB_MREQ # generic +I [Synth 8-7129] RB_MREQ # generic +I [Synth 8-7129] DM_STAT_CO # generic +I [Synth 8-7129] DM_STAT_DP # generic +I [Synth 8-7129] DM_STAT_EXP # generic +I [Synth 8-7129] DM_STAT_SE # generic +I [Synth 8-7129] DM_STAT_VM # generic +I [Synth 8-7129] CP_STAT # generic +I [Synth 8-7129] SER_MONI # generic +# --> ireg indeed not fully used # OK 2022-05-26 +i [Synth 8-7129] IREG[1(1|2|3|4)] .* pdp11_sequencer +# --> ccin indedd not fully used # OK 2022-05-26 +i [Synth 8-7129] CCIN[(1|2)] .* pdp11_lunit +# --> some psr bits are unused # OK 2022-05-26 +i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr +# --> not all moni fields used # OK 2022-05-26 +i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12 +# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26 +i [Synth 8-7129] CNTL[trap_done] .* pdp11_mmu +i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu +# --> so far no usage of usec and msec pulse # OK 2022-05-26 +i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c +# --> msec indeed not used # OK 2022-05-26 +i [Synth 8-7129] CE_MSEC .* ibdr_rl11 +# --> ei_ack not used, interrupt request cleared via register # OK 2022-05-26 +i [Synth 8-7129] EI_ACK .* ibdr_deuna +i [Synth 8-7129] EI_ACK .* ibd_iist +# --> i_mem_wait not used in as driver # OK 2022-05-26 +i [Synth 8-7129] I_MEM_WAIT .* nx_cram_memctl_as +{:} # sequential element removed (2017.1 nonsense) ----------------- I [Synth 8-6014] _reg # generic diff --git a/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vmfset b/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vmfset index 43402655..61b36af0 100644 --- a/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vmfset +++ b/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_w11a_n4d.vmfset 1226 2022-04-23 11:19:32Z mueller $ +# $Id: sys_w11a_n4d.vmfset 1242 2022-05-27 17:08:43Z mueller $ # # Validated code/tool version combinations # Date rev viv +# 2022-05-26 1242 2022.1 # 2022-04-23 1225 2020.1 # 2019-06-05 1159 2019.1 # 2019-02-02 1108 2018.3 @@ -12,7 +13,10 @@ # general issues ----------------------------------------------- {2018.2:} # stupid new warning, Xilinx suggests to safely ingnore -i [Constraints 18-5210] # generic +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] {:} # binding instance .. which has no pins ------------------------ @@ -40,7 +44,7 @@ I [Synth 8-3331] SER_MONI # generic i [Synth 8-3331] pdp11_sequencer .* IREG[1(1|2|3|4)] # --> ccin indedd not fully used # OK 2019-01-02 i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)] -# --> some psr bits are used # OK 2019-01-02 +# --> some psr bits are unused # OK 2019-01-02 i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)] # --> not all moni fields used # OK 2019-01-02 i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)] @@ -56,6 +60,37 @@ i [Synth 8-3331] ibdr_deuna .* EI_ACK i [Synth 8-3331] ibd_iist .* EI_ACK # --> data end marker not used # OK 2019-01-02 i [Synth 8-3331] sramif2migui_core .*APP_RD_DATA_END +# ------------------ +{2022.1:} +I [Synth 8-7129] IB_MREQ # generic +I [Synth 8-7129] RB_MREQ # generic +I [Synth 8-7129] DM_STAT_CO # generic +I [Synth 8-7129] DM_STAT_DP # generic +I [Synth 8-7129] DM_STAT_EXP # generic +I [Synth 8-7129] DM_STAT_SE # generic +I [Synth 8-7129] DM_STAT_VM # generic +I [Synth 8-7129] CP_STAT # generic +I [Synth 8-7129] SER_MONI # generic +# --> ireg indeed not fully used # OK 2022-05-26 +i [Synth 8-7129] IREG[1(1|2|3|4)] .* pdp11_sequencer +# --> ccin indedd not fully used # OK 2022-05-26 +i [Synth 8-7129] CCIN[(1|2)] .* pdp11_lunit +# --> some psr bits are unused # OK 2022-05-26 +i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr +# --> not all moni fields used # OK 2022-05-26 +i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12 +# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26 +i [Synth 8-7129] CNTL[trap_done] .* pdp11_mmu +i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu +# --> so far no usage of usec and msec pulse # OK 2022-05-26 +i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c +# --> msec indeed not used # OK 2022-05-26 +i [Synth 8-7129] CE_MSEC .* ibdr_rl11 +# --> ei_ack not used, interrupt request cleared via register # OK 2022-05-26 +i [Synth 8-7129] EI_ACK .* ibdr_deuna +i [Synth 8-7129] EI_ACK .* ibd_iist +# --> data end marker not used # OK 2019-01-02 +i [Synth 8-7129] APP_RD_DATA_END .* sramif2migui_core {:} # sequential element removed (2017.1 nonsense) ----------------- diff --git a/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vmfset b/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vmfset new file mode 100644 index 00000000..4c838c51 --- /dev/null +++ b/rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vmfset @@ -0,0 +1,159 @@ +# $Id: sys_w11a_br_n4d.vmfset 1242 2022-05-27 17:08:43Z mueller $ +# +# Validated code/tool version combinations +# Date rev viv +# 2022-05-26 1242 2022.1 +# +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[syn] +# general issues ----------------------------------------------- +{2018.2:} +# stupid new warning, Xilinx suggests to safely ingnore +I [Constraints 18-5210] # generic +{2022.1:} +# new warning on 'Parallel synthesis criteria is not met', safe tp ignore +I [Synth 8-7080] +{:} + +# binding instance .. which has no pins ------------------------ +I [Synth 8-115] # generic + +# false_path -hold ignored by synth ---------------------------- +I [Designutils 20-1567] # generic + +# net without driver ------------------------------------------- + +# unconnected ports -------------------------------------------- +{:2019.2} +I [Synth 8-3331] IB_MREQ # generic +I [Synth 8-3331] RB_MREQ # generic +I [Synth 8-3331] DM_STAT_CO # generic +I [Synth 8-3331] DM_STAT_DP # generic +I [Synth 8-3331] DM_STAT_EXP # generic +I [Synth 8-3331] DM_STAT_SE # generic +I [Synth 8-3331] DM_STAT_VM # generic +I [Synth 8-3331] CP_STAT # generic +I [Synth 8-3331] SER_MONI # generic +# --> ireg indeed not fully used # OK 2018-11-18 +i [Synth 8-3331] pdp11_sequencer .* IREG[1(1|2|3|4)] +# --> ccin indedd not fully used # OK 2018-11-18 +i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)] +# --> some psr bits are unused # OK 2018-11-18 +i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)] +# --> not all moni fields used # OK 2018-11-18 +i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)] +# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2018-11-18 +i [Synth 8-3331] pdp11_mmu .* CNTL[trap_done] +i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)] +# --> so far no usage of usec and msec pulse # OK 2018-11-18 +i [Synth 8-3331] rlink_sp2c .* (CE_USEC|CE_MSEC) +# --> only small memory available # OK 2018-11-23 +i [Synth 8-3331] pdp11_bram_memctl .* ADDR[1(6|7|8|9)] +# --> msec indeed not used # OK 2018-11-23 +i [Synth 8-3331] ibdr_rl11 .* CE_MSEC +# --> ei_ack not used, interrupt request cleared via register # OK 2018-11-23 +i [Synth 8-3331] ibdr_deuna .* EI_ACK +i [Synth 8-3331] ibd_iist .* EI_ACK +# ------------------ +{2022.1:} +I [Synth 8-7129] IB_MREQ # generic +I [Synth 8-7129] RB_MREQ # generic +I [Synth 8-7129] DM_STAT_CO # generic +I [Synth 8-7129] DM_STAT_DP # generic +I [Synth 8-7129] DM_STAT_EXP # generic +I [Synth 8-7129] DM_STAT_SE # generic +I [Synth 8-7129] DM_STAT_VM # generic +I [Synth 8-7129] CP_STAT # generic +I [Synth 8-7129] SER_MONI # generic +# --> ireg indeed not fully used # OK 2022-05-26 +i [Synth 8-7129] IREG[1(1|2|3|4)] .* pdp11_sequencer +# --> ccin indedd not fully used # OK 2022-05-26 +i [Synth 8-7129] CCIN[(1|2)] .* pdp11_lunit +# --> some psr bits are unused # OK 2022-05-26 +i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr +# --> not all moni fields used # OK 2022-05-26 +i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12 +# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26 +i [Synth 8-7129] CNTL[trap_done] .* pdp11_mmu +i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu +# --> so far no usage of usec and msec pulse # OK 2022-05-26 +i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c +# --> only small memory available # OK 2022-05-26 +i [Synth 8-7129] ADDR[1(6|7|8|9)] .* pdp11_bram_memctl +# --> msec indeed not used # OK 2022-05-26 +i [Synth 8-7129] CE_MSEC .* ibdr_rl11 +# --> ei_ack not used, interrupt request cleared via register # OK 2022-05-26 +i [Synth 8-7129] EI_ACK .* ibdr_deuna +i [Synth 8-7129] EI_ACK .* ibd_iist +{:} + +# sequential element removed (2017.1 nonsense) ----------------- +I [Synth 8-6014] _reg # generic + +# unused sequential element ------------------------------------ +{2017.2:2018.2} +I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic + +# --> many HIO pins not used # OK 2018-10-13 +I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*] +i [Synth 8-3332] IOB_BTN/R_DI_reg[\d*] +i [Synth 8-3332] DEB.DEB_BTN/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*] +# --> usec not used for serport clock domain # OK 2018-10-13 +i [Synth 8-3332] R_REGS_reg[usec] +# --> mawidth=4, nblock=11, so some cellen unused # OK 2016-06-05 +### i [Synth 8-3332] BRAM_CTL/R_REGS_reg[cellen][1\d] +# --> indeed no types with [3] set # OK 2017-06-06 +i [Synth 8-3332] R_REGS_reg[dtyp][3].* ibdr_rhrp +# --> not yet used # OK 2017-06-06 +i [Synth 8-3332] R_REGS_reg[req_lock].* ibd_iist +i [Synth 8-3332] R_REGS_reg[req_boot].* ibd_iist +# --> monitor outputs moneop,monattn currently not used # OK 2018-10-13 +i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop] +i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn] +# --> PERFEXT(0:2) not used # OK 2018-10-13 +i [Synth 8-3332] R_REGS_reg[psig][2(4|5|6)] +i [Synth 8-3332] PRE[2(4|5|6)].ENA.CNT/R_CNT_reg[\d*] +# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-06 +i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox +# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2017-06-06 +i [Synth 8-3332] R_REGS_reg[ibcacc].* pdp11_vmbox +# --> not yet used # OK 2017-06-06 +i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_sequencer +# --> [8] is for DZ11TX, not yet available # OK 2017-06-06 +# --> [9] is for DZ11RX, unclear why this one isn't removed too !! +i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_sequencer +# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2017-06-06 +i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer +# --> dmcmon not configured, snum not used # OK 2017-06-06 +i [Synth 8-3332] SNUM0.R_VMWAIT_reg.* pdp11_sequencer # OK 2017-06-06 +# --> mawidth=4, nblock=11, so some cellen unused # OK 2018-10-13 +i [Synth 8-3332] R_REGS_reg[cellen][1\d] + +{:} + +# INFO: encoded FSM with state register as -------------------- +# test for sys_w11a_br_arty that all FSMs are one_hot +r [Synth 8-3354] R_BREGS_reg[state.*'one-hot'.*'rlink_core' +r [Synth 8-3354] R_LREGS_reg[state].*'one-hot'.*'rlink_core' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_autobaud' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_rx' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_core_rbus' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_vmbox' +r [Synth 8-3354] R_STATE_reg.*'one-hot'.*'pdp11_sequencer' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_cache' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rhrp' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rl11' +r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'sysmon_rbus_core' + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[imp] +I [Vivado 12-2489] # multiple of 1 ps +I [Physopt 32-742] # BRAM Flop Optimization + +# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +[bit] +# --> DSP multiplier is not pipelined, ok # OK 2018-12-22 +i [DRC DPOP-1] PREG Output pipelining +i [DRC DPOP-2] MREG Output pipelining +{2019.1:} +i [DRC DPIP-1] Input pipelining diff --git a/tools/vivado/viv_tools_build.tcl b/tools/vivado/viv_tools_build.tcl index 9f6817dc..a729e388 100644 --- a/tools/vivado/viv_tools_build.tcl +++ b/tools/vivado/viv_tools_build.tcl @@ -1,9 +1,10 @@ -# $Id: viv_tools_build.tcl 1194 2019-07-20 07:43:21Z mueller $ +# $Id: viv_tools_build.tcl 1242 2022-05-27 17:08:43Z mueller $ # SPDX-License-Identifier: GPL-3.0-or-later -# Copyright 2015-2018 by Walter F.J. Mueller +# Copyright 2015-2022 by Walter F.J. Mueller # # Revision History: # Date Rev Version Comment +# 2022-05-26 1242 1.2.5 increase message limit for Synth 8-7129 # 2018-12-30 1099 1.2.4 downgrade SSN critical warnings to warnings # 2018-12-19 1090 1.2.3 export log and rpt generated in OOC synthesis runs # 2018-11-18 1072 1.2.2 increase message limits (all 200, some 5000) @@ -157,8 +158,10 @@ proc rvtb_default_build {stem step} { # set message limit to 5000 for some cases # Synth 8-3331 : design xxx has unconnected port yyy # Synth 8-3332 : Sequential element xxx is unused .. removed from yyy + # Synth 8-7129 : Port xxx in module yyy is either unconnected or no load set_msg_config -id {[Synth 8-3331]} -limit 5000 set_msg_config -id {[Synth 8-3332]} -limit 5000 + set_msg_config -id {[Synth 8-7129]} -limit 5000 # downgrade 'exceed allowable noise margins' from 'critical' to 'warnings' # otherwise some MIG designs will not accepted to generate a bit file # see https://www.xilinx.com/support/answers/36141.html