From 47a1c58e53d107b50e951bf402a8ede693e3ba98 Mon Sep 17 00:00:00 2001 From: wfjm Date: Thu, 20 Dec 2018 09:18:45 +0100 Subject: [PATCH] tbench: don't test memory controller reset anymore --- tools/tcl/tst_sram/test_regs.tcl | 9 +++++---- tools/tcl/tst_sram/test_seq.tcl | 12 +++--------- 2 files changed, 8 insertions(+), 13 deletions(-) diff --git a/tools/tcl/tst_sram/test_regs.tcl b/tools/tcl/tst_sram/test_regs.tcl index 9fa3bf98..603a1065 100644 --- a/tools/tcl/tst_sram/test_regs.tcl +++ b/tools/tcl/tst_sram/test_regs.tcl @@ -1,6 +1,6 @@ -# $Id: test_regs.tcl 985 2018-01-03 08:59:40Z mueller $ +# $Id: test_regs.tcl 1074 2018-11-25 21:38:59Z mueller $ # -# Copyright 2016-2017 by Walter F.J. Mueller +# Copyright 2016-2018 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2018-11-25 1074 1.2.1 don't reset MEM, only SEQ # 2017-06-25 917 1.2 17bit support; use sstat(awidth); add isnarrow # 2016-07-10 785 1.1 add memory test (touch evenly distributed addr) # 2016-07-09 784 1.0 Initial version (ported from tb_tst_sram_stim.dat) @@ -35,8 +36,8 @@ namespace eval tst_sram { rlc errcnt -clear # rlc log "tst_sram::test_regs ---------------------------------------------" - rlc log " init: reset via init, clear sfail ect" - rlc exec -init sr.mdih 0x0003; # reset MEM,SEQ + rlc log " init: reset SEQ via init, clear sfail ect" + rlc exec -init sr.mdih 0x0001; # reset SEQ (don't reset MEM !) # #------------------------------------------------------------------------- rlc log " test 1a: test mdi* ,maddr*" diff --git a/tools/tcl/tst_sram/test_seq.tcl b/tools/tcl/tst_sram/test_seq.tcl index c5e7e863..ebc3930f 100644 --- a/tools/tcl/tst_sram/test_seq.tcl +++ b/tools/tcl/tst_sram/test_seq.tcl @@ -1,6 +1,6 @@ -# $Id: test_seq.tcl 985 2018-01-03 08:59:40Z mueller $ +# $Id: test_seq.tcl 1074 2018-11-25 21:38:59Z mueller $ # -# Copyright 2016-2017 by Walter F.J. Mueller +# Copyright 2016-2018 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2018-11-25 1074 1.2.1 remove MEM reset via init # 2017-06-25 917 1.2 17bit support; use sstat(awidth); use isnarrow # 2016-07-10 785 1.1 add wswap and wloop tests # 2016-07-09 784 1.0 Initial version (ported from tb_tst_sram_stim.dat) @@ -276,13 +277,6 @@ namespace eval tst_sram { -rreg sr.seaddr -edata 0x0004 \ -rreg sr.sedath -edata 0xb1a1 \ -rreg sr.sedatl -edata 0x9181 - # init 0x2 --> reset MEM, no effect on SEQ state - rlc exec \ - -init sr.mdih 0x0002 \ - -rreg sr.sstat -edata [regbld tst_sram::SSTAT veri fail] $sm \ - -rreg sr.seaddr -edata 0x0004 \ - -rreg sr.sedath -edata 0xb1a1 \ - -rreg sr.sedatl -edata 0x9181 # init 0x1 --> reset SEQ, add registers cleared rlc exec \ -init sr.mdih 0x0001 \