From 4a032e94368ad282ddb7b6df87453eb4de1a7c90 Mon Sep 17 00:00:00 2001 From: "Walter F.J. Mueller" Date: Thu, 14 May 2015 17:00:36 +0000 Subject: [PATCH] - added RH70/RP/RM big disk support - many cleanups --- doc/FILES.txt | 1 + doc/README.txt | 124 +- doc/README_known_issues.txt | 37 + doc/man/man1/ti_rri.1 | 21 +- doc/man/man1/ti_w11.1 | 34 +- doc/w11a_os_guide.txt | 26 +- doc/w11a_tb_guide.txt | 4 +- rtl/bplib/basys3/tb/tb_basys3.vbom | 2 +- rtl/bplib/basys3/tb/tb_basys3.vhd | 48 +- rtl/bplib/fx2rlink/fx2rlinklib.vhd | 10 +- rtl/bplib/fx2rlink/rlink_sp1c_fx2.vbom | 3 + rtl/bplib/fx2rlink/rlink_sp1c_fx2.vhd | 69 +- rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom | 2 +- rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd | 47 +- rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom | 2 +- rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd | 41 +- rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom | 2 +- rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd | 47 +- rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom | 2 +- rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd | 42 +- rtl/bplib/nexys4/tb/tb_nexys4.vbom | 2 +- rtl/bplib/nexys4/tb/tb_nexys4.vhd | 48 +- rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom | 2 +- rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd | 39 +- rtl/bplib/s3board/tb/tb_s3board_fusp.vbom | 2 +- rtl/bplib/s3board/tb/tb_s3board_fusp.vhd | 47 +- rtl/ibus/ibd_ibmon.vbom | 9 + rtl/ibus/ibd_ibmon.vhd | 486 ++++++ rtl/ibus/ibd_kw11l.vhd | 10 +- rtl/ibus/ibdlib.vhd | 25 +- rtl/ibus/ibdr_maxisys.vbom | 2 + rtl/ibus/ibdr_maxisys.vhd | 106 +- rtl/ibus/ibdr_minisys.vhd | 3 +- rtl/ibus/ibdr_rhrp.vbom | 9 + rtl/ibus/ibdr_rhrp.vhd | 1436 +++++++++++++++++ rtl/ibus/ibdr_rk11.vhd | 30 +- rtl/ibus/iblib.vhd | 19 +- rtl/make_ise/generic_xflow.mk | 7 +- rtl/make_ise/syn_s3_speed.opt | 9 +- .../tst_rlink/basys3/sys_tst_rlink_b3.vhd | 9 +- .../tst_rlink/nexys2/sys_tst_rlink_n2.vhd | 11 +- .../tst_rlink/nexys3/sys_tst_rlink_n3.vhd | 11 +- .../tst_rlink/nexys4/sys_tst_rlink_n4.vhd | 9 +- .../tst_rlink/s3board/sys_tst_rlink_s3.vhd | 11 +- rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vhd | 9 +- rtl/sys_gen/w11a/basys3/sys_conf.vhd | 39 +- rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom | 17 +- rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd | 424 ++--- rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd | 29 +- rtl/sys_gen/w11a/nexys2/sys_conf.vhd | 50 +- rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom | 19 +- rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd | 357 ++-- rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd | 52 +- rtl/sys_gen/w11a/nexys3/sys_conf.vhd | 51 +- rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom | 19 +- rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd | 366 ++--- rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd | 53 +- rtl/sys_gen/w11a/nexys4/sys_conf.vhd | 44 +- rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom | 17 +- rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd | 459 ++---- rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd | 46 +- rtl/sys_gen/w11a/s3board/sys_conf.vhd | 45 +- rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom | 23 +- rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd | 461 ++---- rtl/sys_gen/w11a/s3board/tb/sys_conf_sim.vhd | 39 +- rtl/vlib/rbus/rbd_rbmon.vhd | 16 +- rtl/vlib/rbus/rbdlib.vhd | 4 +- rtl/vlib/rlink/rlink_core8.vhd | 9 +- rtl/vlib/rlink/rlink_sp1c.vbom | 3 + rtl/vlib/rlink/rlink_sp1c.vhd | 56 +- rtl/vlib/rlink/rlinklib.vhd | 17 +- rtl/vlib/rlink/tb/tbu_rlink_sp1c.vhd | 7 +- rtl/vlib/serport/serport_1clock.vhd | 22 +- rtl/vlib/serport/serport_2clock.vhd | 18 +- rtl/vlib/serport/serport_master.vbom | 9 + rtl/vlib/serport/serport_master.vhd | 142 ++ rtl/vlib/serport/serport_uart_rxtx_ab.vhd | 3 +- rtl/vlib/serport/serportlib.vhd | 30 +- rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd | 4 +- rtl/w11a/pdp11.vhd | 205 ++- rtl/w11a/pdp11_bram.vhd | 4 +- rtl/w11a/pdp11_cache.vhd | 4 +- rtl/w11a/pdp11_core.vbom | 2 +- rtl/w11a/pdp11_core.vhd | 52 +- rtl/w11a/pdp11_core_rbus.vhd | 43 +- rtl/w11a/pdp11_dpath.vhd | 4 +- rtl/w11a/pdp11_dspmux.vhd | 4 +- rtl/w11a/pdp11_hio70.vbom | 9 + rtl/w11a/pdp11_hio70.vhd | 91 ++ rtl/w11a/pdp11_irq.vhd | 4 +- rtl/w11a/pdp11_ledmux.vhd | 4 +- rtl/w11a/pdp11_mem70.vhd | 4 +- rtl/w11a/pdp11_mmu.vhd | 6 +- rtl/w11a/pdp11_mmu_ssr12.vhd | 4 +- rtl/w11a/pdp11_psr.vhd | 4 +- rtl/w11a/pdp11_reg70.vbom | 8 + rtl/w11a/pdp11_reg70.vhd | 131 ++ rtl/w11a/pdp11_sequencer.vhd | 182 ++- rtl/w11a/pdp11_statleds.vhd | 4 +- rtl/w11a/pdp11_sys70.vbom | 8 + rtl/w11a/pdp11_sys70.vhd | 274 +++- rtl/w11a/pdp11_tmu.vhd | 21 +- rtl/w11a/pdp11_tmu_sb.vhd | 10 +- rtl/w11a/pdp11_vmbox.vhd | 13 +- rtl/w11a/sys_conf.vhd | 24 +- rtl/w11a/tb/tb_pdp11core.vhd | 59 +- rtl/w11a/tb/tb_pdp11core_stim.dat | 198 ++- rtl/w11a/tb/tbd_pdp11core.vhd | 20 +- tools/asm-11/lib/defs_bits.mac | 22 + tools/asm-11/lib/defs_cpu.mac | 29 + tools/asm-11/lib/defs_rk.mac | 71 + tools/asm-11/lib/defs_rp.mac | 77 + tools/asm-11/lib/kprchr.mac | 22 + tools/asm-11/lib/kprdec.mac | 52 + tools/asm-11/lib/kprfmt.mac | 53 + tools/asm-11/lib/kproct.mac | 38 + tools/asm-11/lib/kprstr.mac | 21 + tools/asm-11/lib/vec_cpucatch.mac | 29 + tools/bin/asm-11 | 4 +- tools/bin/create_disk | 23 +- tools/bin/tbrun_tbwrri | 90 +- tools/bin/ti_w11 | 79 +- tools/bin/ticonv_pdpcp | 44 +- tools/bin/tmuconv | 44 +- tools/bin/vbomconv | 3 +- tools/dox/w11_cpp.Doxyfile | 2 +- tools/dox/w11_tcl.Doxyfile | 2 +- tools/dox/w11_vhd_all.Doxyfile | 2 +- tools/oskit/211bsd_rk/README_211bsd_rkset.txt | 11 +- tools/oskit/211bsd_rl/README_211bsd_rlset.txt | 9 +- tools/oskit/211bsd_rp/.cvsignore | 5 + tools/oskit/211bsd_rp/211bsd_rp_boot.scmd | 24 + tools/oskit/211bsd_rp/211bsd_rp_boot.tcl | 28 + tools/oskit/211bsd_rp/README_211bsd_rpset.txt | 134 ++ .../rsx11m-31_rk/README_rsx11m-31_rkset.txt | 5 +- .../rsx11m-40_rk/README_rsx11m-40_rkset.txt | 5 +- tools/oskit/rsx11mp-30_rp/.cvsignore | 5 + .../rsx11mp-30_rp/README_rsx11mp-30_rpset.txt | 79 + .../rsx11mp-30_rp/rsx11mp-30_rp_boot.scmd | 30 + .../rsx11mp-30_rp/rsx11mp-30_rp_boot.tcl | 28 + .../oskit/rt11-40_rk/README_rt11-40_rkset.txt | 5 +- .../oskit/rt11-53_rl/README_rt11-53_rlset.txt | 3 +- .../oskit/unix-v5_rk/README_unix_v5_rkset.txt | 5 +- tools/oskit/xxdp_rl/README_xxdp_rlset.txt | 4 +- tools/src/librlink/ReventLoop.cpp | 14 +- tools/src/librlink/ReventLoop.hpp | 11 +- tools/src/librlink/ReventLoop.ipp | 26 +- tools/src/librlink/RlinkCommand.cpp | 84 +- tools/src/librlink/RlinkCommand.hpp | 27 +- tools/src/librlink/RlinkCommand.ipp | 69 +- tools/src/librlink/RlinkCommandExpect.cpp | 64 +- tools/src/librlink/RlinkCommandExpect.hpp | 24 +- tools/src/librlink/RlinkCommandExpect.ipp | 57 +- tools/src/librlink/RlinkCommandList.cpp | 85 +- tools/src/librlink/RlinkCommandList.hpp | 19 +- tools/src/librlink/RlinkConnect.cpp | 132 +- tools/src/librlink/RlinkConnect.hpp | 24 +- tools/src/librlink/RlinkConnect.ipp | 13 +- tools/src/librlink/RlinkContext.hpp | 12 +- tools/src/librlink/RlinkContext.ipp | 25 +- tools/src/librlink/RlinkPacketBufSnd.cpp | 42 +- tools/src/librlink/RlinkPacketBufSnd.hpp | 14 +- tools/src/librlink/RlinkPacketBufSnd.ipp | 24 +- tools/src/librlink/RlinkPort.cpp | 9 +- tools/src/librlink/RlinkPort.hpp | 9 +- tools/src/librlink/RlinkPort.ipp | 15 +- tools/src/librlink/RlinkPortCuff.cpp | 9 +- tools/src/librlink/RlinkPortFifo.cpp | 12 +- tools/src/librlink/RlinkPortTerm.cpp | 88 +- tools/src/librlink/RlinkPortTerm.hpp | 24 +- tools/src/librlink/RlinkServer.cpp | 13 +- tools/src/librlink/RlinkServerEventLoop.cpp | 10 +- tools/src/librlinktpp/RtclRlinkConnect.cpp | 157 +- tools/src/librlinktpp/RtclRlinkConnect.hpp | 6 +- tools/src/librlinktpp/RtclRlinkServer.cpp | 65 +- tools/src/librlinktpp/RtclRlinkServer.hpp | 14 +- tools/src/librw11/Makefile | 3 +- tools/src/librw11/Rw11CntlDL11.cpp | 12 +- tools/src/librw11/Rw11CntlDL11.hpp | 12 +- tools/src/librw11/Rw11CntlLP11.cpp | 8 +- tools/src/librw11/Rw11CntlLP11.hpp | 8 +- tools/src/librw11/Rw11CntlPC11.cpp | 12 +- tools/src/librw11/Rw11CntlPC11.hpp | 12 +- tools/src/librw11/Rw11CntlRHRP.cpp | 672 ++++++++ tools/src/librw11/Rw11CntlRHRP.hpp | 221 +++ tools/src/librw11/Rw11CntlRHRP.ipp | 56 + tools/src/librw11/Rw11CntlRK11.cpp | 28 +- tools/src/librw11/Rw11CntlRK11.hpp | 18 +- tools/src/librw11/Rw11CntlRL11.cpp | 26 +- tools/src/librw11/Rw11CntlRL11.hpp | 12 +- tools/src/librw11/Rw11Cpu.cpp | 301 ++-- tools/src/librw11/Rw11Cpu.hpp | 119 +- tools/src/librw11/Rw11Cpu.ipp | 47 +- tools/src/librw11/Rw11Unit.cpp | 15 +- tools/src/librw11/Rw11Unit.hpp | 9 +- tools/src/librw11/Rw11UnitDisk.cpp | 7 +- tools/src/librw11/Rw11UnitDisk.hpp | 21 +- tools/src/librw11/Rw11UnitDisk.ipp | 13 +- tools/src/librw11/Rw11UnitRHRP.cpp | 148 ++ tools/src/librw11/Rw11UnitRHRP.hpp | 68 + tools/src/librw11/Rw11UnitRHRP.ipp | 69 + tools/src/librw11/Rw11UnitRK11.cpp | 5 +- tools/src/librw11/Rw11UnitRL11.cpp | 8 +- tools/src/librw11/Rw11UnitVirt.ipp | 11 +- tools/src/librwxxtpp/Makefile | 3 +- tools/src/librwxxtpp/RtclRw11.cpp | 27 +- tools/src/librwxxtpp/RtclRw11.hpp | 10 +- tools/src/librwxxtpp/RtclRw11Cntl.cpp | 19 +- tools/src/librwxxtpp/RtclRw11Cntl.hpp | 6 +- tools/src/librwxxtpp/RtclRw11CntlFactory.cpp | 11 +- tools/src/librwxxtpp/RtclRw11CntlRHRP.cpp | 112 ++ tools/src/librwxxtpp/RtclRw11CntlRHRP.hpp | 50 + tools/src/librwxxtpp/RtclRw11Cpu.cpp | 507 ++++-- tools/src/librwxxtpp/RtclRw11Cpu.hpp | 14 +- tools/src/librwxxtpp/RtclRw11UnitBase.ipp | 12 +- tools/src/librwxxtpp/RtclRw11UnitDisk.cpp | 8 +- tools/src/librwxxtpp/RtclRw11UnitRHRP.cpp | 56 + tools/src/librwxxtpp/RtclRw11UnitRHRP.hpp | 53 + tools/tbench/rhrp_all.dat | 8 + tools/tbench/test_cp_cpubasics.tcl | 119 +- tools/tbench/test_cp_gpr.tcl | 4 +- tools/tbench/test_cp_ibrbasics.tcl | 4 +- tools/tbench/test_cp_membasics.tcl | 4 +- tools/tbench/test_cp_psw.tcl | 4 +- tools/tbench/test_rhrp_basics.tcl | 200 +++ tools/tbench/test_rhrp_func_reg.tcl | 149 ++ tools/tbench/test_rhrp_int.tcl | 490 ++++++ tools/tbench/test_rhrp_regs.tcl | 426 +++++ tools/tcl/ibd_ibmon/.cvsignore | 1 + tools/tcl/ibd_ibmon/util.tcl | 282 ++++ tools/tcl/ibd_rhrp/.cvsignore | 1 + tools/tcl/ibd_rhrp/util.tcl | 165 ++ tools/tcl/rbemon/test_regs.tcl | 32 +- tools/tcl/rbmoni/test_rbtest.tcl | 41 +- tools/tcl/rbmoni/test_regs.tcl | 17 +- tools/tcl/rbmoni/util.tcl | 19 +- tools/tcl/rbtest/test_all.tcl | 6 +- tools/tcl/rbtest/test_attn.tcl | 14 +- tools/tcl/rbtest/test_data.tcl | 29 +- tools/tcl/rbtest/test_fifo.tcl | 51 +- tools/tcl/rbtest/test_labo.tcl | 175 ++ tools/tcl/rbtest/util.tcl | 23 +- tools/tcl/rlink/util.tcl | 6 +- tools/tcl/rutil/util.tcl | 21 +- tools/tcl/rw11/tbench.tcl | 11 +- tools/tcl/rw11/util.tcl | 53 +- tools/tcl/setup_packages | 21 +- 247 files changed, 11301 insertions(+), 3449 deletions(-) create mode 100644 doc/README_known_issues.txt create mode 100644 rtl/ibus/ibd_ibmon.vbom create mode 100644 rtl/ibus/ibd_ibmon.vhd create mode 100644 rtl/ibus/ibdr_rhrp.vbom create mode 100644 rtl/ibus/ibdr_rhrp.vhd create mode 100644 rtl/vlib/serport/serport_master.vbom create mode 100644 rtl/vlib/serport/serport_master.vhd create mode 100644 rtl/w11a/pdp11_hio70.vbom create mode 100644 rtl/w11a/pdp11_hio70.vhd create mode 100644 rtl/w11a/pdp11_reg70.vbom create mode 100644 rtl/w11a/pdp11_reg70.vhd create mode 100644 tools/asm-11/lib/defs_bits.mac create mode 100644 tools/asm-11/lib/defs_cpu.mac create mode 100644 tools/asm-11/lib/defs_rk.mac create mode 100644 tools/asm-11/lib/defs_rp.mac create mode 100644 tools/asm-11/lib/kprchr.mac create mode 100644 tools/asm-11/lib/kprdec.mac create mode 100644 tools/asm-11/lib/kprfmt.mac create mode 100644 tools/asm-11/lib/kproct.mac create mode 100644 tools/asm-11/lib/kprstr.mac create mode 100644 tools/asm-11/lib/vec_cpucatch.mac create mode 100644 tools/oskit/211bsd_rp/.cvsignore create mode 100644 tools/oskit/211bsd_rp/211bsd_rp_boot.scmd create mode 100644 tools/oskit/211bsd_rp/211bsd_rp_boot.tcl create mode 100644 tools/oskit/211bsd_rp/README_211bsd_rpset.txt create mode 100644 tools/oskit/rsx11mp-30_rp/.cvsignore create mode 100644 tools/oskit/rsx11mp-30_rp/README_rsx11mp-30_rpset.txt create mode 100644 tools/oskit/rsx11mp-30_rp/rsx11mp-30_rp_boot.scmd create mode 100644 tools/oskit/rsx11mp-30_rp/rsx11mp-30_rp_boot.tcl create mode 100644 tools/src/librw11/Rw11CntlRHRP.cpp create mode 100644 tools/src/librw11/Rw11CntlRHRP.hpp create mode 100644 tools/src/librw11/Rw11CntlRHRP.ipp create mode 100644 tools/src/librw11/Rw11UnitRHRP.cpp create mode 100644 tools/src/librw11/Rw11UnitRHRP.hpp create mode 100644 tools/src/librw11/Rw11UnitRHRP.ipp create mode 100644 tools/src/librwxxtpp/RtclRw11CntlRHRP.cpp create mode 100644 tools/src/librwxxtpp/RtclRw11CntlRHRP.hpp create mode 100644 tools/src/librwxxtpp/RtclRw11UnitRHRP.cpp create mode 100644 tools/src/librwxxtpp/RtclRw11UnitRHRP.hpp create mode 100644 tools/tbench/rhrp_all.dat create mode 100644 tools/tbench/test_rhrp_basics.tcl create mode 100644 tools/tbench/test_rhrp_func_reg.tcl create mode 100644 tools/tbench/test_rhrp_int.tcl create mode 100644 tools/tbench/test_rhrp_regs.tcl create mode 100644 tools/tcl/ibd_ibmon/.cvsignore create mode 100644 tools/tcl/ibd_ibmon/util.tcl create mode 100644 tools/tcl/ibd_rhrp/.cvsignore create mode 100644 tools/tcl/ibd_rhrp/util.tcl create mode 100644 tools/tcl/rbtest/test_labo.tcl diff --git a/doc/FILES.txt b/doc/FILES.txt index 6659dddd..04db055e 100644 --- a/doc/FILES.txt +++ b/doc/FILES.txt @@ -46,6 +46,7 @@ Short description of the directory layout, what is where ? rtl/w11a - w11a core tools helper programs tools/asm-11 - pdp-11 assembler code + tools/asm-11/lib - definitions and macros for asm-11 tools/asm-11/tests - test bench for asm-11 tools/asm-11/tests-err - test bench for asm-11 (error check part) tools/bin - scripts and binaries diff --git a/doc/README.txt b/doc/README.txt index bf6b391c..5e33c652 100644 --- a/doc/README.txt +++ b/doc/README.txt @@ -1,4 +1,4 @@ -$Id: README.txt 655 2015-03-04 20:35:21Z mueller $ +$Id: README.txt 680 2015-05-14 13:29:46Z mueller $ Release notes for w11a @@ -13,6 +13,7 @@ Release notes for w11a in the doc directory, specifically * README.txt: release notes + * README_known_issues.txt: known issues * INSTALL.txt: installation and building test benches and systems * FILES.txt: short description of the directory layout, what is where ? * w11a_tb_guide.txt: running test benches @@ -21,6 +22,127 @@ Release notes for w11a 2. Change Log ---------------------------------------------------------------- +- trunk (2015-05-14: svn rev 30(oc) 681(wfjm); untagged w11a_V0.65) +++++++++ + - Preface + + - With small RK05 or RL02 sized disks only quite reduced OS setups could + be booted, full featured systems were beyond reach. Now finally large + disks are available, with a RH70 + RP/RM disk controller emulation. It + supports up to four disks and allows now to run full featured 211bsd + or rsx-11mplus systems. + + - to track down issues with ibus devices a 'ibus monitor' was added, it can + record in the default setup up to 511 ibus transactions. An address filter + allows to select accesses of one device. The ibd_ibmon tcl package + contains the appropriate support scripts. + + - several cleanups + - factor out common blocks on sys_w11a_* systems: the core+rbus+cache + logic of single cpu systems now contained in pdp11_sys70, and the + human I/O for digilent boards now in pdp11_hio70. + - cpu start/stop logic cleanup: new command set with simple commands. + Add also a new suspend/resume mechanism, which allows to hold the cpu + without leaving the 'run state'. While suspended all timers are frozen. + Very helpful when debugging, will be the basis for a hardware break + point logic in a later release. + - xon/xoff consolidation: escaping now done in cdata2byte/byte2cdata in + FPGA and in RlinkPacketBufSnd/RlinkPacketBufRcv in backend. The extra + escaping level in serport_xonrx/serport_xontx isn't used anymore, the + special code in RlinkPortTerm has been removed. This allows to use + xon/xoff flow control also in simulation links via RlinkPortFifo. + - status check cleanup: it is very helpful to have a default status check + and an easy way to modify it cases where some error flags are expected + (e.g. on device polls). In the old logic status and data checks were + done via RlinkCommandExpect. The new logic reflects that status checks + are the normal case, and store the status check pattern in RlinkCommand. + The meaning of expect masks for status and data is inverted, now a '1' + means that the bit is checked (before it meant the bit is ignored). + The default status check pattern is still in RlinkContext, but will be + copied to RlinkCommand when the list is processed. RlinkCommandExpect + handles now only data checks. + + - and bug fixes + - rk11 cleanup: since the first days 211bsd autoconfig printed + rk ? csr 177400 vector 220 didn't interrupt + for boots from a RK11 it didn't have consequences, but when booted from + a RL,RP, or RM disk this prevents that the RK11 disks are configured. + Was caused by a missing interrupt after device reset. Now fixed. + + - Summary + - added RH70/RP/RM big disk support + - many cleanups + + - New features + - new directory trees for + - tools/asm-11/lib - definitions and macros for asm-11 + - new modules + - rtl/vlib/serport + - serport_master - serial port module, master side + - rtl/ibus/ibd_ibmon - ibus monitor + - rtl/w11a/pdp11_sys70 - 11/70 system - single core +rbus,debug,cache + - rtl/w11a/pdp11_hio70 - hio led and dsp for sys70 + - tools/src/librw11 + - Rw11(Cntl|Unit)RHRP - Controller/Unit for RHRP + - tools/tbench + - test_rhrp_* - test tbench for RHRP + - new oskits + - tools/oskit/211bsd_rp - new oskit for 2.11BSD on RP06 + - tools/oskit/rsx11mp-30_rp - new oskit for RSX-11Mplus V3.0 on RP06 + + - Changes + - renames + - rtl/w11a/pdp11_sys70 -> pdp11_reg70 (_sys70 now different function) + - functional changes + - rtl/bplib/*/tb/tb_* - use serport_master instead of + serport_uart_rxtx, allow xon/xoff + - rtl/bplib/fx2rlink + - rlink_sp1c_fx2 - add rbd_rbmon (optional via generics) + - rtl/vlib/rlink/rlink_sp1c - add rbd_rbmon (optional via generics) + - rtl/ibus/ibd_kw11l - freeze timer when cpu suspended + - tools/bin/tbrun_tbwrri - add --fusp,--xon + - tools/bin/ti_w11 - rename -fu->-fc, add -f2,-fx; setup defaults + - tools/bin/librlink + - RlinkCommandList - add SetLastExpect() methods + - RlinkPort - add XonEnable() + - RlinkPortCuff - add noinit attribute + - RlinkPort(Fifo|Term) - add xon,noinit attributes + - tools/src/librw11 + - Rw11Cpu - add AddRbibr(), AddWbibr(), RAddrMap() + - tools/bin/librlinktpp + - RtclRlinkConnect - errcnt: add -increment + log: add -bare,-info.. + wtlam: allow tout=0 for attn cleanup + init: new command + exec: drop -estatdef + - RtclRlinkServer - get/set interface added + - tools/src/librwxxtpp + - RtclRw11Cntl - start: new command + - RtclRw11Cpu - cp: add -rbibr, wbibr, -rreg,...,-init + - cp: add -estat(err|nak|tout), drop estatdef + - rename amap->imap; add rmap + + - Bug fixes + - rtl/ibus + - ibdr_rk11 - interrupt after dreset and seek command start + - tools/src/librlink + - RlinkConnect - WaitAttn(): return 0. (not -1.) if poll + - RlinkServer - Stop(): fix race in (could hang) + + - Known issues + - all issues: see README_known_issues.txt + - resolved issues: -- none -- + - new issues: + - V0.65-1: ti_rri sometimes crashes in normal rundown (exit or ^D) when + a cuff: type rlink is active. One gets + terminate called after throwing an instance of 'Retro::Rexception' + what(): RlinkPortCuff::Cleanup(): driver thread failed to stop + doesn't affect normal operation, will be fixed in upcoming release. + - V0.65-2: some exotic RH70/RP/RM features and conditions not implemented + - last block transfered flag (in DS) + - CS2.BAI currently ignored and not handled + - read or write 'with header' gives currently ILF + All this isn't used by any OS, so in practice not relevant. + - trunk (2015-03-01: svn rev 29(oc) 655(wfjm); untagged w11a_V0.64) +++++++++ - Preface diff --git a/doc/README_known_issues.txt b/doc/README_known_issues.txt new file mode 100644 index 00000000..dd41833d --- /dev/null +++ b/doc/README_known_issues.txt @@ -0,0 +1,37 @@ +$Id: README_known_issues.txt 680 2015-05-14 13:29:46Z mueller $ + +Known issues for this release. +The case id indicates the release when the issue was first recognized. + +- V0.65-1: ti_rri sometimes crashes in normal rundown (exit or ^D) when + a cuff: type rlink is active. One gets + terminate called after throwing an instance of 'Retro::Rexception' + what(): RlinkPortCuff::Cleanup(): driver thread failed to stop + doesn't affect normal operation, will be fixed in upcoming release. +- V0.65-2: some exotic RH70/RP/RM features and conditions not implemented yet + - last block transfered flag (in DS) + - CS2.BAI currently ignored and not handled + - read or write 'with header' gives currently ILF + All this isn't used by any OS, so in practice not relevant. + +- V0.64-7: ghdl simulated OS boots via ti_w11 (-n4 ect options) fail due to a + flow control issue (likely since V0.63). +- V0.64-6: IO delays still unconstraint in vivado. All critical IOs use + explicitly IOB flops, thus timing well defined. +- V0.64-5: w11a_tb_guide.txt covers only ISE based tests (see also V0.64-4). +- V0.64-4: No support for the Vivado simulator (xsim) yet. With ghdl only + functional simulations, post synthesis (_ssim) fails to compile. +- V0.64-3: Highest baud rate with basys3 and nexys4 is 10 MBaud. 10 MBaud is + not supported according to FTDI, but works. 12 MBaud in next release. +- V0.64-2: rlink throughput on basys3/nexys4 limited by serial port stack + round trip times. Will be overcome by libusb based custom driver. +- V0.64-1: The large default transfer size for disk accesses leads to bad + throughput in the DL11 emulation for low speed links, like the + 460kBaud the S3board is limited too. Will be overcome by a DL11 + controller with more buffering. + +- V0.62-2: rlink v4 error recovery not yet implemented, will crash on error +- V0.62-1: Command lists aren't split to fit in retransmit buffer size + {last two issues not relevant for w11 backend over USB usage because + the backend produces proper command lists and the USB channel is + usually error free} diff --git a/doc/man/man1/ti_rri.1 b/doc/man/man1/ti_rri.1 index 2fd25280..8486fb52 100644 --- a/doc/man/man1/ti_rri.1 +++ b/doc/man/man1/ti_rri.1 @@ -1,11 +1,11 @@ .\" -*- nroff -*- -.\" $Id: ti_rri.1 653 2015-03-01 12:53:01Z mueller $ +.\" $Id: ti_rri.1 666 2015-04-12 21:17:54Z mueller $ .\" .\" Copyright 2013-2015 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ . -.TH TI_RRI 1 2015-01-28 "Retro Project" "Retro Project Manual" +.TH TI_RRI 1 2015-04-12 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME ti_rri \- \fBRlink\fP Backend Server @@ -76,12 +76,15 @@ name prefix for the named pipe file names. Default is 'rlink_cext_fifo'. Two fifo's are generated, one with a '_tx' and one with a '_tx' appended to the name prefix. .IP \fBopts\fP -comma separated list of further options for the fifo port: +comma separated list of further fifo port options: .RS .PD 0 -.TP -.B keep +.IP \fBkeep\fP fifo is kept open on exit +.IP \fBxon\fP +software flow control (xon/xoff) +.IP \fBnoinit\fP +defer link initialization (debug or test benches) .PD .RE .RE @@ -110,7 +113,7 @@ serial port baud rate, default is '115k'. Allowed baud rate settings are: .PD .RE .IP \fBopts\fP -comma separated list of further options for the serial port connection: +comma separated list of further term port options: .RS .PD 0 .IP \fBbreak\fP @@ -119,6 +122,8 @@ send a break, do autobaud hardware flow control (cts/rts) .IP \fBxon\fP software flow control (xon/xoff) +.IP \fBnoinit\fP +defer link initialization (debug or test benches) .PD .RE .RE @@ -131,11 +136,13 @@ open a USB via Cypress FX2 type \fBrlink\fP port. Optional arguments are USB path, default derived from environment variables RETRO_FX2_VID and RETRO_FX2_PID. .IP \fBopts\fP -comma separated list of further options for the fifo port: +comma separated list of further cuff port options: .RS .PD 0 .IP \fBtrace\fP trace USB activities +.IP \fBnoinit\fP +defer link initialization (debug or test benches) .PD .RE .RE diff --git a/doc/man/man1/ti_w11.1 b/doc/man/man1/ti_w11.1 index 6e5a2869..9c0e01ca 100644 --- a/doc/man/man1/ti_w11.1 +++ b/doc/man/man1/ti_w11.1 @@ -1,11 +1,11 @@ .\" -*- nroff -*- -.\" $Id: ti_w11.1 654 2015-03-01 18:45:38Z mueller $ +.\" $Id: ti_w11.1 680 2015-05-14 13:29:46Z mueller $ .\" .\" Copyright 2013-2015 by Walter F.J. Mueller .\" .\" ------------------------------------------------------------------ . -.TH TI_W11 1 2015-02-22 "Retro Project" "Retro Project Manual" +.TH TI_W11 1 2015-04-12 "Retro Project" "Retro Project Manual" .\" ------------------------------------------------------------------ .SH NAME ti_w11 \- Quick starter for \fBti_rri\fP with \fBw11\fP CPU designs @@ -51,16 +51,36 @@ use /dev/ttyUSB* (* is device number \fIN\fP) .SS "setup options for ghdl simulation runs" .PD 0 .IP \fB-b3\fP -start \fItb_w11a_b3\fP simulation (w11a on Basys3 board) +start \fItb_w11a_b3\fP simulation (w11a on Basys3, default \fB-f1x\fP) .IP \fB-n4\fP -start \fItb_w11a_n4\fP simulation (w11a on Nexys4 board) +start \fItb_w11a_n4\fP simulation (w11a on Nexys4) .IP \fB-n3\fP -start \fItb_w11a_n3\fP simulation (w11a on Nexys3 board) +start \fItb_w11a_n3\fP simulation (w11a on Nexys3, default \fB-fc\fP) .IP \fB-n2\fP -start \fItb_w11a_n2\fP simulation (w11a on Nexys2 board) +start \fItb_w11a_n2\fP simulation (w11a on Nexys2, default \fB-fc\fP) .IP \fB-s3\fP -start \fItb_w11a_s3\fP simulation (w11a on S3board) +start \fItb_w11a_s3\fP simulation (w11a on S3board, default \fB-f2\fP) .PD +.IP \fB-f\fIm\fR +select communication mode for simulation. The \fB-f\fIm\fR can be used after +the \fB-b3\fP,...,\fB-s3\fP options to overwrite the default. Valid values +for mode \fIm\fP are +.RS +.PD 0 +.IP \fBc\fP 4 +use Cypress FX2 data path (cuff, only for -n2 and -n3) +.IP \fB1\fP 4 +use 1st serport +.IP \fB1x\fP 4 +use 1st serport with xon +.IP \fB2\fP 4 +use 2nd serport (fusp, only for -s3,-n2,-n3) +.IP \fB2x\fP 4 +use 2nd serport with xon +.PD +.RE +.IP \fB-tmu\fP +activate trace and monitoring unit . .SS "common options" .IP \fB-e "\fR=\fIfile"\fR diff --git a/doc/w11a_os_guide.txt b/doc/w11a_os_guide.txt index 3cee30ef..915f9d4e 100644 --- a/doc/w11a_os_guide.txt +++ b/doc/w11a_os_guide.txt @@ -1,4 +1,4 @@ -# $Id: w11a_os_guide.txt 654 2015-03-01 18:45:38Z mueller $ +# $Id: w11a_os_guide.txt 680 2015-05-14 13:29:46Z mueller $ Guide to run operating system images on w11a systems @@ -202,11 +202,13 @@ Guide to run operating system images on w11a systems can be freely distributed and used for non-commercial purposes. - Two oskits are currently provided: + Several oskits are provided: - unix-v5_rk: Unix V5 System on RK05 - - 211bsd_rk: 2.11BSD system on RK05 - - 211bsd_rl: 2.11BSD system on RL02 + + - 211bsd_rk: 2.11BSD system on RK05 (very elementary subset) + - 211bsd_rl: 2.11BSD system on RL02 (small subset) + - 211bsd_rp: 2.11BSD system on RP06 (full system) For further details consult the README_set.txt file in the oskit directory. @@ -240,13 +242,17 @@ Guide to run operating system images on w11a systems out the W11A and let the author know whether is works as it should. For convenience the boot scripts are also included ( .tcl ). - Several osskits are currently provided + Several oskits are provided: - - rsx11m-31_rk: RSX-11M V3.1 on RK05 - - rsx11m-40_rk: RSX-11M V4.0 on RK05 - - rt11-40_rk: RT-11 V4.0 on RK05 - - rt11-53_rl: RT-11 V5.3 on RL02 - - xxdp_rl: XXDP 22 and 25 on RL02 + - rsx11m-31_rk: RSX-11M V3.1 on RK05 + - rsx11m-40_rk: RSX-11M V4.0 on RK05 + + - rsx11mp-30_rp: RSX-11M+ V3.0 on RP06 + + - rt11-40_rk: RT-11 V4.0 on RK05 + - rt11-53_rl: RT-11 V5.3 on RL02 + + - xxdp_rl: XXDP 22 and 25 on RL02 For further details consult the README_set.txt file in the oskit directory. diff --git a/doc/w11a_tb_guide.txt b/doc/w11a_tb_guide.txt index 421eb541..ef37bb90 100644 --- a/doc/w11a_tb_guide.txt +++ b/doc/w11a_tb_guide.txt @@ -1,4 +1,4 @@ -# $Id: w11a_tb_guide.txt 654 2015-03-01 18:45:38Z mueller $ +# $Id: w11a_tb_guide.txt 660 2015-03-29 22:10:16Z mueller $ Note: Only ISE based test benches are currently documented ! The Vivado test environemnt is still in it's infancy ! @@ -258,7 +258,7 @@ Guide to running w11a test benches - sys_w11a_n2 test bench cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb - tbrun_tbwrri --lsuf tbench_dsim --pack rw11 --cuff tb_w11a_n2 \ + tbrun_tbwrri --lsuf tbench_dsim --pack rw11 --cuff tb_w11a_n2 \ "rw11::setup_cpu" "rw11::tbench @w11a_all.dat" -> 2638820.0 ns 131930: DONE -> real 0m24.890s user 0m25.286s sys 0m0.439s diff --git a/rtl/bplib/basys3/tb/tb_basys3.vbom b/rtl/bplib/basys3/tb/tb_basys3.vbom index 0081d950..b33dbe91 100644 --- a/rtl/bplib/basys3/tb/tb_basys3.vbom +++ b/rtl/bplib/basys3/tb/tb_basys3.vbom @@ -18,7 +18,7 @@ ${sys_conf := sys_conf_sim.vhd} ../../../vlib/rlink/tb/tbcore_rlink.vbom ../../../vlib/xlib/s7_cmt_sfs_gsim.vbom tb_basys3_core.vbom -../../../vlib/serport/serport_uart_rxtx.vbom +../../../vlib/serport/serport_master.vbom ${basys3_aif := basys3_dummy.vbom} # design tb_basys3.vhd diff --git a/rtl/bplib/basys3/tb/tb_basys3.vhd b/rtl/bplib/basys3/tb/tb_basys3.vhd index e49f6148..257fb381 100644 --- a/rtl/bplib/basys3/tb/tb_basys3.vhd +++ b/rtl/bplib/basys3/tb/tb_basys3.vhd @@ -1,4 +1,4 @@ --- $Id: tb_basys3.vhd 648 2015-02-20 20:16:21Z mueller $ +-- $Id: tb_basys3.vhd 666 2015-04-12 21:17:54Z mueller $ -- -- Copyright 2015- by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- rlink/tb/tbcore_rlink -- xlib/s7_cmt_sfs -- tb_basys3_core --- serport/serport_uart_rxtx +-- serport/serport_master -- basys3_aif [UUT] -- -- To test: generic, any basys3_aif target @@ -30,6 +30,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-12 666 1.1 use serport_master instead of serport_uart_rxtx -- 2015-02-18 648 1.0 Initial version (derived from tb_nexys4) ------------------------------------------------------------------------------ @@ -78,6 +79,10 @@ architecture sim of tb_basys3 is signal O_ANO_N : slv4 := (others=>'0'); signal O_SEG_N : slv8 := (others=>'0'); + signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff + + constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); + constant clock_period : time := 10 ns; constant clock_offset : time := 200 ns; @@ -138,22 +143,26 @@ begin O_SEG_N => O_SEG_N ); - UART : serport_uart_rxtx + SERMSTR : serport_master generic map ( CDWIDTH => CLKDIV'length) port map ( - CLK => CLKCOM, - RESET => RESET, - CLKDIV => CLKDIV, - RXSD => O_TXD, - RXDATA => RXDATA, - RXVAL => RXVAL, - RXERR => RXERR, - RXACT => RXACT, - TXSD => I_RXD, - TXDATA => TXDATA, - TXENA => TXENA, - TXBUSY => TXBUSY + CLK => CLKCOM, + RESET => RESET, + CLKDIV => CLKDIV, + ENAXON => R_PORTSEL_XON, + ENAESC => '0', + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXOK => '1', + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + RXSD => O_TXD, + TXSD => I_RXD, + RXRTS_N => open, + TXCTS_N => '0' ); proc_moni: process @@ -172,4 +181,13 @@ begin end process proc_moni; + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_portsel then + R_PORTSEL_XON <= to_x01(SB_DATA(1)); + end if; + end if; + end process proc_simbus; + end sim; diff --git a/rtl/bplib/fx2rlink/fx2rlinklib.vhd b/rtl/bplib/fx2rlink/fx2rlinklib.vhd index 63d5d935..891c4596 100644 --- a/rtl/bplib/fx2rlink/fx2rlinklib.vhd +++ b/rtl/bplib/fx2rlink/fx2rlinklib.vhd @@ -1,6 +1,6 @@ --- $Id: fx2rlinklib.vhd 610 2014-12-09 22:44:43Z mueller $ +-- $Id: fx2rlinklib.vhd 672 2015-05-02 21:58:28Z mueller $ -- --- Copyright 2013- by Walter F.J. Mueller +-- Copyright 2013-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,6 +20,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-11 666 1.2 rlink_sp1c_fx2: drop ENAESC -- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT -- 2013-04-20 509 1.0 Initial version ------------------------------------------------------------------------------ @@ -53,7 +54,9 @@ component rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none) ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none) CDWIDTH : positive := 13; -- clk divider width - CDINIT : natural := 15); -- clk divider initial/reset setting + CDINIT : natural := 15; -- clk divider initial/reset setting + RBMON_AWIDTH : natural := 0; -- rbmon: buffer size (0=none) + RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr port ( CLK : in slbit; -- clock CE_USEC : in slbit; -- 1 usec clock enable @@ -61,7 +64,6 @@ component rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo CE_INT : in slbit := '0'; -- rri ato time unit clock enable RESET : in slbit; -- reset ENAXON : in slbit; -- enable xon/xoff handling - ENAESC : in slbit; -- enable xon/xoff escaping ENAFX2 : in slbit; -- enable fx2 usage RXSD : in slbit; -- receive serial data (board view) TXSD : out slbit; -- transmit serial data (board view) diff --git a/rtl/bplib/fx2rlink/rlink_sp1c_fx2.vbom b/rtl/bplib/fx2rlink/rlink_sp1c_fx2.vbom index 75d70a38..70a7c825 100644 --- a/rtl/bplib/fx2rlink/rlink_sp1c_fx2.vbom +++ b/rtl/bplib/fx2rlink/rlink_sp1c_fx2.vbom @@ -1,9 +1,12 @@ # libs ../../vlib/slvtypes.vhd ../../vlib/rbus/rblib.vhd +../../vlib/rbus/rbdlib.vhd ../../vlib/rlink/rlinklib.vbom ../../vlib/serport/serportlib.vbom ../fx2lib/fx2lib.vhd +../../vlib/rbus/rbd_rbmon.vbom +../../vlib/rbus/rb_sres_or_2.vbom # components ../../vlib/rlink/rlink_core8.vbom ../../vlib/serport/serport_1clock.vbom diff --git a/rtl/bplib/fx2rlink/rlink_sp1c_fx2.vhd b/rtl/bplib/fx2rlink/rlink_sp1c_fx2.vhd index 682b8951..d664c271 100644 --- a/rtl/bplib/fx2rlink/rlink_sp1c_fx2.vhd +++ b/rtl/bplib/fx2rlink/rlink_sp1c_fx2.vhd @@ -1,6 +1,6 @@ --- $Id: rlink_sp1c_fx2.vhd 610 2014-12-09 22:44:43Z mueller $ +-- $Id: rlink_sp1c_fx2.vhd 672 2015-05-02 21:58:28Z mueller $ -- --- Copyright 2013-2014 by Walter F.J. Mueller +-- Copyright 2013-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,18 +19,23 @@ -- serport/serport_1clock -- rlinklib/rlink_rlbmux -- fx2lib/fx2_2fifoctl_ic +-- rbus/rbd_rbmon +-- rbus/rb_sres_or_2 -- -- Test bench: - -- -- Target Devices: generic --- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 +-- Tool versions: xst 13.1-14.7; viv 2014.4; ghdl 0.29-0.31 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri ifa ofa +-- 2015-05-02 672 14.7 131013 xc6slx16-2 618 875 90 340 s 7.2 - - -- 2013-04-20 509 13.3 O76d xc3s1200e-4 441 903 128 637 s 8.7 - - -- -- Revision History: -- Date Rev Version Comment +-- 2015-05-02 672 1.3 add rbd_rbmon (optional via generics) +-- 2015-04-11 666 1.2 drop ENAESC, rearrange XON handling -- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT -- 2013-04-20 509 1.0 Initial version (derived from rlink_sp1c) ------------------------------------------------------------------------------ @@ -41,6 +46,7 @@ use ieee.numeric_std.all; use work.slvtypes.all; use work.rblib.all; +use work.rbdlib.all; use work.rlinklib.all; use work.serportlib.all; use work.fx2lib.all; @@ -58,7 +64,9 @@ entity rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none) ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none) CDWIDTH : positive := 13; -- clk divider width - CDINIT : natural := 15); -- clk divider initial/reset setting + CDINIT : natural := 15; -- clk divider initial/reset setting + RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none) + RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr port ( CLK : in slbit; -- clock CE_USEC : in slbit; -- 1 usec clock enable @@ -66,7 +74,6 @@ entity rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo CE_INT : in slbit := '0'; -- rri ato time unit clock enable RESET : in slbit; -- reset ENAXON : in slbit; -- enable xon/xoff handling - ENAESC : in slbit; -- enable xon/xoff escaping ENAFX2 : in slbit; -- enable fx2 usage RXSD : in slbit; -- receive serial data (board view) TXSD : out slbit; -- transmit serial data (board view) @@ -117,9 +124,13 @@ architecture syn of rlink_sp1c_fx2 is signal FX2_TXBUSY : slbit := '0'; signal FX2_TXAFULL : slbit := '0'; + signal RB_MREQ_M : rb_mreq_type := rb_mreq_init; + signal RB_SRES_M : rb_sres_type := rb_sres_init; + signal RB_SRES_RBMON : rb_sres_type := rb_sres_init; + begin - CORE : rlink_core8 + CORE : rlink_core8 -- rlink master ---------------------- generic map ( BTOWIDTH => BTOWIDTH, RTAWIDTH => RTAWIDTH, @@ -131,6 +142,8 @@ begin CLK => CLK, CE_INT => CE_INT, RESET => RESET, + ESCXON => ENAXON, + ESCFILL => '0', -- not used in FX2 enabled boards RLB_DI => RLB_DI, RLB_ENA => RLB_ENA, RLB_BUSY => RLB_BUSY, @@ -138,13 +151,13 @@ begin RLB_VAL => RLB_VAL, RLB_HOLD => RLB_HOLD, RL_MONI => RL_MONI, - RB_MREQ => RB_MREQ, - RB_SRES => RB_SRES, + RB_MREQ => RB_MREQ_M, + RB_SRES => RB_SRES_M, RB_LAM => RB_LAM, RB_STAT => RB_STAT ); - SERPORT : serport_1clock + SERPORT : serport_1clock -- serport interface ----------------- generic map ( CDWIDTH => CDWIDTH, CDINIT => CDINIT, @@ -155,7 +168,7 @@ begin CE_MSEC => CE_MSEC, RESET => RESET, ENAXON => ENAXON, - ENAESC => ENAESC, + ENAESC => '0', -- escaping now in rlink_core8 RXDATA => SER_RXDATA, RXVAL => SER_RXVAL, RXHOLD => SER_RXHOLD, @@ -169,7 +182,7 @@ begin TXCTS_N => CTS_N ); - RLBMUX : rlink_rlbmux + RLBMUX : rlink_rlbmux -- rlink control mux ----------------- port map ( SEL => ENAFX2, RLB_DI => RLB_DI, @@ -192,7 +205,12 @@ begin P1_TXBUSY => FX2_TXBUSY ); - FX2CNTL : fx2_2fifoctl_ic + RLB_MONI.rxval <= RLB_VAL; + RLB_MONI.rxhold <= RLB_HOLD; + RLB_MONI.txena <= RLB_ENA; + RLB_MONI.txbusy <= RLB_BUSY; + + FX2CNTL : fx2_2fifoctl_ic -- FX2 interface --------------------- generic map ( RXFAWIDTH => 5, TXFAWIDTH => 5, @@ -222,9 +240,28 @@ begin IO_FX2_DATA => IO_FX2_DATA ); - RLB_MONI.rxval <= RLB_VAL; - RLB_MONI.rxhold <= RLB_HOLD; - RLB_MONI.txena <= RLB_ENA; - RLB_MONI.txbusy <= RLB_BUSY; + RBMON : if RBMON_AWIDTH > 0 generate -- rbus monitor -------------- + begin + I0 : rbd_rbmon + generic map ( + RB_ADDR => RBMON_RBADDR, + AWIDTH => RBMON_AWIDTH) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ_M, + RB_SRES => RB_SRES_RBMON, + RB_SRES_SUM => RB_SRES_M + ); + end generate RBMON; + + RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- + port map ( + RB_SRES_1 => RB_SRES, + RB_SRES_2 => RB_SRES_RBMON, + RB_SRES_OR => RB_SRES_M + ); + + RB_MREQ <= RB_MREQ_M; -- setup output signals end syn; diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom b/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom index e9f0c76f..072d7eea 100644 --- a/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom +++ b/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom @@ -18,7 +18,7 @@ ${sys_conf := sys_conf_sim.vhd} ../../../vlib/rlink/tb/tbcore_rlink.vbom ../../../vlib/xlib/dcm_sfs_gsim.vbom tb_nexys2_core.vbom -../../../vlib/serport/serport_uart_rxtx.vbom +../../../vlib/serport/serport_master.vbom ${nexys2_fusp_aif := nexys2_fusp_dummy.vbom} # design tb_nexys2_fusp.vhd diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd b/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd index 3b587107..596f1455 100644 --- a/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd +++ b/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd @@ -1,6 +1,6 @@ --- $Id: tb_nexys2_fusp.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: tb_nexys2_fusp.vhd 666 2015-04-12 21:17:54Z mueller $ -- --- Copyright 2010-2011 by Walter F.J. Mueller +-- Copyright 2010-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,7 +20,7 @@ -- xlib/dcm_sfs -- rlink/tb/tbcore_rlink -- tb_nexys2_core --- serport/serport_uart_rxtx +-- serport/serport_master -- nexys2_fusp_aif [UUT] -- -- To test: generic, any nexys2_fusp_aif target @@ -30,6 +30,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-12 666 3.3 use serport_master instead of serport_uart_rxtx -- 2011-12-23 444 3.2 new system clock scheme, new tbcore_rlink iface -- 2011-11-26 433 3.1.1 remove O_FLA_CE_N from tb_nexys2_core -- 2011-11-21 432 3.1 update O_FLA_CE_N usage @@ -110,7 +111,8 @@ architecture sim of tb_nexys2_fusp is signal CTS_N : slbit := '0'; signal RTS_N : slbit := '0'; - signal R_PORTSEL : slbit := '0'; + signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport + signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); @@ -197,29 +199,33 @@ begin O_FUSP_TXD => O_FUSP_TXD ); - UART : serport_uart_rxtx + SERMSTR : serport_master generic map ( CDWIDTH => CLKDIV'length) port map ( - CLK => CLKCOM, - RESET => UART_RESET, - CLKDIV => CLKDIV, - RXSD => UART_RXD, - RXDATA => RXDATA, - RXVAL => RXVAL, - RXERR => RXERR, - RXACT => RXACT, - TXSD => UART_TXD, - TXDATA => TXDATA, - TXENA => TXENA, - TXBUSY => TXBUSY + CLK => CLKCOM, + RESET => UART_RESET, + CLKDIV => CLKDIV, + ENAXON => R_PORTSEL_XON, + ENAESC => '0', + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXOK => '1', + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + RXSD => UART_RXD, + TXSD => UART_TXD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N ); - proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N, + proc_port_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N, O_TXD, O_FUSP_TXD, O_FUSP_RTS_N) begin - if R_PORTSEL = '0' then -- use main board rs232, no flow cntl + if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl I_RXD <= UART_TXD; -- write port 0 inputs UART_RXD <= O_TXD; -- get port 0 outputs RTS_N <= '0'; @@ -255,7 +261,8 @@ begin begin if SB_VAL'event and to_x01(SB_VAL)='1' then if SB_ADDR = sbaddr_portsel then - R_PORTSEL <= to_x01(SB_DATA(0)); + R_PORTSEL_SER <= to_x01(SB_DATA(0)); + R_PORTSEL_XON <= to_x01(SB_DATA(1)); end if; end if; end process proc_simbus; diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom b/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom index b8979c8e..ec5397f6 100644 --- a/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom +++ b/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom @@ -18,7 +18,7 @@ ${sys_conf := sys_conf_sim.vhd} ../../../vlib/rlink/tb/tbcore_rlink.vbom ../../../vlib/xlib/dcm_sfs_gsim.vbom tb_nexys2_core.vbom -../../../vlib/serport/serport_uart_rxtx.vbom +../../../vlib/serport/serport_master.vbom ../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom ${nexys2_fusp_cuff_aif := nexys2_fusp_cuff_dummy.vbom} # design diff --git a/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd b/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd index 246f06cf..24bbd31b 100644 --- a/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd +++ b/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd @@ -1,6 +1,6 @@ --- $Id: tb_nexys2_fusp_cuff.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: tb_nexys2_fusp_cuff.vhd 666 2015-04-12 21:17:54Z mueller $ -- --- Copyright 2013- by Walter F.J. Mueller +-- Copyright 2013-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,7 +20,7 @@ -- xlib/dcm_sfs -- rlink/tb/tbcore_rlink_dcm -- tb_nexys2_core --- serport/serport_uart_rxtx +-- serport/serport_master -- fx2lib/tb/fx2_2fifo_core -- nexys2_fusp_cuff_aif [UUT] -- @@ -31,6 +31,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx -- 2013-01-03 469 1.1 add fx2 model and data path -- 2013-01-01 467 1.0 Initial version (derived from tb_nexys2_fusp) ------------------------------------------------------------------------------ @@ -126,6 +127,7 @@ architecture sim of tb_nexys2_fusp_cuff is signal RTS_N : slbit := '0'; signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport + signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff signal R_PORTSEL_FX2 : slbit := '0'; -- if 1 use fx2 constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); @@ -221,22 +223,26 @@ begin IO_FX2_DATA => IO_FX2_DATA ); - UART : serport_uart_rxtx + SERMSTR : serport_master generic map ( CDWIDTH => CLKDIV'length) port map ( - CLK => CLKCOM, - RESET => UART_RESET, - CLKDIV => CLKDIV, - RXSD => UART_RXD, - RXDATA => UART_RXDATA, - RXVAL => UART_RXVAL, - RXERR => UART_RXERR, - RXACT => UART_RXACT, - TXSD => UART_TXD, - TXDATA => UART_TXDATA, - TXENA => UART_TXENA, - TXBUSY => UART_TXBUSY + CLK => CLKCOM, + RESET => UART_RESET, + CLKDIV => CLKDIV, + ENAXON => R_PORTSEL_XON, + ENAESC => '0', + RXDATA => UART_RXDATA, + RXVAL => UART_RXVAL, + RXERR => UART_RXERR, + RXOK => '1', + TXDATA => UART_TXDATA, + TXENA => UART_TXENA, + TXBUSY => UART_TXBUSY, + RXSD => UART_RXD, + TXSD => UART_TXD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N ); FX2 : entity work.fx2_2fifo_core @@ -321,7 +327,8 @@ begin if SB_VAL'event and to_x01(SB_VAL)='1' then if SB_ADDR = sbaddr_portsel then R_PORTSEL_SER <= to_x01(SB_DATA(0)); - R_PORTSEL_FX2 <= to_x01(SB_DATA(1)); + R_PORTSEL_XON <= to_x01(SB_DATA(1)); + R_PORTSEL_FX2 <= to_x01(SB_DATA(2)); end if; end if; end process proc_simbus; diff --git a/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom b/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom index f5847539..a2e141c0 100644 --- a/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom +++ b/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom @@ -18,7 +18,7 @@ ${sys_conf := sys_conf_sim.vhd} ../../../vlib/rlink/tb/tbcore_rlink.vbom ../../../vlib/xlib/s6_cmt_sfs_gsim.vbom tb_nexys3_core.vbom -../../../vlib/serport/serport_uart_rxtx.vbom +../../../vlib/serport/serport_master.vbom ${nexys3_fusp_aif := nexys3_fusp_dummy.vbom} # design tb_nexys3_fusp.vhd diff --git a/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd b/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd index 8b37b4e5..6a3ef480 100644 --- a/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd +++ b/rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd @@ -1,6 +1,6 @@ --- $Id: tb_nexys3_fusp.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: tb_nexys3_fusp.vhd 666 2015-04-12 21:17:54Z mueller $ -- --- Copyright 2011-2013 by Walter F.J. Mueller +-- Copyright 2011-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,7 +20,7 @@ -- xlib/s6_cmt_sfs -- rlink/tb/tbcore_rlink -- tb_nexys3_core --- serport/serport_uart_rxtx +-- serport/serport_master -- nexys3_fusp_aif [UUT] -- -- To test: generic, any nexys3_fusp_aif target @@ -30,6 +30,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx -- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect -- 2011-12-23 444 1.1 new system clock scheme, new tbcore_rlink iface -- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_fusp) @@ -106,7 +107,8 @@ architecture sim of tb_nexys3_fusp is signal CTS_N : slbit := '0'; signal RTS_N : slbit := '0'; - signal R_PORTSEL : slbit := '0'; + signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport + signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); @@ -198,29 +200,33 @@ begin O_FUSP_TXD => O_FUSP_TXD ); - UART : serport_uart_rxtx + SERMSTR : serport_master generic map ( CDWIDTH => CLKDIV'length) port map ( - CLK => CLKCOM, - RESET => UART_RESET, - CLKDIV => CLKDIV, - RXSD => UART_RXD, - RXDATA => RXDATA, - RXVAL => RXVAL, - RXERR => RXERR, - RXACT => RXACT, - TXSD => UART_TXD, - TXDATA => TXDATA, - TXENA => TXENA, - TXBUSY => TXBUSY + CLK => CLKCOM, + RESET => UART_RESET, + CLKDIV => CLKDIV, + ENAXON => R_PORTSEL_XON, + ENAESC => '0', + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXOK => '1', + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + RXSD => UART_RXD, + TXSD => UART_TXD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N ); - proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N, + proc_port_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N, O_TXD, O_FUSP_TXD, O_FUSP_RTS_N) begin - if R_PORTSEL = '0' then -- use main board rs232, no flow cntl + if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl I_RXD <= UART_TXD; -- write port 0 inputs UART_RXD <= O_TXD; -- get port 0 outputs RTS_N <= '0'; @@ -256,7 +262,8 @@ begin begin if SB_VAL'event and to_x01(SB_VAL)='1' then if SB_ADDR = sbaddr_portsel then - R_PORTSEL <= to_x01(SB_DATA(0)); + R_PORTSEL_SER <= to_x01(SB_DATA(0)); + R_PORTSEL_XON <= to_x01(SB_DATA(1)); end if; end if; end process proc_simbus; diff --git a/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom b/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom index 14c6c5ab..2d7e2d45 100644 --- a/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom +++ b/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom @@ -18,7 +18,7 @@ ${sys_conf := sys_conf_sim.vhd} ../../../vlib/rlink/tb/tbcore_rlink.vbom ../../../vlib/xlib/s6_cmt_sfs_gsim.vbom tb_nexys3_core.vbom -../../../vlib/serport/serport_uart_rxtx.vbom +../../../vlib/serport/serport_master.vbom ../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom ${nexys3_fusp_cuff_aif := nexys3_fusp_cuff_dummy.vbom} # design diff --git a/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd b/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd index ed54c4ca..ffde64df 100644 --- a/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd +++ b/rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd @@ -1,6 +1,6 @@ --- $Id: tb_nexys3_fusp_cuff.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: tb_nexys3_fusp_cuff.vhd 666 2015-04-12 21:17:54Z mueller $ -- --- Copyright 2013- by Walter F.J. Mueller +-- Copyright 2013-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,7 +20,7 @@ -- xlib/s6_cmt_sfs -- rlink/tb/tbcore_rlink -- tb_nexys3_core --- serport/serport_uart_rxtx +-- serport/serport_master -- fx2lib/tb/fx2_2fifo_core -- nexys3_fusp_cuff_aif [UUT] -- @@ -31,6 +31,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx -- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect -- 2013-04-21 509 1.0 Initial version (derived from tb_nexys3_fusp and -- tb_nexys2_fusp_cuff) @@ -75,7 +76,6 @@ architecture sim of tb_nexys3_fusp_cuff is signal UART_RXDATA : slv8 := (others=>'0'); signal UART_RXVAL : slbit := '0'; signal UART_RXERR : slbit := '0'; - signal UART_RXACT : slbit := '0'; signal UART_TXDATA : slv8 := (others=>'0'); signal UART_TXENA : slbit := '0'; signal UART_TXBUSY : slbit := '0'; @@ -128,6 +128,7 @@ architecture sim of tb_nexys3_fusp_cuff is signal RTS_N : slbit := '0'; signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport + signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff signal R_PORTSEL_FX2 : slbit := '0'; -- if 1 use fx2 constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); @@ -228,22 +229,26 @@ begin IO_FX2_DATA => IO_FX2_DATA ); - UART : serport_uart_rxtx + SERMSTR : serport_master generic map ( CDWIDTH => CLKDIV'length) port map ( - CLK => CLKCOM, - RESET => UART_RESET, - CLKDIV => CLKDIV, - RXSD => UART_RXD, - RXDATA => UART_RXDATA, - RXVAL => UART_RXVAL, - RXERR => UART_RXERR, - RXACT => UART_RXACT, - TXSD => UART_TXD, - TXDATA => UART_TXDATA, - TXENA => UART_TXENA, - TXBUSY => UART_TXBUSY + CLK => CLKCOM, + RESET => UART_RESET, + CLKDIV => CLKDIV, + ENAXON => R_PORTSEL_XON, + ENAESC => '0', + RXDATA => UART_RXDATA, + RXVAL => UART_RXVAL, + RXERR => UART_RXERR, + RXOK => '1', + TXDATA => UART_TXDATA, + TXENA => UART_TXENA, + TXBUSY => UART_TXBUSY, + RXSD => UART_RXD, + TXSD => UART_TXD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N ); FX2 : entity work.fx2_2fifo_core @@ -328,7 +333,8 @@ begin if SB_VAL'event and to_x01(SB_VAL)='1' then if SB_ADDR = sbaddr_portsel then R_PORTSEL_SER <= to_x01(SB_DATA(0)); - R_PORTSEL_FX2 <= to_x01(SB_DATA(1)); + R_PORTSEL_XON <= to_x01(SB_DATA(1)); + R_PORTSEL_FX2 <= to_x01(SB_DATA(2)); end if; end if; end process proc_simbus; diff --git a/rtl/bplib/nexys4/tb/tb_nexys4.vbom b/rtl/bplib/nexys4/tb/tb_nexys4.vbom index 9cc7aa9c..9a272f2a 100644 --- a/rtl/bplib/nexys4/tb/tb_nexys4.vbom +++ b/rtl/bplib/nexys4/tb/tb_nexys4.vbom @@ -18,7 +18,7 @@ ${sys_conf := sys_conf_sim.vhd} ../../../vlib/rlink/tb/tbcore_rlink.vbom ../../../vlib/xlib/s7_cmt_sfs_gsim.vbom tb_nexys4_core.vbom -../../../vlib/serport/serport_uart_rxtx.vbom +../../../vlib/serport/serport_master.vbom ${nexys4_aif := nexys4_dummy.vbom} # design tb_nexys4.vhd diff --git a/rtl/bplib/nexys4/tb/tb_nexys4.vhd b/rtl/bplib/nexys4/tb/tb_nexys4.vhd index 943ae2c9..3af73e7e 100644 --- a/rtl/bplib/nexys4/tb/tb_nexys4.vhd +++ b/rtl/bplib/nexys4/tb/tb_nexys4.vhd @@ -1,4 +1,4 @@ --- $Id: tb_nexys4.vhd 643 2015-02-07 17:41:53Z mueller $ +-- $Id: tb_nexys4.vhd 666 2015-04-12 21:17:54Z mueller $ -- -- Copyright 2013-2015 by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- rlink/tb/tbcore_rlink -- xlib/s7_cmt_sfs -- tb_nexys4_core --- serport/serport_uart_rxtx +-- serport/serport_master -- nexys4_aif [UUT] -- -- To test: generic, any nexys4_aif target @@ -30,6 +30,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx -- 2015-02-06 643 1.2 factor out memory -- 2015-02-01 641 1.1 separate I_BTNRST_N -- 2013-09-28 535 1.0.1 use proper clock manager @@ -86,6 +87,10 @@ architecture sim of tb_nexys4 is signal O_ANO_N : slv8 := (others=>'0'); signal O_SEG_N : slv8 := (others=>'0'); + signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff + + constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); + constant clock_period : time := 10 ns; constant clock_offset : time := 200 ns; @@ -152,22 +157,26 @@ begin O_SEG_N => O_SEG_N ); - UART : serport_uart_rxtx + SERMSTR : serport_master generic map ( CDWIDTH => CLKDIV'length) port map ( - CLK => CLKCOM, - RESET => RESET, - CLKDIV => CLKDIV, - RXSD => O_TXD, - RXDATA => RXDATA, - RXVAL => RXVAL, - RXERR => RXERR, - RXACT => RXACT, - TXSD => I_RXD, - TXDATA => TXDATA, - TXENA => TXENA, - TXBUSY => TXBUSY + CLK => CLKCOM, + RESET => RESET, + CLKDIV => CLKDIV, + ENAXON => R_PORTSEL_XON, + ENAESC => '0', + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXOK => '1', + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + RXSD => O_TXD, + TXSD => I_RXD, + RXRTS_N => I_CTS_N, + TXCTS_N => O_RTS_N ); proc_moni: process @@ -186,4 +195,13 @@ begin end process proc_moni; + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_portsel then + R_PORTSEL_XON <= to_x01(SB_DATA(1)); + end if; + end if; + end process proc_simbus; + end sim; diff --git a/rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom b/rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom index 82437874..6ae0a3bd 100644 --- a/rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom +++ b/rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom @@ -19,7 +19,7 @@ ${sys_conf := sys_conf_sim.vhd} ../../../vlib/xlib/s7_cmt_sfs_gsim.vbom tb_nexys4_core.vbom ../../micron/mt45w8mw16b.vbom -../../../vlib/serport/serport_uart_rxtx.vbom +../../../vlib/serport/serport_master.vbom ${nexys4_cram_aif := nexys4_cram_dummy.vbom} # design tb_nexys4_cram.vhd diff --git a/rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd b/rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd index 303b53db..119c8884 100644 --- a/rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd +++ b/rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd @@ -1,4 +1,4 @@ --- $Id: tb_nexys4_cram.vhd 643 2015-02-07 17:41:53Z mueller $ +-- $Id: tb_nexys4_cram.vhd 666 2015-04-12 21:17:54Z mueller $ -- -- Copyright 2013-2015 by Walter F.J. Mueller -- @@ -20,7 +20,7 @@ -- rlink/tb/tbcore_rlink -- xlib/s7_cmt_sfs -- tb_nexys4_core --- serport/serport_uart_rxtx +-- serport/serport_master -- nexys4_cram_aif [UUT] -- vlib/parts/micron/mt45w8mw16b -- @@ -31,6 +31,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx -- 2015-02-01 641 1.1 separate I_BTNRST_N -- 2013-09-28 535 1.0.1 use proper clock manager -- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3) @@ -96,6 +97,10 @@ architecture sim of tb_nexys4_cram is signal O_MEM_ADDR : slv23 := (others=>'Z'); signal IO_MEM_DATA : slv16 := (others=>'0'); + signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff + + constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); + constant clock_period : time := 10 ns; constant clock_offset : time := 200 ns; @@ -187,22 +192,26 @@ begin DATA => IO_MEM_DATA ); - UART : serport_uart_rxtx + SERMSTR : serport_master generic map ( CDWIDTH => CLKDIV'length) port map ( - CLK => CLKCOM, - RESET => RESET, - CLKDIV => CLKDIV, - RXSD => O_TXD, - RXDATA => RXDATA, - RXVAL => RXVAL, - RXERR => RXERR, - RXACT => RXACT, - TXSD => I_RXD, - TXDATA => TXDATA, - TXENA => TXENA, - TXBUSY => TXBUSY + CLK => CLKCOM, + RESET => RESET, + CLKDIV => CLKDIV, + ENAXON => R_PORTSEL_XON, + ENAESC => '0', + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXOK => '1', + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + RXSD => O_TXD, + TXSD => I_RXD, + RXRTS_N => I_CTS_N, + TXCTS_N => O_RTS_N ); proc_moni: process diff --git a/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom b/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom index 36784c8e..c2b2230d 100644 --- a/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom +++ b/rtl/bplib/s3board/tb/tb_s3board_fusp.vbom @@ -15,7 +15,7 @@ ../../../vlib/simlib/simclkcnt.vbom ../../../vlib/rlink/tb/tbcore_rlink.vbom tb_s3board_core.vbom -../../../vlib/serport/serport_uart_rxtx.vbom +../../../vlib/serport/serport_master.vbom ${s3board_fusp_aif := s3board_fusp_dummy.vbom} # design tb_s3board_fusp.vhd diff --git a/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd b/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd index a0975a81..8740d9dd 100644 --- a/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd +++ b/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd @@ -1,6 +1,6 @@ --- $Id: tb_s3board_fusp.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: tb_s3board_fusp.vhd 666 2015-04-12 21:17:54Z mueller $ -- --- Copyright 2010-2011 by Walter F.J. Mueller +-- Copyright 2010-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,7 +20,7 @@ -- rlink/tb/tbcore_rlink -- tb_s3board_core -- s3board_fusp_aif [UUT] --- serport/serport_uart_rxtx +-- serport/serport_master -- -- To test: generic, any s3board_fusp_aif target -- @@ -28,6 +28,7 @@ -- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx -- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface -- 2011-11-19 427 3.0.1 now numeric_std clean -- 2010-12-30 351 3.0 use rlink/tb now @@ -100,7 +101,8 @@ architecture sim of tb_s3board_fusp is signal CTS_N : slbit := '0'; signal RTS_N : slbit := '0'; - signal R_PORTSEL : slbit := '0'; + signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport + signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); @@ -167,29 +169,33 @@ begin O_FUSP_TXD => O_FUSP_TXD ); - UART : serport_uart_rxtx + SERMSTR : serport_master generic map ( CDWIDTH => CLKDIV'length) port map ( - CLK => CLK, - RESET => UART_RESET, - CLKDIV => CLKDIV, - RXSD => UART_RXD, - RXDATA => RXDATA, - RXVAL => RXVAL, - RXERR => RXERR, - RXACT => RXACT, - TXSD => UART_TXD, - TXDATA => TXDATA, - TXENA => TXENA, - TXBUSY => TXBUSY + CLK => CLK, + RESET => UART_RESET, + CLKDIV => CLKDIV, + ENAXON => R_PORTSEL_XON, + ENAESC => '0', + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXOK => '1', + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + RXSD => UART_RXD, + TXSD => UART_TXD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N ); - proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N, + proc_port_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N, O_TXD, O_FUSP_TXD, O_FUSP_RTS_N) begin - if R_PORTSEL = '0' then -- use main board rs232, no flow cntl + if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl I_RXD <= UART_TXD; -- write port 0 inputs UART_RXD <= O_TXD; -- get port 0 outputs RTS_N <= '0'; @@ -225,7 +231,8 @@ begin begin if SB_VAL'event and to_x01(SB_VAL)='1' then if SB_ADDR = sbaddr_portsel then - R_PORTSEL <= to_x01(SB_DATA(0)); + R_PORTSEL_SER <= to_x01(SB_DATA(0)); + R_PORTSEL_XON <= to_x01(SB_DATA(1)); end if; end if; end process proc_simbus; diff --git a/rtl/ibus/ibd_ibmon.vbom b/rtl/ibus/ibd_ibmon.vbom new file mode 100644 index 00000000..28957c68 --- /dev/null +++ b/rtl/ibus/ibd_ibmon.vbom @@ -0,0 +1,9 @@ +# libs +../vlib/slvtypes.vhd +../vlib/memlib/memlib.vhd +iblib.vhd +# components +[sim]../vlib/memlib/ram_1swsr_wfirst_gen.vbom +[xst,vsyn]../vlib/memlib/ram_1swsr_wfirst_gen_unisim.vbom +# design +ibd_ibmon.vhd diff --git a/rtl/ibus/ibd_ibmon.vhd b/rtl/ibus/ibd_ibmon.vhd new file mode 100644 index 00000000..477709b2 --- /dev/null +++ b/rtl/ibus/ibd_ibmon.vhd @@ -0,0 +1,486 @@ +-- $Id: ibd_ibmon.vhd 672 2015-05-02 21:58:28Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: ibd_ibmon - syn +-- Description: ibus dev: ibus monitor +-- +-- Dependencies: memlib/ram_1swsr_wfirst_gen +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 14.7; viv 2014.4; ghdl 0.31 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2015-04-24 668 14.7 131013 xc6slx16-2 112 235 0 83 s 5.6 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-05-02 672 1.0.1 use natural for AWIDTH to work around a ghdl issue +-- 2015-04-24 668 1.0 Initial version (derived from rbd_rbmon) +------------------------------------------------------------------------------ +-- +-- Addr Bits Name r/w/f Function +-- 000 cntl r/w/f Control register +-- 05 conena r/w/- con enable +-- 04 remena r/w/- rem enable +-- 03 locena r/w/- loc enable +-- 02 wena r/w/- wrap enable +-- 01 stop r/w/f writing 1 stops moni +-- 00 start r/w/f writing 1 starts moni and clears addr +-- 001 stat r/w/- Status register +-- 15:13 bsize r/-/- buffer size (AWIDTH-9) +-- 00 wrap r/-/- line address wrapped (cleared on go) +-- 010 12:01 hilim r/w/- upper address limit, inclusive (def: 177776) +-- 011 12:01 lolim r/w/- lower address limit, inclusive (def: 160000) +-- 100 addr r/w/- Address register +-- *:02 laddr r/w/- line address +-- 01:00 waddr r/w/- word address +-- 101 data r/w/- Data register +-- +-- data format: +-- word 3 15 : burst (2nd re/we in a aval sequence) +-- 14 : tout (busy in last re-we cycle) +-- 13 : nak (no ack in last non-busy cycle) +-- 12 : ack (ack seen) +-- 11 : busy (busy seen) +-- 10 : -- (reserved in case err is implemented) +-- 09 : we (write cycle) +-- 08 : rmw (read-modify-write) +-- 07:00 : delay to prev (msb's) +-- word 2 15:10 : delay to prev (lsb's) +-- 09:00 : number of busy cycles +-- word 1 : data +-- word 0 15 : be1 (byte enable low) +-- 14 : be0 (byte enable high) +-- 13 : racc (remote access) +-- 12:01 : addr (word address) +-- 0 : cacc (console access) +-- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.memlib.all; +use work.iblib.all; + +-- Note: AWIDTH has type natural to allow AWIDTH=0 can be used in if generates +-- to control the instantiation. ghdl checks even for not instantiated +-- entities the validity of generics, that's why natural needed here .... + +entity ibd_ibmon is -- ibus dev: ibus monitor + generic ( + IB_ADDR : slv16 := slv(to_unsigned(8#160000#,16)); -- base address + AWIDTH : natural := 9); -- buffer size + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + IB_MREQ : in ib_mreq_type; -- ibus: request + IB_SRES : out ib_sres_type; -- ibus: response + IB_SRES_SUM : in ib_sres_type -- ibus: response (sum for monitor) + ); +end entity ibd_ibmon; + + +architecture syn of ibd_ibmon is + + constant ibaddr_cntl : slv3 := "000"; -- cntl address offset + constant ibaddr_stat : slv3 := "001"; -- stat address offset + constant ibaddr_hilim : slv3 := "010"; -- hilim address offset + constant ibaddr_lolim : slv3 := "011"; -- lolim address offset + constant ibaddr_addr : slv3 := "100"; -- addr address offset + constant ibaddr_data : slv3 := "101"; -- data address offset + + constant cntl_ibf_conena : integer := 5; + constant cntl_ibf_remena : integer := 4; + constant cntl_ibf_locena : integer := 3; + constant cntl_ibf_wena : integer := 2; + constant cntl_ibf_stop : integer := 1; + constant cntl_ibf_start : integer := 0; + subtype stat_ibf_bsize is integer range 15 downto 13; + constant stat_ibf_wrap : integer := 0; + subtype addr_ibf_laddr is integer range 2+AWIDTH-1 downto 2; + subtype addr_ibf_waddr is integer range 1 downto 0; + + subtype iba_ibf_pref is integer range 15 downto 13; + subtype iba_ibf_addr is integer range 12 downto 1; + + constant dat3_ibf_burst : integer := 15; + constant dat3_ibf_tout : integer := 14; + constant dat3_ibf_nak : integer := 13; + constant dat3_ibf_ack : integer := 12; + constant dat3_ibf_busy : integer := 11; + constant dat3_ibf_we : integer := 9; + constant dat3_ibf_rmw : integer := 8; + subtype dat3_ibf_ndlymsb is integer range 7 downto 0; + subtype dat2_ibf_ndlylsb is integer range 15 downto 10; + subtype dat2_ibf_nbusy is integer range 9 downto 0; + constant dat0_ibf_be1 : integer := 15; + constant dat0_ibf_be0 : integer := 14; + constant dat0_ibf_racc : integer := 13; + subtype dat0_ibf_addr is integer range 12 downto 1; + constant dat0_ibf_cacc : integer := 0; + + type regs_type is record -- state registers + ibsel : slbit; -- ibus select + conena : slbit; -- conena flag (record console access) + remena : slbit; -- remena flag (record remote access) + locena : slbit; -- locena flag (record local access) + wena : slbit; -- wena flag (wrap enable) + go : slbit; -- go flag + hilim : slv13_1; -- upper address limit + lolim : slv13_1; -- lower address limit + wrap : slbit; -- laddr wrap flag + laddr : slv(AWIDTH-1 downto 0); -- line address + waddr : slv2; -- word address + ibtake_1 : slbit; -- ib capture active in last cycle + ibaddr : slv13_1; -- ibus trace: addr + ibwe : slbit; -- ibus trace: we + ibrmw : slbit; -- ibus trace: rmw + ibbe0 : slbit; -- ibus trace: be0 + ibbe1 : slbit; -- ibus trace: be1 + ibcacc : slbit; -- ibus trace: cacc + ibracc : slbit; -- ibus trace: racc + iback : slbit; -- ibus trace: ack seen + ibbusy : slbit; -- ibus trace: busy seen + ibnak : slbit; -- ibus trace: nak detected + ibtout : slbit; -- ibus trace: tout detected + ibburst : slbit; -- ibus trace: burst detected + ibdata : slv16; -- ibus trace: data + ibnbusy : slv10; -- ibus number of busy cycles + ibndly : slv14; -- ibus delay to prev. access + end record regs_type; + + constant laddrzero : slv(AWIDTH-1 downto 0) := (others=>'0'); + constant laddrlast : slv(AWIDTH-1 downto 0) := (others=>'1'); + + constant regs_init : regs_type := ( + '0', -- ibsel + '1','1','1','1','1', -- conena,remena,locena,wena,go + (others=>'1'), -- hilim (def: 177776) + (others=>'0'), -- lolim (def: 160000) + '0', -- wrap + laddrzero, -- laddr + "00", -- waddr + '0', -- ibtake_1 + (others=>'0'), -- ibaddr + '0','0','0','0','0','0', -- ibwe,ibrmw,ibbe0,ibbe1,ibcacc,ibracc + '0','0', -- iback,ibbusy + '0','0','0', -- ibnak,ibtout,ibburst + (others=>'0'), -- ibdata + (others=>'0'), -- ibnbusy + (others=>'0') -- ibndly + ); + + constant ibnbusylast : slv10 := (others=>'1'); + constant ibndlylast : slv14 := (others=>'1'); + + signal R_REGS : regs_type := regs_init; + signal N_REGS : regs_type := regs_init; + + signal BRAM_EN : slbit := '0'; + signal BRAM_WE : slbit := '0'; + signal BRAM0_DI : slv32 := (others=>'0'); + signal BRAM1_DI : slv32 := (others=>'0'); + signal BRAM0_DO : slv32 := (others=>'0'); + signal BRAM1_DO : slv32 := (others=>'0'); + +begin + + assert AWIDTH>=9 and AWIDTH<=14 + report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported AWIDTH" + severity failure; + + BRAM1 : ram_1swsr_wfirst_gen + generic map ( + AWIDTH => AWIDTH, + DWIDTH => 32) + port map ( + CLK => CLK, + EN => BRAM_EN, + WE => BRAM_WE, + ADDR => R_REGS.laddr, + DI => BRAM1_DI, + DO => BRAM1_DO + ); + + BRAM0 : ram_1swsr_wfirst_gen + generic map ( + AWIDTH => AWIDTH, + DWIDTH => 32) + port map ( + CLK => CLK, + EN => BRAM_EN, + WE => BRAM_WE, + ADDR => R_REGS.laddr, + DI => BRAM0_DI, + DO => BRAM0_DO + ); + + proc_regs: process (CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + end process proc_regs; + + proc_next : process (R_REGS, IB_MREQ, IB_SRES_SUM, BRAM0_DO, BRAM1_DO) + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + variable iib_ack : slbit := '0'; + variable iib_busy : slbit := '0'; + variable iib_dout : slv16 := (others=>'0'); + variable iibena : slbit := '0'; + variable ibramen : slbit := '0'; -- BRAM enable + variable ibramwe : slbit := '0'; -- BRAN we + variable ibtake : slbit := '0'; + variable laddr_inc : slbit := '0'; + variable idat0 : slv16 := (others=>'0'); + variable idat1 : slv16 := (others=>'0'); + variable idat2 : slv16 := (others=>'0'); + variable idat3 : slv16 := (others=>'0'); + begin + + r := R_REGS; + n := R_REGS; + + iib_ack := '0'; + iib_busy := '0'; + iib_dout := (others=>'0'); + + iibena := IB_MREQ.re or IB_MREQ.we; + + ibramen := '0'; + ibramwe := '0'; + + laddr_inc := '0'; + + -- ibus address decoder + n.ibsel := '0'; + if IB_MREQ.aval='1' and IB_MREQ.addr(12 downto 4)=IB_ADDR(12 downto 4) then + n.ibsel := '1'; + ibramen := '1'; + end if; + + -- ibus transactions (react only on console (this includes racc)) + if r.ibsel = '1' and IB_MREQ.cacc='1' then + + iib_ack := iibena; -- ack all accesses + + case IB_MREQ.addr(3 downto 1) is + + when ibaddr_cntl => -- cntl ------------------ + if IB_MREQ.we = '1' then + n.conena := IB_MREQ.din(cntl_ibf_conena); + n.remena := IB_MREQ.din(cntl_ibf_remena); + n.locena := IB_MREQ.din(cntl_ibf_locena); + n.wena := IB_MREQ.din(cntl_ibf_wena); + if IB_MREQ.din(cntl_ibf_start) = '1' then + n.go := '1'; + n.wrap := '0'; + n.laddr := laddrzero; + n.waddr := "00"; + end if; + if IB_MREQ.din(cntl_ibf_stop) = '1' then + n.go := '0'; + end if; + end if; + + when ibaddr_stat => null; -- stat ------------------ + + when ibaddr_hilim => -- hilim ----------------- + if IB_MREQ.we = '1' then + n.hilim := IB_MREQ.din(iba_ibf_addr); + end if; + + when ibaddr_lolim => -- lolim ----------------- + if IB_MREQ.we = '1' then + n.lolim := IB_MREQ.din(iba_ibf_addr); + end if; + + when ibaddr_addr => -- addr ------------------ + if IB_MREQ.we = '1' then + n.go := '0'; + n.wrap := '0'; + n.laddr := IB_MREQ.din(addr_ibf_laddr); + n.waddr := IB_MREQ.din(addr_ibf_waddr); + end if; + + when ibaddr_data => -- data ------------------ + if r.go='1' or IB_MREQ.we='1' then + iib_ack := '0'; -- error, do nak + end if; + if IB_MREQ.re = '1' then + n.waddr := slv(unsigned(r.waddr) + 1); + if r.waddr = "11" then + laddr_inc := '1'; + end if; + end if; + + when others => -- <> -------------------- + iib_ack := '0'; -- error, do nak + + end case; + end if; + + -- ibus output driver + if r.ibsel = '1' then + case IB_MREQ.addr(3 downto 1) is + when ibaddr_cntl => -- cntl ------------------ + iib_dout(cntl_ibf_conena) := r.conena; + iib_dout(cntl_ibf_remena) := r.remena; + iib_dout(cntl_ibf_locena) := r.locena; + iib_dout(cntl_ibf_wena) := r.wena; + iib_dout(cntl_ibf_start) := r.go; + when ibaddr_stat => -- stat ------------------ + iib_dout(stat_ibf_bsize) := slv(to_unsigned(AWIDTH-9,3)); + iib_dout(stat_ibf_wrap) := r.wrap; + when ibaddr_hilim => -- hilim ----------------- + iib_dout(iba_ibf_pref) := (others=>'1'); + iib_dout(iba_ibf_addr) := r.hilim; + when ibaddr_lolim => -- lolim ----------------- + iib_dout(iba_ibf_pref) := (others=>'1'); + iib_dout(iba_ibf_addr) := r.lolim; + when ibaddr_addr => -- addr ------------------ + iib_dout(addr_ibf_laddr) := r.laddr; + iib_dout(addr_ibf_waddr) := r.waddr; + when ibaddr_data => -- data ------------------ + case r.waddr is + when "11" => iib_dout := BRAM1_DO(31 downto 16); + when "10" => iib_dout := BRAM1_DO(15 downto 0); + when "01" => iib_dout := BRAM0_DO(31 downto 16); + when "00" => iib_dout := BRAM0_DO(15 downto 0); + when others => null; + end case; + when others => null; + end case; + end if; + + -- ibus monitor + -- a ibus transaction are captured if the address is in alim window + -- and the access is not refering to ibd_ibmon itself + + ibtake := '0'; + if IB_MREQ.aval='1' and iibena='1' then -- aval and (re or we) + if unsigned(IB_MREQ.addr)>=unsigned(r.lolim) and -- and in addr window + unsigned(IB_MREQ.addr)<=unsigned(r.hilim) and + r.ibsel='0' then -- and not self + if (r.locena='1' and IB_MREQ.cacc='0' and IB_MREQ.racc='0') or + (r.remena='1' and IB_MREQ.racc='1') or + (r.conena='1' and IB_MREQ.cacc='1') then + ibtake := '1'; + end if; + end if; + end if; + + if ibtake = '1' then -- if capture active + n.ibaddr := IB_MREQ.addr; -- keep track of some state + n.ibwe := IB_MREQ.we; + n.ibrmw := IB_MREQ.rmw; + n.ibbe0 := IB_MREQ.be0; + n.ibbe1 := IB_MREQ.be1; + n.ibcacc := IB_MREQ.cacc; + n.ibracc := IB_MREQ.racc; + if IB_MREQ.we='1' then -- for write of din + n.ibdata := IB_MREQ.din; + else -- for read of dout + n.ibdata := IB_SRES_SUM.dout; + end if; + + if r.ibtake_1 = '0' then -- if initial cycle of a transaction + n.iback := IB_SRES_SUM.ack; + n.ibbusy := IB_SRES_SUM.busy; + n.ibnbusy := (others=>'0'); + else -- if non-initial cycles + if r.ibnbusy /= ibnbusylast then -- and count + n.ibnbusy := slv(unsigned(r.ibnbusy) + 1); + end if; + end if; + n.ibnak := not IB_SRES_SUM.ack; + n.ibtout := IB_SRES_SUM.busy; + + else -- if capture not active + if r.go='1' and r.ibtake_1='1' then -- active and transaction just ended + ibramen := '1'; + ibramwe := '1'; + laddr_inc := '1'; + n.ibburst := '1'; -- assume burst + end if; + if r.ibtake_1 = '1' then -- ibus transaction just ended + n.ibndly := (others=>'0'); -- clear delay counter + else -- just idle + if r.ibndly /= ibndlylast then -- count cycles + n.ibndly := slv(unsigned(r.ibndly) + 1); + end if; + end if; + end if; + + if IB_MREQ.aval = '0' then -- if aval gone + n.ibburst := '0'; -- clear burst flag + end if; + + if laddr_inc = '1' then + n.laddr := slv(unsigned(r.laddr) + 1); + if r.go='1' and r.laddr=laddrlast then + if r.wena = '1' then + n.wrap := '1'; + else + n.go := '0'; + end if; + end if; + end if; + + idat3 := (others=>'0'); + idat3(dat3_ibf_burst) := r.ibburst; + idat3(dat3_ibf_tout) := r.ibtout; + idat3(dat3_ibf_nak) := r.ibnak; + idat3(dat3_ibf_ack) := r.iback; + idat3(dat3_ibf_busy) := r.ibbusy; + idat3(dat3_ibf_we) := r.ibwe; + idat3(dat3_ibf_rmw) := r.ibrmw; + idat3(dat3_ibf_ndlymsb):= r.ibndly(13 downto 6); + idat2(dat2_ibf_ndlylsb):= r.ibndly( 5 downto 0); + idat2(dat2_ibf_nbusy) := r.ibnbusy; + idat1 := r.ibdata; + idat0(dat0_ibf_be1) := r.ibbe1; + idat0(dat0_ibf_be0) := r.ibbe0; + idat0(dat0_ibf_racc) := r.ibracc; + idat0(dat0_ibf_addr) := r.ibaddr; + idat0(dat0_ibf_cacc) := r.ibcacc; + + n.ibtake_1 := ibtake; + + N_REGS <= n; + + BRAM_EN <= ibramen; + BRAM_WE <= ibramwe; + + BRAM1_DI <= idat3 & idat2; + BRAM0_DI <= idat1 & idat0; + + IB_SRES.dout <= iib_dout; + IB_SRES.ack <= iib_ack; + IB_SRES.busy <= iib_busy; + + end process proc_next; + +end syn; diff --git a/rtl/ibus/ibd_kw11l.vhd b/rtl/ibus/ibd_kw11l.vhd index f75dc14b..69f5052b 100644 --- a/rtl/ibus/ibd_kw11l.vhd +++ b/rtl/ibus/ibd_kw11l.vhd @@ -1,6 +1,6 @@ --- $Id: ibd_kw11l.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: ibd_kw11l.vhd 676 2015-05-09 16:31:54Z mueller $ -- --- Copyright 2008-2011 by Walter F.J. Mueller +-- Copyright 2008-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -27,6 +27,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-05-09 676 1.2 add CPUSUSP, freeze timer when cpu suspended -- 2011-11-18 427 1.1.1 now numeric_std clean -- 2010-10-17 333 1.1 use ibus V2 interface -- 2009-06-01 221 1.0.5 BUGFIX: add RESET; don't clear tcnt on ibus reset @@ -52,6 +53,7 @@ entity ibd_kw11l is -- ibus dev(loc): KW11-L (line clock) CE_MSEC : in slbit; -- msec pulse RESET : in slbit; -- system reset BRESET : in slbit; -- ibus reset + CPUSUSP : in slbit; -- cpu suspended IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type; -- ibus response EI_REQ : out slbit; -- interrupt request @@ -104,7 +106,7 @@ begin end if; end process proc_regs; - proc_next : process (R_REGS, IB_MREQ, CE_MSEC, EI_ACK) + proc_next : process (R_REGS, IB_MREQ, CE_MSEC, CPUSUSP, EI_ACK) variable r : regs_type := regs_init; variable n : regs_type := regs_init; variable idout : slv16 := (others=>'0'); @@ -142,7 +144,7 @@ begin end if; -- other state changes - if CE_MSEC = '1' then + if CE_MSEC='1' and CPUSUSP='0' then -- on msec and not suspended n.tcnt := slv(unsigned(r.tcnt) + 1); if unsigned(r.tcnt) = tdivide-1 then n.tcnt := (others=>'0'); diff --git a/rtl/ibus/ibdlib.vhd b/rtl/ibus/ibdlib.vhd index f318cf9e..374bc65b 100644 --- a/rtl/ibus/ibdlib.vhd +++ b/rtl/ibus/ibdlib.vhd @@ -1,4 +1,4 @@ --- $Id: ibdlib.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: ibdlib.vhd 678 2015-05-10 16:23:02Z mueller $ -- -- Copyright 2008-2014 by Walter F.J. Mueller -- @@ -19,6 +19,8 @@ -- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-05-09 676 1.3 start/stop/suspend overhaul +-- 2015-03-13 658 1.2.1 add rprm declaration (later renaned to rhrp) -- 2014-06-08 561 1.2 fix rl11 declaration -- 2011-11-18 427 1.1.2 now numeric_std clean -- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM; @@ -95,7 +97,7 @@ component ibd_iist is -- ibus dev(loc): IIST ); end component; -component ibd_kw11p is -- ibus dev(loc): KW11-P (line clock) +component ibd_kw11p is -- ibus dev(loc): KW11-P (prog clock) -- fixed address: 172540 port ( CLK : in slbit; -- clock @@ -103,6 +105,7 @@ component ibd_kw11p is -- ibus dev(loc): KW11-P (line clock) CE_MSEC : in slbit; -- msec pulse RESET : in slbit; -- system reset BRESET : in slbit; -- ibus reset + CPUSUSP : in slbit; -- cpu suspended IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type; -- ibus response EI_REQ : out slbit; -- interrupt request @@ -117,6 +120,22 @@ component ibd_kw11l is -- ibus dev(loc): KW11-L (line clock) CE_MSEC : in slbit; -- msec pulse RESET : in slbit; -- system reset BRESET : in slbit; -- ibus reset + CPUSUSP : in slbit; -- cpu suspended + IB_MREQ : in ib_mreq_type; -- ibus request + IB_SRES : out ib_sres_type; -- ibus response + EI_REQ : out slbit; -- interrupt request + EI_ACK : in slbit -- interrupt acknowledge + ); +end component; + +component ibdr_rhrp is -- ibus dev(rem): RH+RP + -- fixed address: 174400 + port ( + CLK : in slbit; -- clock + CE_USEC : in slbit; -- usec pulse + BRESET : in slbit; -- ibus reset + ITIMER : in slbit; -- instruction timer + RB_LAM : out slbit; -- remote attention IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type; -- ibus response EI_REQ : out slbit; -- interrupt request @@ -265,6 +284,8 @@ component ibdr_maxisys is -- ibus(rem) full system CE_MSEC : in slbit; -- msec pulse RESET : in slbit; -- reset BRESET : in slbit; -- ibus reset + ITIMER : in slbit; -- instruction timer + CPUSUSP : in slbit; -- cpu suspended RB_LAM : out slv16_1; -- remote attention vector IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type; -- ibus response diff --git a/rtl/ibus/ibdr_maxisys.vbom b/rtl/ibus/ibdr_maxisys.vbom index 0214cd32..4ade6eac 100644 --- a/rtl/ibus/ibdr_maxisys.vbom +++ b/rtl/ibus/ibdr_maxisys.vbom @@ -2,9 +2,11 @@ ../vlib/slvtypes.vhd iblib.vhd ibdlib.vhd +${sys_conf := sys_conf.vhd} # components ibd_iist.vbom ibd_kw11l.vbom +ibdr_rhrp.vbom ibdr_rl11.vbom ibdr_rk11.vbom ibdr_dl11.vbom diff --git a/rtl/ibus/ibdr_maxisys.vhd b/rtl/ibus/ibdr_maxisys.vhd index 605c57ac..11f1e916 100644 --- a/rtl/ibus/ibdr_maxisys.vhd +++ b/rtl/ibus/ibdr_maxisys.vhd @@ -1,4 +1,4 @@ --- $Id: ibdr_maxisys.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: ibdr_maxisys.vhd 679 2015-05-13 17:38:46Z mueller $ -- -- Copyright 2009-2015 by Walter F.J. Mueller -- @@ -17,6 +17,7 @@ -- -- Dependencies: ibd_iist -- ibd_kw11l +-- ibdr_rhrp -- ibdr_rl11 -- ibdr_rk11 -- ibdr_dl11 @@ -32,6 +33,7 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2015-04-06 664 14.7 131013 xc6slx16-2 559 1068 29 410 s 9.1 +RHRP -- 2015-01-04 630 14.7 131013 xc6slx16-2 388 761 20 265 s 8.0 +RL11 -- 2014-06-08 560 14.7 131013 xc6slx16-2 311 615 8 216 s 7.1 -- 2010-10-17 333 12.1 M53d xc3s1000-4 312 1058 16 617 s 10.3 @@ -39,9 +41,13 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-05-10 678 1.3 start/stop/suspend overhaul +-- 2015-04-06 664 1.2.3 rename RPRM to RHRP +-- 2015-03-14 658 1.2.2 add RPRM; rearrange intmap (+rhrp,tm11,-kw11-l) +-- use sys_conf, make most devices configurable -- 2015-01-04 630 1.2.1 RL11 back in -- 2014-06-27 565 1.2.1 temporarily hide RL11 --- 2014-06-08 561 1.2 add rl11 +-- 2014-06-08 561 1.2 add RL11 -- 2011-11-18 427 1.1.2 now numeric_std clean -- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM -- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ @@ -56,15 +62,15 @@ -- full system setup -- -- ibbase vec pri slot attn sror device name --- --- 172540 104 ?7 14 17 - 1/1 KW11-P --- 177500 260 6 13 16 - 1/2 IIST --- 177546 100 6 12 15 - 1/3 KW11-L +-- +-- 172540 104 ?7 17 - 1/1 KW11-P +-- 177500 260 6 15 16 - 1/2 IIST +-- 177546 100 6 14 15 - 1/3 KW11-L -- 174510 120 5 14 9 1/4 DEUNA --- 176700 254 5 13 6 2/1 RH70/RP06 --- 174400 160 5 11 12 5 2/2 RL11 --- 177400 220 5 10 11 4 2/3 RK11 --- 172520 224 5 10 7 2/4 TM11 +-- 176700 254 5 13 13 6 2/1 RHRP +-- 174400 160 5 12 12 5 2/2 RL11 +-- 177400 220 5 11 11 4 2/3 RK11 +-- 172520 224 5 10 10 7 2/4 TM11 -- 160100 310? 5 9 9 3 3/1 DZ11-RX -- 314? 5 8 8 ^ DZ11-TX -- 177560 060 4 7 7 1 3/2 DL11-RX 1st @@ -84,6 +90,7 @@ use ieee.numeric_std.all; use work.slvtypes.all; use work.iblib.all; use work.ibdlib.all; +use work.sys_conf.all; -- ---------------------------------------------------------------------------- entity ibdr_maxisys is -- ibus(rem) full system @@ -93,6 +100,8 @@ entity ibdr_maxisys is -- ibus(rem) full system CE_MSEC : in slbit; -- msec pulse RESET : in slbit; -- reset BRESET : in slbit; -- ibus reset + ITIMER : in slbit; -- instruction timer + CPUSUSP : in slbit; -- cpu suspended RB_LAM : out slv16_1; -- remote attention vector IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type; -- ibus response @@ -106,12 +115,12 @@ end ibdr_maxisys; architecture syn of ibdr_maxisys is constant conf_intmap : intmap_array_type := - (intmap_init, -- line 15 - (8#104#,6), -- line 14 KW11-P - (8#260#,6), -- line 13 IIST - (8#100#,6), -- line 12 KW11-L - (8#160#,5), -- line 11 RL11 - (8#220#,5), -- line 10 RK11 + ((8#260#,6), -- line 15 IIST + (8#100#,6), -- line 14 KW11-L + (8#254#,5), -- line 13 RHRP + (8#160#,5), -- line 12 RL11 + (8#220#,5), -- line 11 RK11 + (8#224#,5), -- line 10 TM11 (8#310#,5), -- line 9 DZ11-RX (8#314#,5), -- line 8 DZ11-TX (8#060#,4), -- line 7 DL11-RX 1st @@ -121,11 +130,11 @@ architecture syn of ibdr_maxisys is (8#070#,4), -- line 3 PC11-PTR (8#074#,4), -- line 2 PC11-PTP (8#200#,4), -- line 1 LP11 - intmap_init -- line 0 + intmap_init -- line 0 (must be unused!) ); signal RB_LAM_DENUA : slbit := '0'; - signal RB_LAM_RP06 : slbit := '0'; + signal RB_LAM_RHRP : slbit := '0'; signal RB_LAM_RL11 : slbit := '0'; signal RB_LAM_RK11 : slbit := '0'; signal RB_LAM_TM11 : slbit := '0'; @@ -139,7 +148,7 @@ architecture syn of ibdr_maxisys is signal IB_SRES_KW11P : ib_sres_type := ib_sres_init; signal IB_SRES_KW11L : ib_sres_type := ib_sres_init; signal IB_SRES_DEUNA : ib_sres_type := ib_sres_init; - signal IB_SRES_RP06 : ib_sres_type := ib_sres_init; + signal IB_SRES_RHRP : ib_sres_type := ib_sres_init; signal IB_SRES_RL11 : ib_sres_type := ib_sres_init; signal IB_SRES_RK11 : ib_sres_type := ib_sres_init; signal IB_SRES_TM11 : ib_sres_type := ib_sres_init; @@ -162,7 +171,7 @@ architecture syn of ibdr_maxisys is signal EI_REQ_KW11P : slbit := '0'; signal EI_REQ_KW11L : slbit := '0'; signal EI_REQ_DEUNA : slbit := '0'; - signal EI_REQ_RP06 : slbit := '0'; + signal EI_REQ_RHRP : slbit := '0'; signal EI_REQ_RL11 : slbit := '0'; signal EI_REQ_RK11 : slbit := '0'; signal EI_REQ_TM11 : slbit := '0'; @@ -180,7 +189,7 @@ architecture syn of ibdr_maxisys is signal EI_ACK_KW11P : slbit := '0'; signal EI_ACK_KW11L : slbit := '0'; signal EI_ACK_DEUNA : slbit := '0'; - signal EI_ACK_RP06 : slbit := '0'; + signal EI_ACK_RHRP : slbit := '0'; signal EI_ACK_RL11 : slbit := '0'; signal EI_ACK_RK11 : slbit := '0'; signal EI_ACK_TM11 : slbit := '0'; @@ -201,7 +210,7 @@ architecture syn of ibdr_maxisys is begin - IIST: if true generate + IIST: if sys_conf_ibd_iist generate begin I0 : ibd_iist port map ( @@ -232,13 +241,30 @@ begin CE_MSEC => CE_MSEC, RESET => RESET, BRESET => BRESET, + CPUSUSP => CPUSUSP, IB_MREQ => IB_MREQ, IB_SRES => IB_SRES_KW11L, EI_REQ => EI_REQ_KW11L, EI_ACK => EI_ACK_KW11L ); - RL11: if true generate + RHRP: if sys_conf_ibd_rhrp generate + begin + I0 : ibdr_rhrp + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + BRESET => BRESET, + ITIMER => ITIMER, + RB_LAM => RB_LAM_RHRP, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_RHRP, + EI_REQ => EI_REQ_RHRP, + EI_ACK => EI_ACK_RHRP + ); + end generate RHRP; + + RL11: if sys_conf_ibd_rl11 generate begin I0 : ibdr_rl11 port map ( @@ -253,7 +279,7 @@ begin ); end generate RL11; - RK11: if true generate + RK11: if sys_conf_ibd_rk11 generate begin I0 : ibdr_rk11 port map ( @@ -283,7 +309,7 @@ begin EI_ACK_TX => EI_ACK_DL11TX_0 ); - DL11_1: if true generate + DL11_1: if sys_conf_ibd_dl11_1 generate begin I0 : ibdr_dl11 generic map ( @@ -303,7 +329,7 @@ begin ); end generate DL11_1; - PC11: if true generate + PC11: if sys_conf_ibd_pc11 generate begin I0 : ibdr_pc11 port map ( @@ -320,7 +346,7 @@ begin ); end generate PC11; - LP11: if true generate + LP11: if sys_conf_ibd_lp11 generate begin I0 : ibdr_lp11 port map ( @@ -355,7 +381,7 @@ begin SRES_OR_2 : ib_sres_or_4 port map ( - IB_SRES_1 => IB_SRES_RP06, + IB_SRES_1 => IB_SRES_RHRP, IB_SRES_2 => IB_SRES_RL11, IB_SRES_3 => IB_SRES_RK11, IB_SRES_4 => IB_SRES_TM11, @@ -398,11 +424,12 @@ begin EI_VECT => EI_VECT ); - EI_REQ(14) <= EI_REQ_KW11P; - EI_REQ(13) <= EI_REQ_IIST; - EI_REQ(12) <= EI_REQ_KW11L; - EI_REQ(11) <= EI_REQ_RL11; - EI_REQ(10) <= EI_REQ_RK11; + EI_REQ(15) <= EI_REQ_IIST; + EI_REQ(14) <= EI_REQ_KW11L; + EI_REQ(13) <= EI_REQ_RHRP; + EI_REQ(12) <= EI_REQ_RL11; + EI_REQ(11) <= EI_REQ_RK11; + EI_REQ(10) <= EI_REQ_TM11; EI_REQ( 9) <= EI_REQ_DZ11RX; EI_REQ( 8) <= EI_REQ_DZ11TX; EI_REQ( 7) <= EI_REQ_DL11RX_0; @@ -413,11 +440,12 @@ begin EI_REQ( 2) <= EI_REQ_PC11PTP; EI_REQ( 1) <= EI_REQ_LP11; - EI_ACK_KW11P <= EI_ACK(14); - EI_ACK_IIST <= EI_ACK(13); - EI_ACK_KW11L <= EI_ACK(12); - EI_ACK_RL11 <= EI_ACK(11); - EI_ACK_RK11 <= EI_ACK(10); + EI_ACK_IIST <= EI_ACK(15); + EI_ACK_KW11L <= EI_ACK(14); + EI_ACK_RHRP <= EI_ACK(13); + EI_ACK_RL11 <= EI_ACK(12); + EI_ACK_RK11 <= EI_ACK(11); + EI_ACK_TM11 <= EI_ACK(10); EI_ACK_DZ11RX <= EI_ACK( 9); EI_ACK_DZ11TX <= EI_ACK( 8); EI_ACK_DL11RX_0 <= EI_ACK( 7); @@ -433,7 +461,7 @@ begin RB_LAM( 9) <= RB_LAM_DENUA; RB_LAM( 8) <= RB_LAM_LP11; RB_LAM( 7) <= RB_LAM_TM11; - RB_LAM( 6) <= RB_LAM_RP06; + RB_LAM( 6) <= RB_LAM_RHRP; RB_LAM( 5) <= RB_LAM_RL11; RB_LAM( 4) <= RB_LAM_RK11; RB_LAM( 3) <= RB_LAM_DZ11; diff --git a/rtl/ibus/ibdr_minisys.vhd b/rtl/ibus/ibdr_minisys.vhd index 7248c503..62c6fd13 100644 --- a/rtl/ibus/ibdr_minisys.vhd +++ b/rtl/ibus/ibdr_minisys.vhd @@ -1,4 +1,4 @@ --- $Id: ibdr_minisys.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: ibdr_minisys.vhd 676 2015-05-09 16:31:54Z mueller $ -- -- Copyright 2008-2011 by Walter F.J. Mueller -- @@ -142,6 +142,7 @@ begin CE_MSEC => CE_MSEC, RESET => RESET, BRESET => BRESET, + CPUSUSP => '0', IB_MREQ => IB_MREQ, IB_SRES => IB_SRES_KW11L, EI_REQ => EI_REQ_KW11L, diff --git a/rtl/ibus/ibdr_rhrp.vbom b/rtl/ibus/ibdr_rhrp.vbom new file mode 100644 index 00000000..84a968cb --- /dev/null +++ b/rtl/ibus/ibdr_rhrp.vbom @@ -0,0 +1,9 @@ +# libs +../vlib/slvtypes.vhd +../vlib/memlib/memlib.vhd +iblib.vhd +# components +[sim]../vlib/memlib/ram_1swar_gen.vbom +[xst,vsyn]../vlib/memlib/ram_1swar_gen_unisim.vbom +# design +ibdr_rhrp.vhd diff --git a/rtl/ibus/ibdr_rhrp.vhd b/rtl/ibus/ibdr_rhrp.vhd new file mode 100644 index 00000000..65932458 --- /dev/null +++ b/rtl/ibus/ibdr_rhrp.vhd @@ -0,0 +1,1436 @@ +-- $Id: ibdr_rhrp.vhd 680 2015-05-14 13:29:46Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: ibdr_rhrp - syn +-- Description: ibus dev(rem): RHRP +-- +-- Dependencies: ram_1swar_gen +-- Test bench: - +-- Target Devices: generic +-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2015-05-14 680 14.7 131013 xc6slx16-2 211 408 8 131 s 8.8 +-- 2015-04-06 664 14.7 131013 xc6slx16-2 177 331 8 112 s 8.7 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-05-14 680 1.0 Initial version +-- 2015-03-15 658 0.1 First draft +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.memlib.all; +use work.iblib.all; + +-- ---------------------------------------------------------------------------- +entity ibdr_rhrp is -- ibus dev(rem): RH+RP + -- fixed address: 176700 + port ( + CLK : in slbit; -- clock + CE_USEC : in slbit; -- usec pulse + BRESET : in slbit; -- ibus reset + ITIMER : in slbit; -- instruction timer + RB_LAM : out slbit; -- remote attention + IB_MREQ : in ib_mreq_type; -- ibus request + IB_SRES : out ib_sres_type; -- ibus response + EI_REQ : out slbit; -- interrupt request + EI_ACK : in slbit -- interrupt acknowledge + ); + + -- by default xst uses a binary encoding for the main fsm. + -- that give quite sub-optimal results, so force one-hot + attribute fsm_encoding : string; + attribute fsm_encoding of ibdr_rhrp : entity is "one-hot"; + +end entity ibdr_rhrp; + +architecture syn of ibdr_rhrp is + + constant ibaddr_rhrp : slv16 := slv(to_unsigned(8#176700#,16)); + + -- nam rw mb rp rm storage + constant ibaddr_cs1 : slv5 := "00000"; -- cs1 rw 0 rpcs1 rmcs1 m d,6+r + constant ibaddr_wc : slv5 := "00001"; -- wc rw - rpwc rmwc m 0,7 + constant ibaddr_ba : slv5 := "00010"; -- ba rw - rpba rmba m 1,7 + constant ibaddr_da : slv5 := "00011"; -- da rw 5 rpda rmda m d,0 + constant ibaddr_cs2 : slv5 := "00100"; -- cs2 rw - rpcs2 rmcs2 r cs2* + constant ibaddr_ds : slv5 := "00101"; -- ds r- 1 rpds rmds r ds* + constant ibaddr_er1 : slv5 := "00110"; -- er1 rw 2 rper1 rmer1 r er1* + constant ibaddr_as : slv5 := "00111"; -- as rw 4 rpas rmas r as* + constant ibaddr_la : slv5 := "01000"; -- la r- 7 rpla rmla r sc + constant ibaddr_db : slv5 := "01001"; -- db r? - rpdb rmdb m 2,7 + constant ibaddr_mr1 : slv5 := "01010"; -- mr1 rw 3 rpmr1 rmmr1 m d,3 + constant ibaddr_dt : slv5 := "01011"; -- dt r- 6 rpdt rmdt r dt*+map + constant ibaddr_sn : slv5 := "01100"; -- sn r- 10 rpsn rmsn + constant ibaddr_of : slv5 := "01101"; -- of rw 11 rpof rmof m d,1 + constant ibaddr_dc : slv5 := "01110"; -- dc rw 12 rpdc rmdc m d,2 + constant ibaddr_m13 : slv5 := "01111"; -- m13 rw 13 rpcc m =dc! + -- rw 13 rmhr m d,4 + constant ibaddr_m14 : slv5 := "10000"; -- m14 rw 14 rper2 =0 + -- rw 14 rmmr2 m d,5 + constant ibaddr_m15 : slv5 := "10001"; -- m15 rw 15 rper3 =0 + -- rw 15 rmer2 =0 + constant ibaddr_ec1 : slv5 := "10010"; -- ec1 r- 16 rpec1 rmec1 =0 + constant ibaddr_ec2 : slv5 := "10011"; -- ec1 r- 17 rpec2 rmec2 =0 + constant ibaddr_bae : slv5 := "10100"; -- bae rw - rpbae rmbae r bae + constant ibaddr_cs3 : slv5 := "10101"; -- cs3 rw - rpcs3 rmcs3 r cs3* + + constant omux_cs1 : slv4 := "0000"; + constant omux_cs2 : slv4 := "0001"; + constant omux_ds : slv4 := "0010"; + constant omux_er1 : slv4 := "0011"; + constant omux_as : slv4 := "0100"; + constant omux_la : slv4 := "0101"; + constant omux_dt : slv4 := "0110"; + constant omux_sn : slv4 := "0111"; + constant omux_bae : slv4 := "1000"; + constant omux_cs3 : slv4 := "1001"; + constant omux_mem : slv4 := "1010"; + constant omux_zero : slv4 := "1111"; + + constant amapc_da : slv3 := "000"; + constant amapc_mr1 : slv3 := "011"; + constant amapc_of : slv3 := "001"; + constant amapc_dc : slv3 := "010"; + constant amapc_hr : slv3 := "100"; + constant amapc_mr2 : slv3 := "101"; + constant amapc_cs1 : slv3 := "110"; + constant amapc_ext : slv3 := "111"; + + constant amapr_wc : slv2 := "00"; + constant amapr_ba : slv2 := "01"; + constant amapr_db : slv2 := "10"; + + subtype amap_f_unit is integer range 4 downto 3; -- unit part + subtype amap_f_reg is integer range 2 downto 0; -- reg part + + constant clrmode_breset : slv2 := "00"; + constant clrmode_cs2clr : slv2 := "01"; + constant clrmode_fdclr : slv2 := "10"; + constant clrmode_fpres : slv2 := "11"; + + constant cs1_ibf_sc : integer := 15; -- special condition + constant cs1_ibf_tre : integer := 14; -- transfer error + constant cs1_ibf_dva : integer := 11; -- drive available + subtype cs1_ibf_bae is integer range 9 downto 8; -- bus addr ext (1:0) + constant cs1_ibf_rdy : integer := 7; -- controller ready + constant cs1_ibf_ie : integer := 6; -- interrupt enable + subtype cs1_ibf_func is integer range 5 downto 1; -- function code + constant cs1_ibf_go : integer := 0; -- interrupt enable + + constant func_noop : slv5 := "00000"; -- func: noop + constant func_unl : slv5 := "00001"; -- func: unload + constant func_seek : slv5 := "00010"; -- func: seek + constant func_recal : slv5 := "00011"; -- func: recalibrate + constant func_dclr : slv5 := "00100"; -- func: drive clear + constant func_pore : slv5 := "00101"; -- func: port release + constant func_offs : slv5 := "00110"; -- func: offset + constant func_retc : slv5 := "00111"; -- func: return to center + constant func_pres : slv5 := "01000"; -- func: readin preset + constant func_pack : slv5 := "01001"; -- func: pack acknowledge + constant func_sear : slv5 := "01100"; -- func: search + constant func_wcd : slv5 := "10100"; -- func: write check data + constant func_wchd : slv5 := "10101"; -- func: write check header&data + constant func_write : slv5 := "11000"; -- func: write + constant func_whd : slv5 := "11001"; -- func: write header&data + constant func_read : slv5 := "11100"; -- func: read + constant func_rhd : slv5 := "11101"; -- func: read header&data + + constant rfunc_wunit : slv5 := "00001"; -- rem func: write runit + constant rfunc_cunit : slv5 := "00010"; -- rem func: copy funit->runit + constant rfunc_done : slv5 := "00011"; -- rem func: done (set rdy) + constant rfunc_widly : slv5 := "00100"; -- rem func: write idly + + -- cs1 usage for rem functions + subtype cs1_ibf_runit is integer range 9 downto 8; -- new runit (_wunit) + constant cs1_ibf_rata : integer := 8; -- use ata (_done) + subtype cs1_ibf_ridly is integer range 15 downto 8; -- new idly (_widly) + + subtype da_ibf_ta is integer range 12 downto 8; -- track addr + subtype da_ibf_sa is integer range 5 downto 0; -- sector addr + + constant cs2_ibf_rwco : integer := 15; -- rem: write check odd word + constant cs2_ibf_wce : integer := 14; -- write check error + constant cs2_ibf_ned : integer := 12; -- non-existant drive + constant cs2_ibf_nem : integer := 11; -- non-existant memory + constant cs2_ibf_pge : integer := 10; -- programming error + constant cs2_ibf_mxf : integer := 9; -- missed transfer + constant cs2_ibf_or : integer := 7; -- output ready + constant cs2_ibf_ir : integer := 6; -- input ready + constant cs2_ibf_clr : integer := 5; -- clear controller + constant cs2_ibf_pat : integer := 4; -- parity test + constant cs2_ibf_bai : integer := 3; -- bus address inhibit + constant cs2_ibf_unit2 : integer := 2; -- unit select msb + subtype cs2_ibf_unit is integer range 1 downto 0; -- unit select + + constant ds_ibf_ata : integer := 15; -- attention + constant ds_ibf_erp : integer := 14; -- any errors in er1 or er2 + constant ds_ibf_pip : integer := 13; -- positioning in progress + constant ds_ibf_mol : integer := 12; -- medium online (ATTACHED) + constant ds_ibf_wrl : integer := 11; -- write locked + constant ds_ibf_lbt : integer := 10; -- last block transfered + constant ds_ibf_dpr : integer := 8; -- drive present (ENABLED) + constant ds_ibf_dry : integer := 7; -- drive ready + constant ds_ibf_vv : integer := 6; -- volume valid + constant ds_ibf_om : integer := 0; -- offset mode + + constant er1_ibf_uns : integer := 14; -- drive unsafe + constant er1_ibf_wle : integer := 11; -- write lock error + constant er1_ibf_iae : integer := 10; -- invalid address error + constant er1_ibf_aoe : integer := 9; -- address overflow error + constant er1_ibf_rmr : integer := 2; -- register modification refused + constant er1_ibf_ilf : integer := 0; -- illegal function + + subtype la_ibf_sc is integer range 11 downto 6; -- current sector + + constant dt_ibf_rm : integer := 2; -- rm cntl + constant dt_ibf_e1 : integer := 1; -- encoded type bit 1 + constant dt_ibf_e0 : integer := 0; -- encoded type bit 0 + + constant dte_rp04 : slv3 := "000"; -- encoded dt for rp04 rm=0 + constant dte_rp06 : slv3 := "001"; -- encoded dt for rp06 rm=0 + constant dte_rm03 : slv3 := "100"; -- encoded dt for rm03 rm=1 + constant dte_rm80 : slv3 := "101"; -- encoded dt for rm80 rm=1 + constant dte_rm05 : slv3 := "110"; -- encoded dt for rm05 rm=1 + constant dte_rp07 : slv3 := "111"; -- encoded dt for rp07 rm=1 + + subtype dc_ibf_ca is integer range 9 downto 0; -- cyclinder addr + + subtype bae_ibf_bae is integer range 5 downto 0; -- bus addr ext. + + constant cs3_ibf_wco : integer := 12; -- write check odd + constant cs3_ibf_wce : integer := 11; -- write check even + constant cs3_ibf_ie : integer := 6; -- interrupt enable + constant cs3_ibf_rseardone : integer := 3; -- rem: sear done flag + constant cs3_ibf_rpackdone : integer := 2; -- rem: pack done flag + constant cs3_ibf_rporedone : integer := 1; -- rem: pore done flag + constant cs3_ibf_rseekdone : integer := 0; -- rem: seek done flag + + -- RP controller type disks + constant rp04_dtyp : slv6 := slv(to_unsigned( 8#20#, 6)); + constant rp04_camax : slv10 := slv(to_unsigned( 411-1, 10)); + constant rp04_tamax : slv5 := slv(to_unsigned( 19-1, 5)); + constant rp04_samax : slv6 := slv(to_unsigned( 22-1, 6)); + + constant rp06_dtyp : slv6 := slv(to_unsigned( 8#22#, 6)); + constant rp06_camax : slv10 := slv(to_unsigned( 815-1, 10)); + constant rp06_tamax : slv5 := slv(to_unsigned( 19-1, 5)); + constant rp06_samax : slv6 := slv(to_unsigned( 22-1, 6)); + + -- RM controller type disks (Note: rp07 has a RM stype controller!) + constant rm03_dtyp : slv6 := slv(to_unsigned( 8#24#, 6)); + constant rm03_camax : slv10 := slv(to_unsigned( 823-1, 10)); + constant rm03_tamax : slv5 := slv(to_unsigned( 5-1, 5)); + constant rm03_samax : slv6 := slv(to_unsigned( 32-1, 6)); + + constant rm80_dtyp : slv6 := slv(to_unsigned( 8#26#, 6)); + constant rm80_camax : slv10 := slv(to_unsigned( 559-1, 10)); + constant rm80_tamax : slv5 := slv(to_unsigned( 14-1, 5)); + constant rm80_samax : slv6 := slv(to_unsigned( 31-1, 6)); + + constant rm05_dtyp : slv6 := slv(to_unsigned( 8#27#, 6)); + constant rm05_camax : slv10 := slv(to_unsigned( 823-1, 10)); + constant rm05_tamax : slv5 := slv(to_unsigned( 19-1, 5)); + constant rm05_samax : slv6 := slv(to_unsigned( 32-1, 6)); + + constant rp07_dtyp : slv6 := slv(to_unsigned( 8#42#, 6)); + constant rp07_camax : slv10 := slv(to_unsigned( 630-1, 10)); + constant rp07_tamax : slv5 := slv(to_unsigned( 32-1, 5)); + constant rp07_samax : slv6 := slv(to_unsigned( 50-1, 6)); + + type state_type is ( + s_idle, -- idle: handle ibus + s_wcs1, -- wcs1: write cs1 + s_wcs2, -- wcs2: write cs2 + s_wcs3, -- wcs3: write cs3 + s_wer1, -- wer1: write er1 (rem only) + s_was, -- was: write as + s_wdt, -- wdt: write dt (rem only) + s_wds, -- wdt: write ds (rem only) + s_wbae, -- wbae: write bae + s_wmem, -- wmem: write mem (DA,MR1,OF,DC,MR2) + s_wmembe, -- wmem: write mem with be (WC,BA,DB) + s_whr, -- whr: write hr (holding reg only) + s_funcgo, -- funcgo: handle function go + s_chkdc, -- chkdc: handle dc check + s_chkda, -- chksa: handle da check + s_chkdo, -- chkdo: execute function + s_read, -- read: all register reads + s_setrmr, -- set rmr flag + s_oot_clr0, -- OOT clr0: state 0 + s_oot_clr1, -- OOT clr1: state 1 + s_oot_clr2 -- OOT clr2: state 2 + ); + + type regs_type is record -- state registers + ibsel : slbit; -- ibus select + state : state_type; -- state + amap : slv5; -- mem mapped address + omux : slv4; -- omux select + dinmsk : slv16; -- mbreq.din masked + dtrm : slv4; -- dt: drive rm controller + dte1 : slv4; -- dt: drive type bit 1 + dte0 : slv4; -- dt: drive type bit 0 + bae : slv6; -- bae: bus addr extension (in cs1&bae) + cs1sc : slbit; -- cs1: special condition + cs1tre : slbit; -- cs1: transfer error + cs1rdy : slbit; -- cs1: controller ready + cs1ie : slbit; -- cs1: interrupt enable + ffunc : slv5; -- func code (frozen on ext func go) + fxfer : slbit; -- func is xfer + cs2wce : slbit; -- cs2: write check error + cs2ned : slbit; -- cs2: non-existant drive + cs2nem : slbit; -- cs2: non-existant memory + cs2pge : slbit; -- cs2: programming error + cs2mxf : slbit; -- cs2: missed transfer + cs2pat : slbit; -- cs2: parity test + cs2bai : slbit; -- cs2: bus address inhibit + cs2unit2: slbit; -- cs2: unit lsb + cs2unit : slv2; -- unit (ibus view) + funit : slv2; -- unit (frozen on ext func go) + runit : slv2; -- unit (remote view) + eunit : slv2; -- unit (effective) + dsata : slv4; -- ds: attention + dserp : slv4; -- ds: error summary (or of er1+er2) + dspip : slv4; -- ds: positioning in progress + dsmol : slv4; -- ds: medium online (ATTACHED) + dswrl : slv4; -- ds: write locked + dslbt : slv4; -- ds: last block transfered + dsdpr : slv4; -- ds: drive present (ENABLED) + dsvv : slv4; -- ds: volume valid + dsom : slv4; -- ds: offset mode + er1uns : slv4; -- er1: dive unsafe + er1wle : slv4; -- er1: write lock error + er1iae : slv4; -- er1: invalid address error + er1aoe : slv4; -- er1: address overflow error + er1rmr : slv4; -- er1: register modificaton refused + er1ilf : slv4; -- er1: illegal function + cs3wco : slbit; -- cs3: write check odd word + idlyval : slv8; -- int delay value + idlycnt : slv8; -- int delay counter + seekdone: slbit; -- cs3 rem: seek done + poredone: slbit; -- cs3 rem: port rel done + packdone: slbit; -- cs3 rem: pack ack done + seardone: slbit; -- cs3 rem: search done + ned : slbit; -- current drive non-existant + cerm : slbit; -- current eff. drive rm controller + dtyp : slv6; -- current drive type (5:0) + camax : slv10; -- current max cylinder address + tamax : slv5; -- current max track address + samax : slv6; -- current max sector address + uscnt : slv7; -- usec counter + sc : slv6; -- current sector counter + clrmode : slv2; -- clear: mode + clrreg : slv3; -- clear: register counter + ireq : slbit; -- interrupt request flag + end record regs_type; + + constant regs_init : regs_type := ( + '0', -- ibsel + s_idle, -- state + (others=>'0'), -- amap, + (others=>'0'), -- omux, + (others=>'0'), -- dinmsk, + (others=>'0'), -- dtrm + (others=>'0'), -- dte1 + (others=>'0'), -- dte0 + (others=>'0'), -- bae, + '0','0','1','0', -- cs1sc,cs1tre,cs1rdy,cs1ie + (others=>'0'), -- ffunc + '0', -- fxfer + '0','0','0','0', -- cs2wce,cs2ned,cs2nem,cs2pge + '0','0','0', -- cs2mxf,cs2pat,cs2bai + '0', -- cs2unit2 + (others=>'0'), -- cs2unit + (others=>'0'), -- funit + (others=>'0'), -- runit + (others=>'0'), -- eunit + (others=>'0'), -- dsata + (others=>'0'), -- dserp + (others=>'0'), -- dspip + (others=>'0'), -- dsmol + (others=>'0'), -- dswrl + (others=>'0'), -- dslbt + (others=>'0'), -- dsdpr + (others=>'0'), -- dsvv + (others=>'0'), -- dsom + (others=>'0'), -- er1uns + (others=>'0'), -- er1wle + (others=>'0'), -- er1iae + (others=>'0'), -- er1aoe + (others=>'0'), -- er1rmr + (others=>'0'), -- er1ilf + '0', -- cs3wco + x"0a", -- idlyval (default delay=10) + (others=>'0'), -- idlycnt + '0','0','0','0', -- seekdone,poredone,packdone,seardone + '0','0', -- ned,cerm + (others=>'0'), -- dtyp + (others=>'0'), -- camax + (others=>'0'), -- tamax + (others=>'0'), -- samax + (others=>'0'), -- uscnt + (others=>'0'), -- sc + (others=>'0'), -- clrmode + (others=>'0'), -- clrreg + '0' -- ireq + ); + + signal R_REGS : regs_type := regs_init; + signal N_REGS : regs_type := regs_init; + + signal MEM_1_WE : slbit := '0'; + signal MEM_0_WE : slbit := '0'; + signal MEM_ADDR : slv5 := (others=>'0'); + signal MEM_DIN : slv16 := (others=>'0'); + signal MEM_DOUT : slv16 := (others=>'0'); + + -- the following is unfortunately not accepted by xst: + -- attribute fsm_encoding : string; + -- attribute fsm_encoding of R_REGS.state : signal is "one-hot"; + +begin + + MEM_1 : ram_1swar_gen + generic map ( + AWIDTH => 5, + DWIDTH => 8) + port map ( + CLK => CLK, + WE => MEM_1_WE, + ADDR => MEM_ADDR, + DI => MEM_DIN(ibf_byte1), + DO => MEM_DOUT(ibf_byte1)); + + MEM_0 : ram_1swar_gen + generic map ( + AWIDTH => 5, + DWIDTH => 8) + port map ( + CLK => CLK, + WE => MEM_0_WE, + ADDR => MEM_ADDR, + DI => MEM_DIN(ibf_byte0), + DO => MEM_DOUT(ibf_byte0)); + + proc_regs: process (CLK) + begin + -- BRESET handled in main fsm, not here !! + if rising_edge(CLK) then + R_REGS <= N_REGS; + end if; + end process proc_regs; + + proc_next : process (R_REGS, CE_USEC, BRESET, ITIMER, IB_MREQ, MEM_DOUT, + EI_ACK) + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + variable ibhold : slbit := '0'; + variable idout : slv16 := (others=>'0'); + variable ibrem : slbit := '0'; + variable ibreq : slbit := '0'; + variable ibrd : slbit := '0'; + variable ibw0 : slbit := '0'; + variable ibw1 : slbit := '0'; + variable ibwrem : slbit := '0'; + variable ilam : slbit := '0'; + variable iei_req : slbit := '0'; + + variable imem_we0 : slbit := '0'; + variable imem_we1 : slbit := '0'; + variable imem_addr : slv5 := (others=>'0'); + variable imem_din : slv16 := (others=>'0'); + + variable ieunit : slv2 := (others=>'0'); + + variable iomux : slv4 := (others=>'0'); -- omux select + variable iamap : slv5 := (others=>'0'); -- mem mapped address + variable imask : slv16 := (others=>'0'); -- implemented bits mask + variable inxr : slbit := '0'; -- non-existent register + variable imbreg : slbit := '0'; -- massbus register + variable inormr : slbit := '0'; -- inhibit rmr protect + + variable idte : slv3 := (others=>'0'); -- encoded drive type + variable idtyp : slv6 := (others=>'0'); -- drive type (5:0) + variable icamax : slv10 := (others=>'0'); -- max cylinder address + variable itamax : slv5 := (others=>'0'); -- max track address + variable isamax : slv6 := (others=>'0'); -- max sector address + + variable ined : slbit := '0'; -- non-existanrt drive + variable icerm : slbit := '0'; -- effectiv drive is rm + + variable iclrreg : slbit := '0'; -- clr enable + + variable iscinc : slbit := '0'; -- increment r.sc enable + + begin + + r := R_REGS; + n := R_REGS; + + ibhold := '0'; + idout := (others=>'0'); + ibrem := IB_MREQ.racc; + ibreq := IB_MREQ.re or IB_MREQ.we; + ibrd := IB_MREQ.re; + ibw0 := IB_MREQ.we and IB_MREQ.be0; + ibw1 := IB_MREQ.we and IB_MREQ.be1; + ibwrem := IB_MREQ.we and ibrem; + ilam := '0'; + iei_req := '0'; + + imem_we0 := '0'; + imem_we1 := '0'; + imem_addr := r.amap; -- default address (from mapper) + imem_din := r.dinmsk; -- default input (from masker) + + ieunit := (others=>'0'); + + iomux := (others=>'0'); + iamap := (others=>'0'); + imask := (others=>'1'); -- default: all bits ok + inxr := '0'; + imbreg := '0'; + inormr := '0'; + + idte := (others=>'0'); + idtyp := (others=>'0'); + icamax := (others=>'0'); + itamax := (others=>'0'); + isamax := (others=>'0'); + + ined := '0'; + icerm := '0'; + + iclrreg := '0'; + + iscinc := '0'; + + -- ibus address decoder, accept only offsets 0 to ibaddr_cs3 + n.ibsel := '0'; + if IB_MREQ.aval = '1' and + IB_MREQ.addr(12 downto 6) = ibaddr_rhrp(12 downto 6) and + unsigned(ibaddr_rhrp(5 downto 0)) <= unsigned(ibaddr_cs3) then + n.ibsel := '1'; + end if; + + -- internal state machine + case r.state is + when s_idle => -- idle: handle ibus ----------------- + + if r.ibsel='1' then -- selected + + -- determine effective unit number + if ibrem = '1' then + ieunit := r.runit; + else + ieunit := r.cs2unit; + end if; + n.eunit := ieunit; + + -- determine drive properties (always via iunit) FIXME: correct ?? + idte(2) := r.dtrm(to_integer(unsigned(r.cs2unit))); + idte(1) := r.dte1(to_integer(unsigned(r.cs2unit))); + idte(0) := r.dte0(to_integer(unsigned(r.cs2unit))); + case idte is + when dte_rp04 => -- RP04 + idtyp := rp04_dtyp; + icamax := rp04_camax; + itamax := rp04_tamax; + isamax := rp04_samax; + when dte_rp06 => -- RP06 + idtyp := rp06_dtyp; + icamax := rp06_camax; + itamax := rp06_tamax; + isamax := rp06_samax; + when dte_rm03 => -- RM03 + idtyp := rm03_dtyp; + icamax := rm03_camax; + itamax := rm03_tamax; + isamax := rm03_samax; + when dte_rm80 => -- RM80 + idtyp := rm80_dtyp; + icamax := rm80_camax; + itamax := rm80_tamax; + isamax := rm80_samax; + when dte_rm05 => -- RM05 + idtyp := rm05_dtyp; + icamax := rm05_camax; + itamax := rm05_tamax; + isamax := rm05_samax; + when dte_rp07 => -- RP07 + idtyp := rp07_dtyp; + icamax := rp07_camax; + itamax := rp07_tamax; + isamax := rp07_samax; + when others => + idtyp := (others=>'0'); + icamax := (others=>'0'); + itamax := (others=>'0'); + isamax := (others=>'0'); + end case; -- case idte + n.dtyp := idtyp; + n.camax := icamax; + n.tamax := itamax; + n.samax := isamax; + + -- consider drive non-existant if not 'DPR' or unit>=4 selected + if r.dsdpr(to_integer(unsigned(r.cs2unit))) = '0' or + r.cs2unit2 = '1' then + ined := '1'; + end if; + n.ned := ined; + + icerm := r.dtrm(to_integer(unsigned(ieunit))); + n.cerm := icerm; + + -- setup mapper + case IB_MREQ.addr(5 downto 1) is + + when ibaddr_cs1 => -- RxCS1 control reg 1 + -- cs1 not flagged mbreg !! ned handling done explicitely + iamap := ieunit & amapc_cs1; + iomux := omux_cs1; + + when ibaddr_wc => -- RxWC word count + iamap := amapr_wc & amapc_ext; + iomux := omux_mem; + + when ibaddr_ba => -- RxBA bus address + imask := "1111111111111110"; -- lsb ignored + iamap := amapr_ba & amapc_ext; + iomux := omux_mem; + + when ibaddr_da => -- RxDA disk address + imask := "0001111100111111"; -- 000t tttt 00ss ssss + iamap := ieunit & amapc_da; + iomux := omux_mem; + imbreg := '1'; -- mb 5 + + when ibaddr_cs2 => -- RxCS2 control reg 2 + iomux := omux_cs2; + + when ibaddr_ds => -- RxDS drive status + iomux := omux_ds; + imbreg := '1'; -- mb 1 + + when ibaddr_er1 => -- RxER1 error status 1 + iomux := omux_er1; + imbreg := '1'; -- mb 2 + + when ibaddr_as => -- RxAS attention summary + iomux := omux_as; + imbreg := '1'; -- mb 4 + inormr := '1'; -- AS writes allowed when RDY=0 + + when ibaddr_la => -- RxLA look ahead + iomux := omux_la; + imbreg := '1'; -- mb 7 + + when ibaddr_db => -- RxDB data buffer + iamap := amapr_db & amapc_ext; + iomux := omux_mem; + + when ibaddr_mr1 => -- RxMR1 maintenance reg 1 + iamap := ieunit & amapc_mr1; + iomux := omux_mem; + imbreg := '1'; -- mb 3 + inormr := '1'; -- MR1 writes allowed when RDY=0 + + when ibaddr_dt => -- RxDT drive type + iomux := omux_dt; + imbreg := '1'; -- mb 6 + + when ibaddr_sn => -- RxSN serial number + iomux := omux_sn; + imbreg := '1'; -- mb 10 + + when ibaddr_of => -- RxOF offset reg + imask := "0001110011111111"; -- 000f eh00 d??? ???? + iamap := ieunit & amapc_of; + iomux := omux_mem; + imbreg := '1'; -- mb 11 + + when ibaddr_dc => -- RxDC desired cylinder + imask := "0000001111111111"; -- 0000 00cc cccc cccc + iamap := ieunit & amapc_dc; + iomux := omux_mem; + imbreg := '1'; -- mb 12 + + when ibaddr_m13 => + if icerm = '1' then + iamap := ieunit & amapc_hr; -- RMHR holding reg + else + iamap := ieunit & amapc_dc; -- RPDC current cylinder + end if; + iomux := omux_mem; + imbreg := '1'; -- mb 13 + + when ibaddr_m14 => + if icerm = '1' then + iamap := ieunit & amapc_mr2; -- RMMR2 maintenance reg 2 + iomux := omux_mem; + else + iomux := omux_zero; -- RPER2 error status 2 + end if; + imbreg := '1'; -- mb 14 + + when ibaddr_m15 => -- RxER3 error status 3/2 + iomux := omux_zero; + imbreg := '1'; -- mb 15 + + when ibaddr_ec1 => -- RxEC1 ecc status 1 + iomux := omux_zero; + imbreg := '1'; -- mb 16 + + when ibaddr_ec2 => -- RxEC2 ecc status 2 + iomux := omux_zero; + imbreg := '1'; -- mb 17 + + when ibaddr_bae => -- RxBAE bus addr extension + iomux := omux_bae; + + when ibaddr_cs3 => -- RxCS3 control reg 3 + iomux := omux_cs3; + + when others => -- unknown register + inxr := '1'; + + end case; -- case IB_MREQ.addr + n.amap := iamap; + n.omux := iomux; + n.dinmsk := imask and IB_MREQ.din; + + if IB_MREQ.we = '1' then -- write request + ibhold := '1'; -- assume follow-up state taken + case IB_MREQ.addr(5 downto 1) is + + when ibaddr_cs1 => n.state := s_wcs1; -- RxCS1 + when ibaddr_wc => n.state := s_wmembe; -- RxWC + when ibaddr_ba => n.state := s_wmembe; -- RxBA + when ibaddr_da => n.state := s_wmem; -- RxDA + when ibaddr_cs2 => n.state := s_wcs2; -- RxCS2 + when ibaddr_ds => n.state := s_wds; -- RxDS (read-only) + when ibaddr_er1 => n.state := s_wer1; -- RxER1 (read-only) + when ibaddr_as => n.state := s_was; -- RxAS + when ibaddr_la => n.state := s_whr; -- RxLA (read-only) + when ibaddr_db => n.state := s_wmembe; -- RxDB + when ibaddr_mr1 => n.state := s_wmem; -- RxMR1 + when ibaddr_dt => n.state := s_wdt; -- RxDT (read-only) + when ibaddr_sn => n.state := s_whr; -- RxSN (read-only) + when ibaddr_of => n.state := s_wmem; -- RxOF + when ibaddr_dc => n.state := s_wmem; -- RxDC + when ibaddr_m13 => n.state := s_whr; -- RPCC|RMHR (fits both) + when ibaddr_m14 => + if icerm = '1' then + n.state := s_wmem; -- RMMR2 + else + n.state := s_whr; -- RPER2 + end if; + when ibaddr_m15 => n.state := s_whr; -- RPER3|RMER2 (fits both) + when ibaddr_ec1 => n.state := s_whr; -- RxEC1 + when ibaddr_ec2 => n.state := s_whr; -- RxEC2 + when ibaddr_bae => n.state := s_wbae; -- RxBAE + when ibaddr_cs3 => n.state := s_wcs3; -- RxCS3 + + when others => null; -- doesn't happen, ibsel only for + -- subrange up to cs3, and all + -- 22 regs are decoded above + + end case; -- case IB_MREQ.addr + + -- some general error catchers + if ibrem = '0' and imbreg='1' then -- local massbus write + -- for cs1: imbreg=0 !! + if ined = '1' then + n.cs2ned := '1'; + elsif inormr='0' and r.cs1rdy='0' then -- rmr prot reg and RDY=0 + n.state := s_setrmr; + end if; + end if; + + elsif IB_MREQ.re = '1' then -- read request + if inxr = '1' then -- unknown register + ibreq := '0'; -- suppress ack & hold --> ibus err + else + if ibrem='0' and imbreg='1' and ined='1' then + n.cs2ned := '1'; -- signal error + else + ibhold := '1'; + n.state := s_read; + end if; + end if; + + end if; -- if IB_MREQ.we .. elsif IB_MREQ.re + + -- BRESET and ITIMER can be handled in the 'else' because both can + -- never come during an ibus transaction. Done here to keep logic + -- path in the 'if' short. + else -- if r.ibsel='1' + if BRESET = '1' then + n.eunit := "00"; + n.clrmode := clrmode_breset; + n.state := s_oot_clr0; -- OOT state, no hold! + end if; + + if unsigned(r.idlycnt) = 0 then -- interrupt delay expired + n.dsata := r.dsata or r.dspip; -- convert pip's to ata's + n.dspip := (others=>'0'); -- and mark them done + else + if ITIMER = '1' then -- not expired and ITIMER + n.idlycnt := slv(unsigned(r.idlycnt) - 1); -- count down + end if; + end if; + + end if; -- if r.ibsel='1' + + -- s_idle goes up to here !! + + when s_wcs1 => -- wcs1: write cs1 ------------------- + n.state := s_idle; -- in general return to s_idle + imem_addr := r.amap; -- use mapped address + imem_din := r.dinmsk; -- use masked input + + if ibrem = '0' then -- loc write access + + if IB_MREQ.be1 = '1' then + if IB_MREQ.din(cs1_ibf_tre) = '1' then -- TRE=1 -> clear errors + n.cs2wce := '0'; + n.cs2ned := '0'; + n.cs2nem := '0'; + n.cs2pge := '0'; + n.cs2mxf := '0'; + end if; + if r.cs1rdy = '1' then -- only if RDY + n.bae(1 downto 0) := IB_MREQ.din(cs1_ibf_bae); -- update bae + end if; + end if; -- IB_MREQ.be1 = '1' + + if IB_MREQ.be0 = '1' then + n.cs1ie := IB_MREQ.din(cs1_ibf_ie); + if IB_MREQ.din(cs1_ibf_ie) = '1' and -- if IE and RDY both 1 + IB_MREQ.din(cs1_ibf_rdy) = '1'then + n.ireq := '1'; -- issue software interrupt + end if; + + if r.cs1rdy = '1' then -- controller ready + if r.ned = '0' and -- drive on + IB_MREQ.din(cs1_ibf_go) = '1' then -- GO bit set + ibhold := '1'; + n.state := s_funcgo; + end if; + else -- cntl not rdy + n.cs2pge := '1'; -- issue program error + end if; + + imem_we0 := IB_MREQ.be0; -- remember func field per unit + if r.ned = '1' then -- loc access and drive off + n.cs2ned := '1'; -- signal error + end if; + + end if; -- IB_MREQ.be0 = '1' + + else -- rem write access. GO not checked + -- always treated as remote function + case IB_MREQ.din(cs1_ibf_func) is + + when rfunc_wunit => -- rfunc: wunit --------------- + n.runit := IB_MREQ.din(cs1_ibf_runit); + + when rfunc_cunit => -- rfunc: cunit --------------- + n.runit := r.funit; -- use unit from last ext func go + + when rfunc_done => -- rfunc: done ---------------- + n.cs1rdy := '1'; + if IB_MREQ.din(cs1_ibf_rata) = '0' then + n.ireq := r.cs1ie; -- yes, ireq is set from ie !! + else + n.dsata(to_integer(unsigned(r.funit))) := '1'; + end if; + + when rfunc_widly => -- rfunc: widly --------------- + n.idlyval := IB_MREQ.din(cs1_ibf_ridly); + + when others => null; + + end case; + end if; + + when s_wcs2 => -- wcs2: write cs2 ------------------- + n.state := s_idle; -- in general return to s_idle + if ibrem = '1' then -- rem access + n.cs3wco := IB_MREQ.din(cs2_ibf_rwco); -- cs3.wco rem set via cs2 !! + n.cs2wce := IB_MREQ.din(cs2_ibf_wce); + n.cs2nem := IB_MREQ.din(cs2_ibf_nem); + n.cs2mxf := IB_MREQ.din(cs2_ibf_mxf); -- FIXME: really used ??? + else + if IB_MREQ.be0 = '1' then + n.cs2pat := IB_MREQ.din(cs2_ibf_pat); + n.cs2bai := IB_MREQ.din(cs2_ibf_bai); + n.cs2unit2 := IB_MREQ.din(cs2_ibf_unit2); + n.cs2unit := IB_MREQ.din(cs2_ibf_unit); + if IB_MREQ.din(cs2_ibf_clr) = '1' then + n.eunit := "00"; + n.clrmode := clrmode_cs2clr; + n.state := s_oot_clr0; -- OOT state, no hold! + end if; + end if; + end if; + + when s_wcs3 => -- wcs3: write cs3 ------------------- + n.state := s_idle; -- in general return to s_idle + if ibrem = '0' then -- loc access + if IB_MREQ.be0 = '1' then + n.cs1ie := IB_MREQ.din(cs3_ibf_ie); + end if; + end if; + + when s_wer1 => -- wer1: write er1 (rem only) -------- + n.state := s_idle; -- in general return to s_idle + if ibrem = '1' then -- rem access + if IB_MREQ.din(er1_ibf_uns) = '1' then + n.er1uns(to_integer(unsigned(r.eunit))) := '1'; + end if; + if IB_MREQ.din(er1_ibf_wle) = '1' then + n.er1wle(to_integer(unsigned(r.eunit))) := '1'; + end if; + if IB_MREQ.din(er1_ibf_iae) = '1' then + n.er1iae(to_integer(unsigned(r.eunit))) := '1'; + end if; + if IB_MREQ.din(er1_ibf_aoe) = '1' then + n.er1aoe(to_integer(unsigned(r.eunit))) := '1'; + end if; + if IB_MREQ.din(er1_ibf_ilf) = '1' then + n.er1ilf(to_integer(unsigned(r.eunit))) := '1'; + end if; + else -- loc access + ibhold := '1'; + n.state := s_whr; + end if; + + when s_was => -- was: write as --------------------- + n.state := s_idle; -- in general return to s_idle + -- clear the attention bits marked as '1' in data word (loc and rem !!) + n.dsata := r.dsata and not IB_MREQ.din(r.dsata'range); + if ibrem = '0' then -- loc access + ibhold := '1'; + n.state := s_whr; + end if; + + when s_wdt => -- wdt: write dt --------------------- + n.state := s_idle; -- in general return to s_idle + if ibrem = '1' then -- rem access + n.dtrm(to_integer(unsigned(r.runit))) := IB_MREQ.din(dt_ibf_rm); + n.dte1(to_integer(unsigned(r.runit))) := IB_MREQ.din(dt_ibf_e1); + n.dte0(to_integer(unsigned(r.runit))) := IB_MREQ.din(dt_ibf_e0); + n.state := s_idle; + else -- loc access + ibhold := '1'; + n.state := s_whr; + end if; + + when s_wds => -- wdt: write ds --------------------- + n.state := s_idle; -- in general return to s_idle + if ibrem = '1' then -- rem access + n.dsmol(to_integer(unsigned(r.runit))) := IB_MREQ.din(ds_ibf_mol); + n.dswrl(to_integer(unsigned(r.runit))) := IB_MREQ.din(ds_ibf_wrl); + n.dslbt(to_integer(unsigned(r.runit))) := IB_MREQ.din(ds_ibf_lbt); + n.dsdpr(to_integer(unsigned(r.runit))) := IB_MREQ.din(ds_ibf_dpr); + if IB_MREQ.din(ds_ibf_ata) = '1' then -- set ata on demand + n.dsata(to_integer(unsigned(r.runit))) := '1'; + end if; + if IB_MREQ.din(ds_ibf_vv) = '1' then -- clr vv on demand + n.dsvv(to_integer(unsigned(r.runit))) := '0'; + end if; + if IB_MREQ.din(ds_ibf_erp) = '1' then -- clr er1 on demand + n.er1uns(to_integer(unsigned(r.eunit))) := '0'; -- clr all er1 + n.er1wle(to_integer(unsigned(r.eunit))) := '0'; -- " + n.er1iae(to_integer(unsigned(r.eunit))) := '0'; -- " + n.er1aoe(to_integer(unsigned(r.eunit))) := '0'; -- " + n.er1rmr(to_integer(unsigned(r.eunit))) := '0'; -- " + n.er1ilf(to_integer(unsigned(r.eunit))) := '0'; -- " + end if; + n.state := s_idle; + else -- loc access + ibhold := '1'; -- read-only reg, thus noop + n.state := s_whr; + end if; + + when s_wbae => -- wbae: write bae ------------------- + n.state := s_idle; -- in general return to s_idle + if IB_MREQ.be0 = '1' then + n.bae := IB_MREQ.din(bae_ibf_bae); + end if; + + when s_wmem => -- wmem: write mem (DA,MR1,OF,DC,MR2)- + -- this state only handles massbus registers + n.state := s_idle; -- in general return to s_idle + imem_addr := r.amap; -- use mapped address + imem_din := r.dinmsk; -- use masked input + + if ibrem = '0' then -- loc access + imem_we0 := '1'; -- write memory + imem_we1 := '1'; + ibhold := '1'; + n.state := s_whr; + else -- rem access + imem_we0 := '1'; -- write memory + imem_we1 := '1'; + end if; + + when s_wmembe => -- wmem: write mem with be (WC,BA,DB)- + -- this state only handles controller registers --> no ned checking + n.state := s_idle; -- in general return to s_idle + imem_we0 := IB_MREQ.be0; + imem_we1 := IB_MREQ.be1; + imem_addr := r.amap; + imem_din := r.dinmsk; + + when s_whr => -- whr: write hr --------------------- + n.state := s_idle; -- in general return to s_idle + imem_addr := r.cs2unit & amapc_hr; -- mem address of holding reg + imem_din := not IB_MREQ.din; + if ibrem = '0' then -- loc access + imem_we0 := '1'; -- keep state + imem_we1 := '1'; + end if; + + when s_funcgo => -- funcgo: handle function go -------- + n.state := s_idle; -- in general return to s_idle + n.dsata(to_integer(unsigned(r.cs2unit))) := '0'; + + case IB_MREQ.din(cs1_ibf_func) is + when func_noop => -- func: noop -------------- + null; -- nothing done... + + when func_pore => -- func: port release------- + n.poredone := '1'; -- take note in done flag + + when func_unl => -- func: unload ------------ + -- only for RP, simply clears MOL + if r.dtrm(to_integer(unsigned(r.cs2unit))) = '0' then + n.dsmol(to_integer(unsigned(r.cs2unit))) := '0'; + n.dswrl(to_integer(unsigned(r.cs2unit))) := '0'; + n.dsvv(to_integer(unsigned(r.cs2unit))) := '0'; + n.dsom(to_integer(unsigned(r.cs2unit))) := '0'; + else + n.er1ilf(to_integer(unsigned(r.cs2unit))) := '1'; + end if; + n.dsata(to_integer(unsigned(r.cs2unit))) := '1'; + + when func_dclr => -- func: drive clear ------- + n.eunit := r.cs2unit; -- for follow-up states + n.clrmode := clrmode_fdclr; + n.state := s_oot_clr0; -- OOT state, no hold! + + when func_offs | -- func: offset ------------ + func_retc => -- func: return to center -- + + -- currently always immediate completion, so ata set here + n.dsata(to_integer(unsigned(r.cs2unit))) := '1'; + + if r.dsmol(to_integer(unsigned(r.cs2unit))) = '0' then + n.er1uns(to_integer(unsigned(r.cs2unit))) := '1'; + else + if IB_MREQ.din(cs1_ibf_func) = func_offs then + n.dsom(to_integer(unsigned(r.cs2unit))) := '1'; + else + n.dsom(to_integer(unsigned(r.cs2unit))) := '0'; + end if; + end if; + + when func_pres => -- func: readin preset ----- + n.dsvv(to_integer(unsigned(r.cs2unit))) := '1'; + n.eunit := r.cs2unit; -- for follow-up states + n.clrmode := clrmode_fpres; + n.state := s_oot_clr0; -- OOT state, no hold! + + when func_pack => -- func: pack acknowledge -- + n.dsvv(to_integer(unsigned(r.cs2unit))) := '1'; + n.packdone := '1'; -- take note in done flag + + -- seek like and data transfer functions + when func_seek | -- func: seek -------------- + func_recal | -- func: recalibrate ------- + func_sear | -- func: search ------------ + func_wcd | -- func: write check data -- + func_wchd | -- func: write check h&d --- + func_write | -- func: write ------------ + func_whd | -- func: write header&data - + func_read | -- func: read -------------- + func_rhd => -- func: read header&data -- + + if IB_MREQ.din(cs1_ibf_func) = func_seek then + n.seekdone := '1'; -- take note in done flag + end if; + if IB_MREQ.din(cs1_ibf_func) = func_sear then + n.seardone := '1'; -- take note in done flag + end if; + + -- check for transfer functions + n.fxfer := '0'; + if unsigned(IB_MREQ.din(cs1_ibf_func)) >= unsigned(func_wcd) then + n.fxfer := '1'; + -- in case of write, check for write lock + if IB_MREQ.din(cs1_ibf_func) = func_write or + IB_MREQ.din(cs1_ibf_func) = func_whd then + if r.dswrl(to_integer(unsigned(r.cs2unit))) = '1' then + n.er1wle(to_integer(unsigned(r.cs2unit))) := '1'; + end if; + end if; + end if; + + if r.dsmol(to_integer(unsigned(r.cs2unit))) = '0' then + n.er1uns(to_integer(unsigned(r.cs2unit))) := '1'; + n.dsata(to_integer(unsigned(r.cs2unit))) := '1'; + else + ibhold := '1'; + n.state := s_chkdc; + end if; + + -- illegal function codes + when others => + n.er1ilf(to_integer(unsigned(r.cs2unit))) := '1'; + n.dsata(to_integer(unsigned(r.cs2unit))) := '1'; + + end case; -- IB_MREQ.din(cs1_ibf_func) + + when s_chkdc => -- chkdc: handle dc check ------------ + imem_addr := r.cs2unit & amapc_dc; -- mem address of dc reg + if unsigned(MEM_DOUT(dc_ibf_ca)) > unsigned(r.camax) then + n.er1iae(to_integer(unsigned(r.cs2unit))) := '1'; + end if; + ibhold := '1'; + n.state := s_chkda; + + when s_chkda => -- chkda: handle da check ------------ + imem_addr := r.cs2unit & amapc_da; -- mem address of da reg + if unsigned(MEM_DOUT(da_ibf_sa)) > unsigned(r.samax) or + unsigned(MEM_DOUT(da_ibf_ta)) > unsigned(r.tamax) then + n.er1iae(to_integer(unsigned(r.cs2unit))) := '1'; + end if; + ibhold := '1'; + n.state := s_chkdo; + + when s_chkdo => -- chkdo: execute function ----------- + if r.er1iae(to_integer(unsigned(r.cs2unit))) = '1' or + r.er1wle(to_integer(unsigned(r.cs2unit))) = '1' then + n.dsata(to_integer(unsigned(r.cs2unit))) := '1'; -- ata and done + else + if r.fxfer = '0' then -- must be seek like function + n.dspip(to_integer(unsigned(r.cs2unit))) := '1'; -- pip + n.idlycnt := r.idlyval; -- start delay + else -- must be transfer function + n.ffunc := IB_MREQ.din(cs1_ibf_func); -- latch func + n.funit := r.cs2unit; -- latch unit + n.cs1rdy := '0'; -- controller busy + n.cs2wce := '0'; -- clear errors + n.cs2ned := '0'; + n.cs2nem := '0'; + n.cs2pge := '0'; + n.cs2mxf := '0'; + ilam := '1'; -- issue lam + end if; + end if; + n.state := s_idle; + + when s_read => -- read: all register reads ---------- + n.state := s_idle; -- in general return to s_idle + imem_addr := r.amap; + + case r.omux is + + when omux_cs1 => -- omux: cs1 reg --------------- + idout(cs1_ibf_sc) := r.cs1sc; + idout(cs1_ibf_tre) := r.cs1tre; + idout(cs1_ibf_dva) := '1'; + idout(cs1_ibf_bae) := r.bae(1 downto 0); + idout(cs1_ibf_rdy) := r.cs1rdy; + idout(cs1_ibf_ie) := r.cs1ie; + if ibrem = '0' then -- loc access + idout(cs1_ibf_func) := MEM_DOUT(cs1_ibf_func); --func per unit + if r.ned = '1' then -- drive off + n.cs2ned := '1'; -- signal error + end if; + else -- rem access + idout(cs1_ibf_func) := r.ffunc; + end if; + + when omux_cs2 => -- omux: cs2 reg --------------- + idout(cs2_ibf_wce) := r.cs2wce; + idout(cs2_ibf_ned) := r.cs2ned; + idout(cs2_ibf_nem) := r.cs2nem; + idout(cs2_ibf_pge) := r.cs2pge; + idout(cs2_ibf_mxf) := r.cs2mxf; + idout(cs2_ibf_or) := '1'; + idout(cs2_ibf_ir) := '1'; + idout(cs2_ibf_pat) := r.cs2pat; + idout(cs2_ibf_bai) := r.cs2bai; + idout(cs2_ibf_unit2) := r.cs2unit2; + if ibrem = '0' then -- loc access + idout(cs2_ibf_unit) := r.cs2unit; + else -- rem access + idout(cs2_ibf_unit) := r.funit; + end if; + + when omux_ds => -- omux: ds reg --------------- + idout(ds_ibf_ata) := r.dsata(to_integer(unsigned(r.eunit))); + idout(ds_ibf_erp) := r.dserp(to_integer(unsigned(r.eunit))); + idout(ds_ibf_pip) := r.dspip(to_integer(unsigned(r.eunit))); + idout(ds_ibf_mol) := r.dsmol(to_integer(unsigned(r.eunit))); + idout(ds_ibf_wrl) := r.dswrl(to_integer(unsigned(r.eunit))); + idout(ds_ibf_lbt) := r.dslbt(to_integer(unsigned(r.eunit))); + idout(ds_ibf_dpr) := r.dsdpr(to_integer(unsigned(r.eunit))); + + -- ds.dry is 0 if mol=0 or if transfer or seek is active on unit + -- the logic below checks for the complement ... + if r.dsmol(to_integer(unsigned(r.eunit))) = '1' then + if (r.cs1rdy = '1' or r.funit /= r.eunit) and + r.dspip(to_integer(unsigned(r.eunit))) = '0' then + idout(ds_ibf_dry) := '1'; + end if; + end if; + + idout(ds_ibf_vv) := r.dsvv (to_integer(unsigned(r.eunit))); + idout(ds_ibf_om) := r.dsom (to_integer(unsigned(r.eunit))); + + when omux_er1 => -- omux: er1 reg --------------- + idout(er1_ibf_uns) := r.er1uns(to_integer(unsigned(r.eunit))); + idout(er1_ibf_wle) := r.er1wle(to_integer(unsigned(r.eunit))); + idout(er1_ibf_iae) := r.er1iae(to_integer(unsigned(r.eunit))); + idout(er1_ibf_aoe) := r.er1aoe(to_integer(unsigned(r.eunit))); + idout(er1_ibf_rmr) := r.er1rmr(to_integer(unsigned(r.eunit))); + idout(er1_ibf_ilf) := r.er1ilf(to_integer(unsigned(r.eunit))); + + when omux_as => -- omux: as reg --------------- + idout(r.dsata'range) := r.dsata; + + when omux_la => -- omux: la reg --------------- + idout(la_ibf_sc) := r.sc; + + when omux_dt => -- omux: dt reg --------------- + if ibrem = '0' then -- loc access + idout(13) := '1'; -- set bit 020000 (movable head) + idout(r.dtyp'range) := r.dtyp; + else -- rem access (read back rem side) + idout(dt_ibf_rm) := r.dtrm(to_integer(unsigned(r.runit))); + idout(dt_ibf_e1) := r.dte1(to_integer(unsigned(r.runit))); + idout(dt_ibf_e0) := r.dte0(to_integer(unsigned(r.runit))); + end if; + + when omux_sn => -- omux: sn reg --------------- + -- the serial number is encoded as 4 digit BCD + -- digit 3: always 1 + -- digit 2: 1 if RM type; 0 if RP type + -- digit 1: 0-3 based on encoded drive type + -- digit 0: 0-3 taken from unit + idout(12) := '1'; + idout(8) := r.dtrm(to_integer(unsigned(r.eunit))); + idout(5) := r.dte1(to_integer(unsigned(r.eunit))); + idout(4) := r.dte0(to_integer(unsigned(r.eunit))); + idout(1) := r.eunit(1); + idout(0) := r.eunit(0); + + when omux_bae => -- omux: bae reg --------------- + idout(bae_ibf_bae) := r.bae; + + when omux_cs3 => -- omux: cs3 reg --------------- + idout(cs3_ibf_wco) := r.cs2wce and r.cs3wco; + idout(cs3_ibf_wce) := r.cs2wce and not r.cs3wco; + idout(cs3_ibf_ie) := r.cs1ie; + if ibrem = '1' then -- rem access + idout(cs3_ibf_rseardone) := r.seardone; + idout(cs3_ibf_rpackdone) := r.packdone; + idout(cs3_ibf_rporedone) := r.poredone; + idout(cs3_ibf_rseekdone) := r.seekdone; + if IB_MREQ.re = '1' then -- if read, do read & clear + n.seardone := '0'; + n.packdone := '0'; + n.poredone := '0'; + n.seekdone := '0'; + end if; + end if; + + when omux_mem => -- omux: mem output ------------ + idout := MEM_DOUT; + + when omux_zero => -- omux: zero ------------------ + idout := (others=>'0'); + + when others => null; -- nxr caught before in mapper ! + end case; -- case r.omux + + when s_setrmr => -- set rmr flag ---------------------- + n.er1rmr(to_integer(unsigned(r.cs2unit))) := '1'; + n.state := s_idle; + + when s_oot_clr0 => -- OOT clr0: state 0 ----------------- + if r.clrmode=clrmode_breset or r.clrmode=clrmode_cs2clr then + n.cs1rdy := '1'; -- clear cs1 + n.cs1ie := '0'; + n.cs2wce := '0'; -- clear cs2 + n.cs2ned := '0'; + n.cs2nem := '0'; + n.cs2pge := '0'; + n.cs2mxf := '0'; + n.cs2pat := '0'; + n.cs2bai := '0'; + n.cs2unit2 := '0'; + n.cs2unit := (others=>'0'); + n.bae := (others=>'0'); -- clear bae + n.ireq := '0'; -- clear iff + end if; + + if r.clrmode=clrmode_breset or r.clrmode=clrmode_fdclr then + n.er1uns(to_integer(unsigned(r.eunit))) := '0'; -- clr all er1 + n.er1wle(to_integer(unsigned(r.eunit))) := '0'; -- " + n.er1iae(to_integer(unsigned(r.eunit))) := '0'; -- " + n.er1aoe(to_integer(unsigned(r.eunit))) := '0'; -- " + n.er1rmr(to_integer(unsigned(r.eunit))) := '0'; -- " + n.er1ilf(to_integer(unsigned(r.eunit))) := '0'; -- " + end if; + + n.cerm := r.dtrm(to_integer(unsigned(ieunit))); + + n.clrreg := "000"; + ibhold := r.ibsel; -- delay pending request + n.state := s_oot_clr1; + + when s_oot_clr1 => -- OOT clr1: state 1 ---------------- + imem_addr := r.eunit & r.clrreg; + imem_din := (others=>'0'); + + iclrreg := '0'; + case r.clrmode is + + when clrmode_breset => -- BRESET ------------------------- + iclrreg := '1'; -- simply clear all (cntl+drives) + + when clrmode_cs2clr => -- CS2.CLR (controller clr) ------- + case r.clrreg is + when amapc_ext => iclrreg := '1'; + when amapc_mr1 => iclrreg := r.cerm; + when others => null; + end case; + + when clrmode_fdclr => -- func=DCLR (drive clr) ---------- + case r.clrreg is + when amapc_mr1 => iclrreg := r.cerm; + when others => null; + end case; + + when clrmode_fpres => -- func=PRESET -------------------- + case r.clrreg is + when amapc_da => iclrreg := '1'; + when amapc_of => iclrreg := '1'; + when amapc_dc => iclrreg := '1'; + when others => null; + end case; + + when others => null; + end case; + if iclrreg = '1' then + imem_we0 := IB_MREQ.be0; + imem_we1 := IB_MREQ.be1; + end if; + n.clrreg := slv(unsigned(r.clrreg) + 1); + + ibhold := r.ibsel; -- delay pending request + if r.clrreg = "111" then -- if last register done + n.state := s_oot_clr2; -- proceed with clr2 + end if; + + when s_oot_clr2 => -- OOT clr2: state 2 ---------------- + n.eunit := slv(unsigned(r.eunit) + 1); + + ibhold := r.ibsel; -- delay pending request, so that + -- s_idle can finally process it + if (r.clrmode=clrmode_breset or r.clrmode=clrmode_cs2clr) and + r.eunit /= "11" then + n.state := s_oot_clr0; + else + n.state := s_idle; + end if; + + when others => null; -- <> ------------------------------ + end case; -- case r.state + + -- update cs1tre and cs1sc + n.cs1tre := r.cs2wce or r.cs2ned or r.cs2nem or r.cs2pge or r.cs2mxf; + n.cs1sc := n.cs1tre or r.dsata(0) or r.dsata(1) or r.dsata(2) or r.dsata(3); + -- update dserp + n.dserp := r.er1uns or -- or all er1 + r.er1wle or -- " + r.er1iae or -- " + r.er1aoe or -- " + r.er1rmr or -- " + r.er1ilf; -- " + + -- handle current sector counter (for RxLA emulation) + -- advance every 128 usec, so generate a pulse every 128 usec + if CE_USEC = '1' then + n.uscnt := slv(unsigned(r.uscnt) + 1); + if unsigned(r.uscnt) = 0 then + iscinc := '1'; + end if; + end if; + + -- if current sector larger or equal highest sector wrap to zero + -- note: iscinc is also '1' when unit changes, this ensures that + -- the sector counter is always in range when read to ibus. + if iscinc = '1' then + if unsigned(r.sc) >= unsigned(r.samax) then + n.sc := (others=>'0'); + else + n.sc := slv(unsigned(r.sc) + 1); + end if; + end if; + + -- the RH70 interrupt logic is very unusual + -- 1. done interrupts (rdy 0->1) are edge sensitive (via r.ireq) + -- 2. done interrupts are not canceled when IE is cleared + -- 3. attention interrupts are level sensitive (via r.cs1sc) + -- 4. IE is disabled on interrupt acknowledge + + iei_req := r.ireq or (r.cs1sc and r.cs1ie and r.cs1rdy); + + if EI_ACK = '1' then -- interrupt executed + n.ireq := '0'; -- cancel request + n.cs1ie := '0'; -- disable interrupts + end if; + + N_REGS <= n; + + MEM_0_WE <= imem_we0; + MEM_1_WE <= imem_we1; + MEM_ADDR <= imem_addr; + MEM_DIN <= imem_din; + + IB_SRES.dout <= idout; + IB_SRES.ack <= r.ibsel and ibreq; + IB_SRES.busy <= ibhold and ibreq; + + RB_LAM <= ilam; + EI_REQ <= iei_req; + + end process proc_next; + + +end syn; diff --git a/rtl/ibus/ibdr_rk11.vhd b/rtl/ibus/ibdr_rk11.vhd index 7e9f9cf7..38ff51c2 100644 --- a/rtl/ibus/ibdr_rk11.vhd +++ b/rtl/ibus/ibdr_rk11.vhd @@ -1,6 +1,6 @@ --- $Id: ibdr_rk11.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: ibdr_rk11.vhd 672 2015-05-02 21:58:28Z mueller $ -- --- Copyright 2008-2011 by Walter F.J. Mueller +-- Copyright 2008-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -29,6 +29,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-05-01 672 1.3 BUGFIX: interrupt after dreset,seek command start -- 2011-11-18 427 1.2.2 now numeric_std clean -- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM; -- 2010-10-17 333 1.2 use ibus V2 interface @@ -112,6 +113,15 @@ architecture syn of ibdr_rk11 is constant rkmr_ibf_fdone : integer := 8; -- func done subtype rkmr_ibf_sdone is integer range 7 downto 0; -- seek done + constant func_creset : slv3 := "000"; -- func: control reset + constant func_write : slv3 := "001"; -- func: write + constant func_read : slv3 := "010"; -- func: read + constant func_wchk : slv3 := "011"; -- func: write check + constant func_seek : slv3 := "100"; -- func: seek + constant func_rchk : slv3 := "101"; -- func: read check + constant func_dreset : slv3 := "110"; -- func: drive reset + constant func_wlock : slv3 := "111"; -- func: write lock + type state_type is ( s_idle, s_init @@ -340,7 +350,7 @@ begin if ibw0 = '1' then n.ide := IB_MREQ.din(rkcs_ibf_ide); -- mirror ide bit - if n.ide = '0' then -- if IE 0 or set to 0 + if n.ide = '0' then -- if IE set to 0 n.fireq := '0'; -- cancel all pending n.sireq := (others=>'0'); -- interrupt requests end if; @@ -353,21 +363,23 @@ begin n.wce := '0'; n.fireq := '0'; -- cancel pend. int - if unsigned(IB_MREQ.din(rkcs_ibf_func))=0 then -- control reset? + if IB_MREQ.din(rkcs_ibf_func)=func_creset then -- control reset? n.creset := '1'; -- handle locally else ilam := '1'; -- issue lam end if; - if unsigned(IB_MREQ.din(rkcs_ibf_func))=4 or -- if seek - unsigned(IB_MREQ.din(rkcs_ibf_func))=6 then -- or drive reset - n.sbusy(to_integer(unsigned(r.drsel))) := '1'; -- set busy + if IB_MREQ.din(rkcs_ibf_func)=func_seek or -- if seek + IB_MREQ.din(rkcs_ibf_func)=func_dreset then -- or drive reset + n.sbusy(to_integer(unsigned(r.drsel))) := '1'; -- drive busy + if n.ide = '1' then -- if enabled + n.fireq := '1'; -- interrupt ! + end if; end if; end if; else -- GO=0 - if r.ide = '0' and -- if ide now 0 - IB_MREQ.din(rkcs_ibf_ide)='1' and -- and is set to 1 + if r.ide='0' and n.ide='1' and -- if IDE 0->1 transition r.rdy='1' then -- and controller ready n.fireq := '1'; -- issue interrupt end if; diff --git a/rtl/ibus/iblib.vhd b/rtl/ibus/iblib.vhd index 2f17e61c..243ca30d 100644 --- a/rtl/ibus/iblib.vhd +++ b/rtl/ibus/iblib.vhd @@ -1,6 +1,6 @@ --- $Id: iblib.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: iblib.vhd 672 2015-05-02 21:58:28Z mueller $ -- --- Copyright 2008-2010 by Walter F.J. Mueller +-- Copyright 2008-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,6 +19,7 @@ -- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-04-24 668 2.1 add ibd_ibmon -- 2010-10-23 335 2.0.1 add ib_sel; add ib_sres_or_mon -- 2010-10-17 333 2.0 ibus V2 interface: use aval,re,we,rmw -- 2010-06-11 303 1.1 added racc,cacc signals to ib_mreq_type @@ -28,6 +29,7 @@ library ieee; use ieee.std_logic_1164.all; +use ieee.numeric_std.all; use work.slvtypes.all; @@ -133,6 +135,19 @@ component ib_intmap is -- external interrupt mapper ); end component; +component ibd_ibmon is -- ibus dev: ibus monitor + generic ( + IB_ADDR : slv16 := slv(to_unsigned(8#160000#,16)); + AWIDTH : natural := 9); + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + IB_MREQ : in ib_mreq_type; -- ibus: request + IB_SRES : out ib_sres_type; -- ibus: response + IB_SRES_SUM : in ib_sres_type -- ibus: response (sum for monitor) + ); +end component; + -- -- components for use in test benches (not synthesizable) -- diff --git a/rtl/make_ise/generic_xflow.mk b/rtl/make_ise/generic_xflow.mk index 62fd0094..75c3452e 100644 --- a/rtl/make_ise/generic_xflow.mk +++ b/rtl/make_ise/generic_xflow.mk @@ -1,10 +1,11 @@ -# $Id: generic_xflow.mk 646 2015-02-15 12:04:55Z mueller $ +# $Id: generic_xflow.mk 672 2015-05-02 21:58:28Z mueller $ # # Copyright 2007-2015 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2015-05-02 672 1.11 ucf_cpp handling: remove -C (gcc 4.8 stdc-predef.h) # 2015-02-06 643 1.10 use make_ise; rename xise_msg_filter <- isemsg_filter # drop --ise_path from vbomconv; # 2013-10-12 539 1.9 use xtwi; support trce tsi file; use -C for cpp @@ -300,12 +301,12 @@ endif # generate cpp'ed ucf files from ucf_cpp # %.ucf : %.ucf_cpp - cpp -C -I${RETROBASE}/rtl $*.ucf_cpp $*.ucf + cpp -I${RETROBASE}/rtl $*.ucf_cpp $*.ucf # # generate nested dependency rules for cpp'ed ucf files from ucf_cpp # %.dep_ucf_cpp : %.ucf_cpp - cpp -C -I${RETROBASE}/rtl -MM $*.ucf_cpp |\ + cpp -I${RETROBASE}/rtl -MM $*.ucf_cpp |\ sed 's/\.o:/\.ucf:/' > $*.dep_ucf_cpp # # Cleanup diff --git a/rtl/make_ise/syn_s3_speed.opt b/rtl/make_ise/syn_s3_speed.opt index 6df36d48..16076751 100644 --- a/rtl/make_ise/syn_s3_speed.opt +++ b/rtl/make_ise/syn_s3_speed.opt @@ -1,6 +1,6 @@ FLOWTYPE = FPGA_SYNTHESIS; # -# $Id: syn_s3_speed.opt 540 2013-10-13 18:42:50Z mueller $ +# $Id: syn_s3_speed.opt 672 2015-05-02 21:58:28Z mueller $ # # Revision History: # Date Rev Version Comment @@ -33,8 +33,13 @@ ParamFile: _xst.scr "-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED "-opt_level 2"; # Optimization Effort Criteria: 2=High ## "-shreg_min_size 3"; # not available for Spartan-3 !! -"-shreg_extract NO"; # --> switch shreg extrtaction off instead +"-shreg_extract NO"; # --> switch shreg extraction off instead "-uc .xcf"; # Constraint File name +## Note: +## "-use_new_parser yes"; +## solves some nasty 'INTERNAL_ERROR:Xst:cmain.c:3464:1.56' problems, but +## leads to other problems later on (un-routable designs ect). +## Therefore currently not used. # # The following are HDL Options # diff --git a/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd index a93762eb..496d8831 100644 --- a/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd +++ b/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_rlink_b3.vhd 640 2015-02-01 09:56:53Z mueller $ +-- $Id: sys_tst_rlink_b3.vhd 672 2015-05-02 21:58:28Z mueller $ -- -- Copyright 2015- by Walter F.J. Mueller -- @@ -34,6 +34,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-11 666 1.0.1 rearrange XON handling -- 2015-01-16 636 1.0 Initial version (derived from sys_tst_rlink_n3) ------------------------------------------------------------------------------ -- Usage of Basys 3 Switches, Buttons, LEDs: @@ -193,7 +194,9 @@ begin ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, CDWIDTH => 15, - CDINIT => sys_conf_ser2rri_cdinit) + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => 0, + RBMON_RBADDR => x"ffe8") port map ( CLK => CLK, CE_USEC => CE_USEC, @@ -201,7 +204,7 @@ begin CE_INT => CE_MSEC, RESET => RESET, ENAXON => SWI(1), - ENAESC => SWI(1), + ESCFILL => '0', RXSD => RXD, TXSD => TXD, CTS_N => '0', diff --git a/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd b/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd index 9ed723f5..f758791e 100644 --- a/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd +++ b/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_rlink_n2.vhd 614 2014-12-20 15:00:45Z mueller $ +-- $Id: sys_tst_rlink_n2.vhd 672 2015-05-02 21:58:28Z mueller $ -- --- Copyright 2010-2014 by Walter F.J. Mueller +-- Copyright 2010-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -40,6 +40,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-11 666 1.4.1 rearrange XON handling -- 2014-11-09 603 1.4 use new rlink v4 iface and 4 bit STAT -- 2014-08-15 583 1.3 rb_mreq addr now 16 bit -- 2011-12-23 444 1.2 remove clksys output hack @@ -227,7 +228,9 @@ begin ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, CDWIDTH => 15, - CDINIT => sys_conf_ser2rri_cdinit) + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => 0, + RBMON_RBADDR => x"ffe8") port map ( CLK => CLK, CE_USEC => CE_USEC, @@ -235,7 +238,7 @@ begin CE_INT => CE_MSEC, RESET => RESET, ENAXON => SWI(1), - ENAESC => SWI(1), + ESCFILL => '0', RXSD => RXD, TXSD => TXD, CTS_N => CTS_N, diff --git a/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd b/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd index 90bc1c55..23100b77 100644 --- a/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd +++ b/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_rlink_n3.vhd 614 2014-12-20 15:00:45Z mueller $ +-- $Id: sys_tst_rlink_n3.vhd 672 2015-05-02 21:58:28Z mueller $ -- --- Copyright 2011-2014 by Walter F.J. Mueller +-- Copyright 2011-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -37,6 +37,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-11 666 1.4.1 rearrange XON handling -- 2014-11-09 603 1.4 use new rlink v4 iface and 4 bit STAT -- 2014-08-15 583 1.3 rb_mreq addr now 16 bit -- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect @@ -225,7 +226,9 @@ begin ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, CDWIDTH => 15, - CDINIT => sys_conf_ser2rri_cdinit) + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => 0, + RBMON_RBADDR => x"ffe8") port map ( CLK => CLK, CE_USEC => CE_USEC, @@ -233,7 +236,7 @@ begin CE_INT => CE_MSEC, RESET => RESET, ENAXON => SWI(1), - ENAESC => SWI(1), + ESCFILL => '0', RXSD => RXD, TXSD => TXD, CTS_N => CTS_N, diff --git a/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd index 99ed746e..ea386283 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd +++ b/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_rlink_n4.vhd 643 2015-02-07 17:41:53Z mueller $ +-- $Id: sys_tst_rlink_n4.vhd 672 2015-05-02 21:58:28Z mueller $ -- -- Copyright 2013-2015 by Walter F.J. Mueller -- @@ -34,6 +34,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-11 666 1.4.1 rearrange XON handling -- 2015-02-06 643 1.4 factor out memory -- 2015-02-01 641 1.3.1 separate I_BTNRST_N; autobaud on msb of display -- 2015-01-31 640 1.3 drop fusp iface; use new sn_hio @@ -208,7 +209,9 @@ begin ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, CDWIDTH => 15, - CDINIT => sys_conf_ser2rri_cdinit) + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => 0, + RBMON_RBADDR => x"ffe8") port map ( CLK => CLK, CE_USEC => CE_USEC, @@ -216,7 +219,7 @@ begin CE_INT => CE_MSEC, RESET => RESET, ENAXON => SWI(1), - ENAESC => SWI(1), + ESCFILL => '0', RXSD => RXD, TXSD => TXD, CTS_N => CTS_N, diff --git a/rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd b/rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd index 2dea40a1..020daf2d 100644 --- a/rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd +++ b/rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd @@ -1,6 +1,6 @@ --- $Id: sys_tst_rlink_s3.vhd 614 2014-12-20 15:00:45Z mueller $ +-- $Id: sys_tst_rlink_s3.vhd 672 2015-05-02 21:58:28Z mueller $ -- --- Copyright 2011-2014 by Walter F.J. Mueller +-- Copyright 2011-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -35,6 +35,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-11 666 1.2.1 rearrange XON handling -- 2014-11-09 603 1.2 use new rlink v4 iface and 4 bit STAT -- 2014-08-15 583 1.1 rb_mreq addr now 16 bit -- 2011-12-22 442 1.0 Initial version (derived from sys_tst_rlink_n2) @@ -198,7 +199,9 @@ begin ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, CDWIDTH => 15, - CDINIT => sys_conf_ser2rri_cdinit) + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => 0, + RBMON_RBADDR => x"ffe8") port map ( CLK => CLK, CE_USEC => CE_USEC, @@ -206,7 +209,7 @@ begin CE_INT => CE_MSEC, RESET => RESET, ENAXON => SWI(1), - ENAESC => SWI(1), + ESCFILL => '0', RXSD => RXD, TXSD => TXD, CTS_N => CTS_N, diff --git a/rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vhd b/rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vhd index 12eed490..888a3e25 100644 --- a/rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vhd +++ b/rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vhd @@ -1,6 +1,6 @@ --- $Id: tst_rlink_cuff.vhd 593 2014-09-14 22:21:33Z mueller $ +-- $Id: tst_rlink_cuff.vhd 666 2015-04-12 21:17:54Z mueller $ -- --- Copyright 2012-2014 by Walter F.J. Mueller +-- Copyright 2012-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -29,6 +29,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-11 666 1.2 rearrange XON handling -- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT -- 2013-01-02 467 1.0.1 use 64 usec led pulse width -- 2012-12-29 466 1.0 Initial version @@ -127,6 +128,8 @@ begin CLK => CLK, CE_INT => CE_MSEC, RESET => RESET, + ESCXON => SWI(1), + ESCFILL => '0', RLB_DI => RLB_DI, RLB_ENA => RLB_ENA, RLB_BUSY => RLB_BUSY, @@ -174,7 +177,7 @@ begin CE_MSEC => CE_MSEC, RESET => RESET, ENAXON => SWI(1), - ENAESC => SWI(1), + ENAESC => '0', -- escaping now in rlink_core8 RXDATA => SER_RXDATA, RXVAL => SER_RXVAL, RXHOLD => SER_RXHOLD, diff --git a/rtl/sys_gen/w11a/basys3/sys_conf.vhd b/rtl/sys_gen/w11a/basys3/sys_conf.vhd index f159ab07..47baf032 100644 --- a/rtl/sys_gen/w11a/basys3/sys_conf.vhd +++ b/rtl/sys_gen/w11a/basys3/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: sys_conf.vhd 672 2015-05-02 21:58:28Z mueller $ -- -- Copyright 2015- by Walter F.J. Mueller -- @@ -19,6 +19,7 @@ -- Tool versions: viv 2014.4; ghdl 0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-03-14 658 1.1 add sys_conf_ibd_* definitions -- 2015-02-08 644 1.0 Initial version (derived from _n4 version) ------------------------------------------------------------------------------ @@ -29,6 +30,7 @@ use work.slvtypes.all; package sys_conf is + -- configure clocks -------------------------------------------------------- constant sys_conf_clksys_vcodivide : positive := 1; constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz @@ -39,21 +41,40 @@ package sys_conf is constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud - constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + -- configure memory controller --------------------------------------------- constant sys_conf_memctl_mawidth : positive := 4; constant sys_conf_memctl_nblock : positive := 11; + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs + constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs + + -- configure w11 cpu core -------------------------------------------------- -- sys_conf_mem_losize is highest 64 byte MMU block number -- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks constant sys_conf_mem_losize : integer := 256*sys_conf_memctl_nblock-1; constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled - -- derived constants + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= constant sys_conf_clksys : integer := ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / sys_conf_clksys_outdivide; @@ -68,15 +89,3 @@ package sys_conf is (sys_conf_clkser/sys_conf_ser2rri_defbaud)-1; end package sys_conf; - --- Note: mem_losize holds 16 MSB of the PA of the addressable memory --- 2 211 111 111 110 000 000 000 --- 1 098 765 432 109 876 543 210 --- --- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte --- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte --- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte --- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte --- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte --- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte --- upper 256 kB excluded for 11/70 UB diff --git a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom index 174a0725..f219b34c 100644 --- a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom +++ b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom @@ -16,21 +16,14 @@ sys_conf = sys_conf.vhd [ghdl]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2line_iob.vbom -../../../bplib/bpgen/sn_humanio_rbus.vbom ../../../vlib/rlink/rlink_sp1c.vbom -../../../vlib/rbus/rb_sres_or_3.vbom -../../../w11a/pdp11_core_rbus.vbom -../../../w11a/pdp11_core.vbom -../../../w11a/pdp11_cache.vbom -../../../w11a/pdp11_mem70.vbom -../../../w11a/pdp11_bram_memctl.vbom -../../../ibus/ib_sres_or_2.vbom +../../../w11a/pdp11_sys70.vbom ../../../ibus/ibdr_maxisys.vbom +../../../w11a/pdp11_bram_memctl.vbom ../../../vlib/rlink/ioleds_sp1c.vbom -../../../w11a/pdp11_statleds.vbom -../../../w11a/pdp11_ledmux.vbom -../../../w11a/pdp11_dspmux.vbom -[sim]../../../w11a/pdp11_tmu_sb.vbom +../../../w11a/pdp11_hio70.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../vlib/rbus/rb_sres_or_2.vbom # design sys_w11a_b3.vhd @xdc:../../../bplib/basys3/basys3_pclk.xdc diff --git a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd index 7abd95e7..4bb267b6 100644 --- a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd +++ b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_b3.vhd 652 2015-02-28 12:18:08Z mueller $ +-- $Id: sys_w11a_b3.vhd 677 2015-05-09 21:52:32Z mueller $ -- -- Copyright 2015- by Walter F.J. Mueller -- @@ -18,21 +18,14 @@ -- Dependencies: vlib/xlib/s7_cmt_sfs -- vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_2line_iob --- bplib/bpgen/sn_humanio_rbus -- vlib/rlink/rlink_sp1c --- vlib/rbus/rb_sres_or_3 --- w11a/pdp11_core_rbus --- w11a/pdp11_core --- w11a/pdp11_cache --- w11a/pdp11_mem70 --- w11a/pdp11_bram_memctl --- ibus/ib_sres_or_2 +-- w11a/pdp11_sys70 -- ibus/ibdr_maxisys +-- w11a/pdp11_bram_memctl -- vlib/rlink/ioleds_sp1c --- w11a/pdp11_statleds --- w11a/pdp11_ledmux --- w11a/pdp11_dspmux --- w11a/pdp11_tmu_sb [sim only] +-- w11a/pdp11_hio70 +-- bplib/bpgen/sn_humanio_rbus +-- vlib/rbus/rb_sres_or_2 -- -- Test bench: tb/tb_sys_w11a_b3 -- @@ -45,6 +38,9 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul +-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 +-- 2015-04-11 666 1.1.1 rearrange XON handling -- 2015-02-21 649 1.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) -- 2015-02-08 644 1.0 Initial version (derived from sys_w11a_n4) ------------------------------------------------------------------------------ @@ -130,49 +126,34 @@ architecture syn of sys_w11a_b3 is signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + signal RXD : slbit := '1'; signal TXD : slbit := '0'; - signal SWI : slv16 := (others=>'0'); - signal BTN : slv5 := (others=>'0'); - signal LED : slv16 := (others=>'0'); - signal DSP_DAT : slv16 := (others=>'0'); - signal DSP_DP : slv4 := (others=>'0'); + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); signal SER_MONI : serport_moni_type := serport_moni_init; - signal RB_MREQ : rb_mreq_type := rb_mreq_init; - signal RB_SRES : rb_sres_type := rb_sres_init; - signal RB_SRES_CPU : rb_sres_type := rb_sres_init; - signal RB_SRES_IBD : rb_sres_type := rb_sres_init; - signal RB_SRES_HIO : rb_sres_type := rb_sres_init; - - signal RESET : slbit := '0'; - signal CE_USEC : slbit := '0'; - signal CE_MSEC : slbit := '0'; - - signal CPU_RESET : slbit := '0'; - signal CP_CNTL : cp_cntl_type := cp_cntl_init; - signal CP_ADDR : cp_addr_type := cp_addr_init; - signal CP_DIN : slv16 := (others=>'0'); - signal CP_STAT : cp_stat_type := cp_stat_init; - signal CP_DOUT : slv16 := (others=>'0'); + signal GRESET : slbit := '0'; -- general reset (from rbus) + signal CRESET : slbit := '0'; -- cpu reset (from cp) + signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) + signal ITIMER : slbit := '0'; signal EI_PRI : slv3 := (others=>'0'); signal EI_VECT : slv9_2 := (others=>'0'); signal EI_ACKM : slbit := '0'; + signal CP_STAT : cp_stat_type := cp_stat_init; + signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; - signal EM_MREQ : em_mreq_type := em_mreq_init; - signal EM_SRES : em_sres_type := em_sres_init; - - signal HM_ENA : slbit := '0'; - signal MEM70_FMISS : slbit := '0'; - signal CACHE_FMISS : slbit := '0'; - signal CACHE_CHIT : slbit := '0'; - signal MEM_REQ : slbit := '0'; signal MEM_WE : slbit := '0'; signal MEM_BUSY : slbit := '0'; @@ -184,25 +165,21 @@ architecture syn of sys_w11a_b3 is signal MEM_DI : slv32 := (others=>'0'); signal MEM_DO : slv32 := (others=>'0'); - signal BRESET : slbit := '0'; signal IB_MREQ : ib_mreq_type := ib_mreq_init; - signal IB_SRES : ib_sres_type := ib_sres_init; - - signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init; signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; - signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; - signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; - signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; - signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; - signal DISPREG : slv16 := (others=>'0'); signal STATLEDS : slv8 := (others=>'0'); signal ABCLKDIV : slv16 := (others=>'0'); + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx - constant rbaddr_ibus0 : slv16 := x"4000"; -- 4000/1000: 0100 xxxx xxxx xxxx - constant rbaddr_core0 : slv16 := x"0000"; -- 0000/0020: 0000 0000 000x xxxx begin @@ -210,7 +187,7 @@ begin report "assert sys_conf_clksys on MHz grid" severity failure; - GEN_CLKSYS : s7_cmt_sfs + GEN_CLKSYS : s7_cmt_sfs -- clock generator ------------------- generic map ( VCO_DIVIDE => sys_conf_clksys_vcodivide, VCO_MULTIPLY => sys_conf_clksys_vcomultiply, @@ -225,7 +202,7 @@ begin LOCKED => open ); - CLKDIV : clkdivce + CLKDIV : clkdivce -- usec/msec clock divider ----------- generic map ( CDUWIDTH => 7, USECDIV => sys_conf_clksys_mhz, @@ -236,7 +213,7 @@ begin CE_MSEC => CE_MSEC ); - IOB_RS232 : bp_rs232_2line_iob + IOB_RS232 : bp_rs232_2line_iob -- serport iob ---------------------- port map ( CLK => CLK, RXD => RXD, @@ -245,7 +222,133 @@ begin O_TXD => O_TXD ); - HIO : sn_humanio_rbus + RLINK : rlink_sp1c -- rlink for serport ----------------- + generic map ( + BTOWIDTH => 7, -- 128 cycles access timeout + RTAWIDTH => 12, + SYSID => (others=>'0'), + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 13, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => sys_conf_rbmon_awidth, + RBMON_RBADDR => rbaddr_rbmon) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ESCFILL => '0', + RXSD => RXD, + TXSD => TXD, + CTS_N => '0', + RTS_N => open, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM_CPU => RB_LAM(0), + GRESET => GRESET, + CRESET => CRESET, + BRESET => BRESET, + CP_STAT => CP_STAT, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + ITIMER => ITIMER, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO, + DM_STAT_DP => DM_STAT_DP + ); + + + IBDR_SYS : ibdr_maxisys -- IO system ------------------------- + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => GRESET, + BRESET => BRESET, + ITIMER => ITIMER, + CPUSUSP => CP_STAT.cpususp, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG + ); + + BRAM_CTL: pdp11_bram_memctl -- memory controller ----------------- + generic map ( + MAWIDTH => sys_conf_memctl_mawidth, + NBLOCK => sys_conf_memctl_nblock) + port map ( + CLK => CLK, + RESET => GRESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => open, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO + ); + + LED_IO : ioleds_sp1c -- hio leds from serport ------------- + port map ( + SER_MONI => SER_MONI, + IOLEDS => DSP_DP + ); + + ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; + + HIO70 : pdp11_hio70 -- hio from sys70 -------------------- + generic map ( + LWIDTH => LED'length, + DCWIDTH => 2) + port map ( + SEL_LED => SWI(3), + SEL_DSP => SWI(5 downto 4), + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + CP_STAT => CP_STAT, + DM_STAT_DP => DM_STAT_DP, + ABCLKDIV => ABCLKDIV, + DISPREG => DISPREG, + LED => LED, + DSP_DAT => DSP_DAT + ); + + HIO : sn_humanio_rbus -- hio manager ----------------------- generic map ( SWIDTH => 16, BWIDTH => 5, @@ -271,214 +374,11 @@ begin O_SEG_N => O_SEG_N ); - RLINK : rlink_sp1c - generic map ( - BTOWIDTH => 7, -- 128 cycles access timeout - RTAWIDTH => 12, - SYSID => (others=>'0'), - IFAWIDTH => 5, -- 32 word input fifo - OFAWIDTH => 5, -- 32 word output fifo - ENAPIN_RLMON => sbcntl_sbf_rlmon, - ENAPIN_RBMON => sbcntl_sbf_rbmon, - CDWIDTH => 13, - CDINIT => sys_conf_ser2rri_cdinit) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC, - CE_INT => CE_MSEC, - RESET => RESET, - ENAXON => SWI(1), - ENAESC => SWI(1), - RXSD => RXD, - TXSD => TXD, - CTS_N => '0', - RTS_N => open, - RB_MREQ => RB_MREQ, - RB_SRES => RB_SRES, - RB_LAM => RB_LAM, - RB_STAT => RB_STAT, - RL_MONI => open, - SER_MONI => SER_MONI - ); - - RB_SRES_OR : rb_sres_or_3 + RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- port map ( RB_SRES_1 => RB_SRES_CPU, - RB_SRES_2 => RB_SRES_IBD, - RB_SRES_3 => RB_SRES_HIO, + RB_SRES_2 => RB_SRES_HIO, RB_SRES_OR => RB_SRES ); - RB2CP : pdp11_core_rbus - generic map ( - RB_ADDR_CORE => rbaddr_core0, - RB_ADDR_IBUS => rbaddr_ibus0) - port map ( - CLK => CLK, - RESET => RESET, - RB_MREQ => RB_MREQ, - RB_SRES => RB_SRES_CPU, - RB_STAT => RB_STAT, - RB_LAM => RB_LAM(0), - CPU_RESET => CPU_RESET, - CP_CNTL => CP_CNTL, - CP_ADDR => CP_ADDR, - CP_DIN => CP_DIN, - CP_STAT => CP_STAT, - CP_DOUT => CP_DOUT - ); - - W11A : pdp11_core - port map ( - CLK => CLK, - RESET => CPU_RESET, - CP_CNTL => CP_CNTL, - CP_ADDR => CP_ADDR, - CP_DIN => CP_DIN, - CP_STAT => CP_STAT, - CP_DOUT => CP_DOUT, - EI_PRI => EI_PRI, - EI_VECT => EI_VECT, - EI_ACKM => EI_ACKM, - EM_MREQ => EM_MREQ, - EM_SRES => EM_SRES, - BRESET => BRESET, - IB_MREQ_M => IB_MREQ, - IB_SRES_M => IB_SRES, - DM_STAT_DP => DM_STAT_DP, - DM_STAT_VM => DM_STAT_VM, - DM_STAT_CO => DM_STAT_CO - ); - - CACHE: pdp11_cache - port map ( - CLK => CLK, - GRESET => CPU_RESET, - EM_MREQ => EM_MREQ, - EM_SRES => EM_SRES, - FMISS => CACHE_FMISS, - CHIT => CACHE_CHIT, - MEM_REQ => MEM_REQ, - MEM_WE => MEM_WE, - MEM_BUSY => MEM_BUSY, - MEM_ACK_R => MEM_ACK_R, - MEM_ADDR => MEM_ADDR, - MEM_BE => MEM_BE, - MEM_DI => MEM_DI, - MEM_DO => MEM_DO - ); - - MEM70: pdp11_mem70 - port map ( - CLK => CLK, - CRESET => BRESET, - HM_ENA => HM_ENA, - HM_VAL => CACHE_CHIT, - CACHE_FMISS => MEM70_FMISS, - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_MEM70 - ); - - HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; - CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; - - BRAM_CTL: pdp11_bram_memctl - generic map ( - MAWIDTH => sys_conf_memctl_mawidth, - NBLOCK => sys_conf_memctl_nblock) - port map ( - CLK => CLK, - RESET => CPU_RESET, - REQ => MEM_REQ, - WE => MEM_WE, - BUSY => MEM_BUSY, - ACK_R => MEM_ACK_R, - ACK_W => open, - ACT_R => MEM_ACT_R, - ACT_W => MEM_ACT_W, - ADDR => MEM_ADDR, - BE => MEM_BE, - DI => MEM_DI, - DO => MEM_DO - ); - - IB_SRES_OR : ib_sres_or_2 - port map ( - IB_SRES_1 => IB_SRES_MEM70, - IB_SRES_2 => IB_SRES_IBDR, - IB_SRES_OR => IB_SRES - ); - - IBDR_SYS : ibdr_maxisys - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC, - RESET => CPU_RESET, - BRESET => BRESET, - RB_LAM => RB_LAM(15 downto 1), - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_IBDR, - EI_ACKM => EI_ACKM, - EI_PRI => EI_PRI, - EI_VECT => EI_VECT, - DISPREG => DISPREG - ); - - LED_IO : ioleds_sp1c - port map ( - SER_MONI => SER_MONI, - IOLEDS => DSP_DP - ); - - LED_CPU : pdp11_statleds - port map ( - MEM_ACT_R => MEM_ACT_R, - MEM_ACT_W => MEM_ACT_W, - CP_STAT => CP_STAT, - DM_STAT_DP => DM_STAT_DP, - STATLEDS => STATLEDS - ); - - LED_MUX : pdp11_ledmux - generic map ( - LWIDTH => LED'length) - port map ( - SEL => SWI(3), - STATLEDS => STATLEDS, - DM_STAT_DP => DM_STAT_DP, - LED => LED - ); - - ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; - - DSP_MUX : pdp11_dspmux - generic map ( - DCWIDTH => 2) - port map ( - SEL => SWI(5 downto 4), - ABCLKDIV => ABCLKDIV, - DM_STAT_DP => DM_STAT_DP, - DISPREG => DISPREG, - DSP_DAT => DSP_DAT - ); - --- synthesis translate_off - DM_STAT_SY.emmreq <= EM_MREQ; - DM_STAT_SY.emsres <= EM_SRES; - DM_STAT_SY.chit <= CACHE_CHIT; - - TMU : pdp11_tmu_sb - generic map ( - ENAPIN => 13) - port map ( - CLK => CLK, - DM_STAT_DP => DM_STAT_DP, - DM_STAT_VM => DM_STAT_VM, - DM_STAT_CO => DM_STAT_CO, - DM_STAT_SY => DM_STAT_SY - ); --- synthesis translate_on - end syn; diff --git a/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd index 483c358c..31ae4ae5 100644 --- a/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: sys_conf_sim.vhd 672 2015-05-02 21:58:28Z mueller $ -- -- Copyright 2015- by Walter F.J. Mueller -- @@ -19,6 +19,7 @@ -- Tool versions: viv 2014.4; ghdl 0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-03-14 658 1.1 add sys_conf_ibd_* definitions -- 2015-02-21 649 1.0 Initial version ------------------------------------------------------------------------------ @@ -29,6 +30,7 @@ use work.slvtypes.all; package sys_conf is + -- configure clocks -------------------------------------------------------- constant sys_conf_clksys_vcodivide : positive := 1; constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz @@ -39,21 +41,40 @@ package sys_conf is constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim - constant sys_conf_hio_debounce : boolean := false; -- no debouncers + -- configure memory controller --------------------------------------------- constant sys_conf_memctl_mawidth : positive := 4; constant sys_conf_memctl_nblock : positive := 11; + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs + constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs + + -- configure w11 cpu core -------------------------------------------------- -- sys_conf_mem_losize is highest 64 byte MMU block number -- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks constant sys_conf_mem_losize : integer := 256*sys_conf_memctl_nblock-1; constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled - -- derived constants - + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= constant sys_conf_clksys : integer := ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / sys_conf_clksys_outdivide; diff --git a/rtl/sys_gen/w11a/nexys2/sys_conf.vhd b/rtl/sys_gen/w11a/nexys2/sys_conf.vhd index ba71559e..0153566f 100644 --- a/rtl/sys_gen/w11a/nexys2/sys_conf.vhd +++ b/rtl/sys_gen/w11a/nexys2/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 647 2015-02-17 22:35:36Z mueller $ +-- $Id: sys_conf.vhd 672 2015-05-02 21:58:28Z mueller $ -- -- Copyright 2010-2015 by Walter F.J. Mueller -- @@ -19,6 +19,7 @@ -- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-03-14 658 1.4 add sys_conf_ibd_* definitions -- 2015-02-15 647 1.3 drop bram and minisys options -- 2015-01-04 630 1.2.2 use clksys=54 (no closure after rlink r4 + RL11) -- 2014-12-22 619 1.2.1 add _rbmon_awidth @@ -41,30 +42,47 @@ use work.slvtypes.all; package sys_conf is + -- configure clocks -------------------------------------------------------- constant sys_conf_clkfx_divide : positive := 25; constant sys_conf_clkfx_multiply : positive := 27; -- ==> 54 MHz - constant sys_conf_memctl_read0delay : positive := 3; - constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; - constant sys_conf_memctl_writedelay : positive := 4; - + -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud - - constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers -- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec constant sys_conf_fx2_petowidth : positive := 10; constant sys_conf_fx2_ccwidth : positive := 5; - constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon + -- configure memory controller --------------------------------------------- + constant sys_conf_memctl_read0delay : positive := 3; + constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; + constant sys_conf_memctl_writedelay : positive := 4; + + -- configure w11 cpu core -------------------------------------------------- constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte ---constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled - -- derived constants + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= constant sys_conf_clksys : integer := (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; @@ -73,15 +91,3 @@ package sys_conf is (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; end package sys_conf; - --- Note: mem_losize holds 16 MSB of the PA of the addressable memory --- 2 211 111 111 110 000 000 000 --- 1 098 765 432 109 876 543 210 --- --- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte --- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte --- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte --- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte --- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte --- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte --- upper 256 kB excluded for 11/70 UB diff --git a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom index 488ce852..c571b924 100644 --- a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom +++ b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom @@ -4,7 +4,6 @@ ../../../vlib/genlib/genlib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd -../../../vlib/rbus/rbdlib.vhd ../../../vlib/rlink/rlinklib.vbom ../../../bplib/fx2lib/fx2lib.vhd ../../../bplib/fx2rlink/fx2rlinklib.vbom @@ -20,22 +19,14 @@ sys_conf = sys_conf.vhd [ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom -../../../bplib/bpgen/sn_humanio_rbus.vbom ../../../bplib/fx2rlink/rlink_sp1c_fx2.vbom -../../../vlib/rbus/rb_sres_or_4.vbom -../../../vlib/rbus/rbd_rbmon.vbom -../../../w11a/pdp11_core_rbus.vbom -../../../w11a/pdp11_core.vbom -../../../w11a/pdp11_cache.vbom -../../../w11a/pdp11_mem70.vbom -../../../bplib/nxcramlib/nx_cram_memctl_as.vbom -../../../ibus/ib_sres_or_2.vbom +../../../w11a/pdp11_sys70.vbom ../../../ibus/ibdr_maxisys.vbom +../../../bplib/nxcramlib/nx_cram_memctl_as.vbom ../../../bplib/fx2rlink/ioleds_sp1c_fx2.vbom -../../../w11a/pdp11_statleds.vbom -../../../w11a/pdp11_ledmux.vbom -../../../w11a/pdp11_dspmux.vbom -[sim]../../../w11a/pdp11_tmu_sb.vbom +../../../w11a/pdp11_hio70.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../vlib/rbus/rb_sres_or_2.vbom # design sys_w11a_n2.vhd @ucf_cpp: sys_w11a_n2.ucf diff --git a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd index d8a01d86..f411a03b 100644 --- a/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd +++ b/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_n2.vhd 652 2015-02-28 12:18:08Z mueller $ +-- $Id: sys_w11a_n2.vhd 677 2015-05-09 21:52:32Z mueller $ -- -- Copyright 2010-2015 by Walter F.J. Mueller -- @@ -18,22 +18,14 @@ -- Dependencies: vlib/xlib/dcm_sfs -- vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_2l4l_iob --- bplib/bpgen/sn_humanio_rbus -- bplib/fx2rlink/rlink_sp1c_fx2 --- vlib/rbus/rb_sres_or_4 --- vlib/rbus/rbd_rbmon --- w11a/pdp11_core_rbus --- w11a/pdp11_core --- w11a/pdp11_cache --- w11a/pdp11_mem70 --- bplib/nxcramlib/nx_cram_memctl_as --- ibus/ib_sres_or_2 +-- w11a/pdp11_sys70 -- ibus/ibdr_maxisys +-- bplib/nxcramlib/nx_cram_memctl_as -- bplib/fx2rlink/ioleds_sp1c_fx2 --- w11a/pdp11_statleds --- w11a/pdp11_ledmux --- w11a/pdp11_dspmux --- w11a/pdp11_tmu_sb [sim only] +-- w11a/pdp11_hio70 +-- bplib/bpgen/sn_humanio_rbus +-- vlib/rbus/rb_sres_or_2 -- -- Test bench: tb/tb_sys_w11a_n2 -- @@ -72,6 +64,9 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul +-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 +-- 2015-04-11 666 1.7.2 rearrange XON handling -- 2015-02-21 649 1.7.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) -- 2015-02-15 647 1.7 drop bram and minisys options -- 2014-12-24 620 1.6.2 relocate ibus window and hio rbus address @@ -165,7 +160,6 @@ use work.xlib.all; use work.genlib.all; use work.serportlib.all; use work.rblib.all; -use work.rbdlib.all; use work.rlinklib.all; use work.fx2lib.all; use work.fx2rlinklib.all; @@ -220,16 +214,19 @@ architecture syn of sys_w11a_n2 is signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + signal RXD : slbit := '1'; signal TXD : slbit := '0'; signal RTS_N : slbit := '0'; signal CTS_N : slbit := '0'; - signal SWI : slv8 := (others=>'0'); - signal BTN : slv4 := (others=>'0'); - signal LED : slv8 := (others=>'0'); - signal DSP_DAT : slv16 := (others=>'0'); - signal DSP_DP : slv4 := (others=>'0'); + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); @@ -238,35 +235,23 @@ architecture syn of sys_w11a_n2 is signal SER_MONI : serport_moni_type := serport_moni_init; signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; - signal RB_MREQ : rb_mreq_type := rb_mreq_init; - signal RB_SRES : rb_sres_type := rb_sres_init; - signal RB_SRES_CPU : rb_sres_type := rb_sres_init; - signal RB_SRES_IBD : rb_sres_type := rb_sres_init; - signal RB_SRES_HIO : rb_sres_type := rb_sres_init; - signal RB_SRES_RBMON : rb_sres_type := rb_sres_init; + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); - signal RESET : slbit := '0'; - signal CE_USEC : slbit := '0'; - signal CE_MSEC : slbit := '0'; - - signal CPU_RESET : slbit := '0'; - signal CP_CNTL : cp_cntl_type := cp_cntl_init; - signal CP_ADDR : cp_addr_type := cp_addr_init; - signal CP_DIN : slv16 := (others=>'0'); - signal CP_STAT : cp_stat_type := cp_stat_init; - signal CP_DOUT : slv16 := (others=>'0'); + signal GRESET : slbit := '0'; -- general reset (from rbus) + signal CRESET : slbit := '0'; -- cpu reset (from cp) + signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) + signal ITIMER : slbit := '0'; signal EI_PRI : slv3 := (others=>'0'); signal EI_VECT : slv9_2 := (others=>'0'); signal EI_ACKM : slbit := '0'; - signal EM_MREQ : em_mreq_type := em_mreq_init; - signal EM_SRES : em_sres_type := em_sres_init; - - signal HM_ENA : slbit := '0'; - signal MEM70_FMISS : slbit := '0'; - signal CACHE_FMISS : slbit := '0'; - signal CACHE_CHIT : slbit := '0'; + signal CP_STAT : cp_stat_type := cp_stat_init; + signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; signal MEM_REQ : slbit := '0'; signal MEM_WE : slbit := '0'; @@ -281,17 +266,8 @@ architecture syn of sys_w11a_n2 is signal MEM_ADDR_EXT : slv22 := (others=>'0'); - signal BRESET : slbit := '0'; signal IB_MREQ : ib_mreq_type := ib_mreq_init; - signal IB_SRES : ib_sres_type := ib_sres_init; - - signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init; - signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; - - signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; - signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; - signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; - signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; + signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; signal DISPREG : slv16 := (others=>'0'); signal STATLEDS : slv8 := (others=>'0'); @@ -299,8 +275,6 @@ architecture syn of sys_w11a_n2 is constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx - constant rbaddr_ibus0 : slv16 := x"4000"; -- 4000/1000: 0100 xxxx xxxx xxxx - constant rbaddr_core0 : slv16 := x"0000"; -- 0000/0020: 0000 0000 000x xxxx begin @@ -308,7 +282,7 @@ begin report "assert sys_conf_clksys on MHz grid" severity failure; - DCM : dcm_sfs + DCM : dcm_sfs -- clock generator ------------------- generic map ( CLKFX_DIVIDE => sys_conf_clkfx_divide, CLKFX_MULTIPLY => sys_conf_clkfx_multiply, @@ -319,7 +293,7 @@ begin LOCKED => open ); - CLKDIV : clkdivce + CLKDIV : clkdivce -- usec/msec clock divider ----------- generic map ( CDUWIDTH => 6, USECDIV => sys_conf_clksys_mhz, @@ -330,7 +304,7 @@ begin CE_MSEC => CE_MSEC ); - IOB_RS232 : bp_rs232_2l4l_iob + IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ---------------- port map ( CLK => CLK, RESET => '0', @@ -347,29 +321,7 @@ begin O_RTS1_N => O_FUSP_RTS_N ); - HIO : sn_humanio_rbus - generic map ( - DEBOUNCE => sys_conf_hio_debounce, - RB_ADDR => rbaddr_hio) - port map ( - CLK => CLK, - RESET => RESET, - CE_MSEC => CE_MSEC, - RB_MREQ => RB_MREQ, - RB_SRES => RB_SRES_HIO, - SWI => SWI, - BTN => BTN, - LED => LED, - DSP_DAT => DSP_DAT, - DSP_DP => DSP_DP, - I_SWI => I_SWI, - I_BTN => I_BTN, - O_LED => O_LED, - O_ANO_N => O_ANO_N, - O_SEG_N => O_SEG_N - ); - - RLINK : rlink_sp1c_fx2 + RLINK : rlink_sp1c_fx2 -- rlink for serport + fx2 ----------- generic map ( BTOWIDTH => 7, -- 128 cycles access timeout RTAWIDTH => 12, @@ -381,7 +333,9 @@ begin ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, CDWIDTH => 13, - CDINIT => sys_conf_ser2rri_cdinit) + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => sys_conf_rbmon_awidth, + RBMON_RBADDR => rbaddr_rbmon) port map ( CLK => CLK, CE_USEC => CE_USEC, @@ -389,7 +343,6 @@ begin CE_INT => CE_MSEC, RESET => RESET, ENAXON => SWI(1), - ENAESC => SWI(1), ENAFX2 => SWI(2), RXSD => RXD, TXSD => TXD, @@ -413,113 +366,63 @@ begin IO_FX2_DATA => IO_FX2_DATA ); - RB_SRES_OR : rb_sres_or_4 + SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- port map ( - RB_SRES_1 => RB_SRES_CPU, - RB_SRES_2 => RB_SRES_IBD, - RB_SRES_3 => RB_SRES_HIO, - RB_SRES_4 => RB_SRES_RBMON, - RB_SRES_OR => RB_SRES - ); - - RBMON : if sys_conf_rbmon_awidth > 0 generate - begin - RBMON : rbd_rbmon - generic map ( - RB_ADDR => rbaddr_rbmon, - AWIDTH => sys_conf_rbmon_awidth) - port map ( - CLK => CLK, - RESET => RESET, - RB_MREQ => RB_MREQ, - RB_SRES => RB_SRES_RBMON, - RB_SRES_SUM => RB_SRES - ); - end generate RBMON; - - RB2CP : pdp11_core_rbus - generic map ( - RB_ADDR_CORE => rbaddr_core0, - RB_ADDR_IBUS => rbaddr_ibus0) - port map ( - CLK => CLK, - RESET => RESET, - RB_MREQ => RB_MREQ, - RB_SRES => RB_SRES_CPU, - RB_STAT => RB_STAT, - RB_LAM => RB_LAM(0), - CPU_RESET => CPU_RESET, - CP_CNTL => CP_CNTL, - CP_ADDR => CP_ADDR, - CP_DIN => CP_DIN, - CP_STAT => CP_STAT, - CP_DOUT => CP_DOUT + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM_CPU => RB_LAM(0), + GRESET => GRESET, + CRESET => CRESET, + BRESET => BRESET, + CP_STAT => CP_STAT, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + ITIMER => ITIMER, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO, + DM_STAT_DP => DM_STAT_DP ); - W11A : pdp11_core + IBDR_SYS : ibdr_maxisys -- IO system ------------------------- port map ( - CLK => CLK, - RESET => CPU_RESET, - CP_CNTL => CP_CNTL, - CP_ADDR => CP_ADDR, - CP_DIN => CP_DIN, - CP_STAT => CP_STAT, - CP_DOUT => CP_DOUT, - EI_PRI => EI_PRI, - EI_VECT => EI_VECT, - EI_ACKM => EI_ACKM, - EM_MREQ => EM_MREQ, - EM_SRES => EM_SRES, - BRESET => BRESET, - IB_MREQ_M => IB_MREQ, - IB_SRES_M => IB_SRES, - DM_STAT_DP => DM_STAT_DP, - DM_STAT_VM => DM_STAT_VM, - DM_STAT_CO => DM_STAT_CO - ); - - CACHE: pdp11_cache - port map ( - CLK => CLK, - GRESET => CPU_RESET, - EM_MREQ => EM_MREQ, - EM_SRES => EM_SRES, - FMISS => CACHE_FMISS, - CHIT => CACHE_CHIT, - MEM_REQ => MEM_REQ, - MEM_WE => MEM_WE, - MEM_BUSY => MEM_BUSY, - MEM_ACK_R => MEM_ACK_R, - MEM_ADDR => MEM_ADDR, - MEM_BE => MEM_BE, - MEM_DI => MEM_DI, - MEM_DO => MEM_DO + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => GRESET, + BRESET => BRESET, + ITIMER => ITIMER, + CPUSUSP => CP_STAT.cpususp, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG ); - - MEM70: pdp11_mem70 - port map ( - CLK => CLK, - CRESET => BRESET, - HM_ENA => HM_ENA, - HM_VAL => CACHE_CHIT, - CACHE_FMISS => MEM70_FMISS, - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_MEM70 - ); - - HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; - CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; - + MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) - SRAM_CTL: nx_cram_memctl_as + SRAM_CTL: nx_cram_memctl_as -- memory controller ----------------- generic map ( READ0DELAY => sys_conf_memctl_read0delay, READ1DELAY => sys_conf_memctl_read1delay, WRITEDELAY => sys_conf_memctl_writedelay) port map ( CLK => CLK, - RESET => CPU_RESET, + RESET => GRESET, REQ => MEM_REQ, WE => MEM_WE, BUSY => MEM_BUSY, @@ -545,34 +448,11 @@ begin O_FLA_CE_N <= '1'; -- keep Flash memory disabled - IB_SRES_OR : ib_sres_or_2 - port map ( - IB_SRES_1 => IB_SRES_MEM70, - IB_SRES_2 => IB_SRES_IBDR, - IB_SRES_OR => IB_SRES - ); - - IBDR_SYS : ibdr_maxisys + LED_IO : ioleds_sp1c_fx2 -- hio leds from serport or fx2 ------ port map ( CLK => CLK, CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC, - RESET => CPU_RESET, - BRESET => BRESET, - RB_LAM => RB_LAM(15 downto 1), - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_IBDR, - EI_ACKM => EI_ACKM, - EI_PRI => EI_PRI, - EI_VECT => EI_VECT, - DISPREG => DISPREG - ); - - LED_IO : ioleds_sp1c_fx2 - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - RESET => CPU_RESET, + RESET => GRESET, ENAFX2 => SWI(2), RB_SRES => RB_SRES, RLB_MONI => RLB_MONI, @@ -580,53 +460,52 @@ begin IOLEDS => DSP_DP ); - LED_CPU : pdp11_statleds + ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; + + HIO70 : pdp11_hio70 -- hio from sys70 -------------------- + generic map ( + LWIDTH => LED'length, + DCWIDTH => 2) port map ( + SEL_LED => SWI(3), + SEL_DSP => SWI(5 downto 4), MEM_ACT_R => MEM_ACT_R, MEM_ACT_W => MEM_ACT_W, CP_STAT => CP_STAT, DM_STAT_DP => DM_STAT_DP, - STATLEDS => STATLEDS - ); - - LED_MUX : pdp11_ledmux - generic map ( - LWIDTH => LED'length) - port map ( - SEL => SWI(3), - STATLEDS => STATLEDS, - DM_STAT_DP => DM_STAT_DP, - LED => LED - ); - - ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; - - DSP_MUX : pdp11_dspmux - generic map ( - DCWIDTH => 2) - port map ( - SEL => SWI(5 downto 4), ABCLKDIV => ABCLKDIV, - DM_STAT_DP => DM_STAT_DP, DISPREG => DISPREG, + LED => LED, DSP_DAT => DSP_DAT ); - --- synthesis translate_off - DM_STAT_SY.emmreq <= EM_MREQ; - DM_STAT_SY.emsres <= EM_SRES; - DM_STAT_SY.chit <= CACHE_CHIT; - - TMU : pdp11_tmu_sb + + HIO : sn_humanio_rbus -- hio manager ----------------------- generic map ( - ENAPIN => 13) + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) port map ( - CLK => CLK, - DM_STAT_DP => DM_STAT_DP, - DM_STAT_VM => DM_STAT_VM, - DM_STAT_CO => DM_STAT_CO, - DM_STAT_SY => DM_STAT_SY + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N ); --- synthesis translate_on - + + RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- + port map ( + RB_SRES_1 => RB_SRES_CPU, + RB_SRES_2 => RB_SRES_HIO, + RB_SRES_OR => RB_SRES + ); + end syn; diff --git a/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd index fe33bc83..aed25877 100644 --- a/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 647 2015-02-17 22:35:36Z mueller $ +-- $Id: sys_conf_sim.vhd 672 2015-05-02 21:58:28Z mueller $ -- -- Copyright 2010-2015 by Walter F.J. Mueller -- @@ -19,6 +19,7 @@ -- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-03-14 658 1.4 add sys_conf_ibd_* definitions -- 2015-02-07 643 1.3 drop bram and minisys options -- 2014-12-22 619 1.2.1 add _rbmon_awidth -- 2013-04-21 509 1.2 add fx2 settings @@ -34,46 +35,51 @@ use work.slvtypes.all; package sys_conf is + -- configure clocks -------------------------------------------------------- constant sys_conf_clkfx_divide : positive := 1; constant sys_conf_clkfx_multiply : positive := 1; -- no dcm in sim... -- constant sys_conf_clkfx_divide : positive := 25; -- constant sys_conf_clkfx_multiply : positive := 28; -- ==> 56 MHz - constant sys_conf_memctl_read0delay : positive := 3; - constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; - constant sys_conf_memctl_writedelay : positive := 4; - + -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim - - constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_hio_debounce : boolean := false; -- no debouncers -- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec constant sys_conf_fx2_petowidth : positive := 10; constant sys_conf_fx2_ccwidth : positive := 5; - - constant sys_conf_hio_debounce : boolean := false; -- no debouncers + -- configure memory controller --------------------------------------------- + constant sys_conf_memctl_read0delay : positive := 3; + constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; + constant sys_conf_memctl_writedelay : positive := 4; + + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon + + -- configure w11 cpu core -------------------------------------------------- constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte ---constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled - -- derived constants + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= constant sys_conf_clksys : integer := (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; end package sys_conf; - --- Note: mem_losize holds 16 MSB of the PA of the addressable memory --- 2 211 111 111 110 000 000 000 --- 1 098 765 432 109 876 543 210 --- --- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte --- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte --- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte --- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte --- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte --- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte --- upper 256 kB excluded for 11/70 UB diff --git a/rtl/sys_gen/w11a/nexys3/sys_conf.vhd b/rtl/sys_gen/w11a/nexys3/sys_conf.vhd index ff209063..edbf8842 100644 --- a/rtl/sys_gen/w11a/nexys3/sys_conf.vhd +++ b/rtl/sys_gen/w11a/nexys3/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 647 2015-02-17 22:35:36Z mueller $ +-- $Id: sys_conf.vhd 672 2015-05-02 21:58:28Z mueller $ -- -- Copyright 2011-2015 by Walter F.J. Mueller -- @@ -19,6 +19,7 @@ -- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-03-14 658 1.4 add sys_conf_ibd_* definitions -- 2015-02-15 647 1.3 drop bram and minisys options -- 2014-12-26 621 1.2.2 use 68 MHz, get occasional problems with 72 MHz -- 2014-12-22 619 1.2.1 add _rbmon_awidth @@ -45,32 +46,50 @@ use work.slvtypes.all; package sys_conf is + -- configure clocks -------------------------------------------------------- constant sys_conf_clksys_vcodivide : positive := 25; constant sys_conf_clksys_vcomultiply : positive := 17; -- dcm 68 MHz constant sys_conf_clksys_outdivide : positive := 1; -- sys 68 MHz constant sys_conf_clksys_gentype : string := "DCM"; - constant sys_conf_memctl_read0delay : positive := 4; - constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; - constant sys_conf_memctl_writedelay : positive := 5; - + -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud - - constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers -- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec constant sys_conf_fx2_petowidth : positive := 10; constant sys_conf_fx2_ccwidth : positive := 5; - constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + -- configure memory controller --------------------------------------------- + constant sys_conf_memctl_read0delay : positive := 4; + constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; + constant sys_conf_memctl_writedelay : positive := 5; + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon + + -- configure w11 cpu core -------------------------------------------------- constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte ---constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled - -- derived constants + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= constant sys_conf_clksys : integer := ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / sys_conf_clksys_outdivide; @@ -80,15 +99,3 @@ package sys_conf is (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; end package sys_conf; - --- Note: mem_losize holds 16 MSB of the PA of the addressable memory --- 2 211 111 111 110 000 000 000 --- 1 098 765 432 109 876 543 210 --- --- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte --- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte --- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte --- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte --- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte --- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte --- upper 256 kB excluded for 11/70 UB diff --git a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom index 096fa16d..a65fa688 100644 --- a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom +++ b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom @@ -4,7 +4,6 @@ ../../../vlib/genlib/genlib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd -../../../vlib/rbus/rbdlib.vhd ../../../vlib/rlink/rlinklib.vbom ../../../bplib/fx2lib/fx2lib.vhd ../../../bplib/fx2rlink/fx2rlinklib.vbom @@ -20,22 +19,14 @@ sys_conf = sys_conf.vhd [ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom -../../../bplib/bpgen/sn_humanio_rbus.vbom ../../../bplib/fx2rlink/rlink_sp1c_fx2.vbom -../../../vlib/rbus/rb_sres_or_4.vbom -../../../vlib/rbus/rbd_rbmon.vbom -../../../w11a/pdp11_core_rbus.vbom -../../../w11a/pdp11_core.vbom -../../../w11a/pdp11_cache.vbom -../../../w11a/pdp11_mem70.vbom -../../../bplib/nxcramlib/nx_cram_memctl_as.vbom -../../../ibus/ib_sres_or_2.vbom +../../../w11a/pdp11_sys70.vbom ../../../ibus/ibdr_maxisys.vbom +../../../bplib/nxcramlib/nx_cram_memctl_as.vbom ../../../bplib/fx2rlink/ioleds_sp1c_fx2.vbom -../../../w11a/pdp11_statleds.vbom -../../../w11a/pdp11_ledmux.vbom -../../../w11a/pdp11_dspmux.vbom -[sim]../../../w11a/pdp11_tmu_sb.vbom +../../../w11a/pdp11_hio70.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../vlib/rbus/rb_sres_or_2.vbom # design sys_w11a_n3.vhd @ucf_cpp: sys_w11a_n3.ucf diff --git a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd index e68ea80a..e693733b 100644 --- a/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd +++ b/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_n3.vhd 652 2015-02-28 12:18:08Z mueller $ +-- $Id: sys_w11a_n3.vhd 677 2015-05-09 21:52:32Z mueller $ -- -- Copyright 2011-2015 by Walter F.J. Mueller -- @@ -18,22 +18,14 @@ -- Dependencies: vlib/xlib/s6_cmt_sfs -- vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_2l4l_iob --- bplib/bpgen/sn_humanio_rbus -- bplib/fx2rlink/rlink_sp1c_fx2 --- vlib/rbus/rb_sres_or_4 --- vlib/rbus/rbd_rbmon --- w11a/pdp11_core_rbus --- w11a/pdp11_core --- w11a/pdp11_cache --- w11a/pdp11_mem70 --- bplib/nxcramlib/nx_cram_memctl_as --- ibus/ib_sres_or_2 +-- w11a/pdp11_sys70 -- ibus/ibdr_maxisys +-- bplib/nxcramlib/nx_cram_memctl_as -- bplib/fx2rlink/ioleds_sp1c_fx2 --- w11a/pdp11_statleds --- w11a/pdp11_ledmux --- w11a/pdp11_dspmux --- w11a/pdp11_tmu_sb [sim only] +-- w11a/pdp11_hio70 +-- bplib/bpgen/sn_humanio_rbus +-- vlib/rbus/rb_sres_or_2 -- -- Test bench: tb/tb_sys_w11a_n3 -- @@ -42,7 +34,9 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri --- 2014-02-21 649 14.7 131013 xc6slx16-2 1819 3905 160 1380 ok: +RL11 +-- 2015-04-25 668 14.7 131013 xc6slx16-2 2101 4420 167 1520 ok: +ibmon 66% +-- 2015-04-06 664 14.7 131013 xc6slx16-2 1991 4350 167 1489 ok: +RHRP 65% +-- 2015-02-21 649 14.7 131013 xc6slx16-2 1819 3905 160 1380 ok: +RL11 -- 2014-12-22 619 14.7 131013 xc6slx16-2 1742 3767 150 1350 ok: +rbmon -- 2014-12-20 614 14.7 131013 xc6slx16-2 1640 3692 150 1297 ok: -RL11,rlv4 -- 2014-06-08 561 14.7 131013 xc6slx16-2 1531 3500 142 1165 ok: +RL11 @@ -53,6 +47,10 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul +-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 +-- 2015-04-24 668 1.8.3 added ibd_ibmon +-- 2015-04-11 666 1.8.2 rearrange XON handling -- 2015-02-21 649 1.8.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) -- 2015-02-15 647 1.8 drop bram and minisys options -- 2014-12-24 620 1.7.2 relocate ibus window and hio rbus address @@ -127,7 +125,6 @@ use work.xlib.all; use work.genlib.all; use work.serportlib.all; use work.rblib.all; -use work.rbdlib.all; use work.rlinklib.all; use work.fx2lib.all; use work.fx2rlinklib.all; @@ -183,53 +180,38 @@ architecture syn of sys_w11a_n3 is signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + signal RXD : slbit := '1'; signal TXD : slbit := '0'; signal RTS_N : slbit := '0'; signal CTS_N : slbit := '0'; - signal SWI : slv8 := (others=>'0'); - signal BTN : slv5 := (others=>'0'); - signal LED : slv8 := (others=>'0'); - signal DSP_DAT : slv16 := (others=>'0'); - signal DSP_DP : slv4 := (others=>'0'); + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); - + signal RLB_MONI : rlb_moni_type := rlb_moni_init; signal SER_MONI : serport_moni_type := serport_moni_init; signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; - signal RB_MREQ : rb_mreq_type := rb_mreq_init; - signal RB_SRES : rb_sres_type := rb_sres_init; - signal RB_SRES_CPU : rb_sres_type := rb_sres_init; - signal RB_SRES_IBD : rb_sres_type := rb_sres_init; - signal RB_SRES_HIO : rb_sres_type := rb_sres_init; - signal RB_SRES_RBMON : rb_sres_type := rb_sres_init; - - signal RESET : slbit := '0'; - signal CE_USEC : slbit := '0'; - signal CE_MSEC : slbit := '0'; - - signal CPU_RESET : slbit := '0'; - signal CP_CNTL : cp_cntl_type := cp_cntl_init; - signal CP_ADDR : cp_addr_type := cp_addr_init; - signal CP_DIN : slv16 := (others=>'0'); - signal CP_STAT : cp_stat_type := cp_stat_init; - signal CP_DOUT : slv16 := (others=>'0'); + signal GRESET : slbit := '0'; -- general reset (from rbus) + signal CRESET : slbit := '0'; -- cpu reset (from cp) + signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) + signal ITIMER : slbit := '0'; signal EI_PRI : slv3 := (others=>'0'); signal EI_VECT : slv9_2 := (others=>'0'); signal EI_ACKM : slbit := '0'; - signal EM_MREQ : em_mreq_type := em_mreq_init; - signal EM_SRES : em_sres_type := em_sres_init; - - signal HM_ENA : slbit := '0'; - signal MEM70_FMISS : slbit := '0'; - signal CACHE_FMISS : slbit := '0'; - signal CACHE_CHIT : slbit := '0'; + signal CP_STAT : cp_stat_type := cp_stat_init; + signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; signal MEM_REQ : slbit := '0'; signal MEM_WE : slbit := '0'; @@ -244,26 +226,21 @@ architecture syn of sys_w11a_n3 is signal MEM_ADDR_EXT : slv22 := (others=>'0'); - signal BRESET : slbit := '0'; signal IB_MREQ : ib_mreq_type := ib_mreq_init; - signal IB_SRES : ib_sres_type := ib_sres_init; - - signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init; - signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; - - signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; - signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; - signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; - signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; + signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; signal DISPREG : slv16 := (others=>'0'); signal STATLEDS : slv8 := (others=>'0'); signal ABCLKDIV : slv16 := (others=>'0'); + signal SWI : slv8 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx - constant rbaddr_ibus0 : slv16 := x"4000"; -- 4000/1000: 0100 xxxx xxxx xxxx - constant rbaddr_core0 : slv16 := x"0000"; -- 0000/0020: 0000 0000 000x xxxx begin @@ -271,7 +248,7 @@ begin report "assert sys_conf_clksys on MHz grid" severity failure; - GEN_CLKSYS : s6_cmt_sfs + GEN_CLKSYS : s6_cmt_sfs -- clock generator ------------------- generic map ( VCO_DIVIDE => sys_conf_clksys_vcodivide, VCO_MULTIPLY => sys_conf_clksys_vcomultiply, @@ -286,7 +263,7 @@ begin LOCKED => open ); - CLKDIV : clkdivce + CLKDIV : clkdivce -- usec/msec clock divider ----------- generic map ( CDUWIDTH => 7, USECDIV => sys_conf_clksys_mhz, @@ -297,7 +274,7 @@ begin CE_MSEC => CE_MSEC ); - IOB_RS232 : bp_rs232_2l4l_iob + IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ---------------- port map ( CLK => CLK, RESET => '0', @@ -314,30 +291,7 @@ begin O_RTS1_N => O_FUSP_RTS_N ); - HIO : sn_humanio_rbus - generic map ( - BWIDTH => 5, - DEBOUNCE => sys_conf_hio_debounce, - RB_ADDR => rbaddr_hio) - port map ( - CLK => CLK, - RESET => RESET, - CE_MSEC => CE_MSEC, - RB_MREQ => RB_MREQ, - RB_SRES => RB_SRES_HIO, - SWI => SWI, - BTN => BTN, - LED => LED, - DSP_DAT => DSP_DAT, - DSP_DP => DSP_DP, - I_SWI => I_SWI, - I_BTN => I_BTN, - O_LED => O_LED, - O_ANO_N => O_ANO_N, - O_SEG_N => O_SEG_N - ); - - RLINK : rlink_sp1c_fx2 + RLINK : rlink_sp1c_fx2 -- rlink for serport + fx2 ----------- generic map ( BTOWIDTH => 7, -- 128 cycles access timeout RTAWIDTH => 12, @@ -349,7 +303,9 @@ begin ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, CDWIDTH => 13, - CDINIT => sys_conf_ser2rri_cdinit) + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => sys_conf_rbmon_awidth, + RBMON_RBADDR => rbaddr_rbmon) port map ( CLK => CLK, CE_USEC => CE_USEC, @@ -357,7 +313,6 @@ begin CE_INT => CE_MSEC, RESET => RESET, ENAXON => SWI(1), - ENAESC => SWI(1), ENAFX2 => SWI(2), RXSD => RXD, TXSD => TXD, @@ -381,113 +336,63 @@ begin IO_FX2_DATA => IO_FX2_DATA ); - RB_SRES_OR : rb_sres_or_4 + SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- port map ( - RB_SRES_1 => RB_SRES_CPU, - RB_SRES_2 => RB_SRES_IBD, - RB_SRES_3 => RB_SRES_HIO, - RB_SRES_4 => RB_SRES_RBMON, - RB_SRES_OR => RB_SRES - ); - - RBMON : if sys_conf_rbmon_awidth > 0 generate - begin - RBMON : rbd_rbmon - generic map ( - RB_ADDR => rbaddr_rbmon, - AWIDTH => sys_conf_rbmon_awidth) - port map ( - CLK => CLK, - RESET => RESET, - RB_MREQ => RB_MREQ, - RB_SRES => RB_SRES_RBMON, - RB_SRES_SUM => RB_SRES - ); - end generate RBMON; - - RB2CP : pdp11_core_rbus - generic map ( - RB_ADDR_CORE => rbaddr_core0, - RB_ADDR_IBUS => rbaddr_ibus0) - port map ( - CLK => CLK, - RESET => RESET, - RB_MREQ => RB_MREQ, - RB_SRES => RB_SRES_CPU, - RB_STAT => RB_STAT, - RB_LAM => RB_LAM(0), - CPU_RESET => CPU_RESET, - CP_CNTL => CP_CNTL, - CP_ADDR => CP_ADDR, - CP_DIN => CP_DIN, - CP_STAT => CP_STAT, - CP_DOUT => CP_DOUT + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM_CPU => RB_LAM(0), + GRESET => GRESET, + CRESET => CRESET, + BRESET => BRESET, + CP_STAT => CP_STAT, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + ITIMER => ITIMER, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO, + DM_STAT_DP => DM_STAT_DP ); - W11A : pdp11_core + IBDR_SYS : ibdr_maxisys -- IO system ------------------------- port map ( - CLK => CLK, - RESET => CPU_RESET, - CP_CNTL => CP_CNTL, - CP_ADDR => CP_ADDR, - CP_DIN => CP_DIN, - CP_STAT => CP_STAT, - CP_DOUT => CP_DOUT, - EI_PRI => EI_PRI, - EI_VECT => EI_VECT, - EI_ACKM => EI_ACKM, - EM_MREQ => EM_MREQ, - EM_SRES => EM_SRES, - BRESET => BRESET, - IB_MREQ_M => IB_MREQ, - IB_SRES_M => IB_SRES, - DM_STAT_DP => DM_STAT_DP, - DM_STAT_VM => DM_STAT_VM, - DM_STAT_CO => DM_STAT_CO - ); - - CACHE: pdp11_cache - port map ( - CLK => CLK, - GRESET => CPU_RESET, - EM_MREQ => EM_MREQ, - EM_SRES => EM_SRES, - FMISS => CACHE_FMISS, - CHIT => CACHE_CHIT, - MEM_REQ => MEM_REQ, - MEM_WE => MEM_WE, - MEM_BUSY => MEM_BUSY, - MEM_ACK_R => MEM_ACK_R, - MEM_ADDR => MEM_ADDR, - MEM_BE => MEM_BE, - MEM_DI => MEM_DI, - MEM_DO => MEM_DO + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => GRESET, + BRESET => BRESET, + ITIMER => ITIMER, + CPUSUSP => CP_STAT.cpususp, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG ); - - MEM70: pdp11_mem70 - port map ( - CLK => CLK, - CRESET => BRESET, - HM_ENA => HM_ENA, - HM_VAL => CACHE_CHIT, - CACHE_FMISS => MEM70_FMISS, - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_MEM70 - ); - - HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; - CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; - + MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) - SRAM_CTL: nx_cram_memctl_as + SRAM_CTL: nx_cram_memctl_as -- memory controller ----------------- generic map ( READ0DELAY => sys_conf_memctl_read0delay, READ1DELAY => sys_conf_memctl_read1delay, WRITEDELAY => sys_conf_memctl_writedelay) port map ( CLK => CLK, - RESET => CPU_RESET, + RESET => GRESET, REQ => MEM_REQ, WE => MEM_WE, BUSY => MEM_BUSY, @@ -513,35 +418,12 @@ begin O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled O_PPCM_RST_N <= '1'; -- - - IB_SRES_OR : ib_sres_or_2 - port map ( - IB_SRES_1 => IB_SRES_MEM70, - IB_SRES_2 => IB_SRES_IBDR, - IB_SRES_OR => IB_SRES - ); - IBDR_SYS : ibdr_maxisys + LED_IO : ioleds_sp1c_fx2 -- hio leds from serport or fx2 ------ port map ( CLK => CLK, CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC, - RESET => CPU_RESET, - BRESET => BRESET, - RB_LAM => RB_LAM(15 downto 1), - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_IBDR, - EI_ACKM => EI_ACKM, - EI_PRI => EI_PRI, - EI_VECT => EI_VECT, - DISPREG => DISPREG - ); - - LED_IO : ioleds_sp1c_fx2 - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - RESET => CPU_RESET, + RESET => GRESET, ENAFX2 => SWI(2), RB_SRES => RB_SRES, RLB_MONI => RLB_MONI, @@ -549,53 +431,53 @@ begin IOLEDS => DSP_DP ); - LED_CPU : pdp11_statleds + ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; + + HIO70 : pdp11_hio70 -- hio from sys70 -------------------- + generic map ( + LWIDTH => LED'length, + DCWIDTH => 2) port map ( + SEL_LED => SWI(3), + SEL_DSP => SWI(5 downto 4), MEM_ACT_R => MEM_ACT_R, MEM_ACT_W => MEM_ACT_W, CP_STAT => CP_STAT, DM_STAT_DP => DM_STAT_DP, - STATLEDS => STATLEDS - ); - - LED_MUX : pdp11_ledmux - generic map ( - LWIDTH => LED'length) - port map ( - SEL => SWI(3), - STATLEDS => STATLEDS, - DM_STAT_DP => DM_STAT_DP, - LED => LED - ); - - ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; - - DSP_MUX : pdp11_dspmux - generic map ( - DCWIDTH => 2) - port map ( - SEL => SWI(5 downto 4), ABCLKDIV => ABCLKDIV, - DM_STAT_DP => DM_STAT_DP, DISPREG => DISPREG, + LED => LED, DSP_DAT => DSP_DAT ); - --- synthesis translate_off - DM_STAT_SY.emmreq <= EM_MREQ; - DM_STAT_SY.emsres <= EM_SRES; - DM_STAT_SY.chit <= CACHE_CHIT; - - TMU : pdp11_tmu_sb + + HIO : sn_humanio_rbus -- hio manager ----------------------- generic map ( - ENAPIN => 13) + BWIDTH => 5, + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) port map ( - CLK => CLK, - DM_STAT_DP => DM_STAT_DP, - DM_STAT_VM => DM_STAT_VM, - DM_STAT_CO => DM_STAT_CO, - DM_STAT_SY => DM_STAT_SY + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- + port map ( + RB_SRES_1 => RB_SRES_CPU, + RB_SRES_2 => RB_SRES_HIO, + RB_SRES_OR => RB_SRES ); --- synthesis translate_on end syn; diff --git a/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd index 9afece5e..c5142c18 100644 --- a/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 647 2015-02-17 22:35:36Z mueller $ +-- $Id: sys_conf_sim.vhd 672 2015-05-02 21:58:28Z mueller $ -- -- Copyright 2011-2015 by Walter F.J. Mueller -- @@ -19,6 +19,7 @@ -- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-03-14 658 1.5 add sys_conf_ibd_* definitions -- 2015-02-15 647 1.4 drop bram and minisys options -- 2014-12-22 619 1.3.1 add _rbmon_awidth -- 2013-10-06 538 1.3 pll support, use clksys_vcodivide ect @@ -33,31 +34,49 @@ use work.slvtypes.all; package sys_conf is + -- configure clocks -------------------------------------------------------- constant sys_conf_clksys_vcodivide : positive := 25; constant sys_conf_clksys_vcomultiply : positive := 18; -- dcm 72 MHz constant sys_conf_clksys_outdivide : positive := 1; -- sys 72 MHz constant sys_conf_clksys_gentype : string := "DCM"; - constant sys_conf_memctl_read0delay : positive := 4; -- for <75 MHz - constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; - constant sys_conf_memctl_writedelay : positive := 5; - + -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim - - constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_hio_debounce : boolean := false; -- no debouncers -- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec constant sys_conf_fx2_petowidth : positive := 10; constant sys_conf_fx2_ccwidth : positive := 5; - - constant sys_conf_hio_debounce : boolean := false; -- no debouncers + -- configure memory controller --------------------------------------------- + constant sys_conf_memctl_read0delay : positive := 4; -- for <75 MHz + constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; + constant sys_conf_memctl_writedelay : positive := 5; + + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable rbmon + + -- configure w11 cpu core -------------------------------------------------- constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte ---constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled - -- derived constants + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= constant sys_conf_clksys : integer := ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / @@ -65,15 +84,3 @@ package sys_conf is constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; end package sys_conf; - --- Note: mem_losize holds 16 MSB of the PA of the addressable memory --- 2 211 111 111 110 000 000 000 --- 1 098 765 432 109 876 543 210 --- --- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte --- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte --- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte --- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte --- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte --- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte --- upper 256 kB excluded for 11/70 UB diff --git a/rtl/sys_gen/w11a/nexys4/sys_conf.vhd b/rtl/sys_gen/w11a/nexys4/sys_conf.vhd index 646d7c26..2e731467 100644 --- a/rtl/sys_gen/w11a/nexys4/sys_conf.vhd +++ b/rtl/sys_gen/w11a/nexys4/sys_conf.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf.vhd 643 2015-02-07 17:41:53Z mueller $ +-- $Id: sys_conf.vhd 672 2015-05-02 21:58:28Z mueller $ -- -- Copyright 2013-2015 by Walter F.J. Mueller -- @@ -19,6 +19,7 @@ -- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions -- 2015-02-07 643 1.1 drop bram and minisys options -- 2013-09-22 534 1.0 Initial version (derived from _n3 version) ------------------------------------------------------------------------------ @@ -39,6 +40,7 @@ use work.slvtypes.all; package sys_conf is + -- configure clocks -------------------------------------------------------- constant sys_conf_clksys_vcodivide : positive := 1; constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz @@ -49,21 +51,39 @@ package sys_conf is constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- configure memory controller --------------------------------------------- constant sys_conf_memctl_read0delay : positive := 5; constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; constant sys_conf_memctl_writedelay : positive := 5; - constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud - - constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon + -- configure w11 cpu core -------------------------------------------------- constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte ---constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled - -- derived constants + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= constant sys_conf_clksys : integer := ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / sys_conf_clksys_outdivide; @@ -78,15 +98,3 @@ package sys_conf is (sys_conf_clkser/sys_conf_ser2rri_defbaud)-1; end package sys_conf; - --- Note: mem_losize holds 16 MSB of the PA of the addressable memory --- 2 211 111 111 110 000 000 000 --- 1 098 765 432 109 876 543 210 --- --- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte --- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte --- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte --- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte --- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte --- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte --- upper 256 kB excluded for 11/70 UB diff --git a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom index 304d7ade..9c540220 100644 --- a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom +++ b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom @@ -17,21 +17,14 @@ sys_conf = sys_conf.vhd [ghdl]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_4line_iob.vbom -../../../bplib/bpgen/sn_humanio_rbus.vbom ../../../vlib/rlink/rlink_sp1c.vbom -../../../vlib/rbus/rb_sres_or_3.vbom -../../../w11a/pdp11_core_rbus.vbom -../../../w11a/pdp11_core.vbom -../../../w11a/pdp11_cache.vbom -../../../w11a/pdp11_mem70.vbom -../../../bplib/nxcramlib/nx_cram_memctl_as.vbom -../../../ibus/ib_sres_or_2.vbom +../../../w11a/pdp11_sys70.vbom ../../../ibus/ibdr_maxisys.vbom +../../../bplib/nxcramlib/nx_cram_memctl_as.vbom ../../../vlib/rlink/ioleds_sp1c.vbom -../../../w11a/pdp11_statleds.vbom -../../../w11a/pdp11_ledmux.vbom -../../../w11a/pdp11_dspmux.vbom -[sim]../../../w11a/pdp11_tmu_sb.vbom +../../../w11a/pdp11_hio70.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../ibus/ib_sres_or_2.vbom # design sys_w11a_n4.vhd # constraints diff --git a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd index 02708fee..87ee7dd0 100644 --- a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd +++ b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_n4.vhd 650 2015-02-22 21:39:47Z mueller $ +-- $Id: sys_w11a_n4.vhd 677 2015-05-09 21:52:32Z mueller $ -- -- Copyright 2013-2015 by Walter F.J. Mueller -- @@ -18,21 +18,14 @@ -- Dependencies: vlib/xlib/s7_cmt_sfs -- vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_4line_iob --- bplib/bpgen/sn_humanio_rbus -- vlib/rlink/rlink_sp1c --- vlib/rbus/rb_sres_or_3 --- w11a/pdp11_core_rbus --- w11a/pdp11_core --- w11a/pdp11_cache --- w11a/pdp11_mem70 --- bplib/nxcramlib/nx_cram_memctl_as --- ibus/ib_sres_or_2 +-- w11a/pdp11_sys70 -- ibus/ibdr_maxisys --- vlib/rlink/ioleds_sp1c --- w11a/pdp11_statleds --- w11a/pdp11_ledmux --- w11a/pdp11_dspmux --- w11a/pdp11_tmu_sb [sim only] +-- bplib/nxcramlib/nx_cram_memctl_as +-- bplib/fx2rlink/ioleds_sp1c +-- w11a/pdp11_hio70 +-- bplib/bpgen/sn_humanio_rbus +-- vlib/rbus/rb_sres_or_2 -- -- Test bench: tb/tb_sys_w11a_n4 -- @@ -46,6 +39,9 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-05-09 677 2.1 start/stop/suspend overhaul; ; reset overhaul +-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 +-- 2015-04-11 666 1.4.2 rearrange XON handling -- 2015-02-21 649 1.4.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) -- 2015-02-07 643 1.4 new DSP+LED layout, use pdp11_dr; drop bram and -- minisys options; @@ -156,50 +152,36 @@ architecture syn of sys_w11a_n4 is signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + signal RXD : slbit := '1'; signal TXD : slbit := '0'; signal RTS_N : slbit := '0'; signal CTS_N : slbit := '0'; - signal SWI : slv16 := (others=>'0'); - signal BTN : slv5 := (others=>'0'); - signal LED : slv16 := (others=>'0'); - signal DSP_DAT : slv32 := (others=>'0'); - signal DSP_DP : slv8 := (others=>'0'); + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); signal SER_MONI : serport_moni_type := serport_moni_init; - signal RB_MREQ : rb_mreq_type := rb_mreq_init; - signal RB_SRES : rb_sres_type := rb_sres_init; - signal RB_SRES_CPU : rb_sres_type := rb_sres_init; - signal RB_SRES_IBD : rb_sres_type := rb_sres_init; - signal RB_SRES_HIO : rb_sres_type := rb_sres_init; - - signal RESET : slbit := '0'; - signal CE_USEC : slbit := '0'; - signal CE_MSEC : slbit := '0'; - - signal CPU_RESET : slbit := '0'; - signal CP_CNTL : cp_cntl_type := cp_cntl_init; - signal CP_ADDR : cp_addr_type := cp_addr_init; - signal CP_DIN : slv16 := (others=>'0'); - signal CP_STAT : cp_stat_type := cp_stat_init; - signal CP_DOUT : slv16 := (others=>'0'); - + signal GRESET : slbit := '0'; -- general reset (from rbus) + signal CRESET : slbit := '0'; -- cpu reset (from cp) + signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) + signal ITIMER : slbit := '0'; + signal EI_PRI : slv3 := (others=>'0'); signal EI_VECT : slv9_2 := (others=>'0'); signal EI_ACKM : slbit := '0'; - - signal EM_MREQ : em_mreq_type := em_mreq_init; - signal EM_SRES : em_sres_type := em_sres_init; - - signal HM_ENA : slbit := '0'; - signal MEM70_FMISS : slbit := '0'; - signal CACHE_FMISS : slbit := '0'; - signal CACHE_CHIT : slbit := '0'; + + signal CP_STAT : cp_stat_type := cp_stat_init; + signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; signal MEM_REQ : slbit := '0'; signal MEM_WE : slbit := '0'; @@ -214,25 +196,21 @@ architecture syn of sys_w11a_n4 is signal MEM_ADDR_EXT : slv22 := (others=>'0'); - signal BRESET : slbit := '0'; signal IB_MREQ : ib_mreq_type := ib_mreq_init; - signal IB_SRES : ib_sres_type := ib_sres_init; - - signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init; - signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; - - signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; - signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; - signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; - signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; + signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; signal DISPREG : slv16 := (others=>'0'); signal STATLEDS : slv8 := (others=>'0'); signal ABCLKDIV : slv16 := (others=>'0'); + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv32 := (others=>'0'); + signal DSP_DP : slv8 := (others=>'0'); + + constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx - constant rbaddr_ibus0 : slv16 := x"4000"; -- 4000/1000: 0100 xxxx xxxx xxxx - constant rbaddr_core0 : slv16 := x"0000"; -- 0000/0020: 0000 0000 000x xxxx begin @@ -240,7 +218,7 @@ begin report "assert sys_conf_clksys on MHz grid" severity failure; - GEN_CLKSYS : s7_cmt_sfs + GEN_CLKSYS : s7_cmt_sfs -- clock generator ------------------- generic map ( VCO_DIVIDE => sys_conf_clksys_vcodivide, VCO_MULTIPLY => sys_conf_clksys_vcomultiply, @@ -255,7 +233,7 @@ begin LOCKED => open ); - CLKDIV : clkdivce + CLKDIV : clkdivce -- usec/msec clock divider ----------- generic map ( CDUWIDTH => 7, USECDIV => sys_conf_clksys_mhz, @@ -266,7 +244,7 @@ begin CE_MSEC => CE_MSEC ); - IOB_RS232 : bp_rs232_4line_iob + IOB_RS232 : bp_rs232_4line_iob -- serport iob ---------------------- port map ( CLK => CLK, RXD => RXD, @@ -279,7 +257,145 @@ begin O_RTS_N => O_RTS_N ); - HIO : sn_humanio_rbus + RLINK : rlink_sp1c -- rlink for serport ----------------- + generic map ( + BTOWIDTH => 7, -- 128 cycles access timeout + RTAWIDTH => 12, + SYSID => (others=>'0'), + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 13, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => sys_conf_rbmon_awidth, + RBMON_RBADDR => rbaddr_rbmon) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ESCFILL => '0', + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM_CPU => RB_LAM(0), + GRESET => GRESET, + CRESET => CRESET, + BRESET => BRESET, + CP_STAT => CP_STAT, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + ITIMER => ITIMER, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO, + DM_STAT_DP => DM_STAT_DP + ); + + IBDR_SYS : ibdr_maxisys -- IO system ------------------------- + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => GRESET, + BRESET => BRESET, + ITIMER => ITIMER, + CPUSUSP => CP_STAT.cpususp, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG + ); + + MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) + + CRAM_CTL: nx_cram_memctl_as -- memory controller ----------------- + generic map ( + READ0DELAY => sys_conf_memctl_read0delay, + READ1DELAY => sys_conf_memctl_read1delay, + WRITEDELAY => sys_conf_memctl_writedelay) + port map ( + CLK => CLK, + RESET => GRESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => open, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR_EXT, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + LED_IO : ioleds_sp1c -- hio leds from serport ------------- + port map ( + SER_MONI => SER_MONI, + IOLEDS => DSP_DP(3 downto 0) + ); + DSP_DP(7 downto 4) <= "0010"; + ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; + + HIO70 : pdp11_hio70 -- hio from sys70 -------------------- + generic map ( + LWIDTH => LED'length, + DCWIDTH => 3) + port map ( + SEL_LED => SWI(3), + SEL_DSP => SWI(5 downto 4), + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + CP_STAT => CP_STAT, + DM_STAT_DP => DM_STAT_DP, + ABCLKDIV => ABCLKDIV, + DISPREG => DISPREG, + LED => LED, + DSP_DAT => DSP_DAT + ); + + HIO : sn_humanio_rbus -- hio manager ----------------------- generic map ( SWIDTH => 16, BWIDTH => 5, @@ -304,233 +420,16 @@ begin O_ANO_N => O_ANO_N, O_SEG_N => O_SEG_N ); - - RLINK : rlink_sp1c - generic map ( - BTOWIDTH => 7, -- 128 cycles access timeout - RTAWIDTH => 12, - SYSID => (others=>'0'), - IFAWIDTH => 5, -- 32 word input fifo - OFAWIDTH => 5, -- 32 word output fifo - ENAPIN_RLMON => sbcntl_sbf_rlmon, - ENAPIN_RBMON => sbcntl_sbf_rbmon, - CDWIDTH => 13, - CDINIT => sys_conf_ser2rri_cdinit) - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC, - CE_INT => CE_MSEC, - RESET => RESET, - ENAXON => SWI(1), - ENAESC => SWI(1), - RXSD => RXD, - TXSD => TXD, - CTS_N => CTS_N, - RTS_N => RTS_N, - RB_MREQ => RB_MREQ, - RB_SRES => RB_SRES, - RB_LAM => RB_LAM, - RB_STAT => RB_STAT, - RL_MONI => open, - SER_MONI => SER_MONI - ); - - RB_SRES_OR : rb_sres_or_3 + + RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- port map ( RB_SRES_1 => RB_SRES_CPU, - RB_SRES_2 => RB_SRES_IBD, - RB_SRES_3 => RB_SRES_HIO, + RB_SRES_2 => RB_SRES_HIO, RB_SRES_OR => RB_SRES ); - RB2CP : pdp11_core_rbus - generic map ( - RB_ADDR_CORE => rbaddr_core0, - RB_ADDR_IBUS => rbaddr_ibus0) - port map ( - CLK => CLK, - RESET => RESET, - RB_MREQ => RB_MREQ, - RB_SRES => RB_SRES_CPU, - RB_STAT => RB_STAT, - RB_LAM => RB_LAM(0), - CPU_RESET => CPU_RESET, - CP_CNTL => CP_CNTL, - CP_ADDR => CP_ADDR, - CP_DIN => CP_DIN, - CP_STAT => CP_STAT, - CP_DOUT => CP_DOUT - ); - - W11A : pdp11_core - port map ( - CLK => CLK, - RESET => CPU_RESET, - CP_CNTL => CP_CNTL, - CP_ADDR => CP_ADDR, - CP_DIN => CP_DIN, - CP_STAT => CP_STAT, - CP_DOUT => CP_DOUT, - EI_PRI => EI_PRI, - EI_VECT => EI_VECT, - EI_ACKM => EI_ACKM, - EM_MREQ => EM_MREQ, - EM_SRES => EM_SRES, - BRESET => BRESET, - IB_MREQ_M => IB_MREQ, - IB_SRES_M => IB_SRES, - DM_STAT_DP => DM_STAT_DP, - DM_STAT_VM => DM_STAT_VM, - DM_STAT_CO => DM_STAT_CO - ); - - CACHE: pdp11_cache - port map ( - CLK => CLK, - GRESET => CPU_RESET, - EM_MREQ => EM_MREQ, - EM_SRES => EM_SRES, - FMISS => CACHE_FMISS, - CHIT => CACHE_CHIT, - MEM_REQ => MEM_REQ, - MEM_WE => MEM_WE, - MEM_BUSY => MEM_BUSY, - MEM_ACK_R => MEM_ACK_R, - MEM_ADDR => MEM_ADDR, - MEM_BE => MEM_BE, - MEM_DI => MEM_DI, - MEM_DO => MEM_DO - ); - - MEM70: pdp11_mem70 - port map ( - CLK => CLK, - CRESET => BRESET, - HM_ENA => HM_ENA, - HM_VAL => CACHE_CHIT, - CACHE_FMISS => MEM70_FMISS, - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_MEM70 - ); - - HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; - CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; - - MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) - - CRAM_CTL: nx_cram_memctl_as - generic map ( - READ0DELAY => sys_conf_memctl_read0delay, - READ1DELAY => sys_conf_memctl_read1delay, - WRITEDELAY => sys_conf_memctl_writedelay) - port map ( - CLK => CLK, - RESET => CPU_RESET, - REQ => MEM_REQ, - WE => MEM_WE, - BUSY => MEM_BUSY, - ACK_R => MEM_ACK_R, - ACK_W => open, - ACT_R => MEM_ACT_R, - ACT_W => MEM_ACT_W, - ADDR => MEM_ADDR_EXT, - BE => MEM_BE, - DI => MEM_DI, - DO => MEM_DO, - O_MEM_CE_N => O_MEM_CE_N, - O_MEM_BE_N => O_MEM_BE_N, - O_MEM_WE_N => O_MEM_WE_N, - O_MEM_OE_N => O_MEM_OE_N, - O_MEM_ADV_N => O_MEM_ADV_N, - O_MEM_CLK => O_MEM_CLK, - O_MEM_CRE => O_MEM_CRE, - I_MEM_WAIT => I_MEM_WAIT, - O_MEM_ADDR => O_MEM_ADDR, - IO_MEM_DATA => IO_MEM_DATA - ); - - IB_SRES_OR : ib_sres_or_2 - port map ( - IB_SRES_1 => IB_SRES_MEM70, - IB_SRES_2 => IB_SRES_IBDR, - IB_SRES_OR => IB_SRES - ); - - IBDR_SYS : ibdr_maxisys - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC, - RESET => CPU_RESET, - BRESET => BRESET, - RB_LAM => RB_LAM(15 downto 1), - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_IBDR, - EI_ACKM => EI_ACKM, - EI_PRI => EI_PRI, - EI_VECT => EI_VECT, - DISPREG => DISPREG - ); - - LED_IO : ioleds_sp1c - port map ( - SER_MONI => SER_MONI, - IOLEDS => DSP_DP(3 downto 0) - ); - DSP_DP(7 downto 4) <= "0010"; - - LED_CPU : pdp11_statleds - port map ( - MEM_ACT_R => MEM_ACT_R, - MEM_ACT_W => MEM_ACT_W, - CP_STAT => CP_STAT, - DM_STAT_DP => DM_STAT_DP, - STATLEDS => STATLEDS - ); - - LED_MUX : pdp11_ledmux - generic map ( - LWIDTH => LED'length) - port map ( - SEL => SWI(3), - STATLEDS => STATLEDS, - DM_STAT_DP => DM_STAT_DP, - LED => LED - ); - - ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; - - DSP_MUX : pdp11_dspmux - generic map ( - DCWIDTH => 3) - port map ( - SEL => SWI(5 downto 4), - ABCLKDIV => ABCLKDIV, - DM_STAT_DP => DM_STAT_DP, - DISPREG => DISPREG, - DSP_DAT => DSP_DAT - ); - -- setup unused outputs in nexys4 O_RGBLED0 <= (others=>'0'); O_RGBLED1 <= (others=>not I_BTNRST_N); - --- synthesis translate_off - DM_STAT_SY.emmreq <= EM_MREQ; - DM_STAT_SY.emsres <= EM_SRES; - DM_STAT_SY.chit <= CACHE_CHIT; - - TMU : pdp11_tmu_sb - generic map ( - ENAPIN => 13) - port map ( - CLK => CLK, - DM_STAT_DP => DM_STAT_DP, - DM_STAT_VM => DM_STAT_VM, - DM_STAT_CO => DM_STAT_CO, - DM_STAT_SY => DM_STAT_SY - ); --- synthesis translate_on end syn; diff --git a/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd index 0f96416b..8a7b8252 100644 --- a/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd @@ -1,4 +1,4 @@ --- $Id: sys_conf_sim.vhd 647 2015-02-17 22:35:36Z mueller $ +-- $Id: sys_conf_sim.vhd 672 2015-05-02 21:58:28Z mueller $ -- -- Copyright 2013-2015 by Walter F.J. Mueller -- @@ -19,6 +19,7 @@ -- Tool versions: xst 14.5-14.7; ghdl 0.29-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions -- 2015-02-07 643 1.1 drop bram and minisys options -- 2013-09-34 534 1.0 Initial version (cloned from _n3) ------------------------------------------------------------------------------ @@ -30,6 +31,7 @@ use work.slvtypes.all; package sys_conf is + -- configure clocks -------------------------------------------------------- constant sys_conf_clksys_vcodivide : positive := 1; constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz @@ -40,21 +42,39 @@ package sys_conf is constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- configure memory controller --------------------------------------------- constant sys_conf_memctl_read0delay : positive := 6; -- for 100 MHz constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; constant sys_conf_memctl_writedelay : positive := 7; - constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim - - constant sys_conf_hio_debounce : boolean := false; -- no debouncers - + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon + + -- configure w11 cpu core -------------------------------------------------- constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte ---constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled - -- derived constants + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= constant sys_conf_clksys : integer := ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / sys_conf_clksys_outdivide; @@ -66,15 +86,3 @@ package sys_conf is constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; end package sys_conf; - --- Note: mem_losize holds 16 MSB of the PA of the addressable memory --- 2 211 111 111 110 000 000 000 --- 1 098 765 432 109 876 543 210 --- --- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte --- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte --- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte --- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte --- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte --- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte --- upper 256 kB excluded for 11/70 UB diff --git a/rtl/sys_gen/w11a/s3board/sys_conf.vhd b/rtl/sys_gen/w11a/s3board/sys_conf.vhd index 92755830..f25ac3c3 100644 --- a/rtl/sys_gen/w11a/s3board/sys_conf.vhd +++ b/rtl/sys_gen/w11a/s3board/sys_conf.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf.vhd 619 2014-12-23 13:17:41Z mueller $ +-- $Id: sys_conf.vhd 673 2015-05-03 08:34:52Z mueller $ -- --- Copyright 2007-2014 by Walter F.J. Mueller +-- Copyright 2007-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,6 +19,7 @@ -- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions -- 2014-12-22 619 1.1.2 add _rbmon_awidth -- 2010-05-05 288 1.1.1 add sys_conf_hio_debounce -- 2008-02-23 118 1.1 add memory config @@ -32,31 +33,31 @@ use work.slvtypes.all; package sys_conf is - constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_cdinit : integer := 434-1; -- 50000000/115200 + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- configure debug and monitoring units ------------------------------------ constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon - constant sys_conf_bram : integer := 0; -- no bram, use cache - constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB) + -- configure w11 cpu core -------------------------------------------------- constant sys_conf_mem_losize : integer := 8#037777#; -- 1 MByte ---constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) - --- constant sys_conf_bram : integer := 1; -- bram only --- constant sys_conf_bram_awidth : integer := 15; -- bram size (32 kB) --- constant sys_conf_mem_losize : integer := 8#000777#; -- 32 kByte constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled -end package sys_conf; + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 --- Note: mem_losize holds 16 MSB of the PA of the addressable memory --- 2 211 111 111 110 000 000 000 --- 1 098 765 432 109 876 543 210 --- --- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte --- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte --- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte --- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte --- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte --- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte --- upper 256 kB excluded for 11/70 UB + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + +end package sys_conf; diff --git a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom index 2d4a9ce8..f88ec70a 100644 --- a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom +++ b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vbom @@ -3,9 +3,9 @@ ../../../vlib/genlib/genlib.vhd ../../../vlib/serport/serportlib.vbom ../../../vlib/rbus/rblib.vhd -../../../vlib/rbus/rbdlib.vhd ../../../vlib/rlink/rlinklib.vbom ../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom ../../../bplib/s3board/s3boardlib.vbom ../../../ibus/iblib.vhd ../../../ibus/ibdlib.vhd @@ -14,25 +14,14 @@ sys_conf = sys_conf.vhd # components ../../../vlib/genlib/clkdivce.vbom ../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom -../../../bplib/bpgen/sn_humanio.vbom ../../../vlib/rlink/rlink_sp1c.vbom -../../../vlib/rbus/rb_sres_or_3.vbom -../../../vlib/rbus/rbd_rbmon.vbom -../../../w11a/pdp11_core_rbus.vbom -../../../w11a/pdp11_core.vbom -../../../w11a/pdp11_bram.vbom -../../../bplib/s3board/s3_sram_dummy.vbom -../../../w11a/pdp11_cache.vbom -../../../w11a/pdp11_mem70.vbom -../../../bplib/s3board/s3_sram_memctl.vbom -../../../ibus/ib_sres_or_2.vbom -../../../ibus/ibdr_minisys.vbom +../../../w11a/pdp11_sys70.vbom ../../../ibus/ibdr_maxisys.vbom +../../../bplib/s3board/s3_sram_memctl.vbom ../../../vlib/rlink/ioleds_sp1c.vbom -../../../w11a/pdp11_statleds.vbom -../../../w11a/pdp11_ledmux.vbom -../../../w11a/pdp11_dspmux.vbom -[sim]../../../w11a/pdp11_tmu_sb.vbom +../../../w11a/pdp11_hio70.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../vlib/rbus/rb_sres_or_2.vbom # design sys_w11a_s3.vhd @ucf_cpp: sys_w11a_s3.ucf diff --git a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd index 05217f38..de2a9c9e 100644 --- a/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd +++ b/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_s3.vhd 652 2015-02-28 12:18:08Z mueller $ +-- $Id: sys_w11a_s3.vhd 677 2015-05-09 21:52:32Z mueller $ -- -- Copyright 2007-2015 by Walter F.J. Mueller -- @@ -17,25 +17,14 @@ -- -- Dependencies: vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_2l4l_iob --- bplib/bpgen/sn_humanio -- vlib/rlink/rlink_sp1c --- vlib/rbus/rb_sres_or_3 --- vlib/rbus/rbd_rbmon --- w11a/pdp11_core_rbus --- w11a/pdp11_core --- w11a/pdp11_bram --- vlib/s3board/s3_sram_dummy --- w11a/pdp11_cache --- w11a/pdp11_mem70 --- bplib/s3board/s3_sram_memctl --- ibus/ib_sres_or_2 --- ibus/ibdr_minisys +-- w11a/pdp11_sys70 -- ibus/ibdr_maxisys +-- bplib/s3board/s3_sram_memctl -- vlib/rlink/ioleds_sp1c --- w11a/pdp11_statleds --- w11a/pdp11_ledmux --- w11a/pdp11_dspmux --- w11a/pdp11_tmu_sb [sim only] +-- w11a/pdp11_hio70 +-- bplib/bpgen/sn_humanio_rbus +-- vlib/rbus/rb_sres_or_2 -- -- Test bench: tb/tb_sys_w11a_s3 -- @@ -44,6 +33,7 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2015-05-02 673 14.7 131013 xc3s1000-4 2054 6196 350 3858 OK: +RHRP 50% -- 2015-02-21 649 14.7 131013 xc3s1000-4 1643 5124 318 3176 OK: +RL11 -- 2014-12-22 619 14.7 131013 xc3s1000-4 1569 4768 302 2994 OK: +rbmon -- 2014-12-20 614 14.7 131013 xc3s1000-4 1455 4523 302 2807 OK: -RL11,rlv4 @@ -83,6 +73,9 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul +-- 2015-05-02 673 2.0 use pdp11_sys70 and pdp11_hio70; now in std form +-- 2015-04-11 666 1.7.1 rearrange XON handling -- 2015-02-21 649 1.7 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) -- 2014-12-24 620 1.6.2 relocate ibus window and hio rbus address -- 2014-12-22 619 1.6.1 add rbus monitor rbd_rbmon @@ -186,9 +179,9 @@ use work.slvtypes.all; use work.genlib.all; use work.serportlib.all; use work.rblib.all; -use work.rbdlib.all; use work.rlinklib.all; use work.bpgenlib.all; +use work.bpgenrbuslib.all; use work.s3boardlib.all; use work.iblib.all; use work.ibdlib.all; @@ -225,51 +218,43 @@ architecture syn of sys_w11a_s3 is signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + signal RXD : slbit := '1'; signal TXD : slbit := '0'; signal RTS_N : slbit := '0'; signal CTS_N : slbit := '0'; - signal SWI : slv8 := (others=>'0'); - signal BTN : slv4 := (others=>'0'); - signal LED : slv8 := (others=>'0'); - signal DSP_DAT : slv16 := (others=>'0'); - signal DSP_DP : slv4 := (others=>'0'); + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); signal SER_MONI : serport_moni_type := serport_moni_init; - signal RB_MREQ : rb_mreq_type := rb_mreq_init; - signal RB_SRES : rb_sres_type := rb_sres_init; - signal RB_SRES_CPU : rb_sres_type := rb_sres_init; - signal RB_SRES_IBD : rb_sres_type := rb_sres_init; - signal RB_SRES_RBMON : rb_sres_type := rb_sres_init; + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); - signal RESET : slbit := '0'; - signal CE_USEC : slbit := '0'; - signal CE_MSEC : slbit := '0'; - - signal CPU_RESET : slbit := '0'; - signal CP_CNTL : cp_cntl_type := cp_cntl_init; - signal CP_ADDR : cp_addr_type := cp_addr_init; - signal CP_DIN : slv16 := (others=>'0'); - signal CP_STAT : cp_stat_type := cp_stat_init; - signal CP_DOUT : slv16 := (others=>'0'); + signal GRESET : slbit := '0'; -- general reset (from rbus) + signal CRESET : slbit := '0'; -- cpu reset (from cp) + signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) + signal ITIMER : slbit := '0'; signal EI_PRI : slv3 := (others=>'0'); signal EI_VECT : slv9_2 := (others=>'0'); signal EI_ACKM : slbit := '0'; - - signal EM_MREQ : em_mreq_type := em_mreq_init; - signal EM_SRES : em_sres_type := em_sres_init; - - signal HM_ENA : slbit := '0'; - signal MEM70_FMISS : slbit := '0'; - signal CACHE_FMISS : slbit := '0'; - signal CACHE_CHIT : slbit := '0'; + signal CP_STAT : cp_stat_type := cp_stat_init; + signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; + signal MEM_REQ : slbit := '0'; signal MEM_WE : slbit := '0'; signal MEM_BUSY : slbit := '0'; @@ -281,32 +266,21 @@ architecture syn of sys_w11a_s3 is signal MEM_DI : slv32 := (others=>'0'); signal MEM_DO : slv32 := (others=>'0'); - signal BRESET : slbit := '0'; signal IB_MREQ : ib_mreq_type := ib_mreq_init; - signal IB_SRES : ib_sres_type := ib_sres_init; - - signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init; signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; - signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; - signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; - signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; - signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; - signal DISPREG : slv16 := (others=>'0'); signal STATLEDS : slv8 := (others=>'0'); signal ABCLKDIV : slv16 := (others=>'0'); constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx - constant rbaddr_ibus0 : slv16 := x"4000"; -- 4000/1000: 0100 xxxx xxxx xxxx - constant rbaddr_core0 : slv16 := x"0000"; -- 0000/0020: 0000 0000 000x xxxx begin CLK <= I_CLK50; -- use 50MHz as system clock - CLKDIV : clkdivce + CLKDIV : clkdivce -- usec/msec clock divider ----------- generic map ( CDUWIDTH => 6, USECDIV => 50, @@ -317,7 +291,7 @@ begin CE_MSEC => CE_MSEC ); - IOB_RS232 : bp_rs232_2l4l_iob + IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ---------------- port map ( CLK => CLK, RESET => '0', @@ -334,26 +308,7 @@ begin O_RTS1_N => O_FUSP_RTS_N ); - HIO : sn_humanio - generic map ( - DEBOUNCE => sys_conf_hio_debounce) - port map ( - CLK => CLK, - RESET => RESET, - CE_MSEC => CE_MSEC, - SWI => SWI, - BTN => BTN, - LED => LED, - DSP_DAT => DSP_DAT, - DSP_DP => DSP_DP, - I_SWI => I_SWI, - I_BTN => I_BTN, - O_LED => O_LED, - O_ANO_N => O_ANO_N, - O_SEG_N => O_SEG_N - ); - - RLINK : rlink_sp1c + RLINK : rlink_sp1c -- rlink for serport ----------------- generic map ( BTOWIDTH => 6, -- 64 cycles access timeout RTAWIDTH => 12, @@ -363,7 +318,9 @@ begin ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, CDWIDTH => 13, - CDINIT => sys_conf_ser2rri_cdinit) + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => sys_conf_rbmon_awidth, + RBMON_RBADDR => rbaddr_rbmon) port map ( CLK => CLK, CE_USEC => CE_USEC, @@ -371,7 +328,7 @@ begin CE_INT => CE_MSEC, RESET => RESET, ENAXON => SWI(1), - ENAESC => SWI(1), + ESCFILL => '0', RXSD => RXD, TXSD => TXD, CTS_N => CTS_N, @@ -384,263 +341,127 @@ begin SER_MONI => SER_MONI ); - RB_SRES_OR : rb_sres_or_3 + SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- port map ( - RB_SRES_1 => RB_SRES_CPU, - RB_SRES_2 => RB_SRES_IBD, - RB_SRES_3 => RB_SRES_RBMON, - RB_SRES_OR => RB_SRES + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM_CPU => RB_LAM(0), + GRESET => GRESET, + CRESET => CRESET, + BRESET => BRESET, + CP_STAT => CP_STAT, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + ITIMER => ITIMER, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO, + DM_STAT_DP => DM_STAT_DP + ); + + IBDR_SYS : ibdr_maxisys -- IO system ------------------------- + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => GRESET, + BRESET => BRESET, + ITIMER => ITIMER, + CPUSUSP => CP_STAT.cpususp, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG); + + SRAM_CTL: s3_sram_memctl -- memory controller ----------------- + port map ( + CLK => CLK, + RESET => GRESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => open, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR(17 downto 0), + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA ); - RBMON : if sys_conf_rbmon_awidth > 0 generate - begin - RBMON : rbd_rbmon - generic map ( - RB_ADDR => rbaddr_rbmon, - AWIDTH => sys_conf_rbmon_awidth) - port map ( - CLK => CLK, - RESET => RESET, - RB_MREQ => RB_MREQ, - RB_SRES => RB_SRES_RBMON, - RB_SRES_SUM => RB_SRES - ); - end generate RBMON; - - RP2CP : pdp11_core_rbus - generic map ( - RB_ADDR_CORE => rbaddr_core0, - RB_ADDR_IBUS => rbaddr_ibus0) - port map ( - CLK => CLK, - RESET => RESET, - RB_MREQ => RB_MREQ, - RB_SRES => RB_SRES_CPU, - RB_STAT => RB_STAT, - RB_LAM => RB_LAM(0), - CPU_RESET => CPU_RESET, - CP_CNTL => CP_CNTL, - CP_ADDR => CP_ADDR, - CP_DIN => CP_DIN, - CP_STAT => CP_STAT, - CP_DOUT => CP_DOUT - ); - - W11A : pdp11_core - port map ( - CLK => CLK, - RESET => CPU_RESET, - CP_CNTL => CP_CNTL, - CP_ADDR => CP_ADDR, - CP_DIN => CP_DIN, - CP_STAT => CP_STAT, - CP_DOUT => CP_DOUT, - EI_PRI => EI_PRI, - EI_VECT => EI_VECT, - EI_ACKM => EI_ACKM, - EM_MREQ => EM_MREQ, - EM_SRES => EM_SRES, - BRESET => BRESET, - IB_MREQ_M => IB_MREQ, - IB_SRES_M => IB_SRES, - DM_STAT_DP => DM_STAT_DP, - DM_STAT_VM => DM_STAT_VM, - DM_STAT_CO => DM_STAT_CO - ); - - MEM_BRAM: if sys_conf_bram > 0 generate - signal HM_VAL_BRAM : slbit := '0'; - begin - - MEM : pdp11_bram - generic map ( - AWIDTH => sys_conf_bram_awidth) - port map ( - CLK => CLK, - GRESET => CPU_RESET, - EM_MREQ => EM_MREQ, - EM_SRES => EM_SRES - ); - - HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write - - MEM70: pdp11_mem70 - port map ( - CLK => CLK, - CRESET => BRESET, - HM_ENA => EM_MREQ.req, - HM_VAL => HM_VAL_BRAM, - CACHE_FMISS => MEM70_FMISS, - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_MEM70 - ); - - SRAM_PROT : s3_sram_dummy -- connect SRAM to protection dummy - port map ( - O_MEM_CE_N => O_MEM_CE_N, - O_MEM_BE_N => O_MEM_BE_N, - O_MEM_WE_N => O_MEM_WE_N, - O_MEM_OE_N => O_MEM_OE_N, - O_MEM_ADDR => O_MEM_ADDR, - IO_MEM_DATA => IO_MEM_DATA - ); - - end generate MEM_BRAM; - - MEM_SRAM: if sys_conf_bram = 0 generate - - CACHE: pdp11_cache - port map ( - CLK => CLK, - GRESET => CPU_RESET, - EM_MREQ => EM_MREQ, - EM_SRES => EM_SRES, - FMISS => CACHE_FMISS, - CHIT => CACHE_CHIT, - MEM_REQ => MEM_REQ, - MEM_WE => MEM_WE, - MEM_BUSY => MEM_BUSY, - MEM_ACK_R => MEM_ACK_R, - MEM_ADDR => MEM_ADDR, - MEM_BE => MEM_BE, - MEM_DI => MEM_DI, - MEM_DO => MEM_DO - ); - - MEM70: pdp11_mem70 - port map ( - CLK => CLK, - CRESET => BRESET, - HM_ENA => HM_ENA, - HM_VAL => CACHE_CHIT, - CACHE_FMISS => MEM70_FMISS, - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_MEM70 - ); - - HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; - CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; - - SRAM_CTL: s3_sram_memctl - port map ( - CLK => CLK, - RESET => CPU_RESET, - REQ => MEM_REQ, - WE => MEM_WE, - BUSY => MEM_BUSY, - ACK_R => MEM_ACK_R, - ACK_W => open, - ACT_R => MEM_ACT_R, - ACT_W => MEM_ACT_W, - ADDR => MEM_ADDR(17 downto 0), - BE => MEM_BE, - DI => MEM_DI, - DO => MEM_DO, - O_MEM_CE_N => O_MEM_CE_N, - O_MEM_BE_N => O_MEM_BE_N, - O_MEM_WE_N => O_MEM_WE_N, - O_MEM_OE_N => O_MEM_OE_N, - O_MEM_ADDR => O_MEM_ADDR, - IO_MEM_DATA => IO_MEM_DATA - ); - - end generate MEM_SRAM; - - IB_SRES_OR : ib_sres_or_2 - port map ( - IB_SRES_1 => IB_SRES_MEM70, - IB_SRES_2 => IB_SRES_IBDR, - IB_SRES_OR => IB_SRES); - - IBD_MINI : if false generate - begin - IBDR_SYS : ibdr_minisys - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC, - RESET => CPU_RESET, - BRESET => BRESET, - RB_LAM => RB_LAM(15 downto 1), - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_IBDR, - EI_ACKM => EI_ACKM, - EI_PRI => EI_PRI, - EI_VECT => EI_VECT, - DISPREG => DISPREG); - end generate IBD_MINI; - - IBD_MAXI : if true generate - begin - IBDR_SYS : ibdr_maxisys - port map ( - CLK => CLK, - CE_USEC => CE_USEC, - CE_MSEC => CE_MSEC, - RESET => CPU_RESET, - BRESET => BRESET, - RB_LAM => RB_LAM(15 downto 1), - IB_MREQ => IB_MREQ, - IB_SRES => IB_SRES_IBDR, - EI_ACKM => EI_ACKM, - EI_PRI => EI_PRI, - EI_VECT => EI_VECT, - DISPREG => DISPREG); - end generate IBD_MAXI; - - LED_IO : ioleds_sp1c + LED_IO : ioleds_sp1c -- hio leds from serport ------------- port map ( SER_MONI => SER_MONI, IOLEDS => DSP_DP ); - LED_CPU : pdp11_statleds + ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; + + HIO70 : pdp11_hio70 -- hio from sys70 -------------------- + generic map ( + LWIDTH => LED'length, + DCWIDTH => 2) port map ( + SEL_LED => SWI(3), + SEL_DSP => SWI(5 downto 4), MEM_ACT_R => MEM_ACT_R, MEM_ACT_W => MEM_ACT_W, CP_STAT => CP_STAT, DM_STAT_DP => DM_STAT_DP, - STATLEDS => STATLEDS - ); - - LED_MUX : pdp11_ledmux - generic map ( - LWIDTH => LED'length) - port map ( - SEL => SWI(3), - STATLEDS => STATLEDS, - DM_STAT_DP => DM_STAT_DP, - LED => LED - ); - - ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; - - DSP_MUX : pdp11_dspmux - generic map ( - DCWIDTH => 2) - port map ( - SEL => SWI(5 downto 4), ABCLKDIV => ABCLKDIV, - DM_STAT_DP => DM_STAT_DP, DISPREG => DISPREG, + LED => LED, DSP_DAT => DSP_DAT ); - --- synthesis translate_off - DM_STAT_SY.emmreq <= EM_MREQ; - DM_STAT_SY.emsres <= EM_SRES; - DM_STAT_SY.chit <= CACHE_CHIT; - - TMU : pdp11_tmu_sb + + HIO : sn_humanio_rbus -- hio manager ----------------------- generic map ( - ENAPIN => 13) + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) port map ( - CLK => CLK, - DM_STAT_DP => DM_STAT_DP, - DM_STAT_VM => DM_STAT_VM, - DM_STAT_CO => DM_STAT_CO, - DM_STAT_SY => DM_STAT_SY + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N ); --- synthesis translate_on - + + RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- + port map ( + RB_SRES_1 => RB_SRES_CPU, + RB_SRES_2 => RB_SRES_HIO, + RB_SRES_OR => RB_SRES + ); + end syn; diff --git a/rtl/sys_gen/w11a/s3board/tb/sys_conf_sim.vhd b/rtl/sys_gen/w11a/s3board/tb/sys_conf_sim.vhd index 5f190d83..f4aca269 100644 --- a/rtl/sys_gen/w11a/s3board/tb/sys_conf_sim.vhd +++ b/rtl/sys_gen/w11a/s3board/tb/sys_conf_sim.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf_sim.vhd 619 2014-12-23 13:17:41Z mueller $ +-- $Id: sys_conf_sim.vhd 672 2015-05-02 21:58:28Z mueller $ -- --- Copyright 2007-2014 by Walter F.J. Mueller +-- Copyright 2007-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -19,6 +19,7 @@ -- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions -- 2014-12-22 619 1.1.2 add _rbmon_awidth -- 2010-05-05 288 1.1.1 add sys_conf_hio_debounce -- 2008-02-23 118 1.1 add memory config @@ -32,10 +33,15 @@ use work.slvtypes.all; package sys_conf is - constant sys_conf_hio_debounce : boolean := false; -- no debouncers + -- configure rlink and hio interfaces -------------------------------------- constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim - constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon + + -- configure w11 cpu core -------------------------------------------------- constant sys_conf_bram : integer := 0; -- no bram, use cache constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB) constant sys_conf_mem_losize : integer := 8#037777#; -- 1 MByte @@ -47,16 +53,19 @@ package sys_conf is constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + end package sys_conf; --- Note: mem_losize holds 16 MSB of the PA of the addressable memory --- 2 211 111 111 110 000 000 000 --- 1 098 765 432 109 876 543 210 --- --- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte --- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte --- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte --- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte --- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte --- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte --- upper 256 kB excluded for 11/70 UB diff --git a/rtl/vlib/rbus/rbd_rbmon.vhd b/rtl/vlib/rbus/rbd_rbmon.vhd index 29e27345..557e6a7a 100644 --- a/rtl/vlib/rbus/rbd_rbmon.vhd +++ b/rtl/vlib/rbus/rbd_rbmon.vhd @@ -1,6 +1,6 @@ --- $Id: rbd_rbmon.vhd 620 2014-12-25 10:48:35Z mueller $ +-- $Id: rbd_rbmon.vhd 672 2015-05-02 21:58:28Z mueller $ -- --- Copyright 2010-2014 by Walter F.J. Mueller +-- Copyright 2010-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -30,6 +30,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-05-02 672 5.0.1 use natural for AWIDTH to work around a ghdl issue -- 2014-12-22 619 5.0 reorganized, supports now 16 bit addresses -- 2014-09-13 593 4.1 change default address -> ffe8 -- 2014-08-15 583 4.0 rb_mreq addr now 16 bit (but only 8 bit recorded) @@ -45,9 +46,10 @@ -- 01 stop r/w/f writing 1 stops moni -- 00 start r/w/f writing 1 starts moni and clears addr -- 001 stat r/w/- Status register +-- 15:13 bsize r/-/- buffer size (AWIDTH-9) -- 00 wrap r/-/- line address wrapped (cleared on go) --- 010 hilim r/w/- upper address limit (def: 0xfffb) --- 011 lolim r/w/- lower address limit (def: 0x0000) +-- 010 hilim r/w/- upper address limit, inclusive (def: 0xfffb) +-- 011 lolim r/w/- lower address limit, inclusive (def: 0x0000) -- 100 addr r/w/- Address register -- *:02 laddr r/w/- line address -- 01:00 waddr r/w/- word address @@ -78,10 +80,14 @@ use work.slvtypes.all; use work.memlib.all; use work.rblib.all; +-- Note: AWIDTH has type natural to allow AWIDTH=0 can be used in if generates +-- to control the instantiation. ghdl checks even for not instantiated +-- entities the validity of generics, that's why natural needed here .... + entity rbd_rbmon is -- rbus dev: rbus monitor generic ( RB_ADDR : slv16 := slv(to_unsigned(16#ffe8#,16)); - AWIDTH : positive := 9); + AWIDTH : natural := 9); port ( CLK : in slbit; -- clock RESET : in slbit; -- reset diff --git a/rtl/vlib/rbus/rbdlib.vhd b/rtl/vlib/rbus/rbdlib.vhd index 12693b84..40dd911f 100644 --- a/rtl/vlib/rbus/rbdlib.vhd +++ b/rtl/vlib/rbus/rbdlib.vhd @@ -1,4 +1,4 @@ --- $Id: rbdlib.vhd 620 2014-12-25 10:48:35Z mueller $ +-- $Id: rbdlib.vhd 672 2015-05-02 21:58:28Z mueller $ -- -- Copyright 2010-2014 by Walter F.J. Mueller -- @@ -63,7 +63,7 @@ end component; component rbd_rbmon is -- rbus dev: rbus monitor generic ( RB_ADDR : slv16 := rbaddr_rbmon; - AWIDTH : positive := 9); + AWIDTH : natural := 9); port ( CLK : in slbit; -- clock RESET : in slbit; -- reset diff --git a/rtl/vlib/rlink/rlink_core8.vhd b/rtl/vlib/rlink/rlink_core8.vhd index 9f1a4a80..9991ae93 100644 --- a/rtl/vlib/rlink/rlink_core8.vhd +++ b/rtl/vlib/rlink/rlink_core8.vhd @@ -1,4 +1,4 @@ --- $Id: rlink_core8.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: rlink_core8.vhd 666 2015-04-12 21:17:54Z mueller $ -- -- Copyright 2011-2014 by Walter F.J. Mueller -- @@ -32,6 +32,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-11 666 4.1 add ESCXON,ESCFILL in signals, for cdata2byte -- 2014-10-12 596 4.0 now rlink v4 iface, 4 bit STAT -- 2011-12-09 437 1.0 Initial version ------------------------------------------------------------------------------ @@ -57,6 +58,8 @@ entity rlink_core8 is -- rlink core with 8bit interface CLK : in slbit; -- clock CE_INT : in slbit := '0'; -- rlink ato time unit clock enable RESET : in slbit; -- reset + ESCXON : in slbit; -- enable xon/xoff escaping + ESCFILL : in slbit; -- enable fill escaping RLB_DI : in slv8; -- rlink 8b: data in RLB_ENA : in slbit; -- rlink 8b: data enable RLB_BUSY : out slbit; -- rlink 8b: data busy @@ -129,8 +132,8 @@ begin port map ( CLK => CLK, RESET => RESET, - ESCXON => '0', - ESCFILL => '0', + ESCXON => ESCXON, + ESCFILL => ESCFILL, DI => RL_DO, ENA => RL_VAL, BUSY => RL_HOLD, diff --git a/rtl/vlib/rlink/rlink_sp1c.vbom b/rtl/vlib/rlink/rlink_sp1c.vbom index 8223d4e2..fa232511 100644 --- a/rtl/vlib/rlink/rlink_sp1c.vbom +++ b/rtl/vlib/rlink/rlink_sp1c.vbom @@ -1,10 +1,13 @@ # libs ../slvtypes.vhd ../rbus/rblib.vhd +../rbus/rbdlib.vhd rlinklib.vbom ../serport/serportlib.vbom # components rlink_core8.vbom ../serport/serport_1clock.vbom +../rbus/rbd_rbmon.vbom +../rbus/rb_sres_or_2.vbom # design rlink_sp1c.vhd diff --git a/rtl/vlib/rlink/rlink_sp1c.vhd b/rtl/vlib/rlink/rlink_sp1c.vhd index 1c98e496..ddbe8e7b 100644 --- a/rtl/vlib/rlink/rlink_sp1c.vhd +++ b/rtl/vlib/rlink/rlink_sp1c.vhd @@ -1,6 +1,6 @@ --- $Id: rlink_sp1c.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: rlink_sp1c.vhd 672 2015-05-02 21:58:28Z mueller $ -- --- Copyright 2011-2014 by Walter F.J. Mueller +-- Copyright 2011-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -17,6 +17,8 @@ -- -- Dependencies: rlink_core8 -- serport/serport_1clock +-- rbus/rbd_rbmon +-- rbus/rb_sres_or_2 -- -- Test bench: - -- @@ -25,10 +27,13 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri ifa ofa +-- 2015-05-02 672 14.7 131013 xc6slx16-2 495 671 56 255 s 8.8 - - -- 2011-12-09 437 13.1 O40d xc3s1000-4 337 733 64 469 s 9.8 - - -- -- Revision History: -- Date Rev Version Comment +-- 2015-05-02 672 4.2 add rbd_rbmon (optional via generics) +-- 2015-04-11 666 4.1 rename ENAESC->ESCFILL, rearrange XON handling -- 2014-08-28 588 4.0 use rlink v4 iface, 4 bit STAT -- 2011-12-09 437 1.0 Initial version ------------------------------------------------------------------------------ @@ -39,6 +44,7 @@ use ieee.numeric_std.all; use work.slvtypes.all; use work.rblib.all; +use work.rbdlib.all; use work.rlinklib.all; use work.serportlib.all; @@ -53,7 +59,9 @@ entity rlink_sp1c is -- rlink_core8+serport_1clock combo ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none) ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none) CDWIDTH : positive := 13; -- clk divider width - CDINIT : natural := 15); -- clk divider initial/reset setting + CDINIT : natural := 15; -- clk divider initial/reset setting + RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none) + RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr port ( CLK : in slbit; -- clock CE_USEC : in slbit; -- 1 usec clock enable @@ -61,7 +69,7 @@ entity rlink_sp1c is -- rlink_core8+serport_1clock combo CE_INT : in slbit := '0'; -- rri ato time unit clock enable RESET : in slbit; -- reset ENAXON : in slbit; -- enable xon/xoff handling - ENAESC : in slbit; -- enable xon/xoff escaping + ESCFILL : in slbit; -- enable fill escaping RXSD : in slbit; -- receive serial data (board view) TXSD : out slbit; -- transmit serial data (board view) CTS_N : in slbit := '0'; -- clear to send (act.low, board view) @@ -85,9 +93,13 @@ architecture syn of rlink_sp1c is signal RLB_VAL : slbit := '0'; signal RLB_HOLD : slbit := '0'; + signal RB_MREQ_M : rb_mreq_type := rb_mreq_init; + signal RB_SRES_M : rb_sres_type := rb_sres_init; + signal RB_SRES_RBMON : rb_sres_type := rb_sres_init; + begin - CORE : rlink_core8 + CORE : rlink_core8 -- rlink master ---------------------- generic map ( BTOWIDTH => BTOWIDTH, RTAWIDTH => RTAWIDTH, @@ -99,6 +111,8 @@ begin CLK => CLK, CE_INT => CE_INT, RESET => RESET, + ESCXON => ENAXON, + ESCFILL => ESCFILL, RLB_DI => RLB_DI, RLB_ENA => RLB_ENA, RLB_BUSY => RLB_BUSY, @@ -106,13 +120,13 @@ begin RLB_VAL => RLB_VAL, RLB_HOLD => RLB_HOLD, RL_MONI => RL_MONI, - RB_MREQ => RB_MREQ, - RB_SRES => RB_SRES, + RB_MREQ => RB_MREQ_M, + RB_SRES => RB_SRES_M, RB_LAM => RB_LAM, RB_STAT => RB_STAT ); - SERPORT : serport_1clock + SERPORT : serport_1clock -- serport interface ----------------- generic map ( CDWIDTH => CDWIDTH, CDINIT => CDINIT, @@ -123,7 +137,7 @@ begin CE_MSEC => CE_MSEC, RESET => RESET, ENAXON => ENAXON, - ENAESC => ENAESC, + ENAESC => '0', -- escaping now in rlink_core8 RXDATA => RLB_DI, RXVAL => RLB_ENA, RXHOLD => RLB_BUSY, @@ -137,4 +151,28 @@ begin TXCTS_N => CTS_N ); + RBMON : if RBMON_AWIDTH > 0 generate -- rbus monitor -------------- + begin + I0 : rbd_rbmon + generic map ( + RB_ADDR => RBMON_RBADDR, + AWIDTH => RBMON_AWIDTH) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ_M, + RB_SRES => RB_SRES_RBMON, + RB_SRES_SUM => RB_SRES_M + ); + end generate RBMON; + + RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- + port map ( + RB_SRES_1 => RB_SRES, + RB_SRES_2 => RB_SRES_RBMON, + RB_SRES_OR => RB_SRES_M + ); + + RB_MREQ <= RB_MREQ_M; -- setup output signals + end syn; diff --git a/rtl/vlib/rlink/rlinklib.vhd b/rtl/vlib/rlink/rlinklib.vhd index ae435648..53f57487 100644 --- a/rtl/vlib/rlink/rlinklib.vhd +++ b/rtl/vlib/rlink/rlinklib.vhd @@ -1,4 +1,4 @@ --- $Id: rlinklib.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: rlinklib.vhd 672 2015-05-02 21:58:28Z mueller $ -- -- Copyright 2007-2015 by Walter F.J. Mueller -- @@ -20,7 +20,10 @@ -- -- Revision History: -- Date Rev Version Comment --- 2014-02-21 649 4.1.1 add ioleds_sp1c +-- +-- 2015-04-11 666 4.1.2 rlink_core8: add ESC(XON|FILL); +-- rlink_sp1c: rename ENAESC->ESCFILL +-- 2015-02-21 649 4.1.1 add ioleds_sp1c -- 2014-12-21 617 4.1 use stat(2) to signal rbus timeout -- 2014-10-12 596 4.0 now rlink v4.0 iface, 4 bit STAT -- 2014-08-15 583 3.5 rb_mreq addr now 16 bit @@ -171,6 +174,8 @@ component rlink_core8 is -- rlink core with 8bit iface CLK : in slbit; -- clock CE_INT : in slbit := '0'; -- rlink ato time unit clock enable RESET : in slbit; -- reset + ESCXON : in slbit := '0'; -- enable xon/xoff escaping + ESCFILL : in slbit := '0'; -- enable fill escaping RLB_DI : in slv8; -- rlink 8b: data in RLB_ENA : in slbit; -- rlink 8b: data enable RLB_BUSY : out slbit; -- rlink 8b: data busy @@ -224,15 +229,17 @@ component rlink_sp1c is -- rlink_core8+serport_1clock combo ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none) ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none) CDWIDTH : positive := 13; -- clk divider width - CDINIT : natural := 15); -- clk divider initial/reset setting + CDINIT : natural := 15; -- clk divider initial/reset setting + RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none) + RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr port ( CLK : in slbit; -- clock CE_USEC : in slbit; -- 1 usec clock enable CE_MSEC : in slbit; -- 1 msec clock enable CE_INT : in slbit := '0'; -- rri ato time unit clock enable RESET : in slbit; -- reset - ENAXON : in slbit; -- enable xon/xoff handling - ENAESC : in slbit; -- enable xon/xoff escaping + ENAXON : in slbit := '0'; -- enable xon/xoff handling + ESCFILL : in slbit := '0'; -- enable fill escaping RXSD : in slbit; -- receive serial data (board view) TXSD : out slbit; -- transmit serial data (board view) CTS_N : in slbit := '0'; -- clear to send (act.low, board view) diff --git a/rtl/vlib/rlink/tb/tbu_rlink_sp1c.vhd b/rtl/vlib/rlink/tb/tbu_rlink_sp1c.vhd index 8f2534cc..114564f8 100644 --- a/rtl/vlib/rlink/tb/tbu_rlink_sp1c.vhd +++ b/rtl/vlib/rlink/tb/tbu_rlink_sp1c.vhd @@ -1,6 +1,6 @@ --- $Id: tbu_rlink_sp1c.vhd 593 2014-09-14 22:21:33Z mueller $ +-- $Id: tbu_rlink_sp1c.vhd 666 2015-04-12 21:17:54Z mueller $ -- --- Copyright 2007-2014 by Walter F.J. Mueller +-- Copyright 2007-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -36,6 +36,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-11 666 4.1 rename ENAESC->ESCFILL -- 2014-08-31 590 4.0 now full rlink v4 iface, 4 bit STAT -- 2014-08-15 583 3.5 rb_mreq addr now 16 bit -- 2011-12-22 442 3.2 renamed and retargeted to test rlink_sp1c @@ -138,7 +139,7 @@ begin CE_INT => CE_INT, RESET => RESET, ENAXON => '0', - ENAESC => '0', + ESCFILL => '0', RXSD => RXSD, TXSD => TXSD, CTS_N => CTS_N, diff --git a/rtl/vlib/serport/serport_1clock.vhd b/rtl/vlib/serport/serport_1clock.vhd index d1a920e4..448ec5e2 100644 --- a/rtl/vlib/serport/serport_1clock.vhd +++ b/rtl/vlib/serport/serport_1clock.vhd @@ -1,4 +1,4 @@ --- $Id: serport_1clock.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: serport_1clock.vhd 666 2015-04-12 21:17:54Z mueller $ -- -- Copyright 2011-2015 by Walter F.J. Mueller -- @@ -25,10 +25,12 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2015-04-12 666 14.7 131013 xc6slx16-2 171 239 32 94 s 6.3 -- 2011-11-13 424 13.1 O40d xc3s1000-4 157 337 64 232 s 9.9 -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-11 666 1.1.1 add sim assertions for RXOVR and RXERR -- 2015-02-01 641 1.1 add CLKDIV_F for autobaud; -- 2011-12-10 438 1.0.2 internal reset on abact -- 2011-12-09 437 1.0.1 rename stat->moni port @@ -251,4 +253,22 @@ begin MONI.abclkdiv_f <= ABCLKDIV_F; end process proc_abclkdiv; +-- synthesis translate_off + + proc_check: process (CLK) + begin + if rising_edge(CLK) then + assert RXOVR = '0' + report "serport_1clock-W: RXOVR = " & slbit'image(RXOVR) & + "; data loss in receive fifo" + severity warning; + assert RXERR = '0' + report "serport_1clock-W: RXERR = " & slbit'image(RXERR) & + "; spurious receive error" + severity warning; + end if; + end process proc_check; + +-- synthesis translate_on + end syn; diff --git a/rtl/vlib/serport/serport_2clock.vhd b/rtl/vlib/serport/serport_2clock.vhd index 7f12b95a..bad11409 100644 --- a/rtl/vlib/serport/serport_2clock.vhd +++ b/rtl/vlib/serport/serport_2clock.vhd @@ -1,4 +1,4 @@ --- $Id: serport_2clock.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: serport_2clock.vhd 666 2015-04-12 21:17:54Z mueller $ -- -- Copyright 2011-2015 by Walter F.J. Mueller -- @@ -26,10 +26,12 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2015-04-12 666 14.7 131013 xc6slx16-2 285 283 32 138 s 6.2/5.9 -- 2011-11-13 424 13.1 O40d xc3s1000-4 224 362 64 295 s 8.6/10.1 -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-11 666 1.1.1 add sim assertions for RXOVR and RXERR -- 2015-02-01 641 1.1 add CLKDIV_F for autobaud; -- 2011-12-10 438 1.0.2 internal reset on abact -- 2011-12-09 437 1.0.1 rename stat->moni port @@ -382,5 +384,19 @@ begin MONI.abclkdiv <= (others=>'0'); MONI.abclkdiv(R_SYNU.abclkdiv_s'range) <= R_SYNU.abclkdiv_s; end process proc_abclkdiv; + +-- synthesis translate_off + + proc_check: process (CLKS) + begin + assert RXOVR = '0' + report "serport_2clock-W: RXOVR = '1'; data loss in receive fifo" + severity warning; + assert RXERR = '0' + report "serport_2clock-W: RXERR = '1'; spurious receive error" + severity warning; + end process proc_check; + +-- synthesis translate_on end syn; diff --git a/rtl/vlib/serport/serport_master.vbom b/rtl/vlib/serport/serport_master.vbom new file mode 100644 index 00000000..f508a528 --- /dev/null +++ b/rtl/vlib/serport/serport_master.vbom @@ -0,0 +1,9 @@ +# libs +../slvtypes.vhd +serportlib.vbom +# components +serport_uart_rxtx.vbom +serport_xonrx.vbom +serport_xontx.vbom +# design +serport_master.vhd diff --git a/rtl/vlib/serport/serport_master.vhd b/rtl/vlib/serport/serport_master.vhd new file mode 100644 index 00000000..c21776b6 --- /dev/null +++ b/rtl/vlib/serport/serport_master.vhd @@ -0,0 +1,142 @@ +-- $Id: serport_master.vhd 666 2015-04-12 21:17:54Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: serport_master - syn +-- Description: serial port: serial port module, master side +-- +-- Dependencies: serport_uart_rxtx_ab +-- serport_xonrx +-- serport_xontx +-- Test bench: - +-- Target Devices: generic +-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2015-04-12 666 14.7 131013 xc6slx16-2 104 171 0 63 s 6.4 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-04-12 666 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.serportlib.all; + +entity serport_master is -- serial port module, 1 clock domain + generic ( + CDWIDTH : positive := 13); -- clk divider width + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting + ENAXON : in slbit := '0'; -- enable xon/xoff handling + ENAESC : in slbit := '0'; -- enable xon/xoff escaping + RXDATA : out slv8; -- receiver data out + RXVAL : out slbit; -- receiver data valid + RXERR : out slbit; -- receiver data error (frame error) + RXOK : in slbit := '1'; -- rx channel ok + TXDATA : in slv8; -- transmit data in + TXENA : in slbit; -- transmit data enable + TXBUSY : out slbit; -- transmit busy + RXSD : in slbit; -- receive serial data (uart view) + TXSD : out slbit; -- transmit serial data (uart view) + RXRTS_N : out slbit; -- receive rts (uart view, act.low) + TXCTS_N : in slbit := '0' -- transmit cts (uart view, act.low) + ); +end serport_master; + + +architecture syn of serport_master is + + signal UART_RXDATA : slv8 := (others=>'0'); + signal UART_RXVAL : slbit := '0'; + signal UART_TXDATA : slv8 := (others=>'0'); + signal UART_TXENA : slbit := '0'; + signal UART_TXBUSY : slbit := '0'; + + signal XONTX_TXENA : slbit := '0'; + signal XONTX_TXBUSY : slbit := '0'; + + signal TXOK : slbit := '0'; + +begin + + UART : serport_uart_rxtx -- uart, rx+tx combo + generic map ( + CDWIDTH => CDWIDTH) + port map ( + CLK => CLK, + RESET => RESET, + CLKDIV => CLKDIV, + RXSD => RXSD, + RXDATA => UART_RXDATA, + RXVAL => UART_RXVAL, + RXERR => RXERR, + RXACT => open, + TXSD => TXSD, + TXDATA => UART_TXDATA, + TXENA => UART_TXENA, + TXBUSY => UART_TXBUSY + ); + + XONRX : serport_xonrx -- xon/xoff logic rx path + port map ( + CLK => CLK, + RESET => RESET, + ENAXON => ENAXON, + ENAESC => ENAESC, + UART_RXDATA => UART_RXDATA, + UART_RXVAL => UART_RXVAL, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => '0', + RXOVR => open, + TXOK => TXOK + ); + + XONTX : serport_xontx -- xon/xoff logic tx path + port map ( + CLK => CLK, + RESET => RESET, + ENAXON => ENAXON, + ENAESC => ENAESC, + UART_TXDATA => UART_TXDATA, + UART_TXENA => XONTX_TXENA, + UART_TXBUSY => XONTX_TXBUSY, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + RXOK => RXOK, + TXOK => TXOK + ); + + RXRTS_N <= not RXOK; + + proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY) + begin + if TXCTS_N = '0' then -- transmit cts asserted + UART_TXENA <= XONTX_TXENA; + XONTX_TXBUSY <= UART_TXBUSY; + else -- transmit cts not asserted + UART_TXENA <= '0'; + XONTX_TXBUSY <= '1'; + end if; + end process proc_cts; + +end syn; diff --git a/rtl/vlib/serport/serport_uart_rxtx_ab.vhd b/rtl/vlib/serport/serport_uart_rxtx_ab.vhd index 1b60bff2..04f7f25b 100644 --- a/rtl/vlib/serport/serport_uart_rxtx_ab.vhd +++ b/rtl/vlib/serport/serport_uart_rxtx_ab.vhd @@ -1,4 +1,4 @@ --- $Id: serport_uart_rxtx_ab.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: serport_uart_rxtx_ab.vhd 666 2015-04-12 21:17:54Z mueller $ -- -- Copyright 2007-2015 by Walter F.J. Mueller -- @@ -23,6 +23,7 @@ -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri +-- 2015-04-12 666 14.7 131013 xc6slx16-2 100 142 0 48 s 6.2 -- 2010-12-25 348 12.1 M53d xc3s1000-4 99 197 - 124 s 9.8 -- -- Revision History: diff --git a/rtl/vlib/serport/serportlib.vhd b/rtl/vlib/serport/serportlib.vhd index b5ac8f22..3bfc5e52 100644 --- a/rtl/vlib/serport/serportlib.vhd +++ b/rtl/vlib/serport/serportlib.vhd @@ -1,4 +1,4 @@ --- $Id: serportlib.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: serportlib.vhd 666 2015-04-12 21:17:54Z mueller $ -- -- Copyright 2007-2015 by Walter F.J. Mueller -- @@ -20,10 +20,11 @@ -- -- Revision History: -- Date Rev Version Comment --- 2015-02-01 641 1.3 add CLKDIV_F for autobaud; +-- 2015-04-11 666 1.3.1 add serport_master +-- 2015-02-01 641 1.3 add CLKDIV_F for autobaud -- 2013-01-26 476 1.2.6 renamed package to serportlib -- 2011-12-09 437 1.2.5 rename stat->moni port --- 2011-10-23 419 1.2.4 remove serport_clkdiv_ consts; +-- 2011-10-23 419 1.2.4 remove serport_clkdiv_ consts -- 2011-10-22 417 1.2.3 add serport_xon(rx|tx) defs -- 2011-10-14 416 1.2.2 add c_serport defs -- 2010-12-26 348 1.2.1 add ABCLKDIV to serport_uart_rxtx_ab @@ -239,4 +240,27 @@ component serport_2clock is -- serial port module, 2 clock domain ); end component; +component serport_master is -- serial port module, master side + generic ( + CDWIDTH : positive := 13); -- clk divider width + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting + ENAXON : in slbit := '0'; -- enable xon/xoff handling + ENAESC : in slbit := '0'; -- enable xon/xoff escaping + RXDATA : out slv8; -- receiver data out + RXVAL : out slbit; -- receiver data valid + RXERR : out slbit; -- receiver data error (frame error) + RXOK : in slbit := '1'; -- rx channel ok + TXDATA : in slv8; -- transmit data in + TXENA : in slbit; -- transmit data enable + TXBUSY : out slbit; -- transmit busy + RXSD : in slbit; -- receive serial data (uart view) + TXSD : out slbit; -- transmit serial data (uart view) + RXRTS_N : out slbit; -- receive rts (uart view, act.low) + TXCTS_N : in slbit :='0' -- transmit cts (uart view, act.low) + ); +end component; + end package serportlib; diff --git a/rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd b/rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd index 6ab0e228..7411e00a 100644 --- a/rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd +++ b/rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd @@ -1,4 +1,4 @@ --- $Id: s7_cmt_sfs_gsim.vhd 554 2014-04-21 14:01:51Z mueller $ +-- $Id: s7_cmt_sfs_gsim.vhd 675 2015-05-08 21:05:08Z mueller $ -- -- Copyright 2013- by Walter F.J. Mueller -- @@ -19,7 +19,7 @@ -- Dependencies: - -- Test bench: - -- Target Devices: generic Series-7 --- Tool versions: xst 14.5; viv 2014.1; ghdl 0.29 +-- Tool versions: xst 14.5; viv 2014.4; ghdl 0.29 -- -- Revision History: -- Date Rev Version Comment diff --git a/rtl/w11a/pdp11.vhd b/rtl/w11a/pdp11.vhd index 877ffe85..13e3a5c0 100644 --- a/rtl/w11a/pdp11.vhd +++ b/rtl/w11a/pdp11.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: pdp11.vhd 677 2015-05-09 21:52:32Z mueller $ -- --- Copyright 2006-2014 by Walter F.J. Mueller +-- Copyright 2006-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,6 +20,9 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-05-09 677 1.6 start/stop/suspend overhaul; reset overhaul +-- 2015-05-01 672 1.5.5 add pdp11_sys70, sys_hio70 +-- 2015-04-30 670 1.5.4 rename pdp11_sys70 -> pdp11_reg70 -- 2015-02-20 649 1.5.3 add pdp11_statleds -- 2015-02-08 644 1.5.2 add pdp11_bram_memctl -- 2014-08-28 588 1.5.1 use new rlink v4 iface and 4 bit STAT @@ -343,12 +346,18 @@ package pdp11 is cmdmerr : slbit; -- command memory access error cpugo : slbit; -- CPU go state cpustep : slbit; -- CPU step flag - cpuhalt : slbit; -- CPU halt flag + cpususp : slbit; -- CPU susp flag cpuwait : slbit; -- CPU wait flag cpurust : slv4; -- CPU run status + suspint : slbit; -- internal suspend flag + suspext : slbit; -- external suspend flag cpfunc : slv5; -- current control port function cprnum : slv3; -- current control port register number waitsusp : slbit; -- WAIT instruction suspended + itimer : slbit; -- ITIMER pulse + creset : slbit; -- CRESET pulse + breset : slbit; -- BRESET pulse + intack : slbit; -- INT_ACK pulse intvect : slv9_2; -- current interrupt vector trap_mmu : slbit; -- mmu trace trap pending trap_ysv : slbit; -- ysv trap pending @@ -358,11 +367,13 @@ package pdp11 is end record cpustat_type; constant cpustat_init : cpustat_type := ( - '0','0','0','0', -- cmd.. - '0','0','0','0', -- cpu.. + '0','0','0','0', -- cmdbusy,cmdack,cmderr,cmdmerr + '0','0','0','0', -- cpugo,cpustep,cpususp,cpuwait c_cpurust_init, -- cpurust + '0','0', -- suspint,suspext "00000","000", -- cpfunc, cprnum '0', -- waitsusp + '0','0','0','0', -- itimer,creset,breset,intack (others=>'0'), -- intvect '0','0','0', -- trap_(mmu|ysv), prefdone '0','0' -- do_gprwe, do_intrsv @@ -529,18 +540,21 @@ package pdp11 is rnum : slv3; -- register number end record cp_cntl_type; - constant c_cpfunc_noop : slv5 := "00000"; -- noop : no operation - constant c_cpfunc_sta : slv5 := "00001"; -- sta : cpu start - constant c_cpfunc_sto : slv5 := "00010"; -- sto : cpu stop - constant c_cpfunc_cont : slv5 := "00011"; -- cont : cpu continue - constant c_cpfunc_step : slv5 := "00100"; -- step : cpu step - constant c_cpfunc_rst : slv5 := "01111"; -- rst : cpu reset (soft) - constant c_cpfunc_rreg : slv5 := "10000"; -- rreg : read register - constant c_cpfunc_wreg : slv5 := "10001"; -- wreg : write register - constant c_cpfunc_rpsw : slv5 := "10010"; -- rpsw : read psw - constant c_cpfunc_wpsw : slv5 := "10011"; -- wpsw : write psw - constant c_cpfunc_rmem : slv5 := "10100"; -- rmem : read memory - constant c_cpfunc_wmem : slv5 := "10101"; -- wmem : write memory + constant c_cpfunc_noop : slv5 := "00000"; -- noop : no operation + constant c_cpfunc_start : slv5 := "00001"; -- sta : cpu start + constant c_cpfunc_stop : slv5 := "00010"; -- sto : cpu stop + constant c_cpfunc_step : slv5 := "00011"; -- cont : cpu step + constant c_cpfunc_creset : slv5 := "00100"; -- step : cpu cpu reset + constant c_cpfunc_breset : slv5 := "00101"; -- rst : cpu bus reset + constant c_cpfunc_suspend : slv5 := "00110"; -- rst : cpu suspend + constant c_cpfunc_resume : slv5 := "00111"; -- rst : cpu resume + + constant c_cpfunc_rreg : slv5 := "10000"; -- rreg : read register + constant c_cpfunc_wreg : slv5 := "10001"; -- wreg : write register + constant c_cpfunc_rpsw : slv5 := "10010"; -- rpsw : read psw + constant c_cpfunc_wpsw : slv5 := "10011"; -- wpsw : write psw + constant c_cpfunc_rmem : slv5 := "10100"; -- rmem : read memory + constant c_cpfunc_wmem : slv5 := "10101"; -- wmem : write memory constant cp_cntl_init : cp_cntl_type := ('0',c_cpfunc_noop,"000"); @@ -551,15 +565,18 @@ package pdp11 is cmdmerr : slbit; -- command memory access error cpugo : slbit; -- CPU go state cpustep : slbit; -- CPU step flag - cpuhalt : slbit; -- CPU halt flag cpuwait : slbit; -- CPU wait flag + cpususp : slbit; -- CPU susp flag cpurust : slv4; -- CPU run status + suspint : slbit; -- internal suspend + suspext : slbit; -- external suspend end record cp_stat_type; constant cp_stat_init : cp_stat_type := ( '0','0','0','0', -- cmd... '0','0','0','0', -- cpu... - (others=>'0') -- cpurust + (others=>'0'), -- cpurust + '0','0' -- susp... ); type cp_addr_type is record -- control port address @@ -619,10 +636,15 @@ package pdp11 is type dm_stat_co_type is record -- debug and monitor status - core cpugo : slbit; -- cpugo state flag - cpuhalt : slbit; -- cpuhalt state flag + cpususp : slbit; -- cpususp state flag + suspint : slbit; -- suspint state flag + suspext : slbit; -- suspext state flag end record dm_stat_co_type; - constant dm_stat_co_init : dm_stat_co_type := ('0','0'); + constant dm_stat_co_init : dm_stat_co_type := ( + '0','0', -- cpu... + '0','0' -- susp... + ); type dm_stat_sy_type is record -- debug and monitor status - system emmreq : em_mreq_type; -- external memory: request @@ -630,7 +652,11 @@ package pdp11 is chit : slbit; -- cache hit end record dm_stat_sy_type; - constant dm_stat_sy_init : dm_stat_sy_type := (em_mreq_init,em_sres_init,'0'); + constant dm_stat_sy_init : dm_stat_sy_type := ( + em_mreq_init, -- emmreq + em_sres_init, -- emsres + '0' -- chit + ); -- rbus interface definitions ------------------------------------------------ @@ -659,11 +685,13 @@ package pdp11 is constant c_ah_rbf_ena_22bit: integer := 6; -- ah: 22bit subtype c_ah_rbf_addr is integer range 5 downto 0; -- ah: address - constant c_stat_rbf_cmderr: integer := 0; -- stat field: cmderr - constant c_stat_rbf_cmdmerr: integer := 1; -- stat field: cmdmerr - constant c_stat_rbf_cpugo: integer := 2; -- stat field: cpugo - constant c_stat_rbf_cpuhalt: integer := 3; -- stat field: cpuhalt + constant c_stat_rbf_suspext: integer := 9; -- stat field: suspext + constant c_stat_rbf_suspint: integer := 8; -- stat field: suspint subtype c_stat_rbf_cpurust is integer range 7 downto 4; -- cpurust + constant c_stat_rbf_cpususp: integer := 3; -- stat field: cpususp + constant c_stat_rbf_cpugo: integer := 2; -- stat field: cpugo + constant c_stat_rbf_cmdmerr: integer := 1; -- stat field: cmdmerr + constant c_stat_rbf_cmderr: integer := 0; -- stat field: cmderr subtype c_membe_rbf_be is integer range 1 downto 0; -- membe: be's constant c_membe_rbf_stick: integer := 2; -- membe: sticky flag @@ -694,7 +722,7 @@ constant c_gpr_pc : slv3 := "111"; -- register number of PC component pdp11_psr is -- processor status word register port ( CLK : in slbit; -- clock - CRESET : in slbit; -- console reset + CRESET : in slbit; -- cpu reset DIN : in slv16; -- input data CCIN : in slv4; -- cc input CCWE : in slbit; -- enable update cc @@ -843,7 +871,7 @@ end component; component pdp11_mmu_ssr12 is -- mmu register ssr1 and ssr2 port ( CLK : in slbit; -- clock - CRESET : in slbit; -- console reset + CRESET : in slbit; -- cpu reset TRACE : in slbit; -- trace enable MONI : in mmu_moni_type; -- MMU monitor port data IB_MREQ : in ib_mreq_type; -- ibus request @@ -854,8 +882,8 @@ end component; component pdp11_mmu is -- mmu - memory management unit port ( CLK : in slbit; -- clock - CRESET : in slbit; -- console reset - BRESET : in slbit; -- ibus reset + CRESET : in slbit; -- cpu reset + BRESET : in slbit; -- bus reset CNTL : in mmu_cntl_type; -- control port VADDR : in slv16; -- virtual address MONI : in mmu_moni_type; -- monitor port @@ -869,9 +897,9 @@ end component; component pdp11_vmbox is -- virtual memory port ( CLK : in slbit; -- clock - GRESET : in slbit; -- global reset - CRESET : in slbit; -- console reset - BRESET : in slbit; -- ibus reset + GRESET : in slbit; -- general reset + CRESET : in slbit; -- cpu reset + BRESET : in slbit; -- bus reset CP_ADDR : in cp_addr_type; -- console port address VM_CNTL : in vm_cntl_type; -- vm control port VM_ADDR : in slv16; -- vm address @@ -891,7 +919,7 @@ end component; component pdp11_dpath is -- CPU datapath port ( CLK : in slbit; -- clock - CRESET : in slbit; -- console reset + CRESET : in slbit; -- cpu reset CNTL : in dpath_cntl_type; -- control interface STAT : out dpath_stat_type; -- status interface CP_DIN : in slv16; -- console port data in @@ -904,7 +932,7 @@ component pdp11_dpath is -- CPU datapath VM_DIN : out slv16; -- virt. memory data in IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type; -- ibus response - DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status + DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status - dpath ); end component; @@ -918,7 +946,7 @@ end component; component pdp11_sequencer is -- cpu sequencer port ( CLK : in slbit; -- clock - GRESET : in slbit; -- global reset + GRESET : in slbit; -- general reset PSW : in psw_type; -- processor status PC : in slv16; -- program counter IREG : in slv16; -- IREG @@ -928,13 +956,18 @@ component pdp11_sequencer is -- cpu sequencer VM_STAT : in vm_stat_type; -- virtual memory status port INT_PRI : in slv3; -- interrupt priority INT_VECT : in slv9_2; -- interrupt vector - CRESET : out slbit; -- console reset - BRESET : out slbit; -- ibus reset + INT_ACK : out slbit; -- interrupt acknowledge + CRESET : out slbit; -- cpu reset + BRESET : out slbit; -- bus reset MMU_MONI : out mmu_moni_type; -- mmu monitor port DP_CNTL : out dpath_cntl_type; -- data path control VM_CNTL : out vm_cntl_type; -- virtual memory control port CP_STAT : out cp_stat_type; -- console port status - INT_ACK : out slbit; -- interrupt acknowledge + ESUSP_O : out slbit; -- external suspend output + ESUSP_I : in slbit; -- external suspend input + ITIMER : out slbit; -- instruction timer + EBREAK : in slbit; -- execution break + DBREAK : in slbit; -- data break IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type -- ibus response ); @@ -943,7 +976,7 @@ end component; component pdp11_irq is -- interrupt requester port ( CLK : in slbit; -- clock - BRESET : in slbit; -- ibus reset + BRESET : in slbit; -- bus reset INT_ACK : in slbit; -- interrupt acknowledge from CPU EI_PRI : in slv3; -- external interrupt priority EI_VECT : in slv9_2; -- external interrupt vector @@ -966,10 +999,10 @@ component pdp11_ubmap is -- 11/70 unibus mapper ); end component; -component pdp11_sys70 is -- 11/70 memory system registers +component pdp11_reg70 is -- 11/70 memory system registers port ( CLK : in slbit; -- clock - CRESET : in slbit; -- console reset + CRESET : in slbit; -- cpu reset IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type -- ibus response ); @@ -978,7 +1011,7 @@ end component; component pdp11_mem70 is -- 11/70 memory system registers port ( CLK : in slbit; -- clock - CRESET : in slbit; -- console reset + CRESET : in slbit; -- cpu reset HM_ENA : in slbit; -- hit/miss enable HM_VAL : in slbit; -- hit/miss value CACHE_FMISS : out slbit; -- cache force miss @@ -990,7 +1023,7 @@ end component; component pdp11_cache is -- cache port ( CLK : in slbit; -- clock - GRESET : in slbit; -- global reset + GRESET : in slbit; -- general reset EM_MREQ : in em_mreq_type; -- em request EM_SRES : out em_sres_type; -- em response FMISS : in slbit; -- force miss @@ -1015,12 +1048,18 @@ component pdp11_core is -- full processor core CP_DIN : in slv16; -- console data in CP_STAT : out cp_stat_type; -- console status port CP_DOUT : out slv16; -- console data out + ESUSP_O : out slbit; -- external suspend output + ESUSP_I : in slbit; -- external suspend input + ITIMER : out slbit; -- instruction timer + EBREAK : in slbit; -- execution break + DBREAK : in slbit; -- data break EI_PRI : in slv3; -- external interrupt priority EI_VECT : in slv9_2; -- external interrupt vector EI_ACKM : out slbit; -- external interrupt acknowledge EM_MREQ : out em_mreq_type; -- external memory: request EM_SRES : in em_sres_type; -- external memory: response - BRESET : out slbit; -- ibus reset + CRESET : out slbit; -- cpu reset + BRESET : out slbit; -- bus reset IB_MREQ_M : out ib_mreq_type; -- ibus master request (master) IB_SRES_M : in ib_sres_type; -- ibus slave response (master) DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath @@ -1033,10 +1072,10 @@ component pdp11_tmu is -- trace and monitor unit port ( CLK : in slbit; -- clock ENA : in slbit := '0'; -- enable trace output - DM_STAT_DP : in dm_stat_dp_type; -- DM dpath - DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox - DM_STAT_CO : in dm_stat_co_type; -- DM core - DM_STAT_SY : in dm_stat_sy_type -- DM system + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath + DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox + DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core + DM_STAT_SY : in dm_stat_sy_type -- debug and monitor status - system ); end component; @@ -1045,10 +1084,10 @@ component pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper ENAPIN : integer := 13); -- SB_CNTL signal to use for enable port ( CLK : in slbit; -- clock - DM_STAT_DP : in dm_stat_dp_type; -- DM dpath - DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox - DM_STAT_CO : in dm_stat_co_type; -- DM core - DM_STAT_SY : in dm_stat_sy_type -- DM system + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath + DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox + DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core + DM_STAT_SY : in dm_stat_sy_type -- debug and monitor status - system ); end component; @@ -1057,7 +1096,7 @@ component pdp11_du_drv is -- display unit low level driver CDWIDTH : positive := 3); -- clock divider width port ( CLK : in slbit; -- clock - GRESET : in slbit; -- global reset + GRESET : in slbit; -- general reset ROW0 : in slv22; -- led row 0 (22 leds, top) ROW1 : in slv16; -- led row 1 (16 leds) ROW2 : in slv16; -- led row 2 (16 leds) @@ -1076,7 +1115,7 @@ component pdp11_bram is -- BRAM based ext. memory dummy AWIDTH : positive := 14); -- address width port ( CLK : in slbit; -- clock - GRESET : in slbit; -- global reset + GRESET : in slbit; -- general reset EM_MREQ : in em_mreq_type; -- em request EM_SRES : out em_sres_type -- em response ); @@ -1108,7 +1147,7 @@ component pdp11_statleds is -- status leds MEM_ACT_R : in slbit; -- memory active read MEM_ACT_W : in slbit; -- memory active write CP_STAT : in cp_stat_type; -- console port status - DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath STATLEDS : out slv8 -- 8 bit CPU status ); end component; @@ -1119,7 +1158,7 @@ component pdp11_ledmux is -- hio led mux port ( SEL : in slbit; -- select (0=stat;1=dr) STATLEDS : in slv8; -- 8 bit CPU status - DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath LED : out slv(LWIDTH-1 downto 0) -- hio leds ); end component; @@ -1130,7 +1169,7 @@ component pdp11_dspmux is -- hio dsp mux port ( SEL : in slv2; -- select ABCLKDIV : in slv16; -- serport clock divider - DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath DISPREG : in slv16; -- display register DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data ); @@ -1147,7 +1186,7 @@ component pdp11_core_rbus is -- core to rbus interface RB_SRES : out rb_sres_type; -- rbus: response RB_STAT : out slv4; -- rbus: status flags RB_LAM : out slbit; -- remote attention - CPU_RESET : out slbit; -- cpu master reset + GRESET : out slbit; -- general reset CP_CNTL : out cp_cntl_type; -- console control port CP_ADDR : out cp_addr_type; -- console address port CP_DIN : out slv16; -- console data in @@ -1156,6 +1195,54 @@ component pdp11_core_rbus is -- core to rbus interface ); end component; +component pdp11_sys70 is -- 11/70 system 1 core +rbus,debug,cache + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + RB_MREQ : in rb_mreq_type; -- rbus request (slave) + RB_SRES : out rb_sres_type; -- rbus response + RB_STAT : out slv4; -- rbus status flags + RB_LAM_CPU : out slbit; -- rbus lam (cpu) + GRESET : out slbit; -- general reset (from rbus) + CRESET : out slbit; -- cpu reset (from cp) + BRESET : out slbit; -- bus reset (from cp or cpu) + CP_STAT : out cp_stat_type; -- console port status + EI_PRI : in slv3; -- external interrupt priority + EI_VECT : in slv9_2; -- external interrupt vector + EI_ACKM : out slbit; -- external interrupt acknowledge + ITIMER : out slbit; -- instruction timer + IB_MREQ : out ib_mreq_type; -- ibus request (master) + IB_SRES : in ib_sres_type; -- ibus response (from IO system) + MEM_REQ : out slbit; -- memory: request + MEM_WE : out slbit; -- memory: write enable + MEM_BUSY : in slbit; -- memory: controller busy + MEM_ACK_R : in slbit; -- memory: acknowledge read + MEM_ADDR : out slv20; -- memory: address + MEM_BE : out slv4; -- memory: byte enable + MEM_DI : out slv32; -- memory: data in (memory view) + MEM_DO : in slv32; -- memory: data out (memory view) + DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status - dpath + ); +end component; + +component pdp11_hio70 is -- hio led and dsp for sys70 + generic ( + LWIDTH : positive := 8; -- led width + DCWIDTH : positive := 2); -- digit counter width (2 or 3) + port ( + SEL_LED : in slbit; -- led select (0=stat;1=dr) + SEL_DSP : in slv2; -- dsp select + MEM_ACT_R : in slbit; -- memory active read + MEM_ACT_W : in slbit; -- memory active write + CP_STAT : in cp_stat_type; -- console port status + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status + ABCLKDIV : in slv16; -- serport clock divider + DISPREG : in slv16; -- display register + LED : out slv(LWIDTH-1 downto 0); -- hio leds + DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data + ); +end component; + -- ----- move later to pdp11_conf -------------------------------------------- constant conf_vect_pirq : integer := 8#240#; diff --git a/rtl/w11a/pdp11_bram.vhd b/rtl/w11a/pdp11_bram.vhd index 2e7ee518..760885be 100644 --- a/rtl/w11a/pdp11_bram.vhd +++ b/rtl/w11a/pdp11_bram.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_bram.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: pdp11_bram.vhd 677 2015-05-09 21:52:32Z mueller $ -- -- Copyright 2008-2011 by Walter F.J. Mueller -- @@ -40,7 +40,7 @@ entity pdp11_bram is -- cache AWIDTH : positive := 14); -- address width port ( CLK : in slbit; -- clock - GRESET : in slbit; -- global reset + GRESET : in slbit; -- general reset EM_MREQ : in em_mreq_type; -- em request EM_SRES : out em_sres_type -- em response ); diff --git a/rtl/w11a/pdp11_cache.vhd b/rtl/w11a/pdp11_cache.vhd index 268a0875..9e860df7 100644 --- a/rtl/w11a/pdp11_cache.vhd +++ b/rtl/w11a/pdp11_cache.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_cache.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: pdp11_cache.vhd 677 2015-05-09 21:52:32Z mueller $ -- -- Copyright 2008-2011 by Walter F.J. Mueller -- @@ -40,7 +40,7 @@ use work.pdp11.all; entity pdp11_cache is -- cache port ( CLK : in slbit; -- clock - GRESET : in slbit; -- global reset + GRESET : in slbit; -- general reset EM_MREQ : in em_mreq_type; -- em request EM_SRES : out em_sres_type; -- em response FMISS : in slbit; -- force miss diff --git a/rtl/w11a/pdp11_core.vbom b/rtl/w11a/pdp11_core.vbom index d9fadc67..52215ab7 100644 --- a/rtl/w11a/pdp11_core.vbom +++ b/rtl/w11a/pdp11_core.vbom @@ -8,7 +8,7 @@ pdp11_dpath.vbom pdp11_decode.vbom pdp11_sequencer.vbom pdp11_irq.vbom -pdp11_sys70.vbom +pdp11_reg70.vbom ../ibus/ib_sres_or_4.vbom # design pdp11_core.vhd diff --git a/rtl/w11a/pdp11_core.vhd b/rtl/w11a/pdp11_core.vhd index 8aa56bd1..26a761ad 100644 --- a/rtl/w11a/pdp11_core.vhd +++ b/rtl/w11a/pdp11_core.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_core.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: pdp11_core.vhd 677 2015-05-09 21:52:32Z mueller $ -- --- Copyright 2006-2011 by Walter F.J. Mueller +-- Copyright 2006-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -20,7 +20,7 @@ -- pdp11_decode -- pdp11_sequencer -- pdp11_irq --- pdp11_sys70 +-- pdp11_reg70 -- ibus/ib_sres_or_4 -- -- Test bench: tb/tb_pdp11core @@ -30,6 +30,8 @@ -- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-05-09 679 1.4 start/stop/suspend overhaul; reset overhaul +-- 2015-04-30 670 1.3.2 rename pdp11_sys70 -> pdp11_reg70 -- 2011-11-18 427 1.3.1 now numeric_std clean -- 2010-06-13 305 1.3 add CP_ADDR in port; drop R_CPDIN, R_CPOUT; _vmbox -- CP_ADDR now from in port; dpath CP_DIN now from in @@ -69,14 +71,20 @@ entity pdp11_core is -- full processor core CP_DIN : in slv16; -- console data in CP_STAT : out cp_stat_type; -- console status port CP_DOUT : out slv16; -- console data out + ESUSP_O : out slbit; -- external suspend output + ESUSP_I : in slbit; -- external suspend input + ITIMER : out slbit; -- instruction timer + EBREAK : in slbit; -- execution break + DBREAK : in slbit; -- data break EI_PRI : in slv3; -- external interrupt priority EI_VECT : in slv9_2; -- external interrupt vector EI_ACKM : out slbit; -- external interrupt acknowledge EM_MREQ : out em_mreq_type; -- external memory: request EM_SRES : in em_sres_type; -- external memory: response - BRESET : out slbit; -- ibus reset - IB_MREQ_M : out ib_mreq_type; -- inbus master request (master) - IB_SRES_M : in ib_sres_type; -- inbus slave response (master) + CRESET : out slbit; -- cpu reset + BRESET : out slbit; -- bus reset + IB_MREQ_M : out ib_mreq_type; -- ibus master request (master) + IB_SRES_M : in ib_sres_type; -- ibus slave response (master) DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath DM_STAT_VM : out dm_stat_vm_type; -- debug and monitor status - vmbox DM_STAT_CO : out dm_stat_co_type -- debug and monitor status - core @@ -86,10 +94,8 @@ end pdp11_core; architecture syn of pdp11_core is signal GRESET : slbit := '0'; - signal CRESET : slbit := '0'; + signal CRESET_L : slbit := '0'; signal BRESET_L : slbit := '0'; - signal SEQ_CRESET : slbit := '0'; - signal SEQ_BRESET : slbit := '0'; signal VM_CNTL : vm_cntl_type := vm_cntl_init; signal VM_STAT : vm_stat_type := vm_stat_init; signal MMU_MONI : mmu_moni_type := mmu_moni_init; @@ -118,14 +124,12 @@ architecture syn of pdp11_core is begin GRESET <= RESET; - CRESET <= RESET or SEQ_CRESET; - BRESET_L <= RESET or SEQ_CRESET or SEQ_BRESET; VMBOX : pdp11_vmbox port map ( CLK => CLK, GRESET => GRESET, - CRESET => CRESET, + CRESET => CRESET_L, BRESET => BRESET_L, CP_ADDR => CP_ADDR, VM_CNTL => VM_CNTL, @@ -145,7 +149,7 @@ begin DPATH : pdp11_dpath port map ( CLK => CLK, - CRESET => CRESET, + CRESET => CRESET_L, CNTL => DP_CNTL, STAT => DP_STAT, CP_DIN => CP_DIN, @@ -180,13 +184,18 @@ begin VM_STAT => VM_STAT, INT_PRI => INT_PRI, INT_VECT => INT_VECT, - CRESET => SEQ_CRESET, - BRESET => SEQ_BRESET, + INT_ACK => INT_ACK, + CRESET => CRESET_L, + BRESET => BRESET_L, MMU_MONI => MMU_MONI, DP_CNTL => DP_CNTL, VM_CNTL => VM_CNTL, CP_STAT => CP_STAT_L, - INT_ACK => INT_ACK, + ESUSP_O => ESUSP_O, + ESUSP_I => ESUSP_I, + ITIMER => ITIMER, + EBREAK => EBREAK, + DBREAK => DBREAK, IB_MREQ => IB_MREQ, IB_SRES => IB_SRES_SEQ ); @@ -205,10 +214,10 @@ begin IB_SRES => IB_SRES_IRQ ); - SYS70 : pdp11_sys70 + REG70 : pdp11_reg70 port map ( CLK => CLK, - CRESET => CRESET, + CRESET => CRESET_L, IB_MREQ => IB_MREQ, IB_SRES => IB_SRES_SYS ); @@ -226,10 +235,13 @@ begin CP_STAT <= CP_STAT_L; + CRESET <= CRESET_L; BRESET <= BRESET_L; - DM_STAT_CO.cpugo <= CP_STAT_L.cpugo; - DM_STAT_CO.cpuhalt <= CP_STAT_L.cpuhalt; + DM_STAT_CO.cpugo <= CP_STAT_L.cpugo; + DM_STAT_CO.cpususp <= CP_STAT_L.cpususp; + DM_STAT_CO.suspint <= CP_STAT_L.suspint; + DM_STAT_CO.suspext <= CP_STAT_L.suspext; end syn; diff --git a/rtl/w11a/pdp11_core_rbus.vhd b/rtl/w11a/pdp11_core_rbus.vhd index 7f89cf95..62599cca 100644 --- a/rtl/w11a/pdp11_core_rbus.vhd +++ b/rtl/w11a/pdp11_core_rbus.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_core_rbus.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: pdp11_core_rbus.vhd 677 2015-05-09 21:52:32Z mueller $ -- --- Copyright 2007-2014 by Walter F.J. Mueller +-- Copyright 2007-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -27,6 +27,7 @@ -- -- Revision History: - -- Date Rev Version Comment +-- 2015-05-09 677 1.5 start/stop/suspend overhaul; reset overhaul -- 2014-12-26 621 1.4 use full size 4k word ibus window -- 2014-12-21 617 1.3.1 use separate RB_STAT bits for cmderr and cmdmerr -- 2014-09-05 591 1.3 use new rlink v4 iface and 4 bit STAT @@ -65,12 +66,16 @@ -- 0000: noop -- 0001: start -- 0010: stop --- 0011: continue --- 0100: step --- 1111: reset (soft) +-- 0011: step +-- 0100: creset +-- 0101: breset +-- 0110: suspend +-- 0111: resume -- 00010 stat r/-/- cpu status +-- 9 suspext r/-/- cp_stat: statext +-- 8 suspint r/-/- cp_stat: statint -- 7:04 cpurust r/-/- cp_stat: cpurust --- 3 cpuhalt r/-/- cp_stat: cpuhalt +-- 3 cpususp r/-/- cp_stat: cpususp -- 2 cpugo r/-/- cp_stat: cpugo -- 1 cmdmerr r/-/- cp_stat: cmdmerr -- 0 cmderr r/-/- cp_stat: cmderr @@ -109,7 +114,7 @@ entity pdp11_core_rbus is -- core to rbus interface RB_SRES : out rb_sres_type; -- rbus: response RB_STAT : out slv4; -- rbus: status flags RB_LAM : out slbit; -- remote attention - CPU_RESET : out slbit; -- cpu master reset + GRESET : out slbit; -- general reset CP_CNTL : out cp_cntl_type; -- console control port CP_ADDR : out cp_addr_type; -- console address port CP_DIN : out slv16; -- console data in @@ -131,6 +136,7 @@ architecture syn of pdp11_core_rbus is state : state_type; -- state rbselc : slbit; -- rbus select for core rbseli : slbit; -- rbus select for ibus + rbinit : slbit; -- rbus init seen (1 cycle pulse) cpreq : slbit; -- cp request flag cpfunc : slv5; -- cp function cpugo_1 : slbit; -- prev cycle cpugo @@ -146,6 +152,7 @@ architecture syn of pdp11_core_rbus is constant regs_init : regs_type := ( s_idle, -- state '0','0', -- rbselc,rbseli + '0', -- rbinit '0', -- cpreq (others=>'0'), -- cpfunc '0', -- cpugo_1 @@ -186,7 +193,6 @@ architecture syn of pdp11_core_rbus is variable irbena : slbit := '0'; variable icpreq : slbit := '0'; - variable icpureset : slbit := '0'; variable icpaddr : cp_addr_type := cp_addr_init; begin @@ -203,11 +209,12 @@ architecture syn of pdp11_core_rbus is irbena := RB_MREQ.re or RB_MREQ.we; icpreq := '0'; - icpureset := '0'; - -- look for init's against the rbus base address, generate subsystem resets + -- generate single cycle pulse in case init against rbus base address seen + -- is used to generate some state machine resets via GRESET + n.rbinit := '0'; if RB_MREQ.init='1' and RB_MREQ.addr=RB_ADDR_CORE then - icpureset := RB_MREQ.din(0); + n.rbinit := RB_MREQ.din(0); end if; -- rbus address decoder @@ -259,11 +266,13 @@ architecture syn of pdp11_core_rbus is end if; when c_rbaddr_stat => -- stat ------------------ - irb_dout(c_stat_rbf_cmderr) := CP_STAT.cmderr; - irb_dout(c_stat_rbf_cmdmerr) := CP_STAT.cmdmerr; - irb_dout(c_stat_rbf_cpugo) := CP_STAT.cpugo; - irb_dout(c_stat_rbf_cpuhalt) := CP_STAT.cpuhalt; + irb_dout(c_stat_rbf_suspext) := CP_STAT.suspext; + irb_dout(c_stat_rbf_suspint) := CP_STAT.suspint; irb_dout(c_stat_rbf_cpurust) := CP_STAT.cpurust; + irb_dout(c_stat_rbf_cpususp) := CP_STAT.cpususp; + irb_dout(c_stat_rbf_cpugo) := CP_STAT.cpugo; + irb_dout(c_stat_rbf_cmdmerr) := CP_STAT.cmdmerr; + irb_dout(c_stat_rbf_cmderr) := CP_STAT.cmderr; when c_rbaddr_psw => -- psw ------------------- if irbena = '1' then @@ -412,12 +421,12 @@ architecture syn of pdp11_core_rbus is RB_STAT(3) <= CP_STAT.cmderr; RB_STAT(2) <= CP_STAT.cmdmerr; - RB_STAT(1) <= CP_STAT.cpuhalt or CP_STAT.cpurust(CP_STAT.cpurust'left); + RB_STAT(1) <= CP_STAT.cpususp; RB_STAT(0) <= CP_STAT.cpugo; RB_LAM <= irb_lam; - CPU_RESET <= icpureset; + GRESET <= R_REGS.rbinit; CP_CNTL.req <= r.cpreq; CP_CNTL.func <= r.cpfunc; diff --git a/rtl/w11a/pdp11_dpath.vhd b/rtl/w11a/pdp11_dpath.vhd index 4a631c2a..8227cc1f 100644 --- a/rtl/w11a/pdp11_dpath.vhd +++ b/rtl/w11a/pdp11_dpath.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_dpath.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: pdp11_dpath.vhd 677 2015-05-09 21:52:32Z mueller $ -- -- Copyright 2006-2014 by Walter F.J. Mueller -- @@ -59,7 +59,7 @@ use work.pdp11.all; entity pdp11_dpath is -- CPU datapath port ( CLK : in slbit; -- clock - CRESET : in slbit; -- console reset + CRESET : in slbit; -- cpu reset CNTL : in dpath_cntl_type; -- control interface STAT : out dpath_stat_type; -- status interface CP_DIN : in slv16; -- console port data in diff --git a/rtl/w11a/pdp11_dspmux.vhd b/rtl/w11a/pdp11_dspmux.vhd index 280555f1..c2aaa09c 100644 --- a/rtl/w11a/pdp11_dspmux.vhd +++ b/rtl/w11a/pdp11_dspmux.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_dspmux.vhd 652 2015-02-28 12:18:08Z mueller $ +-- $Id: pdp11_dspmux.vhd 677 2015-05-09 21:52:32Z mueller $ -- -- Copyright 2015- by Walter F.J. Mueller -- @@ -56,7 +56,7 @@ entity pdp11_dspmux is -- hio dsp mux port ( SEL : in slv2; -- select ABCLKDIV : in slv16; -- serport clock divider - DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath DISPREG : in slv16; -- display register DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data ); diff --git a/rtl/w11a/pdp11_hio70.vbom b/rtl/w11a/pdp11_hio70.vbom new file mode 100644 index 00000000..e8aea325 --- /dev/null +++ b/rtl/w11a/pdp11_hio70.vbom @@ -0,0 +1,9 @@ +# libs +../vlib/slvtypes.vhd +pdp11.vbom +# components +pdp11_statleds.vbom +pdp11_ledmux.vbom +pdp11_dspmux.vbom +# design +pdp11_hio70.vhd diff --git a/rtl/w11a/pdp11_hio70.vhd b/rtl/w11a/pdp11_hio70.vhd new file mode 100644 index 00000000..3f0db5c3 --- /dev/null +++ b/rtl/w11a/pdp11_hio70.vhd @@ -0,0 +1,91 @@ +-- $Id: pdp11_hio70.vhd 672 2015-05-02 21:58:28Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: pdp11_hio70 - syn +-- Description: pdp11: hio led and dsp for sys70 +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-05-01 672 1.0 Initial version (extracted from sys_w11a_*) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.pdp11.all; + +-- ---------------------------------------------------------------------------- + +entity pdp11_hio70 is -- hio led and dsp for sys70 + generic ( + LWIDTH : positive := 8; -- led width + DCWIDTH : positive := 2); -- digit counter width (2 or 3) + port ( + SEL_LED : in slbit; -- led select (0=stat;1=dr) + SEL_DSP : in slv2; -- dsp select + MEM_ACT_R : in slbit; -- memory active read + MEM_ACT_W : in slbit; -- memory active write + CP_STAT : in cp_stat_type; -- console port status + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status + ABCLKDIV : in slv16; -- serport clock divider + DISPREG : in slv16; -- display register + LED : out slv(LWIDTH-1 downto 0); -- hio leds + DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data + ); +end pdp11_hio70; + +architecture syn of pdp11_hio70 is + + signal STATLEDS : slv8 := (others=>'0'); + +begin + + LED_CPU : pdp11_statleds + port map ( + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + CP_STAT => CP_STAT, + DM_STAT_DP => DM_STAT_DP, + STATLEDS => STATLEDS + ); + + LED_MUX : pdp11_ledmux + generic map ( + LWIDTH => LWIDTH) + port map ( + SEL => SEL_LED, + STATLEDS => STATLEDS, + DM_STAT_DP => DM_STAT_DP, + LED => LED + ); + + DSP_MUX : pdp11_dspmux + generic map ( + DCWIDTH => DCWIDTH) + port map ( + SEL => SEL_DSP, + ABCLKDIV => ABCLKDIV, + DM_STAT_DP => DM_STAT_DP, + DISPREG => DISPREG, + DSP_DAT => DSP_DAT + ); + +end syn; diff --git a/rtl/w11a/pdp11_irq.vhd b/rtl/w11a/pdp11_irq.vhd index 1de0342d..56132ec0 100644 --- a/rtl/w11a/pdp11_irq.vhd +++ b/rtl/w11a/pdp11_irq.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_irq.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: pdp11_irq.vhd 677 2015-05-09 21:52:32Z mueller $ -- -- Copyright 2007-2011 by Walter F.J. Mueller -- @@ -48,7 +48,7 @@ use work.pdp11.all; entity pdp11_irq is -- interrupt requester port ( CLK : in slbit; -- clock - BRESET : in slbit; -- ibus reset + BRESET : in slbit; -- bus reset INT_ACK : in slbit; -- interrupt acknowledge from CPU EI_PRI : in slv3; -- external interrupt priority EI_VECT : in slv9_2; -- external interrupt vector diff --git a/rtl/w11a/pdp11_ledmux.vhd b/rtl/w11a/pdp11_ledmux.vhd index fec08db3..4cf07ddb 100644 --- a/rtl/w11a/pdp11_ledmux.vhd +++ b/rtl/w11a/pdp11_ledmux.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_ledmux.vhd 652 2015-02-28 12:18:08Z mueller $ +-- $Id: pdp11_ledmux.vhd 677 2015-05-09 21:52:32Z mueller $ -- -- Copyright 2015- by Walter F.J. Mueller -- @@ -41,7 +41,7 @@ entity pdp11_ledmux is -- hio led mux port ( SEL : in slbit; -- select (0=stat;1=dr) STATLEDS : in slv8; -- 8 bit CPU status - DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath LED : out slv(LWIDTH-1 downto 0) -- hio leds ); end pdp11_ledmux; diff --git a/rtl/w11a/pdp11_mem70.vhd b/rtl/w11a/pdp11_mem70.vhd index e606e113..aa755daf 100644 --- a/rtl/w11a/pdp11_mem70.vhd +++ b/rtl/w11a/pdp11_mem70.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_mem70.vhd 644 2015-02-08 22:56:54Z mueller $ +-- $Id: pdp11_mem70.vhd 677 2015-05-09 21:52:32Z mueller $ -- -- Copyright 2008-2011 by Walter F.J. Mueller -- @@ -43,7 +43,7 @@ use work.sys_conf.all; entity pdp11_mem70 is -- 11/70 memory system registers port ( CLK : in slbit; -- clock - CRESET : in slbit; -- console reset + CRESET : in slbit; -- cpu reset HM_ENA : in slbit; -- hit/miss enable HM_VAL : in slbit; -- hit/miss value CACHE_FMISS : out slbit; -- cache force miss diff --git a/rtl/w11a/pdp11_mmu.vhd b/rtl/w11a/pdp11_mmu.vhd index cafa4f2f..c9b591a5 100644 --- a/rtl/w11a/pdp11_mmu.vhd +++ b/rtl/w11a/pdp11_mmu.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_mmu.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: pdp11_mmu.vhd 677 2015-05-09 21:52:32Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -61,8 +61,8 @@ use work.pdp11.all; entity pdp11_mmu is -- mmu - memory management unit port ( CLK : in slbit; -- clock - CRESET : in slbit; -- console reset - BRESET : in slbit; -- ibus reset + CRESET : in slbit; -- cpu reset + BRESET : in slbit; -- bus reset CNTL : in mmu_cntl_type; -- control port VADDR : in slv16; -- virtual address MONI : in mmu_moni_type; -- monitor port diff --git a/rtl/w11a/pdp11_mmu_ssr12.vhd b/rtl/w11a/pdp11_mmu_ssr12.vhd index 78c9b0b0..9508982c 100644 --- a/rtl/w11a/pdp11_mmu_ssr12.vhd +++ b/rtl/w11a/pdp11_mmu_ssr12.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_mmu_ssr12.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: pdp11_mmu_ssr12.vhd 677 2015-05-09 21:52:32Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -47,7 +47,7 @@ use work.pdp11.all; entity pdp11_mmu_ssr12 is -- mmu register ssr1 and ssr2 port ( CLK : in slbit; -- clock - CRESET : in slbit; -- console reset + CRESET : in slbit; -- cpu reset TRACE : in slbit; -- trace enable MONI : in mmu_moni_type; -- MMU monitor port data IB_MREQ : in ib_mreq_type; -- ibus request diff --git a/rtl/w11a/pdp11_psr.vhd b/rtl/w11a/pdp11_psr.vhd index d5685d01..a7ef8d85 100644 --- a/rtl/w11a/pdp11_psr.vhd +++ b/rtl/w11a/pdp11_psr.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_psr.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: pdp11_psr.vhd 677 2015-05-09 21:52:32Z mueller $ -- -- Copyright 2006-2011 by Walter F.J. Mueller -- @@ -47,7 +47,7 @@ use work.pdp11.all; entity pdp11_psr is -- processor status word register port ( CLK : in slbit; -- clock - CRESET : in slbit; -- console reset + CRESET : in slbit; -- cpu reset DIN : in slv16; -- input data CCIN : in slv4; -- cc input CCWE : in slbit; -- enable update cc diff --git a/rtl/w11a/pdp11_reg70.vbom b/rtl/w11a/pdp11_reg70.vbom new file mode 100644 index 00000000..c6326362 --- /dev/null +++ b/rtl/w11a/pdp11_reg70.vbom @@ -0,0 +1,8 @@ +# libs +../vlib/slvtypes.vhd +../ibus/iblib.vhd +pdp11.vbom +${sys_conf := sys_conf.vhd} +# components +# design +pdp11_reg70.vhd diff --git a/rtl/w11a/pdp11_reg70.vhd b/rtl/w11a/pdp11_reg70.vhd new file mode 100644 index 00000000..a6449846 --- /dev/null +++ b/rtl/w11a/pdp11_reg70.vhd @@ -0,0 +1,131 @@ +-- $Id: pdp11_reg70.vhd 677 2015-05-09 21:52:32Z mueller $ +-- +-- Copyright 2008-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: pdp11_reg70 - syn +-- Description: pdp11: 11/70 system registers +-- +-- Dependencies: - +-- Test bench: tb/tb_pdp11_core (implicit) +-- Target Devices: generic +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-04-30 670 1.1.2 rename sys70 -> reg70 +-- 2011-11-18 427 1.1.1 now numeric_std clean +-- 2010-10-17 333 1.1 use ibus V2 interface +-- 2008-08-22 161 1.0.1 use iblib +-- 2008-04-20 137 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.pdp11.all; +use work.iblib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity pdp11_reg70 is -- 11/70 memory system registers + port ( + CLK : in slbit; -- clock + CRESET : in slbit; -- cpu reset + IB_MREQ : in ib_mreq_type; -- ibus request + IB_SRES : out ib_sres_type -- ibus response + ); +end pdp11_reg70; + +architecture syn of pdp11_reg70 is + + constant ibaddr_mbrk : slv16 := slv(to_unsigned(8#177770#,16)); + constant ibaddr_sysid : slv16 := slv(to_unsigned(8#177764#,16)); + + type regs_type is record -- state registers + ibsel_mbrk : slbit; -- ibus select mbrk + ibsel_sysid : slbit; -- ibus select sysid + mbrk : slv8; -- status of mbrk register + end record regs_type; + + constant regs_init : regs_type := ( + '0','0', -- ibsel_* + mbrk=>(others=>'0') -- mbrk + ); + + signal R_REGS : regs_type := regs_init; + signal N_REGS : regs_type := regs_init; + +begin + + proc_regs: process (CLK) + begin + if rising_edge(CLK) then + if CRESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + end process proc_regs; + + proc_next: process (R_REGS, IB_MREQ) + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + variable idout : slv16 := (others=>'0'); + variable ibreq : slbit := '0'; + variable ibw0 : slbit := '0'; + begin + + r := R_REGS; + n := R_REGS; + + idout := (others=>'0'); + ibreq := IB_MREQ.re or IB_MREQ.we; + ibw0 := IB_MREQ.we and IB_MREQ.be0; + + -- ibus address decoder + n.ibsel_mbrk := '0'; + n.ibsel_sysid := '0'; + if IB_MREQ.aval = '1' then + if IB_MREQ.addr = ibaddr_mbrk(12 downto 1) then + n.ibsel_mbrk := '1'; + end if; + if IB_MREQ.addr = ibaddr_sysid(12 downto 1) then + n.ibsel_sysid := '1'; + end if; + end if; + + -- ibus transactions + if r.ibsel_mbrk = '1' then + idout(r.mbrk'range) := r.mbrk; + end if; + if r.ibsel_sysid = '1' then + idout := slv(to_unsigned(8#123456#,16)); + end if; + + if r.ibsel_mbrk='1' and ibw0='1' then + n.mbrk := IB_MREQ.din(n.mbrk'range); + end if; + + N_REGS <= n; + + IB_SRES.dout <= idout; + IB_SRES.ack <= (r.ibsel_mbrk or r.ibsel_sysid) and ibreq; + IB_SRES.busy <= '0'; + + end process proc_next; + +end syn; diff --git a/rtl/w11a/pdp11_sequencer.vhd b/rtl/w11a/pdp11_sequencer.vhd index 291391d2..e4353183 100644 --- a/rtl/w11a/pdp11_sequencer.vhd +++ b/rtl/w11a/pdp11_sequencer.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_sequencer.vhd 643 2015-02-07 17:41:53Z mueller $ +-- $Id: pdp11_sequencer.vhd 679 2015-05-13 17:38:46Z mueller $ -- -- Copyright 2006-2015 by Walter F.J. Mueller -- @@ -18,10 +18,11 @@ -- Dependencies: ib_sel -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.1; ghdl 0.18-0.31 +-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 -- -- Revision History: -- Date Rev Version Comment +-- 2015-05-10 678 1.6 start/stop/suspend overhaul; reset overhaul -- 2015-02-07 643 1.5.2 s_op_wait: load R0 in DSRC for DR emulation -- 2014-07-12 569 1.5.1 rename s_opg_div_zero -> s_opg_div_quit; -- use DP_STAT.div_quit; set munit_s_div_sr; @@ -76,7 +77,7 @@ use work.pdp11.all; entity pdp11_sequencer is -- CPU sequencer port ( CLK : in slbit; -- clock - GRESET : in slbit; -- global reset + GRESET : in slbit; -- general reset PSW : in psw_type; -- processor status PC : in slv16; -- program counter IREG : in slv16; -- IREG @@ -86,13 +87,18 @@ entity pdp11_sequencer is -- CPU sequencer VM_STAT : in vm_stat_type; -- virtual memory status port INT_PRI : in slv3; -- interrupt priority INT_VECT : in slv9_2; -- interrupt vector - CRESET : out slbit; -- console reset - BRESET : out slbit; -- ibus reset + INT_ACK : out slbit; -- interrupt acknowledge + CRESET : out slbit; -- cpu reset + BRESET : out slbit; -- bus reset MMU_MONI : out mmu_moni_type; -- mmu monitor port DP_CNTL : out dpath_cntl_type; -- data path control VM_CNTL : out vm_cntl_type; -- virtual memory control port CP_STAT : out cp_stat_type; -- console port status - INT_ACK : out slbit; -- interrupt acknowledge + ESUSP_O : out slbit; -- external suspend output + ESUSP_I : in slbit; -- external suspend input + ITIMER : out slbit; -- instruction timer + EBREAK : in slbit; -- execution break + DBREAK : in slbit; -- data break IB_MREQ : in ib_mreq_type; -- ibus request IB_SRES : out ib_sres_type -- ibus response ); @@ -311,16 +317,12 @@ begin proc_next: process (R_STATE, R_STATUS, PSW, PC, CP_CNTL, ID_STAT, R_IDSTAT, IREG, VM_STAT, DP_STAT, R_CPUERR, R_VMSTAT, IB_MREQ, IBSEL_CPUERR, - INT_PRI, INT_VECT) + INT_PRI, INT_VECT, ESUSP_I, EBREAK, DBREAK) variable nstate : state_type; variable nstatus : cpustat_type := cpustat_init; variable ncpuerr : cpuerr_type := cpuerr_init; - variable ncreset : slbit := '0'; - variable nbreset : slbit := '0'; - variable nintack : slbit := '0'; - variable ndpcntl : dpath_cntl_type := dpath_cntl_init; variable nvmcntl : vm_cntl_type := vm_cntl_init; variable nidstat : decode_stat_type := decode_stat_init; @@ -498,10 +500,12 @@ begin R_STATUS.trap_ysv='1' or nstatus.trap_ysv='1' or PSW.tflag='1' then nstate := s_trap_disp; - elsif R_STATUS.cpugo='1' and not R_STATUS.cmdbusy='1' then - nstate := s_ifetch; + elsif R_STATUS.cpugo='1' and -- running + R_STATUS.cpususp='0' and -- and not suspended + not R_STATUS.cmdbusy='1' then -- and no cmd pending + nstate := s_ifetch; -- fetch next else - nstate := s_idle; + nstate := s_idle; -- otherwise idle end if; end procedure do_fork_next; @@ -520,13 +524,15 @@ begin R_STATUS.trap_ysv='1' or nstatus.trap_ysv='1' or PSW.tflag='1' then nstate := s_trap_disp; - elsif R_STATUS.cpugo='1' and not R_STATUS.cmdbusy='1' then - nvmcntl.req := '1'; - ndpcntl.gpr_pcinc := '1'; - nmmumoni.istart := '1'; - nstate := s_ifetch_w; + elsif R_STATUS.cpugo='1' and -- running + R_STATUS.cpususp='0' and -- and not suspended + not R_STATUS.cmdbusy='1' then -- and no cmd pending + nvmcntl.req := '1'; -- read next instruction + ndpcntl.gpr_pcinc := '1'; -- inc PC + nmmumoni.istart := '1'; -- signal istart to MMU + nstate := s_ifetch_w; -- next: wait for fetched instruction else - nstate := s_idle; + nstate := s_idle; -- otherwise idle end if; end procedure do_fork_next_pref; @@ -552,10 +558,20 @@ begin ncpuerr := R_CPUERR; nstatus.cpuwait := '0'; -- wait flag 0 unless set in s_op_wait + + -- itimer pulse logic: + -- if neither running nor suspended --> free run, set itimer = 1 + -- otherwise clear to ensure single cycle pulses generated by + -- s_idecode or s_op_wait + if R_STATUS.cpugo='0' and R_STATUS.cpususp='0' then + nstatus.itimer := '1'; + else + nstatus.itimer := '0'; + end if; - ncreset := '0'; - nbreset := '0'; - nintack := '0'; + nstatus.creset := '0'; -- ensure single cycle pulse + nstatus.breset := '0'; -- dito + nstatus.intack := '0'; -- dito nidstat := R_IDSTAT; @@ -669,55 +685,76 @@ begin if R_STATUS.cmdbusy = '1' then case R_STATUS.cpfunc is - when c_cpfunc_noop => -- noop : no operation -------- + when c_cpfunc_noop => -- noop : no operation ------- nstatus.cmdack := '1'; nstate := s_idle; - when c_cpfunc_sta => -- sta : cpu start ----------- - ncreset := '1'; + when c_cpfunc_start => -- start : cpu start --------- nstatus.cmdack := '1'; - nstatus.cpugo := '1'; - nstatus.cpuhalt := '0'; - nstatus.cpurust := c_cpurust_runs; - nstatus.waitsusp := '0'; + if R_STATUS.cpugo = '1' then -- if already running + nstatus.cmderr := '1'; -- reject + else -- if not running + nstatus.cpugo := '1'; -- start cpu + nstatus.cpurust := c_cpurust_runs; + nstatus.waitsusp := '0'; + end if; nstate := s_idle; - when c_cpfunc_sto => -- sto : cpu stop ------------ + when c_cpfunc_stop => -- stop : cpu stop ----------- nstatus.cmdack := '1'; nstatus.cpugo := '0'; nstatus.cpurust := c_cpurust_stop; nstatus.waitsusp := '0'; nstate := s_idle; - when c_cpfunc_cont => -- cont : cpu continue -------- - nstatus.cmdack := '1'; - nstatus.cpugo := '1'; - nstatus.cpuhalt := '0'; - nstatus.cpurust := c_cpurust_runs; - nstatus.waitsusp := '0'; - nstate := s_idle; - - when c_cpfunc_step => -- step : cpu step ------------ + when c_cpfunc_step => -- step : cpu step ----------- nstatus.cmdack := '1'; nstatus.cpustep := '1'; - nstatus.cpuhalt := '0'; nstatus.cpurust := c_cpurust_step; nstatus.waitsusp := '0'; if int_pending = '1' then - nintack := '1'; + nstatus.intack := '1'; nstatus.intvect := INT_VECT; nstate := s_int_ext; else nstate := s_ifetch; end if; - when c_cpfunc_rst => -- rst : cpu reset (soft) ---- - ncreset := '1'; + when c_cpfunc_creset => -- creset : cpu reset -------- nstatus.cmdack := '1'; - nstatus.cpugo := '0'; - nstatus.cpuhalt := '0'; - nstatus.cpurust := c_cpurust_reset; - nstatus.waitsusp := '0'; + if R_STATUS.cpugo = '1' then -- if already running + nstatus.cmderr := '1'; -- reject + else -- if not running + nstatus.creset := '1'; -- do cpu reset + nstatus.breset := '1'; -- and bus reset ! + nstatus.suspint := '0'; -- clear suspend + nstatus.cpurust := c_cpurust_init; + end if; + nstate := s_idle; + + when c_cpfunc_breset => -- breset : bus reset -------- + nstatus.cmdack := '1'; + if R_STATUS.cpugo = '1' then -- if already running + nstatus.cmderr := '1'; -- reject + else -- if not running + nstatus.breset := '1'; -- do bus reset only + end if; + nstate := s_idle; + + when c_cpfunc_suspend => -- suspend : cpu suspend ----- + nstatus.cmdack := '1'; + nstatus.suspint := '1'; + nstatus.cpurust := c_cpurust_susp; + nstate := s_idle; + + when c_cpfunc_resume => -- resume : cpu resume ------- + nstatus.cmdack := '1'; + nstatus.suspint := '0'; + if R_STATUS.cpugo = '1' then + nstatus.cpurust := c_cpurust_runs; + else + nstatus.cpurust := c_cpurust_stop; + end if; nstate := s_idle; when c_cpfunc_rreg => -- rreg : read register ------ @@ -768,13 +805,14 @@ begin nstatus.waitsusp := '0'; nstate := s_op_wait; - elsif R_STATUS.cpugo = '1' then - if int_pending = '1' then - nintack := '1'; - nstatus.intvect := INT_VECT; - nstate := s_int_ext; + elsif R_STATUS.cpugo = '1' and -- running + R_STATUS.cpususp='0' then -- and not suspended + if int_pending = '1' then -- interrupt pending + nstatus.intack := '1'; -- acknowledle it + nstatus.intvect := INT_VECT; -- latch vector address + nstate := s_int_ext; -- and handle else - nstate := s_ifetch; + nstate := s_ifetch; -- otherwise fetch intruction end if; end if; @@ -829,6 +867,7 @@ begin end if; when s_idecode => + nstatus.itimer := '1'; -- signal instruction started nidstat := ID_STAT; -- register decode status if ID_STAT.force_srcsp = '1' then ndpcntl.gpr_asrc := c_gpr_sp; @@ -842,7 +881,8 @@ begin ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC if ID_STAT.do_pref_dec='1' and PSW.tflag='0' and int_pending='0' and - R_STATUS.cpugo='1' and not R_STATUS.cmdbusy='1' + R_STATUS.cpugo='1' and R_STATUS.cpususp='0' and + not R_STATUS.cmdbusy='1' then nvmcntl.req := '1'; ndpcntl.gpr_pcinc := '1'; -- (pc)++ @@ -1473,7 +1513,6 @@ begin if is_kmode = '1' then -- if in kernel mode execute nmmumoni.idone := '1'; nstatus.cpugo := '0'; - nstatus.cpuhalt := '1'; nstatus.cpurust := c_cpurust_halt; nstate := s_idle; else -- otherwise trap @@ -1485,7 +1524,7 @@ begin ndpcntl.gpr_asrc := "000"; -- load R0 in DSRC for DR emulation ndpcntl.dsrc_sel := c_dpath_dsrc_src; ndpcntl.dsrc_we := '1'; - + nstate := s_op_wait; -- spin here if is_kmode = '0' then -- but act as nop if not in kernel nstate := s_idle; @@ -1497,7 +1536,8 @@ begin nstate := s_idle; else nstatus.cpuwait := '1'; -- if spinning here, signal with cpuwait - end if; + nstatus.itimer := '1'; -- itimer will stay 1 during a WAIT + end if; when s_op_trap => -- traps lvector := "0000" & R_IDSTAT.trap_vec; -- vector @@ -1505,7 +1545,7 @@ begin when s_op_reset => -- RESET if is_kmode = '1' then -- if in kernel mode execute - nbreset := '1'; + nstatus.breset := '1'; -- issue bus reset end if; nstate := s_idle; @@ -2255,6 +2295,18 @@ begin end case; + if DBREAK = '1' then -- handle BREAK + nstatus.suspint :='1'; + end if; + nstatus.suspext := ESUSP_I; + + -- handle cpususp transitions + if nstatus.suspint='1' or nstatus.suspext='1' then + nstatus.cpususp := '1'; + elsif R_STATUS.suspint='0' and R_STATUS.suspext='0' then + nstatus.cpususp := '0'; + end if; + if nstatus.cmdack = '1' then -- cmdack in next cycle ? Yes we test -- nstatus here !! nstatus.cmdbusy := '0'; @@ -2266,9 +2318,11 @@ begin N_CPUERR <= ncpuerr; N_IDSTAT <= nidstat; - CRESET <= ncreset; - BRESET <= nbreset; - INT_ACK <= nintack; + INT_ACK <= R_STATUS.intack; + CRESET <= R_STATUS.creset; + BRESET <= R_STATUS.breset; + ESUSP_O <= R_STATUS.suspint; -- FIXME_code: handle masking later + ITIMER <= R_STATUS.itimer; DP_CNTL <= ndpcntl; VM_CNTL <= nvmcntl; @@ -2288,9 +2342,11 @@ begin CP_STAT.cmdmerr <= R_STATUS.cmdmerr; CP_STAT.cpugo <= R_STATUS.cpugo; CP_STAT.cpustep <= R_STATUS.cpustep; - CP_STAT.cpuhalt <= R_STATUS.cpuhalt; CP_STAT.cpuwait <= R_STATUS.cpuwait; + CP_STAT.cpususp <= R_STATUS.cpususp; CP_STAT.cpurust <= R_STATUS.cpurust; + CP_STAT.suspint <= R_STATUS.suspint; + CP_STAT.suspext <= R_STATUS.suspext; end process proc_cpstat; end syn; diff --git a/rtl/w11a/pdp11_statleds.vhd b/rtl/w11a/pdp11_statleds.vhd index 22f440a9..497bd014 100644 --- a/rtl/w11a/pdp11_statleds.vhd +++ b/rtl/w11a/pdp11_statleds.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_statleds.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: pdp11_statleds.vhd 677 2015-05-09 21:52:32Z mueller $ -- -- Copyright 2015- by Walter F.J. Mueller -- @@ -51,7 +51,7 @@ entity pdp11_statleds is -- status leds MEM_ACT_R : in slbit; -- memory active read MEM_ACT_W : in slbit; -- memory active write CP_STAT : in cp_stat_type; -- console port status - DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath STATLEDS : out slv8 -- 8 bit CPU status ); end pdp11_statleds; diff --git a/rtl/w11a/pdp11_sys70.vbom b/rtl/w11a/pdp11_sys70.vbom index 6e6c94a7..1e937761 100644 --- a/rtl/w11a/pdp11_sys70.vbom +++ b/rtl/w11a/pdp11_sys70.vbom @@ -1,8 +1,16 @@ # libs ../vlib/slvtypes.vhd +../vlib/rbus/rblib.vhd ../ibus/iblib.vhd pdp11.vbom ${sys_conf := sys_conf.vhd} # components +pdp11_core_rbus.vbom +pdp11_core.vbom +pdp11_cache.vbom +pdp11_mem70.vbom +../ibus/ibd_ibmon.vbom +../ibus/ib_sres_or_3.vbom +[sim]pdp11_tmu_sb.vbom # design pdp11_sys70.vhd diff --git a/rtl/w11a/pdp11_sys70.vhd b/rtl/w11a/pdp11_sys70.vhd index 6b41cf36..67835c14 100644 --- a/rtl/w11a/pdp11_sys70.vhd +++ b/rtl/w11a/pdp11_sys70.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_sys70.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: pdp11_sys70.vhd 677 2015-05-09 21:52:32Z mueller $ -- --- Copyright 2008-2011 by Walter F.J. Mueller +-- Copyright 2015- by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -13,19 +13,24 @@ -- ------------------------------------------------------------------------------ -- Module Name: pdp11_sys70 - syn --- Description: pdp11: 11/70 system registers +-- Description: pdp11: 11/70 system - single core +rbus,debug,cache +-- +-- Dependencies: w11a/pdp11_core_rbus +-- w11a/pdp11_core +-- w11a/pdp11_cache +-- w11a/pdp11_mem70 +-- ibus/ibd_ibmon +-- ibus/ib_sres_or_3 +-- w11a/pdp11_tmu_sb [sim only] -- --- Dependencies: - -- Test bench: tb/tb_pdp11_core (implicit) -- Target Devices: generic --- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 +-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 -- -- Revision History: -- Date Rev Version Comment --- 2011-11-18 427 1.1.1 now numeric_std clean --- 2010-10-17 333 1.1 use ibus V2 interface --- 2008-08-22 161 1.0.1 use iblib --- 2008-04-20 137 1.0 Initial version +-- 2015-05-09 677 1.1 start/stop/suspend overhaul; reset overhaul +-- 2015-05-01 672 1.0 Initial version (extracted from sys_w11a_*) ------------------------------------------------------------------------------ library ieee; @@ -33,98 +38,205 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; +use work.rblib.all; use work.pdp11.all; use work.iblib.all; use work.sys_conf.all; -- ---------------------------------------------------------------------------- -entity pdp11_sys70 is -- 11/70 memory system registers +entity pdp11_sys70 is -- 11/70 system 1 core +rbus,debug,cache port ( CLK : in slbit; -- clock - CRESET : in slbit; -- console reset - IB_MREQ : in ib_mreq_type; -- ibus request - IB_SRES : out ib_sres_type -- ibus response + RESET : in slbit; -- reset + RB_MREQ : in rb_mreq_type; -- rbus request (slave) + RB_SRES : out rb_sres_type; -- rbus response + RB_STAT : out slv4; -- rbus status flags + RB_LAM_CPU : out slbit; -- rbus lam (cpu) + GRESET : out slbit; -- general reset (from rbus) + CRESET : out slbit; -- cpu reset (from cp) + BRESET : out slbit; -- bus reset (from cp or cpu) + CP_STAT : out cp_stat_type; -- console port status + EI_PRI : in slv3; -- external interrupt priority + EI_VECT : in slv9_2; -- external interrupt vector + EI_ACKM : out slbit; -- external interrupt acknowledge + ITIMER : out slbit; -- instruction timer + IB_MREQ : out ib_mreq_type; -- ibus request (master) + IB_SRES : in ib_sres_type; -- ibus response + MEM_REQ : out slbit; -- memory: request + MEM_WE : out slbit; -- memory: write enable + MEM_BUSY : in slbit; -- memory: controller busy + MEM_ACK_R : in slbit; -- memory: acknowledge read + MEM_ADDR : out slv20; -- memory: address + MEM_BE : out slv4; -- memory: byte enable + MEM_DI : out slv32; -- memory: data in (memory view) + MEM_DO : in slv32; -- memory: data out (memory view) + DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status - dpath ); end pdp11_sys70; architecture syn of pdp11_sys70 is - constant ibaddr_mbrk : slv16 := slv(to_unsigned(8#177770#,16)); - constant ibaddr_sysid : slv16 := slv(to_unsigned(8#177764#,16)); + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; - type regs_type is record -- state registers - ibsel_mbrk : slbit; -- ibus select mbrk - ibsel_sysid : slbit; -- ibus select sysid - mbrk : slv8; -- status of mbrk register - end record regs_type; + signal CP_CNTL : cp_cntl_type := cp_cntl_init; + signal CP_ADDR : cp_addr_type := cp_addr_init; + signal CP_DIN : slv16 := (others=>'0'); + signal CP_STAT_L : cp_stat_type := cp_stat_init; + signal CP_DOUT : slv16 := (others=>'0'); - constant regs_init : regs_type := ( - '0','0', -- ibsel_* - mbrk=>(others=>'0') -- mbrk - ); + signal EM_MREQ : em_mreq_type := em_mreq_init; + signal EM_SRES : em_sres_type := em_sres_init; + + signal GRESET_L : slbit := '0'; + signal CRESET_L : slbit := '0'; + signal BRESET_L : slbit := '0'; - signal R_REGS : regs_type := regs_init; - signal N_REGS : regs_type := regs_init; + signal HM_ENA : slbit := '0'; + signal MEM70_FMISS : slbit := '0'; + signal CACHE_FMISS : slbit := '0'; + signal CACHE_CHIT : slbit := '0'; + + signal DM_STAT_DP_L : dm_stat_dp_type := dm_stat_dp_init; + signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; + signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; + signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; + + signal IB_MREQ_M : ib_mreq_type := ib_mreq_init; + signal IB_SRES_M : ib_sres_type := ib_sres_init; + signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init; + signal IB_SRES_IBMON : ib_sres_type := ib_sres_init; + + constant rbaddr_ibus0 : slv16 := x"4000"; -- 4000/1000: 0100 xxxx xxxx xxxx + constant rbaddr_core0 : slv16 := x"0000"; -- 0000/0020: 0000 0000 000x xxxx begin - proc_regs: process (CLK) + RB2CP : pdp11_core_rbus + generic map ( + RB_ADDR_CORE => rbaddr_core0, + RB_ADDR_IBUS => rbaddr_ibus0) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM => RB_LAM_CPU, + GRESET => GRESET_L, + CP_CNTL => CP_CNTL, + CP_ADDR => CP_ADDR, + CP_DIN => CP_DIN, + CP_STAT => CP_STAT_L, + CP_DOUT => CP_DOUT + ); + + W11A : pdp11_core + port map ( + CLK => CLK, + RESET => GRESET_L, + CP_CNTL => CP_CNTL, + CP_ADDR => CP_ADDR, + CP_DIN => CP_DIN, + CP_STAT => CP_STAT_L, + CP_DOUT => CP_DOUT, + ESUSP_O => open, + ESUSP_I => '0', + ITIMER => ITIMER, + EBREAK => '0', + DBREAK => '0', + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + EM_MREQ => EM_MREQ, + EM_SRES => EM_SRES, + CRESET => CRESET_L, + BRESET => BRESET_L, + IB_MREQ_M => IB_MREQ_M, + IB_SRES_M => IB_SRES_M, + DM_STAT_DP => DM_STAT_DP_L, + DM_STAT_VM => DM_STAT_VM, + DM_STAT_CO => DM_STAT_CO + ); + + CACHE: pdp11_cache + port map ( + CLK => CLK, + GRESET => GRESET_L, + EM_MREQ => EM_MREQ, + EM_SRES => EM_SRES, + FMISS => CACHE_FMISS, + CHIT => CACHE_CHIT, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO + ); + + MEM70: pdp11_mem70 + port map ( + CLK => CLK, + CRESET => BRESET_L, + HM_ENA => HM_ENA, + HM_VAL => CACHE_CHIT, + CACHE_FMISS => MEM70_FMISS, + IB_MREQ => IB_MREQ_M, + IB_SRES => IB_SRES_MEM70 + ); + + HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; + CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; + + IBMON : if sys_conf_ibmon_awidth > 0 generate begin - if rising_edge(CLK) then - if CRESET = '1' then - R_REGS <= regs_init; - else - R_REGS <= N_REGS; - end if; - end if; - end process proc_regs; + I0 : ibd_ibmon + generic map ( + IB_ADDR => slv(to_unsigned(8#160000#,16)), + AWIDTH => sys_conf_ibmon_awidth) + port map ( + CLK => CLK, + RESET => RESET, + IB_MREQ => IB_MREQ_M, + IB_SRES => IB_SRES_IBMON, + IB_SRES_SUM => DM_STAT_VM.ibsres + ); + end generate IBMON; - proc_next: process (R_REGS, IB_MREQ) - variable r : regs_type := regs_init; - variable n : regs_type := regs_init; - variable idout : slv16 := (others=>'0'); - variable ibreq : slbit := '0'; - variable ibw0 : slbit := '0'; - begin - - r := R_REGS; - n := R_REGS; + IB_SRES_OR : ib_sres_or_3 + port map ( + IB_SRES_1 => IB_SRES_MEM70, + IB_SRES_2 => IB_SRES, + IB_SRES_3 => IB_SRES_IBMON, + IB_SRES_OR => IB_SRES_M + ); - idout := (others=>'0'); - ibreq := IB_MREQ.re or IB_MREQ.we; - ibw0 := IB_MREQ.we and IB_MREQ.be0; - - -- ibus address decoder - n.ibsel_mbrk := '0'; - n.ibsel_sysid := '0'; - if IB_MREQ.aval = '1' then - if IB_MREQ.addr = ibaddr_mbrk(12 downto 1) then - n.ibsel_mbrk := '1'; - end if; - if IB_MREQ.addr = ibaddr_sysid(12 downto 1) then - n.ibsel_sysid := '1'; - end if; - end if; - - -- ibus transactions - if r.ibsel_mbrk = '1' then - idout(r.mbrk'range) := r.mbrk; - end if; - if r.ibsel_sysid = '1' then - idout := slv(to_unsigned(8#123456#,16)); - end if; - - if r.ibsel_mbrk='1' and ibw0='1' then - n.mbrk := IB_MREQ.din(n.mbrk'range); - end if; - - N_REGS <= n; - - IB_SRES.dout <= idout; - IB_SRES.ack <= (r.ibsel_mbrk or r.ibsel_sysid) and ibreq; - IB_SRES.busy <= '0'; - - end process proc_next; - + RB_SRES <= RB_SRES_CPU; -- currently single rbus device + IB_MREQ <= IB_MREQ_M; -- setup output signals + GRESET <= GRESET_L; + CRESET <= CRESET_L; + BRESET <= BRESET_L; + CP_STAT <= CP_STAT_L; + DM_STAT_DP <= DM_STAT_DP_L; + +-- synthesis translate_off + DM_STAT_SY.emmreq <= EM_MREQ; + DM_STAT_SY.emsres <= EM_SRES; + DM_STAT_SY.chit <= CACHE_CHIT; + + TMU : pdp11_tmu_sb + generic map ( + ENAPIN => 13) + port map ( + CLK => CLK, + DM_STAT_DP => DM_STAT_DP_L, + DM_STAT_VM => DM_STAT_VM, + DM_STAT_CO => DM_STAT_CO, + DM_STAT_SY => DM_STAT_SY + ); +-- synthesis translate_on + end syn; diff --git a/rtl/w11a/pdp11_tmu.vhd b/rtl/w11a/pdp11_tmu.vhd index 126b706b..96d62247 100644 --- a/rtl/w11a/pdp11_tmu.vhd +++ b/rtl/w11a/pdp11_tmu.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_tmu.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: pdp11_tmu.vhd 677 2015-05-09 21:52:32Z mueller $ -- --- Copyright 2008-2011 by Walter F.J. Mueller +-- Copyright 2008-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -23,6 +23,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-05-03 674 1.2 start/stop/suspend overhaul -- 2011-12-23 444 1.1 use local clkcycle count instead of simbus global -- 2011-11-18 427 1.0.7 now numeric_std clean -- 2010-10-17 333 1.0.6 use ibus V2 interface @@ -51,10 +52,10 @@ entity pdp11_tmu is -- trace and monitor unit port ( CLK : in slbit; -- clock ENA : in slbit := '0'; -- enable trace output - DM_STAT_DP : in dm_stat_dp_type; -- DM dpath - DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox - DM_STAT_CO : in dm_stat_co_type; -- DM core - DM_STAT_SY : in dm_stat_sy_type -- DM system + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath + DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox + DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core + DM_STAT_SY : in dm_stat_sy_type -- debug and monitor status - system ); end pdp11_tmu; @@ -116,7 +117,9 @@ begin write(oline, string'(" vm.ibsres.dout:o")); write(oline, string'(" co.cpugo:b")); - write(oline, string'(" co.cpuhalt:b")); + write(oline, string'(" co.cpususp:b")); + write(oline, string'(" co.suspint:b")); + write(oline, string'(" co.suspext:b")); write(oline, string'(" sy.emmreq.req:b")); write(oline, string'(" sy.emmreq.we:b")); @@ -202,7 +205,9 @@ begin writeoct(oline, DM_STAT_VM.ibsres.dout, right, 7); write(oline, DM_STAT_CO.cpugo, right, 2); - write(oline, DM_STAT_CO.cpuhalt, right, 2); + write(oline, DM_STAT_CO.cpususp, right, 2); + write(oline, DM_STAT_CO.suspint, right, 2); + write(oline, DM_STAT_CO.suspext, right, 2); write(oline, DM_STAT_SY.emmreq.req, right, 2); write(oline, DM_STAT_SY.emmreq.we, right, 2); diff --git a/rtl/w11a/pdp11_tmu_sb.vhd b/rtl/w11a/pdp11_tmu_sb.vhd index 170e79d2..63095b4e 100644 --- a/rtl/w11a/pdp11_tmu_sb.vhd +++ b/rtl/w11a/pdp11_tmu_sb.vhd @@ -1,4 +1,4 @@ --- $Id: pdp11_tmu_sb.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: pdp11_tmu_sb.vhd 677 2015-05-09 21:52:32Z mueller $ -- -- Copyright 2009- by Walter F.J. Mueller -- @@ -36,10 +36,10 @@ entity pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper ENAPIN : integer := 13); -- SB_CNTL signal to use for enable port ( CLK : in slbit; -- clock - DM_STAT_DP : in dm_stat_dp_type; -- DM dpath - DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox - DM_STAT_CO : in dm_stat_co_type; -- DM core - DM_STAT_SY : in dm_stat_sy_type -- DM system + DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath + DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox + DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core + DM_STAT_SY : in dm_stat_sy_type -- debug and monitor status - system ); end pdp11_tmu_sb; diff --git a/rtl/w11a/pdp11_vmbox.vhd b/rtl/w11a/pdp11_vmbox.vhd index bcfcd299..86ef4282 100644 --- a/rtl/w11a/pdp11_vmbox.vhd +++ b/rtl/w11a/pdp11_vmbox.vhd @@ -1,6 +1,6 @@ --- $Id: pdp11_vmbox.vhd 641 2015-02-01 22:12:15Z mueller $ +-- $Id: pdp11_vmbox.vhd 677 2015-05-09 21:52:32Z mueller $ -- --- Copyright 2006-2011 by Walter F.J. Mueller +-- Copyright 2006-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -27,6 +27,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-04-04 662 1.6.4 atowidth now 6 (was 5) to support ibdr_rprm reset -- 2011-11-18 427 1.6.3 now numeric_std clean -- 2010-10-23 335 1.6.2 add r.paddr_iopage, use ib_sel -- 2010-10-22 334 1.6.1 deassert ibus be's at end-cycle; fix rmw logic @@ -74,9 +75,9 @@ use work.sys_conf.all; entity pdp11_vmbox is -- virtual memory port ( CLK : in slbit; -- clock - GRESET : in slbit; -- global reset - CRESET : in slbit; -- console reset - BRESET : in slbit; -- ibus reset + GRESET : in slbit; -- general reset + CRESET : in slbit; -- cpu reset + BRESET : in slbit; -- bus reset CP_ADDR : in cp_addr_type; -- console port address VM_CNTL : in vm_cntl_type; -- vm control port VM_ADDR : in slv16; -- vm address @@ -96,7 +97,7 @@ end pdp11_vmbox; architecture syn of pdp11_vmbox is constant ibaddr_slim : slv16 := slv(to_unsigned(8#177774#,16)); - constant atowidth : natural := 5; -- size of access timeout counter + constant atowidth : natural := 6; -- size of access timeout counter type state_type is ( s_idle, -- s_idle: wait for vm_cntl request diff --git a/rtl/w11a/sys_conf.vhd b/rtl/w11a/sys_conf.vhd index da06d8aa..90dbf2a6 100644 --- a/rtl/w11a/sys_conf.vhd +++ b/rtl/w11a/sys_conf.vhd @@ -1,6 +1,6 @@ --- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: sys_conf.vhd 672 2015-05-02 21:58:28Z mueller $ -- --- Copyright 2007-2008 by Walter F.J. Mueller +-- Copyright 2007-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -13,12 +13,13 @@ -- ------------------------------------------------------------------------------ -- Package Name: sys_conf --- Description: Default definitions for pdp11core (for simple test benches) +-- Description: Default definitions -- -- Dependencies: - --- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 +-- Tool versions: xst 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 -- Revision History: -- Date Rev Version Comment +-- 2015-05-01 672 1.1 adopt to pdp11_sys70 -- 2008-02-23 118 1.0 Initial version ------------------------------------------------------------------------------ @@ -29,19 +30,12 @@ use work.slvtypes.all; package sys_conf is + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + constant sys_conf_bram_awidth : integer := 15; -- 32 kB BRAM constant sys_conf_mem_losize : integer := 8#000777#;-- 32 kByte --- constant sys_conf_bram_awidth : integer := 14; -- 16 kB BRAM --- constant sys_conf_mem_losize : integer := 8#000377#;-- 16 kByte + + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon end package sys_conf; --- Note: mem_losize holds 16 MSB of the PA of the addressable memory --- 2 211 111 111 110 000 000 000 --- 1 098 765 432 109 876 543 210 --- --- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte --- 0 000 000 011 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte --- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte --- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte --- upper 256 kB excluded for 11/70 UB diff --git a/rtl/w11a/tb/tb_pdp11core.vhd b/rtl/w11a/tb/tb_pdp11core.vhd index d74a3fbc..02220ea5 100644 --- a/rtl/w11a/tb/tb_pdp11core.vhd +++ b/rtl/w11a/tb/tb_pdp11core.vhd @@ -1,6 +1,6 @@ --- $Id: tb_pdp11core.vhd 621 2014-12-26 21:20:05Z mueller $ +-- $Id: tb_pdp11core.vhd 675 2015-05-08 21:05:08Z mueller $ -- --- Copyright 2006-2014 by Walter F.J. Mueller +-- Copyright 2006-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -47,6 +47,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-05-08 675 1.5 start/stop/suspend overhaul -- 2014-12-26 621 1.4.1 adopt wmembe,ribr,wibr emulation to new 4k window -- 2011-12-23 444 1.4 use new simclk/simclkcnt -- 2011-11-18 427 1.3.2 now numeric_std clean @@ -114,8 +115,11 @@ architecture sim of tb_pdp11core is signal CP_STAT_cmdmerr : slbit := '0'; signal CP_STAT_cpugo : slbit := '0'; signal CP_STAT_cpustep : slbit := '0'; - signal CP_STAT_cpuhalt : slbit := '0'; + signal CP_STAT_cpuwait : slbit := '0'; + signal CP_STAT_cpususp : slbit := '0'; signal CP_STAT_cpurust : slv4 := (others=>'0'); + signal CP_STAT_suspint : slbit := '0'; + signal CP_STAT_suspext : slbit := '0'; signal CP_DOUT : slv16 := (others=>'0'); signal CLK_STOP : slbit := '0'; @@ -164,8 +168,11 @@ begin CP_STAT_cmdmerr => CP_STAT_cmdmerr, CP_STAT_cpugo => CP_STAT_cpugo, CP_STAT_cpustep => CP_STAT_cpustep, - CP_STAT_cpuhalt => CP_STAT_cpuhalt, + CP_STAT_cpuwait => CP_STAT_cpuwait, + CP_STAT_cpususp => CP_STAT_cpususp, CP_STAT_cpurust => CP_STAT_cpurust, + CP_STAT_suspint => CP_STAT_suspint, + CP_STAT_suspext => CP_STAT_suspext, CP_DOUT => CP_DOUT ); @@ -327,7 +334,7 @@ begin end if; when others => -- bad directive - write(oline, string'("?? unknown directive: ")); + write(oline, string'("-E: unknown directive: ")); write(oline, dname); writeline(output, oline); report "aborting" severity failure; @@ -438,16 +445,20 @@ begin idosta := '1'; -- request 'sta' to be done next when "sta " => -- sta - ifunc := c_cpfunc_sta; + ifunc := c_cpfunc_start; when "sto " => -- sto - ifunc := c_cpfunc_sto; - when "cont " => -- cont - ifunc := c_cpfunc_cont; + ifunc := c_cpfunc_stop; when "step " => -- step ifunc := c_cpfunc_step; iwtstp := true; - when "rst " => -- rst - ifunc := c_cpfunc_rst; + when "cres " => -- cres + ifunc := c_cpfunc_creset; + when "bres " => -- bres + ifunc := c_cpfunc_breset; + when "susp " => -- susp + ifunc := c_cpfunc_suspend; + when "resu " => -- resu + ifunc := c_cpfunc_resume; when "wtgo " => -- wtgo iwtgo := true; @@ -458,7 +469,7 @@ begin next file_loop; when others => -- bad directive - write(oline, string'("?? unknown directive: ")); + write(oline, string'("-E: unknown directive: ")); write(oline, dname); writeline(output, oline); report "aborting" severity failure; @@ -553,11 +564,13 @@ begin else write(oline, string'("wmem")); end if; - when c_cpfunc_sta => write(oline, string'("sta ")); - when c_cpfunc_sto => write(oline, string'("sto ")); - when c_cpfunc_cont => write(oline, string'("cont")); - when c_cpfunc_step => write(oline, string'("step")); - when c_cpfunc_rst => write(oline, string'("rst ")); + when c_cpfunc_start => write(oline, string'("sta ")); + when c_cpfunc_stop => write(oline, string'("sto ")); + when c_cpfunc_step => write(oline, string'("step")); + when c_cpfunc_creset => write(oline, string'("cres")); + when c_cpfunc_breset => write(oline, string'("bres")); + when c_cpfunc_suspend => write(oline, string'("susp")); + when c_cpfunc_resume => write(oline, string'("resu")); when others => write(oline, string'("?")); writeoct(oline, ifunc, right, 2); @@ -575,8 +588,11 @@ begin write(oline, R_CP_STAT.cmdmerr, right, 2); writeoct(oline, R_CP_DOUT, right, 8); write(oline, R_CP_STAT.cpugo, right, 3); - write(oline, R_CP_STAT.cpustep, right, 2); - write(oline, R_CP_STAT.cpuhalt, right, 2); + write(oline, R_CP_STAT.cpustep, right, 1); + write(oline, R_CP_STAT.cpuwait, right, 1); + write(oline, R_CP_STAT.cpususp, right, 1); + write(oline, R_CP_STAT.suspint, right, 1); + write(oline, R_CP_STAT.suspext, right, 1); writeoct(oline, R_CP_STAT.cpurust, right, 3); if R_WAITOK = '1' then @@ -667,8 +683,11 @@ begin R_CP_STAT.cmdmerr <= CP_STAT_cmdmerr; R_CP_STAT.cpugo <= CP_STAT_cpugo; R_CP_STAT.cpustep <= CP_STAT_cpustep; - R_CP_STAT.cpuhalt <= CP_STAT_cpuhalt; + R_CP_STAT.cpuwait <= CP_STAT_cpuwait; + R_CP_STAT.cpususp <= CP_STAT_cpususp; R_CP_STAT.cpurust <= CP_STAT_cpurust; + R_CP_STAT.suspint <= CP_STAT_suspint; + R_CP_STAT.suspext <= CP_STAT_suspext; R_CP_DOUT <= CP_DOUT; end loop; diff --git a/rtl/w11a/tb/tb_pdp11core_stim.dat b/rtl/w11a/tb/tb_pdp11core_stim.dat index 9774bd99..1be46e96 100644 --- a/rtl/w11a/tb/tb_pdp11core_stim.dat +++ b/rtl/w11a/tb/tb_pdp11core_stim.dat @@ -1,7 +1,8 @@ -# $Id: tb_pdp11core_stim.dat 621 2014-12-26 21:20:05Z mueller $ +# $Id: tb_pdp11core_stim.dat 675 2015-05-08 21:05:08Z mueller $ # # Revision History: # Date Rev Version Comment +# 2015-05-08 675 2.6 start/stop/suspend overhaul # 2014-12-26 621 2.5 adopt wmembe,ribr,wibr emulation to new 4k window # 2014-12-20 614 2.4 adopted to rlink v4 # 2014-07-13 569 2.3 after ECO-026: correct test 31.1 wrong V=1 cases @@ -249,9 +250,10 @@ brm 2 .merr 0 .sdef s=00000000,01110000 # -C test access error handling to IB space (use 00160000) +C test access error handling to IB space (use 00160016) +C (is above ibd_ibmon decoded range, and below other debug stuff) C with wm/rm -wal 160000 +wal 160016 .merr 1 .sdef s=01000001 wm 000000 @@ -260,7 +262,7 @@ rm d=- .sdef s=00000000,01110000 C with bwm/brm # -wal 160000 +wal 160016 .merr 1 .sdef s=01000001 bwm 2 @@ -269,7 +271,7 @@ bwm 2 .merr 0 .sdef s=00000000,01110000 # -wal 160000 +wal 160016 .merr 1 .sdef s=01000001 brm 2 @@ -358,12 +360,12 @@ bwm 3 077002 -- sob r0,-2 000000 -- halt # -C Exec code 1 (very basics: cont,start; 'simple' instructions) +C Exec code 1 (very basics: start; 'simple' instructions) C Exec test 1.1 (sec+clc+halt) # wpc 002100 -- pc=2100 wps 000010 -- psw: set N flag -cont -- cont @ 2100 +sta -- start @ 2100 wtgo rpc d=002106 -- ! pc rps d=000001 -- ! N cleared, C set now @@ -371,6 +373,7 @@ rps d=000001 -- ! N cleared, C set now C Exec test 1.2 (4 *inc R2, starting from -2) # wr2 177776 -- r2=-2 +cres stapc 002120 -- start @ 2120 wtgo rr2 d=000002 -- ! r2=2 @@ -379,6 +382,7 @@ rpc d=002132 -- ! pc C Exec test 1.3 (dec r3; bne -2; halt) # wr3 000002 -- r3=2 +cres stapc 002140 -- start @ 2140 wtgo rr3 d=000000 -- ! r3=0 @@ -388,6 +392,7 @@ C Exec test 1.4 (inc r1; sob r0,-2; halt) # wr0 000002 -- r0=2 wr1 000000 -- r1=0 +cres stapc 002160 -- start @ 2160 wtgo rr0 d=000000 -- ! r0=0 @@ -406,6 +411,7 @@ bwm 4 C Exec code 2 (bpt against trap catcher @14) # wsp 001400 -- sp=1400 +cres stapc 002200 -- start @ 2200 wtgo rsp d=001374 -- ! sp @@ -438,6 +444,7 @@ C Exec code 3 (bpt against trap handler doing inc r0; rtt) wr0 000000 -- r0=0 wr1 000000 -- r1=0 wsp 001400 -- sp=1400 +cres stapc 002300 -- start @ 2300 wtgo rr0 d=000001 -- ! r0 @@ -463,6 +470,7 @@ wal 001374 -- setup stack with rtt return frame setting T flag bwm 2 002402 -- start address 000020 -- set T flag in PSW +cres stapc 002400 -- start @ 2400 -> rtt -> 2402 from stack wtgo rr0 d=000002 -- ! r0 @@ -470,7 +478,7 @@ rr1 d=000002 -- ! r1 rsp d=001400 -- ! sp rpc d=002410 -- ! pc # -rst -- console reset (to clear T flag) +cres -- console reset (to clear T flag) wal 000014 -- vector: 14 -> trap catcher again bwm 2 000016 -- PC:16 @@ -505,6 +513,7 @@ wr3 000000 -- r3=0 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 002500 -- start @ 2500 wtgo rr0 d=002544 -- ! r0 @@ -542,6 +551,7 @@ wr3 000000 -- r3=0 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 002600 -- start @ 2600 wtgo rr0 d=002540 -- ! r0 @@ -593,6 +603,7 @@ wr3 002760 -- r3=2760 wr4 002774 -- r4=2774 wr5 000666 -- r5=666 wsp 001400 -- sp=1400 +cres stapc 002700 -- start @ 2700 wtgo rr0 d=002750 -- ! r0 @@ -654,6 +665,7 @@ wr2 003070 -- r2=3070 wr3 003060 -- r3=3060 wr4 003074 -- r4=3074 wsp 001400 -- sp=1400 +cres stapc 003000 -- start @ 3000 wtgo rr0 d=003050 -- ! r0 @@ -737,6 +749,7 @@ wr3 003242 -- r3=3242 wr4 003144 -- r4=3144 wr5 003160 -- r5=3160 wsp 001400 -- sp=1400 +cres stapc 003100 -- start @ 3100 wtgo rr0 d=003210 -- ! r0=3210 @@ -795,6 +808,7 @@ wr0 177776 -- r0=177776 wr1 177777 -- r1=177777 wr5 003400 -- r5=3400 wsp 001400 -- sp=1400 +cres stapc 003300 -- start @ 3300 wtgo rr5 d=003424 -- ! r5=3424 @@ -836,6 +850,7 @@ bwm 2 # C Exec code 13.1a (run WAIT) # +cres stapc 003500 -- start @ 3500 .wait 20 -- let it go rpc d=003502 -- ! should hang here ... @@ -860,6 +875,7 @@ rpc d=003510 -- ! # C Exec code 13.2 (test bwm/brm while CPU busy looping) wr0 000000 -- r0=0 +cres stapc 003520 -- start @ 3520 # wal 003560 -- write data while CPU active @@ -889,6 +905,7 @@ rpc d=003526 -- ! # C Exec code 13.3 (test bwm/brm while CPU on WAIT) # +cres stapc 003540 -- start @ 3540 # wal 003560 -- write data while CPU active @@ -967,6 +984,7 @@ wr2 000033 -- r2=33 wr3 000044 -- r3=44 wr5 003700 -- r5=3700 wsp 001400 -- sp=140 +cres stapc 003600 -- start @ 3600 wtgo rr5 d=003720 -- ! r5=3720 @@ -1077,6 +1095,7 @@ rr1 d=004044 -- ! r1 C Exec test 16.1 (check CRESET of PSW, SSR0, SSR3 after start) # wps 000000 -- psw: set pri=0 +cres stapc 004030 -- start @ 4030 (just HALT, testing console reset) wtgo rpc d=004032 -- ! pc=4032 @@ -1185,6 +1204,7 @@ wal 001374 -- setup stack with rtt return frame setting T flag bwm 2 004100 -- start address (code 17 @ 4100) 000020 -- set T flag in PSW +cres stapc 004274 -- start @ 4274 -> rtt -> 4100 from stack wtgo rr1 d=004711 -- ! r1=4711 @@ -1261,7 +1281,7 @@ brm 31 d=000020 -- ! mem(4572)=0000; xor r1,(r4)+ (#4711, #070707) d=000024 -- ! mem(4574)=0Z00; sxt (r4)+ (#111111 with N=0) # -rst -- console reset (to clear T flag) +cres -- console reset (to clear T flag) wal 000014 -- vector: 14 -> trap catcher again bwm 2 000016 -- PC:16 @@ -1293,7 +1313,7 @@ bwm 4 #---------- C Exec code 20 (check CPUERR and error handling) C Exec test 20.1 (odd address abort) -rst -- console reset +cres -- console reset wps 000000 -- psw: clear wal 001374 -- clean stack bwm 2 @@ -1931,7 +1951,7 @@ C Exec code 22 (MMU ; run user mode code with I/D) wr5 005260 -- r5=5260 wsp 001400 -- sp=1400 wpc 005000 -- pc=5000 -cont -- cont @ 5000 +sta -- start @ 5000 wtgo rsp d=001372 -- ! sp rpc d=005030 -- ! pc (halt in TRAP handler) @@ -2131,6 +2151,7 @@ wr1 000005 -- r1=5 wr2 177776 -- r2=177776 (PS address) wr5 006300 -- r5=6300 (output data) wsp 001400 -- sp=1400 +cres stapc 005700 -- start @ 5700 wtgo rr0 d=006212 -- ! r0 @@ -2158,6 +2179,7 @@ wr1 000003 -- r1=3 wr2 177776 -- r2=177776 (PS address) wr5 006330 -- sp=6330 (output data) wsp 001400 -- sp=1400 +cres stapc 005720 -- start @ 5720 wtgo rr0 d=006226 -- ! r0 @@ -2181,6 +2203,7 @@ wr1 000007 -- r1=7 wr2 177776 -- r2=177776 (PS address) wr5 006344 -- sp=6344 (output data) wsp 001400 -- sp=1400 +cres stapc 005740 -- start @ 5740 wtgo rr0 d=006264 -- ! r0 @@ -2249,6 +2272,7 @@ C Exec code 24 (test MARK instruction) wr0 006470 -- r0=6470 wr5 123456 -- r5=123456 wsp 001400 -- sp=1400 +cres stapc 006400 -- start @ 6400 wtgo rr0 d=006476 -- ! r0=6476 (3 words written) @@ -2338,6 +2362,7 @@ wal 001374 -- setup stack with rtt return frame setting T flag bwm 2 006500 -- start address (code 25 @ 6500) 000020 -- set T flag in PSW +cres stapc 006564 -- start @ 6564 -> rtt -> 6500 from stack wtgo rr1 d=000123 -- ! r1=123 @@ -2394,7 +2419,7 @@ brm 21 d=000020 -- ! mem(6674)=0000; aslb (r4)+ (#020) d=000023 -- ! mem(6676)=00VC; aslb (r4)+ (#220) # -rst -- console reset (to clear T flag) +cres -- console reset (to clear T flag) wal 000014 -- vector: 14 -> trap catcher again bwm 2 000016 -- PC:16 @@ -2495,6 +2520,7 @@ C Exec test 26.1 (test src-dst update hazards with (r0)+,(r0)+ ect): wr0 007060 -- r0=7060 (input data for (r0)+...) wr1 007100 -- r1=7100 (input data for -(r1)...) wsp 001400 -- sp=1400 +cres stapc 006700 -- start @ 6700 wtgo rr0 d=007070 -- ! r0 @@ -2515,6 +2541,7 @@ brm 4 C Exec test 26.2 (test indexed mode with pc (mode 67)): # wsp 001400 -- sp=1400 +cres stapc 006720 -- start @ 6720 wtgo rpc d=006736 -- ! pc @@ -2528,6 +2555,7 @@ C Exec test 26.3 (test (pc)+ as dst): # wr0 000111 -- r0=0111 wsp 001400 -- sp=1400 +cres stapc 006750 -- start @ 6750 wtgo rr0 d=000112 -- ! r0 @@ -2549,6 +2577,7 @@ wr1 000110 -- r1=0110 wr2 000120 -- r2=0120 wr3 000130 -- r3=0130 wsp 001400 -- sp=1400 +cres stapc 007000 -- start @ 7000 wtgo rr0 d=000101 -- ! r0 @@ -2565,6 +2594,7 @@ C Exec test 26.5 (test pc as dst in mov and add): # wr1 000000 -- r1=0 wsp 001400 -- sp=1400 +cres stapc 007020 -- start @ 7020 wtgo rr1 d=000002 -- ! r1 @@ -2688,6 +2718,7 @@ wr1 007500 -- r1=7500 (output data) wr2 000014 -- r2=14 (test count) wr3 177776 -- r3=177776 (#PSW) wsp 001400 -- sp=1400 +cres stapc 007100 -- start @ 7100 wtgo rr0 d=007260 -- ! r0 @@ -2727,6 +2758,7 @@ wr1 007600 -- r1=7600 (output data) wr2 000012 -- r2=12 (test count) wr3 177776 -- r3=177776 (#PSW) wsp 001400 -- sp=1400 +cres stapc 007120 -- start @ 7120 wtgo rr0 d=007374 -- ! r0 @@ -2772,6 +2804,7 @@ wr1 007740 -- r1=7740 (output data) wr2 000003 -- r2=3 (test count) wr3 177776 -- r3=177776 (#PSW) wsp 001400 -- sp=1400 +cres stapc 007150 -- start @ 7150 wtgo rr0 d=007454 -- ! r0 @@ -2846,6 +2879,7 @@ wr1 010300 -- r1=10300 (output data) wr2 000010 -- r2=10 (test count) wr3 177776 -- r3=177776 (#PSW) wsp 001400 -- sp=1400 +cres stapc 010200 -- start @ 10200 wtgo rr0 d=010300 -- ! r0 @@ -2886,6 +2920,7 @@ wr2 000010 -- r2=10 (test count) wr3 000000 -- r3=0 wr4 000000 -- r4=0 wsp 001400 -- sp=1400 +cres stapc 010220 -- start @ 10220 wtgo rr0 d=010300 -- ! r0 @@ -3053,10 +3088,10 @@ wr1 010700 -- r1=10700 (output data) wr2 000025 -- r2=25 (test count) wr3 177776 -- r3=177776 (#PSW) wsp 001400 -- sp=1400 -rst -- console reset ; do reset; cont to start with +cres -- console reset ; do reset; cont to start with wps 000000 -- clear psw ; psw cc code dump below wpc 010400 -- pc=10400 -cont -- cont @ 10400 +sta -- start @ 10400 wtgo rr0 d=010676 -- ! r0 rr1 d=011076 -- ! r1 @@ -3138,6 +3173,7 @@ wr0 010500 -- r0=10500 (input data from DIV) wr1 010700 -- r1=10700 (output data from DIV) wr5 000016 -- r5=16 (test count) wsp 001400 -- sp=1400 +cres stapc 010420 -- start @ 10420 wtgo rr0 d=010624 -- ! r0 @@ -3217,6 +3253,7 @@ wr3 177772 -- r3=177772 (#PIRQ) wr4 177776 -- r4=177776 (#PSW) wr5 011220 -- r1=11220 (output data) wsp 001400 -- sp=1400 +cres stapc 011100 -- start @ 11100 wtgo rr5 d=011300 -- ! r5 @@ -3339,6 +3376,7 @@ C Exec test 33.1 (adc) wr0 011300 -- r0=11300 wr1 000003 -- r1=3 wsp 001400 -- sp=1400 +cres stapc 011200 -- start @ 11200 wtgo rr0 d=011322 -- ! r0=11322 @@ -3360,6 +3398,7 @@ C Exec test 33.2 (sbc) wr0 011324 -- r0=11324 wr1 000003 -- r1=3 wsp 001400 -- sp=1400 +cres stapc 011220 -- start @ 11220 wtgo rr0 d=011346 -- ! r0=11346 @@ -3381,6 +3420,7 @@ C Exec test 33.3 (adcb) wr0 011350 -- r0=11350 wr1 000003 -- r1=3 wsp 001400 -- sp=1400 +cres stapc 011240 -- start @ 11240 wtgo rr0 d=011364 -- ! r0=11364 @@ -3399,6 +3439,7 @@ C Exec test 33.4 (sbcb) wr0 011364 -- r0=11364 wr1 000003 -- r1=3 wsp 001400 -- sp=1400 +cres stapc 011260 -- start @ 11260 wtgo rr0 d=011400 -- ! r0=11400 @@ -3488,6 +3529,7 @@ bwm 8 # C Exec code 34 (11/34 self test code) # D RE RQ FU DAT +cres stapc 011400 -- start @ 11400 wtgo rr0 d=000000 -- ! r0 @@ -3636,6 +3678,7 @@ bwm 117 # C Exec code 35 (11/70 self test code) # D RE RQ FU DAT +cres stapc 011600 -- start @ 11600 wtgo rpc d=012152 -- ! pc @@ -3696,6 +3739,7 @@ wr3 000013 -- r3=13 -> test count wr4 036000 -- r4=36000 -> input area wr5 037000 -- r5=37000 -> output area wsp 001400 -- sp=1400 +cres stapc 012200 -- start @ 12200 wtgo rpc d=012216 -- ! pc @@ -3803,6 +3847,7 @@ wr3 000023 -- r3=23 -> test count wr4 036000 -- r4=36000 -> input area wr5 037000 -- r5=37000 -> output area wsp 001400 -- sp=1400 +cres stapc 012300 -- start @ 12300 wtgo rpc d=012322 -- ! pc @@ -3934,6 +3979,7 @@ wr3 000021 -- r3=21 (17.) -> test count wr4 036000 -- r4=36000 -> input area wr5 037000 -- r5=37000 -> output area wsp 001400 -- sp=1400 +cres stapc 012300 -- start @ 12300 wtgo rpc d=012322 -- ! pc @@ -4185,6 +4231,7 @@ wr3 000062 -- r3=62 -> test count wr4 036000 -- r4=36000 -> input area wr5 037000 -- r5=37000 -> output area wsp 001400 -- sp=1400 +cres stapc 012400 -- start @ 12400 wtgo rpc d=012436 -- ! pc @@ -4546,6 +4593,7 @@ wr3 000057 -- r3=57 (47.) wr4 036000 -- r4=36000 wr5 037000 -- r5=37000 wsp 001400 -- sp=1400 +cres stapc 012500 -- start @ 12500 wtgo rpc d=012546 -- ! pc @@ -4918,6 +4966,7 @@ wr3 000067 -- r3=67 (55.) -> test count wr4 036000 -- r4=36000 -> input area wr5 037000 -- r5=37000 -> output area wsp 001400 -- sp=1400 +cres stapc 012600 -- start @ 12600 wtgo rpc d=012636 -- ! pc @@ -5095,6 +5144,7 @@ C Exec code 43 (Begemot MARK test) C Exec test 43.1 (basics) # D RE RQ FU DAT wsp 001400 -- sp=1400 +cres stapc 012700 -- start @ 12700 wtgo rpc d=012734 -- ! pc @@ -5111,6 +5161,7 @@ brm 5 C Exec test 43.2 (MARK with max. # of args) # D RE RQ FU DAT wsp 001400 -- sp=1400 +cres stapc 012740 -- start @ 12740 wtgo rpc d=012764 -- ! pc @@ -5155,7 +5206,7 @@ bwm 2 C Exec code 44 (Implementation variations) C test 44.1: OPR R,(R)+ : incremented before {J11} or after {70} use as source # -rst -- console reset +cres -- console reset wps 000000 -- clear psw wr4 001600 -- r4=1600 wsp 001400 -- sp=1400 @@ -5242,7 +5293,7 @@ bwm 2 000020 -- set T flag in PSW wsp 001374 -- sp=1374 wpc 013020 -- pc=13020 -cont -- cont (rtt) +sta -- start (rtt) wtgo rpc d=000020 -- ! pc=20 ; T-trap executed rsp d=001374 -- ! sp=1374 @@ -5250,7 +5301,7 @@ wal 001374 -- check stack brm 2 d=013072 -- trap address: address after noop expected for 11/70 d=000020 -- PSW -rst -- console reset (to clear T flag) +cres -- console reset (to clear T flag) # C test 44.11: If RTI sets T bit, T trap occurs immediately {70,J11} # @@ -5260,7 +5311,7 @@ bwm 2 000020 -- set T flag in PSW wsp 001374 -- sp=1374 wpc 013024 -- pc=13024 -cont -- cont (rti) +sta -- start (rti) wtgo rpc d=000020 -- ! pc=20 ; T-trap executed rsp d=001374 -- ! sp=1374 @@ -5268,7 +5319,7 @@ wal 001374 -- check stack brm 2 d=013070 -- trap address: address of noop expected for 11/70 d=000020 -- PSW -rst -- console reset (to clear T flag) +cres -- console reset (to clear T flag) # C test 44.14: Direct access to PSW can {05..20} / cannot {others} set T bit # @@ -5291,7 +5342,7 @@ wal 000000 -- check emergency stack brm 2 d=013034 -- ! PC of abort [[s:0]] d=000000 -- ! PS of abort (currently gets lost...) -rst -- console reset (to clear CPUERR reg) +cres -- console reset (to clear CPUERR reg) wal 000000 -- clean tainted memory bwm 2 000000 -- @@ -5308,12 +5359,13 @@ wmi 077400 -- slf=127; ed=0(up); acf=0 (non resident) # C test 44.28: If PC->bad memory, PC incremented {others} / not inc'ed {35,40} # +cres wal 177572 -- SSR0 wmi 000001 -- set enable bit wr4 100000 -- r4=100000 wsp 001400 -- sp=1400 wpc 013034 -- pc=13034 -cont -- cont (jmp (r4)) +sta -- start (jmp (r4)) wtgo rpc d=000254 -- ! pc=254 ; trap 240 ; Note: halt is executed, was cont ! rsp d=001374 -- ! sp=1374 @@ -5321,7 +5373,7 @@ wal 001374 -- check stack brm 2 d=100002 -- trap address: PC inc'ed expected for 11/70 [[s:100000]] d=000340 -- PSW -rst -- console reset (to clear CPUERR reg) +cres -- console reset (to clear CPUERR reg) # # simh notes: # 1. simh reads instruction, later increments PC. Thus PC not inc'ed in simh. @@ -5342,7 +5394,7 @@ wal 177572 -- check SSR0/1 brm 2 d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]] d=000021 -- ! SSR1: ra=1,2 -rst -- console reset (to clear CPUERR reg) +cres -- console reset (to clear CPUERR reg) # C test 44.29/30b: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44} C test for srcr chain (mov (r1)+,r0) @@ -5360,7 +5412,7 @@ wal 177572 -- check SSR0/1 brm 2 d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]] d=000021 -- ! SSR1: ra=1,2 -rst -- console reset (to clear CPUERR reg) +cres -- console reset (to clear CPUERR reg) # C test 44.29/30c: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44} C test for dstr chain (inc (r1)+) @@ -5378,7 +5430,7 @@ wal 177572 -- check SSR0/1 brm 2 d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]] d=000021 -- ! SSR1: ra=1,2 -rst -- console reset (to clear CPUERR reg) +cres -- console reset (to clear CPUERR reg) C test 44.29/30d: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44} C test for dsta chain (mtpd (r1)+) # @@ -5397,7 +5449,7 @@ wal 177572 -- check SSR0/1 brm 2 d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]] d=010426 -- ! SSR1: rb=1,2; ra=6,2 -rst -- console reset (to clear CPUERR reg) +cres -- console reset (to clear CPUERR reg) # # simh notes: # 1. simh first pops, than writes to destination, reversing ra,rb in SSR1 @@ -5428,7 +5480,7 @@ wal 001374 -- check stack brm 2 d=013044 -- ! PC after failed instruction [[s:013042]] d=100000 -- ! PS -rst -- console reset (to clear CPUERR reg, PSW) +cres -- console reset (to clear CPUERR reg, PSW) # # simh notes: # 1. simh saves PC of failed instruction on stack, not PC after instruction @@ -5449,7 +5501,7 @@ brm 2 d=170000 -- ! PS wal 177766 -- check CPUERR rm d=000200 -- ! CPUERR: (illhalt=1) -rst -- console reset (to clear CPUERR reg, PSW) +cres -- console reset (to clear CPUERR reg, PSW) # C test 44.44: PDR bit<0> implemented {70} or not {others} # @@ -5488,7 +5540,7 @@ wal 172300 -- kernel I space DR, reset segment 0 and 1 bwm 2 077406 -- slf=127; ed=0(up); acf=6(w/r) 077406 -- slf=127; ed=0(up); acf=6(w/r) -rst -- console reset (to clear CPUERR reg) +cres -- console reset (to clear CPUERR reg) # C test 44.46: Full PAR implemented {44,70,J11} or not {others} # @@ -5547,7 +5599,7 @@ brm 3 d=000001 -- ! SSR0: (ena=1) d=000000 -- ! SSR1: ra=none d=000016 -- ! SSR2: PC of halt -rst -- console reset (to clear CPUERR reg, PSW) +cres -- console reset (to clear CPUERR reg, PSW) # # simh notes: # 1. when simh steps over a BPT,IOT,..., the PC is pointing after the @@ -5588,7 +5640,7 @@ rpc d=013050 -- ! pc=next rsp d=001376 -- ! sp=1376 wal 001376 -- check stack rmi d=013046 -- ! it returns PC like 11/70 unpredictable [[s:0]] -rst -- console reset (to clear CPUERR reg) +cres -- console reset (to clear CPUERR reg) # # simh note: # 1. simh returns 0 here, just unpredictable in a different way ... @@ -5625,7 +5677,7 @@ wps 144000 -- psw: cm=user(11),set=1 rsp d=110601 -- ! usp [[usp]] # --> all preset values intact; -> mtpd thus noop --> like 11/70 unpredictable # -rst -- console reset (to clear CPUERR reg) +cres -- console reset (to clear CPUERR reg) # # simh notes on MMR0: # 1. simh doesn't freeze MMR0 bit 7, the instr.compl. bit is set again after @@ -5646,6 +5698,7 @@ bwm 5 C Exec code 45 (mmr1 and instructions with implicit stack push/pop) C test 45.1: mtpd (r1)+ # +cres wal 177572 -- SSR0 wmi 000001 -- set enable bit wal 001376 -- setup stack with value for mtpd @@ -5664,7 +5717,7 @@ brm 3 d=013100 -- ! SSR2: PC of mtpd wal 030000 -- check target memory rm d=123456 -- ! -rst -- console reset +cres -- console reset # C test 45.2: mfpd (r1)+ # @@ -5686,7 +5739,7 @@ wal 001376 -- check stack rmi d=123456 -- ! wal 030000 -- clear tainted target memory wm 000000 -- -rst -- console reset +cres -- console reset # C test 45.3: jsr pc,(r1)+ and rts pc # @@ -5714,7 +5767,7 @@ brm 3 d=000001 -- ! SSR0: (seg=0,ena=1) d=000026 -- ! SSR1: ra=6,2 [[s:0]] d=013110 -- ! SSR2: PC of rts -rst -- console reset +cres -- console reset # # simh notes: # 1. simh reads stack and incremets sp later. In case of an MMU abort on @@ -5799,6 +5852,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -5829,6 +5883,7 @@ wr3 037000 -- r3=37000 wr4 001400 -- r4=1400 wr5 001402 -- r5=1402 wsp 001400 -- sp=1400 +cres stapc 013220 -- start @ 13220 (1op mem) wtgo rpc d=013240 -- ! pc=halt @@ -5859,6 +5914,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -5889,6 +5945,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -5919,6 +5976,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -5949,6 +6007,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -5979,6 +6038,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -6009,6 +6069,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -6039,6 +6100,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -6069,6 +6131,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -6099,6 +6162,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -6129,6 +6193,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -6159,6 +6224,7 @@ wr3 037000 -- r3=37000 wr4 001400 -- r4=1400 wr5 001402 -- r5=1402 wsp 001400 -- sp=1400 +cres stapc 013220 -- start @ 13220 (1op mem) wtgo rpc d=013240 -- ! pc=halt @@ -6198,6 +6264,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -6232,6 +6299,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -6266,6 +6334,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -6300,6 +6369,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -6334,6 +6404,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -6368,6 +6439,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -6402,6 +6474,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -6436,6 +6509,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -6478,6 +6552,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -6504,6 +6579,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -6530,6 +6606,7 @@ wr3 037000 -- r3=37000 wr4 001400 -- r4=1400 wr5 001402 -- r5=1402 wsp 001400 -- sp=1400 +cres stapc 013270 -- start @ 13270 (2op mem) wtgo rpc d=013312 -- ! pc=halt @@ -6570,6 +6647,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -6602,6 +6680,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -6634,6 +6713,7 @@ wr3 037000 -- r3=37000 wr4 001400 -- r4=1400 wr5 001402 -- r5=1402 wsp 001400 -- sp=1400 +cres stapc 013270 -- start @ 13270 (2op mem) wtgo rpc d=013312 -- ! pc=halt @@ -6666,6 +6746,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -6698,6 +6779,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -6730,6 +6812,7 @@ wr3 037000 -- r3=37000 wr4 001400 -- r4=1400 wr5 001402 -- r5=1402 wsp 001400 -- sp=1400 +cres stapc 013270 -- start @ 13270 (2op mem) wtgo rpc d=013312 -- ! pc=halt @@ -6762,6 +6845,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -6794,6 +6878,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -6826,6 +6911,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -6858,6 +6944,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -6930,6 +7017,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -6988,6 +7076,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -7046,6 +7135,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -7115,6 +7205,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7161,6 +7252,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7191,6 +7283,7 @@ wr3 037000 -- r3=37000 wr4 001400 -- r4=1400 wr5 001402 -- r5=1402 wsp 001400 -- sp=1400 +cres stapc 013220 -- start @ 13220 (1op mem) wtgo rpc d=013240 -- ! pc=halt @@ -7221,6 +7314,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7251,6 +7345,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7281,6 +7376,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7311,6 +7407,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7341,6 +7438,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7371,6 +7469,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7401,6 +7500,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7431,6 +7531,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7461,6 +7562,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7491,6 +7593,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7521,6 +7624,7 @@ wr3 037000 -- r3=37000 wr4 001400 -- r4=1400 wr5 001402 -- r5=1402 wsp 001400 -- sp=1400 +cres stapc 013220 -- start @ 13220 (1op mem) wtgo rpc d=013240 -- ! pc=halt @@ -7560,6 +7664,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7594,6 +7699,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7628,6 +7734,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7662,6 +7769,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7696,6 +7804,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7730,6 +7839,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7764,6 +7874,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7798,6 +7909,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013200 -- start @ 13200 (1op reg) wtgo rpc d=013220 -- ! pc=halt @@ -7840,6 +7952,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -7866,6 +7979,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -7892,6 +8006,7 @@ wr3 037000 -- r3=37000 wr4 001400 -- r4=1400 wr5 001402 -- r5=1402 wsp 001400 -- sp=1400 +cres stapc 013270 -- start @ 13270 (2op mem) wtgo rpc d=013312 -- ! pc=halt @@ -7932,6 +8047,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -7964,6 +8080,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -7996,6 +8113,7 @@ wr3 037000 -- r3=37000 wr4 001400 -- r4=1400 wr5 001402 -- r5=1402 wsp 001400 -- sp=1400 +cres stapc 013270 -- start @ 13270 (2op mem) wtgo rpc d=013312 -- ! pc=halt @@ -8028,6 +8146,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -8060,6 +8179,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -8092,6 +8212,7 @@ wr3 037000 -- r3=37000 wr4 001400 -- r4=1400 wr5 001402 -- r5=1402 wsp 001400 -- sp=1400 +cres stapc 013270 -- start @ 13270 (2op mem) wtgo rpc d=013312 -- ! pc=halt @@ -8124,6 +8245,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -8156,6 +8278,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -8228,6 +8351,7 @@ wr3 037000 -- r3=37000 wr4 000000 -- r4=0 wr5 000000 -- r5=0 wsp 001400 -- sp=1400 +cres stapc 013240 -- start @ 13240 (2op reg) wtgo rpc d=013262 -- ! pc=halt @@ -8321,6 +8445,7 @@ wr1 000000 -- r1=0 wr2 000000 -- r2=0 wr3 005201 -- r3= inc r1 wr4 005202 -- r4= inc r2 +cres stapc 013402 -- start @ 13402 wtgo rpc d=013434 -- ! pc @@ -8352,6 +8477,7 @@ brm 13 C Exec test 47.1 (pipeline tester adapted from KDJ11A.MAC, test 121, p. 70) # wr1 013474 -- r1=13474 (alternate halt) +cres stapc 013440 -- start @ 13440 wtgo rpc d=013472 -- ! pc @@ -8399,7 +8525,7 @@ bwm 17 C Exec code 50 (check that all reserved instructions trap to 10) C Test odd address abort # -rst -- console reset +cres -- console reset wps 000000 -- clear psw wal 001374 -- clean stack bwm 2 diff --git a/rtl/w11a/tb/tbd_pdp11core.vhd b/rtl/w11a/tb/tbd_pdp11core.vhd index aee601d0..69347ef5 100644 --- a/rtl/w11a/tb/tbd_pdp11core.vhd +++ b/rtl/w11a/tb/tbd_pdp11core.vhd @@ -1,6 +1,6 @@ --- $Id: tbd_pdp11core.vhd 649 2015-02-21 21:10:16Z mueller $ +-- $Id: tbd_pdp11core.vhd 674 2015-05-04 16:17:40Z mueller $ -- --- Copyright 2007-2011 by Walter F.J. Mueller +-- Copyright 2007-2015 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -41,6 +41,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2015-05-03 674 1.6 start/stop/suspend overhaul -- 2011-11-18 427 1.5.1 now numeric_std clean -- 2010-12-30 351 1.5 rename tbd_pdp11_core -> tbd_pdp11core -- 2010-10-23 335 1.4.2 rename RRI_LAM->RB_LAM; @@ -91,9 +92,12 @@ entity tbd_pdp11core is -- full core [no records] CP_STAT_cmderr : out slbit; -- console status port CP_STAT_cmdmerr : out slbit; -- console status port CP_STAT_cpugo : out slbit; -- console status port - CP_STAT_cpuhalt : out slbit; -- console status port CP_STAT_cpustep : out slbit; -- console status port + CP_STAT_cpuwait : out slbit; -- console status port + CP_STAT_cpususp : out slbit; -- console status port CP_STAT_cpurust : out slv4; -- console status port + CP_STAT_suspint : out slbit; -- console status port + CP_STAT_suspext : out slbit; -- console status port CP_DOUT : out slv16 -- console data out ); end tbd_pdp11core; @@ -140,9 +144,12 @@ begin CP_STAT_cmderr <= CP_STAT.cmderr; CP_STAT_cmdmerr <= CP_STAT.cmdmerr; CP_STAT_cpugo <= CP_STAT.cpugo; - CP_STAT_cpuhalt <= CP_STAT.cpuhalt; CP_STAT_cpustep <= CP_STAT.cpustep; + CP_STAT_cpuwait <= CP_STAT.cpuwait; + CP_STAT_cpususp <= CP_STAT.cpususp; CP_STAT_cpurust <= CP_STAT.cpurust; + CP_STAT_suspint <= CP_STAT.suspint; + CP_STAT_suspext <= CP_STAT.suspext; CLKDIV : clkdivce generic map ( @@ -164,6 +171,11 @@ begin CP_DIN => CP_DIN, CP_STAT => CP_STAT, CP_DOUT => CP_DOUT, + ESUSP_O => open, -- not tested + ESUSP_I => '0', -- dito + ITIMER => open, -- dito + EBREAK => '0', -- dito + DBREAK => '0', -- dito EI_PRI => EI_PRI, EI_VECT => EI_VECT, EI_ACKM => EI_ACKM, diff --git a/tools/asm-11/lib/defs_bits.mac b/tools/asm-11/lib/defs_bits.mac new file mode 100644 index 00000000..ccc60b55 --- /dev/null +++ b/tools/asm-11/lib/defs_bits.mac @@ -0,0 +1,22 @@ +; $Id: defs_bits.mac 622 2014-12-28 20:45:26Z mueller $ +; Copyright 2014- by Walter F.J. Mueller +; License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +; +; definitions for generic bits names (as in defs_bits.das) +; + bit15=100000 + bit14=040000 + bit13=020000 + bit12=010000 + bit11=004000 + bit10=002000 + bit09=001000 + bit08=000400 + bit07=000200 + bit06=000100 + bit05=000040 + bit04=000020 + bit03=000010 + bit02=000004 + bit01=000002 + bit00=000001 diff --git a/tools/asm-11/lib/defs_cpu.mac b/tools/asm-11/lib/defs_cpu.mac new file mode 100644 index 00000000..dfce353e --- /dev/null +++ b/tools/asm-11/lib/defs_cpu.mac @@ -0,0 +1,29 @@ +; $Id: defs_cpu.mac 622 2014-12-28 20:45:26Z mueller $ +; Copyright 2014- by Walter F.J. Mueller +; License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +; +; definitions for basic CPU registers (as in defs_cpu.das) +; + cp.psw = 177776 + cp.dsr = 177570 +; +; symbol definitions for cp.psw +; + cp.cms=040000 + cp.cmu=140000 + cp.pms=010000 + cp.pmu=030000 + cp.ars=004000 + cp.pr0=000000 + cp.pr1=000040 + cp.pr2=000100 + cp.pr3=000140 + cp.pr4=000200 + cp.pr5=000240 + cp.pr6=000300 + cp.pr7=000340 + cp.t=000020 + cp.n=000010 + cp.z=000004 + cp.v=000002 + cp.c=000001 diff --git a/tools/asm-11/lib/defs_rk.mac b/tools/asm-11/lib/defs_rk.mac new file mode 100644 index 00000000..a13be0c2 --- /dev/null +++ b/tools/asm-11/lib/defs_rk.mac @@ -0,0 +1,71 @@ +; $Id: defs_rk.mac 667 2015-04-18 20:16:05Z mueller $ +; Copyright 2014- by Walter F.J. Mueller +; License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +; +; definitions for RK11 controler (as in defs_rk.das) +; +; register addresses +; + rk.ds=177400 + rk.er=177402 + rk.cs=177404 + rk.wc=177406 + rk.ba=177410 + rk.da=177412 + rk.mr=177414 +; +; symbol definitions for rk.cs +; + rk.err=100000 + rk.he=040000 + rk.scp=020000 + rk.mai=010000 + rk.iba=004000 + rk.fmt=002000 + rk.rwa=001000 + rk.sse=000400 + rk.rdy=000200 + rk.ie=000100 + rk.fwr=000002 + rk.frd=000004 + rk.fwc=000006 + rk.fse=000010 + rk.frc=000012 + rk.fdr=000014 + rk.fwl=000016 + rk.go=000001 +; +; symbol definitions for rk.ds +; + rk.id1=020000 + rk.id2=040000 + rk.id3=060000 + rk.id4=100000 + rk.id5=120000 + rk.id6=140000 + rk.id7=160000 + rk.dpl=010000 + rk.hde=004000 + rk.dru=002000 + rk.sin=001000 + rk.sok=000400 + rk.dry=000200 + rk.ary=000100 + rk.wps=000040 + rk.seq=000020 +; +; symbol definitions for rk.er +; + rk.dre=100000 + rk.ovr=040000 + rk.wlo=020000 + rk.ske=010000 + rk.pce=004000 + rk.nxm=002000 + rk.dlt=001000 + rk.rte=000400 + rk.nxd=000200 + rk.nxc=000100 + rk.nxs=000040 + rk.cse=000002 + rk.wce=000001 diff --git a/tools/asm-11/lib/defs_rp.mac b/tools/asm-11/lib/defs_rp.mac new file mode 100644 index 00000000..760dcc6e --- /dev/null +++ b/tools/asm-11/lib/defs_rp.mac @@ -0,0 +1,77 @@ +; $Id: defs_rp.mac 667 2015-04-18 20:16:05Z mueller $ +; Copyright 2015- by Walter F.J. Mueller +; License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +; +; definitions for RH70/RPRM controler +; +; register addresses +; + rp.cs1=176700 + rp.wc =176702 + rp.ba =176704 + rp.da =176706 + rp.cs2=176710 + rp.ds =176712 + rp.er1=176714 + rp.as =176716 + rp.la =176720 + rp.db =176722 + rp.mr1=176724 + rp.dt =176726 + rp.sn =176730 + rp.of =176732 + rp.dc =176734 + rp.m13=176736 + rp.m14=176740 + rp.m15=176742 + rp.ec1=176744 + rp.ec2=176746 + rp.bae=176750 + rp.cs3=176752 +; +; symbol definitions for rp.cs1 +; + rp.sc =100000 + rp.tre=040000 + rp.dva=004000 + rp.rdy=000200 + rp.ie =000100 + rp.fsk=000004 ; seek + rp.fcl=000010 ; drive clear + rp.fse=000030 ; search + rp.fwr=000060 ; write + rp.fwr=000070 ; read + rp.go =000001 +; +; symbol definitions for rp.ds +; + rp.ata=100000 + rp.erp=040000 + rp.pip=020000 + rp.mol=010000 + rp.wrl=004000 + rp.lbt=002000 + rp.pgm=001000 + rp.dpr=000400 + rp.dry=000200 + rp.vv =000100 + rp.om =000001 +; +; symbol definitions for rp.er1 +; + rp.dck=100000 + rp.uns=040000 + rp.opi=020000 + rp.dte=010000 + rp.wle=004000 + rp.iae=002000 + rp.aoe=001000 + rp.hcr=000400 + rp.hce=000200 + rp.ech=000100 + rp.wcf=000040 + rp.fer=000020 + rp.par=000010 + rp.rmr=000004 + rp.ilr=000002 + rp.ilf=000001 diff --git a/tools/asm-11/lib/kprchr.mac b/tools/asm-11/lib/kprchr.mac new file mode 100644 index 00000000..5b29efb0 --- /dev/null +++ b/tools/asm-11/lib/kprchr.mac @@ -0,0 +1,22 @@ +; $Id: kprchr.mac 503 2013-04-06 19:44:13Z mueller $ +; Copyright 2013- by Walter F.J. Mueller +; License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +; +; synchronous (polling) console print: single character +; Call: +; jsr pc, kprchr +; Arguments: +; r0: character to be printed +; +; All registers preserved +; + + XCSR = 177564 + XBUF = 177566 + +kprchr: tstb @#XCSR + bpl kprchr + movb r0,@#XBUF +1$: tstb @#XCSR + bpl 1$ + rts pc diff --git a/tools/asm-11/lib/kprdec.mac b/tools/asm-11/lib/kprdec.mac new file mode 100644 index 00000000..768cc2d8 --- /dev/null +++ b/tools/asm-11/lib/kprdec.mac @@ -0,0 +1,52 @@ +; $Id: kprdec.mac 503 2013-04-06 19:44:13Z mueller $ +; Copyright 2013- by Walter F.J. Mueller +; License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +; +; synchronous (polling) console print: print signed decimal number +; Call: +; jsr pc, kprdec +; Arguments: +; r0: number to print +; +; r1-r5 registers preserved +; + +kprdec: mov r1,-(sp) ; save r1,..,r3 + mov r2,-(sp) + mov r3,-(sp) + + mov r0,r2 ; setup number to convert + bge 1$ ; if negative + neg r2 ; negate + mov #'-,r0 ; and print a '-' + jsr pc,kprchr + +1$: mov #101$,r1 ; r1 points behind end of buffer + clrb -(r1) ; ensure 0-termination + movb #'.,-(r1) ; and trailing '.' to indicate decimal + mov #5,r0 ; loop over 5 digits + + tst r2 ; number 0 + bne 2$ ; if not convert + movb #'0,-(r1) ; if yes, ensure that '0' is printed + br 3$ + +2$: mov r2,r3 ; r2 is rest to convert + beq 3$ ; break if zero + clr r2 ; now (r2,r3) 32bit rest to convert + div #10.,r2 ; div: r2->quotient; r3->reminder + add #'0,r3 ; r3 is reminder, convert to char + movb r3,-(r1) ; write (backwards) to buffer + sob r0,2$ ; go for next digit + +3$: mov r1,r0 ; r1 now points to convered string + jsr pc,kprstr ; print it + + mov (sp)+,r3 ; restore r1,..,r3 + mov (sp)+,r2 + mov (sp)+,r1 + rts pc + +100$: .blkb 7. ; buffer +101$: ; end-of-buffer + .even diff --git a/tools/asm-11/lib/kprfmt.mac b/tools/asm-11/lib/kprfmt.mac new file mode 100644 index 00000000..b9b21b98 --- /dev/null +++ b/tools/asm-11/lib/kprfmt.mac @@ -0,0 +1,53 @@ +; $Id: kprfmt.mac 503 2013-04-06 19:44:13Z mueller $ +; Copyright 2013- by Walter F.J. Mueller +; License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +; +; synchronous (polling) console print: very simple printf +; Call: +; jsr pc, kprfmt +; Arguments: +; r0: pointer format string +; r1: pointer to argument list +; +; r2-r5 registers preserved +; + +kprfmt: mov r2,-(sp) ; save r2 + + mov r0,r2 ; r2 now ptr to fmt string + +1$: movb (r2)+,r0 ; next fmt char + beq 20$ ; if zero quit + cmpb #'%,r0 ; is it '%' ? + bne 10$ ; if not, print + movb (r2)+,r0 ; if yes, get next + beq 20$ ; if zero quit + + cmpb #'s,r0 ; %s found ? + bne 2$ + mov (r1)+,r0 ; get next arg + jsr pc,kprstr ; and print string + br 1$ ; go for next fmt char + +2$: cmpb #'o,r0 ; %o found ? + bne 3$ + mov (r1)+,r0 ; get next arg + jsr pc,kproct ; and print octal number + br 1$ ; go for next fmt char + +3$: cmpb #'d,r0 ; %d found + bne 4$ + mov (r1)+,r0 ; get next arg + jsr pc,kprdec ; and print as decimal number + br 1$ + +4$: movb -2(r2),r0 ; was neither %s,%o,%d + jsr pc,kprchr ; so simply print these two letters... + movb -1(r2),r0 + +10$: jsr pc,kprchr ; print fmt char + br 1$ ; go for next fmt char + +20$: mov (sp)+,r2 ; restore r2 + rts pc + diff --git a/tools/asm-11/lib/kproct.mac b/tools/asm-11/lib/kproct.mac new file mode 100644 index 00000000..889a40a4 --- /dev/null +++ b/tools/asm-11/lib/kproct.mac @@ -0,0 +1,38 @@ +; $Id: kproct.mac 503 2013-04-06 19:44:13Z mueller $ +; Copyright 2013- by Walter F.J. Mueller +; License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +; +; synchronous (polling) console print: print octal number +; Call: +; jsr pc, kproct +; Arguments: +; r0: number to print +; +; r1-r5 registers preserved +; + +kproct: mov r1,-(sp) ; save r1,..,r3 + mov r2,-(sp) + mov r3,-(sp) + mov #101$,r1 ; r1 points behind end of buffer + clrb -(r1) ; ensure 0-termination + mov #6,r2 ; loop over 6 digits +1$: mov r0,r3 ; get reminder + bic #177770,r3 ; mask 3 lsb + add #'0,r3 ; add ascii 0 code + movb r3,-(r1) ; write (backwards) to buffer + clc ; unsigned divide by 8 + ror r0 + asr r0 + asr r0 + sob r2,1$ ; go for next digit + mov r1,r0 ; r1 now points to convered string + jsr pc,kprstr ; print it + mov (sp)+,r3 ; restore r1,..,r3 + mov (sp)+,r2 + mov (sp)+,r1 + rts pc + +100$: .blkb 7. ; buffer +101$: ; end-of-buffer + .even diff --git a/tools/asm-11/lib/kprstr.mac b/tools/asm-11/lib/kprstr.mac new file mode 100644 index 00000000..9849e921 --- /dev/null +++ b/tools/asm-11/lib/kprstr.mac @@ -0,0 +1,21 @@ +; $Id: kprstr.mac 503 2013-04-06 19:44:13Z mueller $ +; Copyright 2013- by Walter F.J. Mueller +; License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +; +; synchronous (polling) console print: print 0-terminated string +; Call: +; jsr pc, kprstr +; Arguments: +; r0: pointer to 0-terminated string +; +; r1-r5 registers preserved +; + +kprstr: mov r1,-(sp) ; save r1 + mov r0,r1 ; r1 now ptr to string +1$: movb (r1)+,r0 ; get next char + beq 2$ ; quit if 0 char + jsr pc,kprchr ; otherwise print char + br 1$ ; go for next char +2$: mov (sp)+,r1 ; restore r1 + rts pc diff --git a/tools/asm-11/lib/vec_cpucatch.mac b/tools/asm-11/lib/vec_cpucatch.mac new file mode 100644 index 00000000..95a9fa13 --- /dev/null +++ b/tools/asm-11/lib/vec_cpucatch.mac @@ -0,0 +1,29 @@ +; $Id: vec_cpucatch.mac 503 2013-04-06 19:44:13Z mueller $ +; Copyright 2013- by Walter F.J. Mueller +; License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +; +; vector catcher for the basic cpu interrupts +; + . = 000004 +v..iit: .word v..iit+2 ; vec 4 + .word 0 +v..rit: .word v..rit+2 ; vec 10 + .word 0 +v..bpt: .word v..bpt+2 ; vec 14 (T bit; BPT) + .word 0 +v..iot: .word v..iot+2 ; vec 20 (IOT) + .word 0 +v..pwr: .word v..pwr+2 ; vec 24 (Power fail, not used) + .word 0 +v..emt: .word v..emt+2 ; vec 30 (EMT) + .word 0 +v..trp: .word v..trp+2 ; vec 34 (TRAP) + .word 0 + + . = 000240 +v..pir: .word v..pir+2 ; vec 240 (PIRQ) + .word 0 +v..fpp: .word v..fpp+2 ; vec 244 (FPP) + .word 0 +v..mmu: .word v..mmu+2 ; vec 250 (MMU) + .word 0 diff --git a/tools/bin/asm-11 b/tools/bin/asm-11 index b1077dbc..eb4a03a6 100755 --- a/tools/bin/asm-11 +++ b/tools/bin/asm-11 @@ -1,5 +1,5 @@ #!/usr/bin/perl -w -# $Id: asm-11 575 2014-07-27 20:55:41Z mueller $ +# $Id: asm-11 659 2015-03-22 23:15:51Z mueller $ # # Copyright 2013-2014 by Walter F.J. Mueller # @@ -506,7 +506,7 @@ sub parse_line { printf "-- parse: '$line'\n" if $opts{tparse} || $opts{ttoken}; - # quit if illegal character found (non 7 bit ascii in asm-11) + # quit if invalid character found (non 7 bit ascii in asm-11) foreach my $c (@{$l{cl}}) { if (ord($c) > 127) { add_err(\%l, 'I'); diff --git a/tools/bin/create_disk b/tools/bin/create_disk index 09baccc4..82f49434 100755 --- a/tools/bin/create_disk +++ b/tools/bin/create_disk @@ -1,5 +1,5 @@ #!/usr/bin/perl -w -# $Id: create_disk 562 2014-06-15 17:23:18Z mueller $ +# $Id: create_disk 679 2015-05-13 17:38:46Z mueller $ # # Copyright 2013-2014 by Walter F.J. Mueller # @@ -14,6 +14,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-04-06 665 1.1.1 add alias RM03 (for RM02) and RP05 (for RP04) # 2014-06-14 562 1.1 BUGFIX: repair --boot; add RM02,RM05,RP04,RP07 # 2013-05-20 521 1.0 First draft # @@ -69,6 +70,10 @@ if (-e $fnam) { } my $typ = uc($opts{typ}); + +$typ = "RM02" if defined $typ && $typ eq "RM03"; # RM03 is equivalent to RM02 +$typ = "RP04" if defined $typ && $typ eq "RP05"; # RM05 is equivalent to RP04 + unless (defined $typ && exists $disktype{$typ}) { print STDERR "create_disk-E: no or invalid --typ specification, use --help\n"; exit 1; @@ -213,12 +218,12 @@ sub do_boot { $buf .= "++======================================++\r\n"; $buf .= "\r\n"; $buf .= "Disk image created with 'create_disk --typ=$typ':\r\n"; - $buf .= sprintf " number of cylinders: %6d\r\n", $cyl; - $buf .= sprintf " tracks per cylinder: %6d\r\n", $hd; - $buf .= sprintf " sectors per track: %6d\r\n", $sec; - $buf .= sprintf " block size: %6d\r\n", $bps; - $buf .= sprintf " total number of sectors: %6d\r\n", $nblk; - $buf .= sprintf " capacity in kByte: %6d\r\n", $cap/1024; + $buf .= sprintf " number of cylinders: %7d\r\n", $cyl; + $buf .= sprintf " tracks per cylinder: %7d\r\n", $hd; + $buf .= sprintf " sectors per track: %7d\r\n", $sec; + $buf .= sprintf " block size: %7d\r\n", $bps; + $buf .= sprintf " total number of sectors:%7d\r\n", $nblk; + $buf .= sprintf " capacity in kByte: %7d\r\n", $cap/1024; $buf .= "\r\n"; $buf .= "CPU WILL HALT\r\n"; $buf .= "\r\n"; @@ -260,6 +265,10 @@ sub print_help { ($disktype{$typ}{bad} ? 'yes' : ' no'); } + print "\n"; + print " RM03 is accepted as an alias for RM02 (same capacity)\n"; + print " RP05 is accepted as an alias for RP04 (same capacity)\n"; + print "\n"; print "currently supported initialization patterns:\n"; print " zero all zero (the default anyway if no -ini given)\n"; diff --git a/tools/bin/tbrun_tbwrri b/tools/bin/tbrun_tbwrri index f41c0c91..666bc0f9 100755 --- a/tools/bin/tbrun_tbwrri +++ b/tools/bin/tbrun_tbwrri @@ -1,14 +1,23 @@ #!/bin/bash -# $Id: tbrun_tbwrri 641 2015-02-01 22:12:15Z mueller $ +# $Id: tbrun_tbwrri 666 2015-04-12 21:17:54Z mueller $ # -# Copyright 2014- by Walter F.J. Mueller +# Copyright 2014-2015 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2015-04-11 666 1.1 add --fusp,--xon # 2014-12-27 622 1.0 Initial version # +chkval () +{ + if [[ $1 =~ --.* || $1 =~ -[a-z]* ]]; then + echo "tbrun_tbwrri-E: value forgotten prior to '$1'" + exit 1 + fi +} + docmd () { echo "$1" @@ -26,40 +35,58 @@ optpack="" optrri="" optpcom="" optcuff="" +optfusp="" +optxon="" # handle options while (( $# > 0 )) ; do case $1 in - -dry|--dry) optdry=$1 ; shift 1 ;; - -lsuf|--lsuf) optlsuf=$2 ; shift 2 ;; - -stack|--stack) optstack=$2 ; shift 2 ;; - -ghw|--ghw) optghw=$2 ; shift 2 ;; - -tbw|--tbw) opttbw=$2 ; shift 2 ;; - -pack|--pack) optpack=$2 ; shift 2 ;; - -rri|--rri) optrri=$2 ; shift 2 ;; - -cuff|--cuff) optcuff=$1 ; shift 1 ;; - -pcom|--pcom) optpcom=$1 ; shift 1 ;; + -dry|--dry) optdry=$1 ; shift 1 ;; + -lsuf|--lsuf) optlsuf=$2 ; chkval $2 ; shift 2 ;; + -stack|--stack) optstack=$2 ; chkval $2 ; shift 2 ;; + -ghw|--ghw) optghw=$2 ; chkval $2 ; shift 2 ;; + -tbw|--tbw) opttbw=$2 ; chkval $2 ; shift 2 ;; + -pack|--pack) optpack=$2 ; chkval $2 ; shift 2 ;; + -rri|--rri) optrri=$2 ; chkval $2 ; shift 2 ;; + -cuff|--cuff) optcuff=$1 ; shift 1 ;; + -fusp|--fusp) optfusp=$1 ; shift 1 ;; + -xon|--xon) optxon=$1 ; shift 1 ;; + -pcom|--pcom) optpcom=$1 ; shift 1 ;; + -\?|-h*|--h*) opthelp=$1 ; shift 1 ;; -*) echo "tbrun_tbwrri-E: invalid option '$1'"; exit 1 ;; *) break;; esac done # complain if no tbench defined -if (( $# == 0 )) ; then +if [[ -n "$opthelp" || $# -eq 0 ]] ; then echo "Usage: tbrun_tbwrri [opts] testbench rricmds..." echo " Options:" echo " --dry dry run, print commands, don't execute" echo " --lsuf suff use '_.log' as suffix for log file" echo " --stack nnn use as ghdl stack size" - echo " --ghw fname write ghw file with name '.ghw" + echo " --ghw fname write ghw file with name '.ghw'" echo " --tbw opts append to tbw command" echo " --pack plist add '--pack=<=plist>' option to ti_rri" echo " --rri opts append to ti_rri command" echo " --cuff use cuff and not serport" + echo " --fusp use 2nd serport" + echo " --xon use xon with 1st serport" echo " --pcom print test comments" exit 1 fi +# check that only one of --cuff --fusp or --xon given +ncfxcount=0 +if [[ -n "$optcuff" ]] ; then ncfxcount=$(($ncfxcount+1)); fi +if [[ -n "$optfusp" ]] ; then ncfxcount=$(($ncfxcount+1)); fi +if [[ -n "$optxon" ]] ; then ncfxcount=$(($ncfxcount+1)); fi + +if (( $ncfxcount > 1 )) ; then + echo "tbrun_tbwrri-E: only one of --cuff,-fusp,--xon allowed" + exit 1 +fi + tbench=$1 shift 1 @@ -92,17 +119,48 @@ logfile="${tbenchname}${logsuff}.log" cmd="time ti_rri --run=\"tbw $tbench -fifo" if [[ -n "$opttbw" ]] ; then cmd+=" $opttbw"; fi if [[ -n "$optstack" ]] ; then cmd+=" --stack-max-size=$optstack"; fi -if [[ -n "$optghw" ]] ; then cmd+=" --wave=$optghw.ghw"; fi +if [[ -n "$optghw" ]] ; then + if [[ "$optghw" != *.ghw ]]; then optghw="$optghw.ghw"; fi + cmd+=" --wave=$optghw"; +fi cmd+=" 2>&1 | ghdl_assert_filter\"" -cmd+=" --fifo --logl=3" + +# Note: the following ensurs that we always have 'fifo=, 0 )) ; then fifoopts+=",noinit"; fi + +if [[ -n "$fifoopts" ]] ; then + cmd+=" --fifo=$fifoopts" +else + cmd+=" --fifo" +fi + +cmd+=" --logl=3" + if [[ -n "$optpack" ]] ; then cmd+=" --pack=$optpack"; fi if [[ -n "$optrri" ]] ; then cmd+=" $optrri"; fi + cmd+=" --" if [[ -n "$optcuff" ]] ; then - cmd+=" \"rlc oob -sbdata 8 0x2\" \"rlc oob -sbdata 16 0x4\"" + cmd+=" \"rlc oob -sbdata 8 0x4\"" # portsel = 0100 -> fx2 + cmd+=" \"rlc oob -sbdata 16 0x4\"" # swi = 0100 -> fx2 fi +if [[ -n "$optfusp" ]] ; then + cmd+=" \"rlc oob -sbdata 8 0x1\"" # portsel = 0001 -> 2nd ser + cmd+=" \"rlc oob -sbdata 16 0x1\"" # swi = 0001 -> 2nd ser +fi + +if [[ -n "$optxon" ]] ; then + cmd+=" \"rlc oob -sbdata 8 0x2\"" # portsel = 0010 -> 1st ser XON + cmd+=" \"rlc oob -sbdata 16 0x2\"" # swi = 0010 -> 1st ser XON +fi + +if (( $ncfxcount > 0 )) ; then cmd+=" \"rlc init\""; fi + while (( $# > 0 )) ; do cmd+=" " if [[ $1 =~ " " ]] ; then cmd+="\""; fi diff --git a/tools/bin/ti_w11 b/tools/bin/ti_w11 index c3599e41..9402499b 100755 --- a/tools/bin/ti_w11 +++ b/tools/bin/ti_w11 @@ -1,11 +1,13 @@ #!/usr/bin/perl -w -# $Id: ti_w11 654 2015-03-01 18:45:38Z mueller $ +# $Id: ti_w11 680 2015-05-14 13:29:46Z mueller $ # # Copyright 2013-2015 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2015-05-14 680 1.3.1 use now -f1,-f1e,-f2,-f2e (fx now f1e) +# 2015-04-13 667 1.3 rename -fu->-fc, add -f2,-fx; setup good defaults # 2015-01-02 640 1.2.2 BUGFIX: allow 'M' unit in baud rates # 2014-12-23 619 1.2.1 use -fifo tbw option for test bench starts # 2014-07-13 570 1.2 BUGFIX: split options args into ti_rri opts and cmds @@ -23,6 +25,7 @@ autoflush STDOUT 1; # autoflush, so nothing lost on exec later my $sysbase = "$ENV{RETROBASE}/rtl/sys_gen/w11a"; +my $opt_dry; my $opt_b; my $opt_io = ''; my $opt_f = ''; @@ -46,7 +49,11 @@ my @arglist; while (scalar(@ARGV)) { my $curarg = $ARGV[0]; - if ($curarg =~ m{^-b$} ) { # -b + if ($curarg =~ m{^-dry$} ) { # -dry + $opt_dry = 1; + shift @ARGV; + + } elsif ($curarg =~ m{^-b$} ) { # -b $opt_b = 1; shift @ARGV; @@ -54,37 +61,43 @@ while (scalar(@ARGV)) { $opt_tmu = 1; shift @ARGV; - } elsif ($curarg =~ m{^-s3$} ) { # -s3 + } elsif ($curarg =~ m{^-s3$} ) { # -s3 (use -f2 by default) $opt_io = 'f'; + $opt_f = '2'; $val_tb = $val_tb_s3; shift @ARGV; - } elsif ($curarg =~ m{^-n2$} ) { # -n2 + } elsif ($curarg =~ m{^-n2$} ) { # -n2 (use -fc by default) $opt_io = 'f'; + $opt_f = 'c'; $val_tb = $val_tb_n2; shift @ARGV; - } elsif ($curarg =~ m{^-n3$} ) { # -n3 + } elsif ($curarg =~ m{^-n3$} ) { # -n3 (use -fc by default) $opt_io = 'f'; + $opt_f = 'c'; $val_tb = $val_tb_n3; shift @ARGV; - } elsif ($curarg =~ m{^-b4$} ) { # -b3 + } elsif ($curarg =~ m{^-b3$} ) { # -b3 (use -f1x by default) $opt_io = 'f'; + $opt_f = '1x'; $val_tb = $val_tb_b3; shift @ARGV; - } elsif ($curarg =~ m{^-n4$} ) { # -n4 + } elsif ($curarg =~ m{^-n4$} ) { # -n4 (prim serport fine) $opt_io = 'f'; + $opt_f = '1'; $val_tb = $val_tb_n4; shift @ARGV; - } elsif ($curarg =~ m{^-bn4$} ) { # -bn4 + } elsif ($curarg =~ m{^-bn4$} ) { # -bn4 (prim serport fine) $opt_io = 'f'; + $opt_f = '1'; $val_tb = $val_tb_bn4; shift @ARGV; - } elsif ($curarg =~ m{^-f(s\d?|u)$} ) { # -f[su] + } elsif ($curarg =~ m{^-f(c|1|1x|2|2x)$} ) { # -f.. $opt_f = $1; shift @ARGV; @@ -152,18 +165,20 @@ while (scalar(@ARGV)) { # # check that either -(s3|n2|n3|n4|bn4) or -t or -u given -# setup pi_rri options for either case +# setup options for either case # if ($opt_io eq 'f') { - push @arglist, '--fifo'; + my $fifoopts = ",noinit"; # fifo always with deferred init + $fifoopts .= ",xon" if $opt_f eq 'x'; + push @arglist, "--fifo=$fifoopts"; push @arglist, "--run=$val_tb"; } elsif ($opt_io eq 't') { push @arglist, "--term=$val_term"; } elsif ($opt_io eq 'u') { push @arglist, '--cuff'; } else { - print STDERR "ti_w11-E: neither -(s3|n2|n3|b3|n4|bn4) nor -t or -u specified\n"; + print STDERR "ti_w11-E: neither -(s3|n2|n3|b3|n4|bn4) nor -t,-u specified\n"; print_usage(); exit 1; } @@ -187,12 +202,26 @@ if ($opt_io eq 'f') { if ($opt_tmu) { push @arglist, 'rlc oob -sbcntl 13 1'; } - if ($opt_f eq 'u') { - push @arglist, 'rlc oob -sbdata 8 0x2'; - push @arglist, 'rlc oob -sbdata 16 0x4'; + if ($opt_f eq 'c') { + push @arglist, 'rlc oob -sbdata 8 0x4'; # portsel = 0100 -> fx2 + push @arglist, 'rlc oob -sbdata 16 0x4'; # swi = 0100 -> fx2 + } elsif ($opt_f eq '1x') { + push @arglist, 'rlc oob -sbdata 8 0x2'; # portsel = 0010 -> 1st ser XON + push @arglist, 'rlc oob -sbdata 16 0x2'; # swi = 0010 -> 1st ser XON + } elsif ($opt_f eq '2') { + push @arglist, 'rlc oob -sbdata 8 0x1'; # portsel = 0001 -> 2nd ser + push @arglist, 'rlc oob -sbdata 16 0x1'; # swi = 0001 -> 2nd ser + } elsif ($opt_f eq '2x') { + push @arglist, 'rlc oob -sbdata 8 0x3'; # portsel = 0011 -> 2nd ser XON + push @arglist, 'rlc oob -sbdata 16 0x3'; # swi = 0011 -> 2nd ser XON } } +# +# --fifo always uses deferred init, so add a rlc init after the oob's +# +push @arglist, 'rlc init' if $opt_io eq 'f'; + # # initialize w11 cpu system # @@ -227,12 +256,16 @@ if ($tirri eq '' || ! -e $tirri) { } # -# print command file +# print command line # if (1) { print 'ti_rri ', join (' ', map {(m{\s}) ? "\"$_\"" : $_} @arglist) , "\n"; } +# +# if dry run, stop here +# +exit 0 if $opt_dry; # # and do it # @@ -245,14 +278,18 @@ exit 1; sub print_usage { print "usage: ti_w11 ...\n"; print " setup options for ghdl simulation runs:\n"; - print " -b3 start tb_w11a_b3 simulation\n"; + print " -b3 start tb_w11a_b3 simulation (default: -f1x)\n"; print " -n4 start tb_w11a_n4 simulation\n"; print " -bn4 start tb_w11a_br_n4 simulation\n"; - print " -n3 start tb_w11a_n3 simulation\n"; - print " -n2 start tb_w11a_n2 simulation\n"; - print " -s3 start tb_w11a_s3 simulation\n"; + print " -n3 start tb_w11a_n3 simulation (default: -fc)\n"; + print " -n2 start tb_w11a_n2 simulation (default: -fc)\n"; + print " -s3 start tb_w11a_s3 simulation (default: -f2)\n"; print " -f.. simulation communication options\n"; - print " -fu use cuff data path\n"; + print " -fc use fx2 data path (cuff)\n"; + print " -f1 use 1st serport\n"; + print " -f1x use 1st serport with xon\n"; + print " -f2 use 2nd serport (fusp)\n"; + print " -f2x use 2nd serport with xon\n"; print " -tmu activate trace and monitoring unit\n"; print " setup options for FPGA connects:\n"; print " -u use --cuff connect\n"; diff --git a/tools/bin/ticonv_pdpcp b/tools/bin/ticonv_pdpcp index 173a7df9..e4c8f176 100755 --- a/tools/bin/ticonv_pdpcp +++ b/tools/bin/ticonv_pdpcp @@ -1,7 +1,7 @@ #!/usr/bin/perl -w -# $Id: ticonv_pdpcp 646 2015-02-15 12:04:55Z mueller $ +# $Id: ticonv_pdpcp 675 2015-05-08 21:05:08Z mueller $ # -# Copyright 2013-2014 by Walter F.J. Mueller +# Copyright 2013-2015 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -14,6 +14,8 @@ # # Revision History: # Date Rev Version Comment +# 2015-05-08 675 1.3.1 start/stop/suspend overhaul +# 2015-04-03 661 1.3 adopt to new stat checking and mask polarity # 2014-12-27 622 1.2.1 use wmembe now # 2014-12-07 609 1.2 use rlink::anena (for rlink v4) # 2014-07-31 576 1.1 add --cmax option (default = 3); support .sdef @@ -51,11 +53,16 @@ my $fnam = $ARGV[1]; my $tout = $opts{tout} || 10.; my $cmax = $opts{cmax} || 6; -my $ref_sdef = 0x00; # by default check for 'hard' errors -my $msk_sdef = 0xf0; # ignore the status bits + attn flag - open IFILE, $fnam or die "failed to open '$fnam'"; +print "set old_statvalue [rlc get statvalue]\n"; +print "set old_statmask [rlc get statmask]\n"; +print "\n"; + +print "rlc set statvalue 0x00\n"; +print "rlc set statmask \$rlink::STAT_DEFMASK\n"; +print "\n"; + while () { chomp; s/--.*//; # drop all -- style comments @@ -94,8 +101,12 @@ while () { # .sdef s=ref[,msk] ------------------------------------------------ } elsif ($cmd =~ /^\.sdef\s+s=([01]+),?([01]*)$/) { cmdlist_do(); - $ref_sdef = oct("0b$1"); - $msk_sdef = oct("0b$2"); + my $ref_sdef = oct("0b$1"); + my $msk_sdef = oct("0b$2"); + $msk_sdef = 0 unless defined $msk_sdef; # nothing ignored if not defined + printf "rlc log \".sdef 0x%2.2x,0x%2.2x\"\n", $ref_sdef, $msk_sdef; + printf "rlc set statvalue 0x%2.2x\n", $ref_sdef; + printf "rlc set statmask 0x%2.2x\n", (0xff & ~$msk_sdef); # .rlmon,.rbmon ---------------------------------------------------- } elsif ($cmd =~ /^\.(r[lb]mon)\s+(\d)$/) { @@ -171,10 +182,10 @@ while () { next if $dat =~ m/^#/; if ($dat =~ m/d=([0-7]+)/ ) { push @data, "0$1"; - push @mask, "0"; + push @mask, "0177777"; } elsif ($dat =~ m/d=-/) { push @data, "0"; - push @mask, "0177777"; + push @mask, "0"; $domask = 1; } else { exit 1; @@ -194,13 +205,13 @@ while () { push @cmdlist, "-$1 0$2"; add_edata($'); - # simple action commands: sta,sto,cont,step,rst -------------------- - } elsif ($cmd =~ /^(sta|sto|cont|step|rst)$/) { + # simple action commands: sta,sto,step,cres,bres ------------------- + } elsif ($cmd =~ /^(sta|sto|step|cres|bres)$/) { my %cmdmap = (sta => 'start', sto => 'stop', - cont => 'continue', step => 'step', - rst => 'reset'); + cres => 'creset', + bres => 'breset'); push @cmdlist, sprintf "-%s", $cmdmap{$1}; # wtgo -> wtcpu ---------------------------------------------------- @@ -230,6 +241,11 @@ while () { } cmdlist_do(); + +print "\n"; +print "rlc set statvalue \$old_statvalue\n"; +print "rlc set statmask \$old_statmask\n"; + exit 0; #------------------------------------------------------------------------------- @@ -246,7 +262,7 @@ sub cmdlist_do { return unless scalar(@cmdlist); # printf "$cpu cp \\\n"; - printf "$cpu cp -estatdef 0x%2.2x 0x%2.2x \\\n", $ref_sdef, $msk_sdef; + print "$cpu cp \\\n"; while (scalar(@cmdlist)) { print " "; print shift @cmdlist; diff --git a/tools/bin/tmuconv b/tools/bin/tmuconv index c1218aef..3c9420a4 100755 --- a/tools/bin/tmuconv +++ b/tools/bin/tmuconv @@ -1,7 +1,7 @@ #!/usr/bin/perl -w -# $Id: tmuconv 334 2010-10-23 08:24:24Z mueller $ +# $Id: tmuconv 676 2015-05-09 16:31:54Z mueller $ # -# Copyright 2008-2010 by Walter F.J. Mueller +# Copyright 2008-2015 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -55,7 +55,9 @@ # vm.ibsres.busy:b # vm.ibsres.dout:o # co.cpugo:b -# co.cpuhalt:b +# co.cpususp:b +# co.suspint:b +# co.suspext:b # sy.emmreq.req:b # sy.emmreq.we:b # sy.emmreq.be:b @@ -314,6 +316,28 @@ my %pdp11_regs = ( # use simh naming convention 177414=> "rk.mr ", 177416=> "rk.db ", 177060=> "xor.cs", # XOR Tester + 176700=> "rpa.cs1", + 176702=> "rpa.wc ", + 176704=> "rpa.ba ", + 176706=> "rpa.da ", + 176710=> "rpa.cs2", + 176712=> "rpa.ds ", + 176714=> "rpa.er1", + 176716=> "rpa.as ", + 176720=> "rpa.la ", + 176722=> "rpa.db ", + 176724=> "rpa.mr1", + 176726=> "rpa.dt ", + 176730=> "rpa.sn ", + 176732=> "rpa.of ", + 176734=> "rpa.dc ", + 176736=> "rpa.m13", + 176740=> "rpa.m14", + 176742=> "rpa.m15", + 176744=> "rpa.ec1", + 176746=> "rpa.ec2", + 176750=> "rpa.bae", + 176752=> "rpa.cs3", 176500=> "ti2.cs", 176502=> "ti2.bu", 176504=> "to2.cs", @@ -797,20 +821,20 @@ sub code2mnemo { $sign = "-"; } return sprintf "$name .%s%d.", $sign, abs(2*$off); - + } elsif ($type eq "sob") { my $reg = ($code>>6) & 07; my $off = $code & 077; return sprintf "$name r%d,.-%d.", $reg, 2*$off; - + } elsif ($type eq "trap") { my $off = $code & 0377; return sprintf "$name %3.3o", $off; - + } elsif ($type eq "spl") { my $off = $code & 07; return sprintf "$name %d", $off; - + } elsif ($type eq "ccop") { my $cc = $code & 017; return "nop" if ($cc == 0); @@ -823,17 +847,17 @@ sub code2mnemo { if ($code & 002) { $str .= $del . $name . "v", $del = "+" } if ($code & 001) { $str .= $del . $name . "c", $del = "+" } return $str; - + } elsif ($type eq "jsr") { my $reg = ($code>>6) & 07; my $dst = $code & 077; my $dst_str = regmod($dst); return "$name r$reg,$dst_str"; - + } elsif ($type eq "mark") { my $off = $code & 077; return sprintf "$name %3.3o", $off; - + } elsif ($type eq "rfpp") { my $reg = ($code>>6) & 03; my $dst = $code & 077; diff --git a/tools/bin/vbomconv b/tools/bin/vbomconv index 105e0f65..2acc08d5 100755 --- a/tools/bin/vbomconv +++ b/tools/bin/vbomconv @@ -1,5 +1,5 @@ #!/usr/bin/perl -w -# $Id: vbomconv 646 2015-02-15 12:04:55Z mueller $ +# $Id: vbomconv 672 2015-05-02 21:58:28Z mueller $ # # Copyright 2007-2015 by Walter F.J. Mueller # @@ -383,6 +383,7 @@ if (exists $opts{ghdl_m} || exists $opts{ghdl_m_cmd} ) { # --xst_prj ---------------------------------------------------------- if (exists $opts{xst_prj}) { + ## $xst_writevhdl = 0; # needed in case "-use_new_parser yes" used foreach (@srcfile_list) { if ($xst_writevhdl) { print "vhdl work $_\n"; diff --git a/tools/dox/w11_cpp.Doxyfile b/tools/dox/w11_cpp.Doxyfile index d9e62b9e..698d2438 100644 --- a/tools/dox/w11_cpp.Doxyfile +++ b/tools/dox/w11_cpp.Doxyfile @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - cpp" -PROJECT_NUMBER = 0.64 +PROJECT_NUMBER = 0.65 PROJECT_BRIEF = "Backend server for Rlink and w11" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/cpp diff --git a/tools/dox/w11_tcl.Doxyfile b/tools/dox/w11_tcl.Doxyfile index 268523af..9bca05f6 100644 --- a/tools/dox/w11_tcl.Doxyfile +++ b/tools/dox/w11_tcl.Doxyfile @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - tcl" -PROJECT_NUMBER = 0.64 +PROJECT_NUMBER = 0.65 PROJECT_BRIEF = "Backend server for Rlink and w11" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/tcl diff --git a/tools/dox/w11_vhd_all.Doxyfile b/tools/dox/w11_vhd_all.Doxyfile index ffda9d04..84faf754 100644 --- a/tools/dox/w11_vhd_all.Doxyfile +++ b/tools/dox/w11_vhd_all.Doxyfile @@ -5,7 +5,7 @@ #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = "w11 - vhd" -PROJECT_NUMBER = 0.64 +PROJECT_NUMBER = 0.65 PROJECT_BRIEF = "W11 CPU core and support modules" PROJECT_LOGO = OUTPUT_DIRECTORY = $(RETRODOXY)/w11/vhd diff --git a/tools/oskit/211bsd_rk/README_211bsd_rkset.txt b/tools/oskit/211bsd_rk/README_211bsd_rkset.txt index a0719119..156b3e6a 100644 --- a/tools/oskit/211bsd_rk/README_211bsd_rkset.txt +++ b/tools/oskit/211bsd_rk/README_211bsd_rkset.txt @@ -1,4 +1,4 @@ -# $Id: README_211bsd_rkset.txt 558 2014-06-01 22:20:51Z mueller $ +# $Id: README_211bsd_rkset.txt 680 2015-05-14 13:29:46Z mueller $ Notes on oskit: 2.11BSD system on RK05 volumes @@ -33,7 +33,8 @@ Notes on oskit: 2.11BSD system on RK05 volumes - Start backend server and boot system (see section 3 in w11a_os_guide.txt) boot script: 211bsd_rk_boot.tcl - example: ti_w11 -u @211bsd_rk_boot.tcl + example: ti_w11 @211bsd_rk_boot.tcl + where is the proper option set for the board. - Hit in the xterm window to connnect to backend server. The boot dialog in the console xterm window will look like @@ -55,10 +56,10 @@ Notes on oskit: 2.11BSD system on RK05 volumes dz ? csr 160100 vector 310 skipped: No CSR. lp 0 csr 177514 vector 200 attached - rk ? csr 177400 vector 220 didn't interrupt. - rl ? csr 174400 vector 160 skipped: No CSR. + rk 0 csr 177400 vector 220 attached + rl 0 csr 174400 vector 160 attached tm ? csr 172520 vector 224 skipped: No CSR. - xp ? csr 176700 vector 254 skipped: No CSR. + xp 0 csr 176700 vector 254 attached cn 1 csr 176500 vector 300 attached erase, kill ^U, intr ^C diff --git a/tools/oskit/211bsd_rl/README_211bsd_rlset.txt b/tools/oskit/211bsd_rl/README_211bsd_rlset.txt index 81f87fe2..8cd0aaff 100644 --- a/tools/oskit/211bsd_rl/README_211bsd_rlset.txt +++ b/tools/oskit/211bsd_rl/README_211bsd_rlset.txt @@ -1,4 +1,4 @@ -# $Id: README_211bsd_rlset.txt 633 2015-01-11 22:58:48Z mueller $ +# $Id: README_211bsd_rlset.txt 680 2015-05-14 13:29:46Z mueller $ Notes on oskit: 2.11BSD system on RL02 volumes @@ -33,7 +33,8 @@ Notes on oskit: 2.11BSD system on RL02 volumes - Start backend server and boot system (see section 3 in w11a_os_guide.txt) boot script: 211bsd_rl_boot.tcl - example: ti_w11 -u @211bsd_rl_boot.tcl + example: ti_w11 @211bsd_rl_boot.tcl + where is the proper option set for the board. - Hit in the xterm window to connnect to backend server. The boot dialog in the console xterm window will look like @@ -55,10 +56,10 @@ Notes on oskit: 2.11BSD system on RL02 volumes dz ? csr 160100 vector 310 skipped: No CSR. lp 0 csr 177514 vector 200 attached - rk ? csr 177400 vector 220 didn't interrupt. + rk 0 csr 177400 vector 220 attached rl 0 csr 174400 vector 160 attached tm ? csr 172520 vector 224 skipped: No CSR. - xp ? csr 176700 vector 254 skipped: No CSR. + xp 0 csr 176700 vector 254 attached cn 1 csr 176500 vector 300 attached erase, kill ^U, intr ^C diff --git a/tools/oskit/211bsd_rp/.cvsignore b/tools/oskit/211bsd_rp/.cvsignore new file mode 100644 index 00000000..d9d13510 --- /dev/null +++ b/tools/oskit/211bsd_rp/.cvsignore @@ -0,0 +1,5 @@ +*.dat +*.dsk +*.log +*license.txt +*license.pdf diff --git a/tools/oskit/211bsd_rp/211bsd_rp_boot.scmd b/tools/oskit/211bsd_rp/211bsd_rp_boot.scmd new file mode 100644 index 00000000..e7b8bb9f --- /dev/null +++ b/tools/oskit/211bsd_rp/211bsd_rp_boot.scmd @@ -0,0 +1,24 @@ +; $Id: 211bsd_rp_boot.scmd 666 2015-04-12 21:17:54Z mueller $ +; +; Setup file for 211bsd RP06 based system +; +; Usage: +; +; pdp11 211bsd_rp_boot.scmd +; +do ../../simh/setup_w11a_max.scmd +set tto 7b +set dlo0 7b +; +set rp0 rp06 +set rp1 rp06 +; +set rl0 rl02 +set rl1 rl02 +set rl2 rl02 +set rl3 rl02 +; +att rp0 211bsd_rp.dsk +att rk6 rk_home.dsk +; +boo rp0 diff --git a/tools/oskit/211bsd_rp/211bsd_rp_boot.tcl b/tools/oskit/211bsd_rp/211bsd_rp_boot.tcl new file mode 100644 index 00000000..d93403a5 --- /dev/null +++ b/tools/oskit/211bsd_rp/211bsd_rp_boot.tcl @@ -0,0 +1,28 @@ +# $Id: 211bsd_rp_boot.tcl 679 2015-05-13 17:38:46Z mueller $ +# +# Setup file for 211bsd RP06 based system +# +# Usage: +# +# console_starter -d DL0 & +# console_starter -d DL1 & +# ti_w11 -xxx @211bsd_rp_boot.tcl ( -xxx depends on sim or fpga connect) +# + +# setup w11 cpu +puts [rlw] + +# setup tt,lp (211bsd uses parity -> use 7 bit mode) +rw11::setup_tt "cpu0" {to7bit 1} +rw11::setup_lp + +# mount disks +cpu0rpa0 set type rp06 +cpu0rpa1 set type rp06 + +cpu0rpa0 att 211bsd_rp.dsk + +# and boot +rw11::cpumon +rw11::cpucons +cpu0 boot rpa0 diff --git a/tools/oskit/211bsd_rp/README_211bsd_rpset.txt b/tools/oskit/211bsd_rp/README_211bsd_rpset.txt new file mode 100644 index 00000000..a63b5da7 --- /dev/null +++ b/tools/oskit/211bsd_rp/README_211bsd_rpset.txt @@ -0,0 +1,134 @@ +# $Id: README_211bsd_rpset.txt 680 2015-05-14 13:29:46Z mueller $ + +Notes on oskit: 2.11BSD system on a RP06 volume + + Table of content: + + 1. General remarks + 2. Installation + 3. Usage + +1. General remarks --------------------------------------------------- + + See notes on + + 1. I/O emulation setup + 2. FPGA Board setup + 3. Rlink and Backend Server setup + 4. Legal terms + + in $RETROBASE/doc/w11a_os_guide.txt + +2. Installation ------------------------------------------------------ + + - A disk set is available from + http://www.retro11.de/data/oc_w11/oskits/211bsd_rpset.tgz + Download, unpack and copy the disk images (*.dsk), e.g. + + cd $RETROBASE/tools/oskit/211bsd_rp/ + wget http://www.retro11.de/data/oc_w11/oskits/211bsd_rpset.tgz + tar -xzf 211bsd_rpset.tgz + +3. Usage ------------------------------------------------------------- + + - Start backend server and boot system (see section 3 in w11a_os_guide.txt) + boot script: 211bsd_rp_boot.tcl + example: ti_w11 @211bsd_rp_boot.tcl + where is the proper option set for the board. + + - Hit in the xterm window to connnect to backend server. + The boot dialog in the console xterm window will look like + (required input is in {..}, with {} denoting a carriage return: + + 70Boot from xp(0,0,0) at 0176700 + : {} + : xp(0,0,0)unix + Boot: bootdev=05000 bootcsr=0176700 + + 2.11 BSD UNIX #9: Wed Dec 10 06:24:37 PST 2008 + root@curly.2bsd.com:/usr/src/sys/RETRONFPNW + + attaching lo0 + + phys mem = 3932160 + avail mem = 3461952 + user mem = 307200 + + January 3 23:00:35 init: configure system + + dz ? csr 160100 vector 310 skipped: No CSR. + lp 0 csr 177514 vector 200 attached + rk 0 csr 177400 vector 220 attached + rl 0 csr 174400 vector 160 attached + tm ? csr 172520 vector 224 skipped: No CSR. + xp 0 csr 176700 vector 254 attached + cn 1 csr 176500 vector 300 attached + erase, kill ^U, intr ^C + + In first '#' prompt the system is in single-user mode. Just enter a ^D + to continue the system startup to multi-user mode: + + #^D + Fast boot ... skipping disk checks + checking quotas: done. + Assuming NETWORKING system ... + ifconfig: ioctl (SIOCGIFFLAGS): no such interface + add host curly.2bsd.com: gateway localhost.2bsd.com + add net default: gateway 206.139.202.1: Network is unreachable + starting system logger + checking for core dump... + preserving editor files + clearing /tmp + standard daemons: update cron accounting. + starting network daemons: inetd printer. + January 3 23:00:47 lpd[76]: /dev/ttyS5: No such file or directory + starting local daemons:Sat Jan 3 23:00:47 PST 2009 + January 3 23:00:47 init: kernel security level changed from 0 to 1 + January 3 23:00:49 getty: /dev/tty04: Device not configured + January 3 23:00:49 getty: /dev/tty03: Device not configured + January 3 23:00:49 getty: /dev/tty00: Device not configured + January 3 23:00:49 getty: /dev/tty01: Device not configured + January 3 23:00:49 getty: /dev/tty02: Device not config + + 2.11 BSD UNIX (curly.2bsd.com) (console) + + login: + + The login prompt is sometimes mangled with the 'Device not configured' + system messages, if its not visible just hit to get a fresh one. + + login: {root} + erase, kill ^U, intr ^C + + Now the system is in multi-user mode, daemons runnng. You can explore + the system, e.g. with a 'pstat -T' or a 'mount' command. The second + xterm can be activated too, it will connect to a second emulated DL11. + At the end is important to shutdown properly with a 'halt': + + # {pstat -T} + 7/186 files + 40/208 inodes + 11/150 processes + 6/ 46 texts active, 31 used + 2/135 swapmap entries, 420 kB used, 2139 kB free, 2133 kB max + 34/150 coremap entries, 2906 kB free, 2818 kB max + 1/ 10 ub_map entries, 10 free, 10 max + # {mount} + /dev/xp0a on / + /dev/xp0c on /usr + # {halt} + syncing disks... done + halting + + While the system was running the server process display the + cpumon> + prompt. When the w11 has halted after 211bsd shutdown a message like + + CPU down attention + Processor registers and status: + Processor registers and status: + PS: 030350 cm,pm=k,u s,p,t=0,7,0 NZVC=1000 rust: 01 HALTed + R0: 177560 R1: 010330 R2: 056172 R3: 000010 + R4: 005000 R5: 147510 SP: 147466 PC: 000014 + + will be visible. Now the server process can be stopped with ^D. diff --git a/tools/oskit/rsx11m-31_rk/README_rsx11m-31_rkset.txt b/tools/oskit/rsx11m-31_rk/README_rsx11m-31_rkset.txt index 26d5ecc2..96fd1728 100644 --- a/tools/oskit/rsx11m-31_rk/README_rsx11m-31_rkset.txt +++ b/tools/oskit/rsx11m-31_rk/README_rsx11m-31_rkset.txt @@ -1,4 +1,4 @@ -# $Id: README_rsx11m-31_rkset.txt 558 2014-06-01 22:20:51Z mueller $ +# $Id: README_rsx11m-31_rkset.txt 680 2015-05-14 13:29:46Z mueller $ Notes on oskit: RSX-11M V3.1 system on RK05 volumes @@ -29,7 +29,8 @@ Notes on oskit: RSX-11M V3.1 system on RK05 volumes - Start them in simulator pdp11 rsx11m-31_rk_boot.scmd or ONLY IF YOU HAVE A VALID LICENSE on w11a - ti_w11 -u @rsx11m-31_rk_boot.tcl + ti_w11 @rsx11m-31_rk_boot.tcl + where is the proper option set for the board. - Hit in the xterm window to connect to simh or backend server. The boot dialog in the console xterm window will look like diff --git a/tools/oskit/rsx11m-40_rk/README_rsx11m-40_rkset.txt b/tools/oskit/rsx11m-40_rk/README_rsx11m-40_rkset.txt index 154cb397..c53bb948 100644 --- a/tools/oskit/rsx11m-40_rk/README_rsx11m-40_rkset.txt +++ b/tools/oskit/rsx11m-40_rk/README_rsx11m-40_rkset.txt @@ -1,4 +1,4 @@ -# $Id: README_rsx11m-40_rkset.txt 580 2014-08-10 15:47:10Z mueller $ +# $Id: README_rsx11m-40_rkset.txt 680 2015-05-14 13:29:46Z mueller $ Notes on oskit: RSX-11M V4.0 system on RK05 volumes @@ -29,7 +29,8 @@ Notes on oskit: RSX-11M V4.0 system on RK05 volumes - Start them in simulator pdp11 rsx11m-40_rk_boot.scmd or ONLY IF YOU HAVE A VALID LICENSE on w11a - ti_w11 -u @rsx11m-40_rk_boot.tcl + ti_w11 @rsx11m-40_rk_boot.tcl + where is the proper option set for the board. - Hit in the xterm window to connect to simh or backend server. The boot dialog in the console xterm window will look like diff --git a/tools/oskit/rsx11mp-30_rp/.cvsignore b/tools/oskit/rsx11mp-30_rp/.cvsignore new file mode 100644 index 00000000..d9d13510 --- /dev/null +++ b/tools/oskit/rsx11mp-30_rp/.cvsignore @@ -0,0 +1,5 @@ +*.dat +*.dsk +*.log +*license.txt +*license.pdf diff --git a/tools/oskit/rsx11mp-30_rp/README_rsx11mp-30_rpset.txt b/tools/oskit/rsx11mp-30_rp/README_rsx11mp-30_rpset.txt new file mode 100644 index 00000000..28391910 --- /dev/null +++ b/tools/oskit/rsx11mp-30_rp/README_rsx11mp-30_rpset.txt @@ -0,0 +1,79 @@ +# $Id: README_rsx11mp-30_rpset.txt 680 2015-05-14 13:29:46Z mueller $ + +Notes on oskit: RSX-11Mplus V3.0 system on RP06 volumes + + Table of content: + + 1. General remarks + 2. Installation + 3. Usage + +1. General remarks --------------------------------------------------- + + See notes, especially on legal terms, in $RETROBASE/doc/w11a_os_guide.txt + + Also read README_license.txt which is included in the oskit !! + +2. Installation ------------------------------------------------------ + + - A disk set is available from + http://www.retro11.de/data/oc_w11/oskits/rsx11mp-30_rpset.tgz + Download, unpack and copy the disk images (*.dsk), e.g. + + cd $RETROBASE/tools/oskit/rsx11mp-30_rp + wget http://www.retro11.de/data/oc_w11/oskits/rsx11mp-30_rpset.tgz + tar -xzf rsx11mp-30_rpset.tgz + +3. Usage ------------------------------------------------------------- + + - Start them in simulator + pdp11 rsx11mp-30_rp_boot.scmd + or ONLY IF YOU HAVE A VALID LICENSE on w11a + ti_w11 @rsx11mp-30_rp_boot.tcl + where is the proper option set for the board. + + - Hit in the xterm window to connect to simh or backend server. + The boot dialog in the console xterm window will look like + (required input is in {..}, with {} denoting a carriage return: + + RSX-11M-PLUS V3.0 BL24 1920.KW System:"RSXMPL" + >RED DB:=SY: + >RED DB:=LB: + >RED DB:=SP: + >MOU DB:"RSX11MPBL24" + >@DB:[1,2]STARTUP + >; ... some comments ... + + This os version was released in July 1985, so it's no suprise + that it is not y2k ready. So enter a date before prior to 2000. + + >* Please enter time and date (HH:MM DD-MMM-YY) [S]: {<.. see above ..>} + + >TIME 12:42 14-MAY-95 + >ACS SY:/BLKS=1024. + >CON ONLINE ALL + >ELI /LOG/LIM + >CLI /INIT=DCL/CTRLC + >INS LB:[1,1]RMSRESAB.TSK/RON=YES/PAR=GEN + >INS LB:[1,1]RMSLBL.TSK/RON=YES/PAR=GEN + >INS LB:[1,1]RMSLBM.TSK/RON=YES/PAR=GEN + >INS $QMGCLI + >INS $QMGCLI/TASK=...PRI + >INS $QMGCLI/TASK=...SUB + >QUE /START:QMG + >INS $QMGPRT/TASK=PRT.../SLV=NO + >QUE LP0:/CR/NM + >START/ACCOUNTING + >CON ESTAT LP0: + >QUE LP0:/SP/FL:2/LOWER/FO:0 + >QUE BAP0:/BATCH + >QUE LP0:/AS:PRINT + >QUE BAP0:/AS:BATCH + >@ + > + + Now you are at the MCR prompt and can exercise the system. + + At the end it is important to shutdown properly with a 'run $shutup'. + The simululaor (or the rlink backend) can be stopped when the + CPU has halted. diff --git a/tools/oskit/rsx11mp-30_rp/rsx11mp-30_rp_boot.scmd b/tools/oskit/rsx11mp-30_rp/rsx11mp-30_rp_boot.scmd new file mode 100644 index 00000000..a6f0a4cc --- /dev/null +++ b/tools/oskit/rsx11mp-30_rp/rsx11mp-30_rp_boot.scmd @@ -0,0 +1,30 @@ +; $Id: rsx11mp-30_rp_boot.scmd 669 2015-04-26 21:20:32Z mueller $ +; +; Setup file for RSX11-M+ V3.0 RP06 based system +; +; Usage: +; +; pdp11 rsx11mp-30_rp_boot.scmd +; +do ../../simh/setup_w11a_max.scmd +set tto 7b +set dlo0 7b +; +set rp0 rp06 +set rp1 rp06 +; +set rl0 rl02 +set rl1 rl02 +set rl2 rl02 +set rl3 rl02 +; +set console debug=rpboot_simh.log +set rp debug + +dep rp rtime 1 +dep rp stime 1 + +; +att rp0 rsx11mp-30.dsk +; +boo rp0 diff --git a/tools/oskit/rsx11mp-30_rp/rsx11mp-30_rp_boot.tcl b/tools/oskit/rsx11mp-30_rp/rsx11mp-30_rp_boot.tcl new file mode 100644 index 00000000..2f5c8892 --- /dev/null +++ b/tools/oskit/rsx11mp-30_rp/rsx11mp-30_rp_boot.tcl @@ -0,0 +1,28 @@ +# $Id: rsx11mp-30_rp_boot.tcl 679 2015-05-13 17:38:46Z mueller $ +# +# Setup file for RSX11-M+ V3.0 RP06 based system +# +# Usage: +# +# console_starter -d DL0 & +# console_starter -d DL1 & +# ti_w11 -xxx @rsx11mp-30_rp_boot.tcl ( -xxx depends on sim or fpga connect) +# + +# setup w11 cpu +puts [rlw] + +# setup tt,lp (211bsd uses parity -> use 7 bit mode) +rw11::setup_tt "cpu0" {to7bit 1} +rw11::setup_lp + +# mount disks +cpu0rpa0 set type rp06 +cpu0rpa1 set type rp06 + +cpu0rpa0 att rsx11mp-30.dsk + +# and boot +rw11::cpumon +rw11::cpucons +cpu0 boot rpa0 diff --git a/tools/oskit/rt11-40_rk/README_rt11-40_rkset.txt b/tools/oskit/rt11-40_rk/README_rt11-40_rkset.txt index 4b8189e2..81d75f03 100644 --- a/tools/oskit/rt11-40_rk/README_rt11-40_rkset.txt +++ b/tools/oskit/rt11-40_rk/README_rt11-40_rkset.txt @@ -1,4 +1,4 @@ -# $Id: README_rt11-40_rkset.txt 558 2014-06-01 22:20:51Z mueller $ +# $Id: README_rt11-40_rkset.txt 680 2015-05-14 13:29:46Z mueller $ Notes on oskit: RT-11 V4.0 system on RK05 volumes @@ -29,7 +29,8 @@ Notes on oskit: RT-11 V4.0 system on RK05 volumes - Start them in simulator pdp11 rt11-40_rk_boot.scmd or ONLY IF YOU HAVE A VALID LICENSE on w11a - ti_w11 -u @rt11-40_rk_boot.tcl + ti_w11 @rt11-40_rk_boot.tcl + where is the proper option set for the board. - Hit in the xterm window to connect to simh or backend server. The boot dialog in the console xterm window will look like diff --git a/tools/oskit/rt11-53_rl/README_rt11-53_rlset.txt b/tools/oskit/rt11-53_rl/README_rt11-53_rlset.txt index 686c8c1d..1557f092 100644 --- a/tools/oskit/rt11-53_rl/README_rt11-53_rlset.txt +++ b/tools/oskit/rt11-53_rl/README_rt11-53_rlset.txt @@ -29,7 +29,8 @@ Notes on oskit: RT-11 V5.3 system on a RL02 volume - Start them in simulator pdp11 rt11-53_rl_boot.scmd or ONLY IF YOU HAVE A VALID LICENSE on w11a - ti_w11 -u @rt11-53_rl_boot.tcl + ti_w11 @rt11-53_rl_boot.tcl + where is the proper option set for the board. - Hit in the xterm window to connect to simh or backend server. The boot dialog in the console xterm window will look like diff --git a/tools/oskit/unix-v5_rk/README_unix_v5_rkset.txt b/tools/oskit/unix-v5_rk/README_unix_v5_rkset.txt index 5e7000b9..025967cc 100644 --- a/tools/oskit/unix-v5_rk/README_unix_v5_rkset.txt +++ b/tools/oskit/unix-v5_rk/README_unix_v5_rkset.txt @@ -1,4 +1,4 @@ -# $Id: README_unix_v5_rkset.txt 558 2014-06-01 22:20:51Z mueller $ +# $Id: README_unix_v5_rkset.txt 680 2015-05-14 13:29:46Z mueller $ Notes on oskit: Unix V5 system on RK05 volumes @@ -33,7 +33,8 @@ Notes on oskit: Unix V5 system on RK05 volumes - Start backend server and boot system (see section 3 in w11a_os_guide.txt) boot script: uv5_rk_boot.tcl - example: ti_w11 -u @uv5_rk_boot.tcl + example: ti_w11 @uv5_rk_boot.tcl + where is the proper option set for the board. - Hit in the xterm window to connect to backend server. The boot dialog in the console xterm window will look like diff --git a/tools/oskit/xxdp_rl/README_xxdp_rlset.txt b/tools/oskit/xxdp_rl/README_xxdp_rlset.txt index 553252ea..cace384f 100644 --- a/tools/oskit/xxdp_rl/README_xxdp_rlset.txt +++ b/tools/oskit/xxdp_rl/README_xxdp_rlset.txt @@ -1,4 +1,4 @@ -# $Id: README_xxdp_rlset.txt 652 2015-02-28 12:18:08Z mueller $ +# $Id: README_xxdp_rlset.txt 680 2015-05-14 13:29:46Z mueller $ Notes on oskit: XXDP V2.2 and V2.5 system on RL02 volumes @@ -38,7 +38,7 @@ Notes on oskit: XXDP V2.2 and V2.5 system on RL02 volumes or on w11a ti_w11 @xxdp22_rl_boot.tcl ti_w11 @xxdp25_rl_boot.tcl - where opt is the proper option set for the board. + where is the proper option set for the board. - Hit in the xterm window to connect to simh or backend server. The boot dialog in the console xterm window will look like diff --git a/tools/src/librlink/ReventLoop.cpp b/tools/src/librlink/ReventLoop.cpp index 5fc19102..1ab43faf 100644 --- a/tools/src/librlink/ReventLoop.cpp +++ b/tools/src/librlink/ReventLoop.cpp @@ -1,6 +1,6 @@ -// $Id: ReventLoop.cpp 511 2013-04-27 13:51:46Z mueller $ +// $Id: ReventLoop.cpp 662 2015-04-05 08:02:54Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-04 662 1.2 BUGFIX: fix race in Stop(), add UnStop,StopPending // 2013-04-27 511 1.1.3 BUGFIX: logic in DoCall() fixed (loop range) // 2013-03-05 495 1.1.2 add exception catcher to EventLoop // 2013-03-01 493 1.1.1 DoCall(): remove handler on negative return @@ -22,7 +23,7 @@ /*! \file - \version $Id: ReventLoop.cpp 511 2013-04-27 13:51:46Z mueller $ + \version $Id: ReventLoop.cpp 662 2015-04-05 08:02:54Z mueller $ \brief Implemenation of class ReventLoop. */ @@ -54,7 +55,7 @@ namespace Retro { //! FIXME_docs ReventLoop::ReventLoop() - : fLoopActive(false), + : fStopPending(false), fUpdatePoll(false), fPollDscMutex(), fPollDsc(), @@ -161,11 +162,10 @@ void ReventLoop::RemovePollHandler(int fd) void ReventLoop::EventLoop() { - fLoopActive = true; fUpdatePoll = true; try { - while (fLoopActive) { + while (!StopPending()) { int irc = DoPoll(); if (fPollFd.size() == 0) break; if (irc>0) DoCall(); @@ -188,7 +188,7 @@ void ReventLoop::Dump(std::ostream& os, int ind, const char* text) const { RosFill bl(ind); os << bl << (text?text:"--") << "ReventLoop @ " << this << endl; - os << bl << " fLoopActive: " << fLoopActive << endl; + os << bl << " fStopPending: " << fStopPending << endl; os << bl << " fUpdatePoll: " << fUpdatePoll << endl; { boost::lock_guard lock(((ReventLoop*)this)->fPollDscMutex); diff --git a/tools/src/librlink/ReventLoop.hpp b/tools/src/librlink/ReventLoop.hpp index ee986dcf..25617a0a 100644 --- a/tools/src/librlink/ReventLoop.hpp +++ b/tools/src/librlink/ReventLoop.hpp @@ -1,6 +1,6 @@ -// $Id: ReventLoop.hpp 513 2013-05-01 14:02:06Z mueller $ +// $Id: ReventLoop.hpp 662 2015-04-05 08:02:54Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-04 662 1.2 BUGFIX: fix race in Stop(), add UnStop,StopPending // 2013-05-01 513 1.1.1 fTraceLevel now uint32_t // 2013-02-22 491 1.1 use new RlogFile/RlogMsg interfaces // 2013-01-11 473 1.0 Initial version @@ -21,7 +22,7 @@ /*! \file - \version $Id: ReventLoop.hpp 513 2013-05-01 14:02:06Z mueller $ + \version $Id: ReventLoop.hpp 662 2015-04-05 08:02:54Z mueller $ \brief Declaration of class \c ReventLoop. */ @@ -60,6 +61,8 @@ namespace Retro { uint32_t TraceLevel() const; void Stop(); + void UnStop(); + bool StopPending(); virtual void EventLoop(); virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; @@ -79,7 +82,7 @@ namespace Retro { fHandler(hdl),fFd(fd),fEvents(evts) {} }; - bool fLoopActive; + bool fStopPending; bool fUpdatePoll; boost::mutex fPollDscMutex; std::vector fPollDsc; diff --git a/tools/src/librlink/ReventLoop.ipp b/tools/src/librlink/ReventLoop.ipp index cf48c6e1..1dd44e46 100644 --- a/tools/src/librlink/ReventLoop.ipp +++ b/tools/src/librlink/ReventLoop.ipp @@ -1,6 +1,6 @@ -// $Id: ReventLoop.ipp 513 2013-05-01 14:02:06Z mueller $ +// $Id: ReventLoop.ipp 662 2015-04-05 08:02:54Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-04 662 1.2 BUGFIX: fix race in Stop(), add UnStop,StopPending // 2013-05-01 513 1.1.1 fTraceLevel now uint32_t // 2013-02-22 491 1.1 use new RlogFile/RlogMsg interfaces // 2013-01-11 473 1.0 Initial version @@ -20,7 +21,7 @@ /*! \file - \version $Id: ReventLoop.ipp 513 2013-05-01 14:02:06Z mueller $ + \version $Id: ReventLoop.ipp 662 2015-04-05 08:02:54Z mueller $ \brief Implemenation (inline) of class ReventLoop. */ @@ -32,13 +33,30 @@ namespace Retro { inline void ReventLoop::Stop() { - fLoopActive = false; + fStopPending = true; return; } //------------------------------------------+----------------------------------- //! FIXME_docs +inline void ReventLoop::UnStop() +{ + fStopPending = false; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline bool ReventLoop::StopPending() +{ + return fStopPending; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + inline void ReventLoop::SetLogFile(const boost::shared_ptr& splog) { fspLog = splog; diff --git a/tools/src/librlink/RlinkCommand.cpp b/tools/src/librlink/RlinkCommand.cpp index 57d09183..a75c6fc2 100644 --- a/tools/src/librlink/RlinkCommand.cpp +++ b/tools/src/librlink/RlinkCommand.cpp @@ -1,4 +1,4 @@ -// $Id: RlinkCommand.cpp 643 2015-02-07 17:41:53Z mueller $ +// $Id: RlinkCommand.cpp 662 2015-04-05 08:02:54Z mueller $ // // Copyright 2011-2015 by Walter F.J. Mueller // @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-02 661 1.3 expect logic: add stat check, Print() without cntx // 2015-02-07 642 1.2.3 Print()+Dump(): adopt for large nblk; // 2014-12-21 617 1.2.2 use kStat_M_RbTout for rbus timeout // 2014-12-20 616 1.2.1 Print(): display BlockDone; add kFlagChkDone @@ -26,7 +27,7 @@ /*! \file - \version $Id: RlinkCommand.cpp 643 2015-02-07 17:41:53Z mueller $ + \version $Id: RlinkCommand.cpp 662 2015-04-05 08:02:54Z mueller $ \brief Implemenation of class RlinkCommand. */ @@ -97,6 +98,9 @@ RlinkCommand::RlinkCommand() fStatus(0), fFlags(0), fRcvSize(0), + fExpectStatusSet(false), + fExpectStatusVal(0), + fExpectStatusMsk(0x0), fpExpect(nullptr) {} @@ -114,6 +118,9 @@ RlinkCommand::RlinkCommand(const RlinkCommand& rhs) fStatus(rhs.fStatus), fFlags(rhs.fFlags), fRcvSize(rhs.fRcvSize), + fExpectStatusSet(rhs.fExpectStatusSet), + fExpectStatusVal(rhs.fExpectStatusVal), + fExpectStatusMsk(rhs.fExpectStatusMsk), fpExpect(rhs.fpExpect ? new RlinkCommandExpect(*rhs.fpExpect) : nullptr) {} @@ -256,24 +263,24 @@ void RlinkCommand::SetExpect(RlinkCommandExpect* pexp) //------------------------------------------+----------------------------------- //! FIXME_docs -void RlinkCommand::Print(std::ostream& os, const RlinkContext& cntx, +void RlinkCommand::Print(std::ostream& os, const RlinkAddrMap* pamap, size_t abase, size_t dbase, size_t sbase) const { uint8_t ccode = Command(); // separator + command mnemonic, code and flags - // separator: ++ first in packet - // -- non-first in packet - // ?? FIXME_code: separator for labo canceled commands - const char* sep = "??"; - if (TestFlagAny(kFlagPktBeg)) { - sep = "++"; - } else { - sep = "--"; - } - - os << sep << " " << CommandName(ccode) + // separator: ++ first in packet + // -- non-first in packet + // -! +! labo with abort + // -. +. labo canceled command + + char sep0 = TestFlagAny(kFlagPktBeg) ? '+' : '-'; + char sep1 = sep0; + if (ccode==kCmdLabo && fData) sep1 = '!'; // indicate aborting labo + if (TestFlagAny(kFlagLabo)) sep1 = '.'; // indicate aborted command + + os << sep0 << sep1 << " " << CommandName(ccode) << " (" << RosPrintBvi(Request(), 8) << "," << RosPrintBvi(fFlags, 16, 20) << ")"; @@ -290,6 +297,12 @@ void RlinkCommand::Print(std::ostream& os, const RlinkContext& cntx, } } + // don't write more that command and address for canceled commands + if (TestFlagAny(kFlagLabo)) { + os << " CANCELED" << endl; + return; + } + // data field (scalar) if (ccode== kCmdRreg || ccode==kCmdWreg || ccode== kCmdLabo || ccode==kCmdAttn || @@ -301,7 +314,7 @@ void RlinkCommand::Print(std::ostream& os, const RlinkContext& cntx, if (TestFlagAny(kFlagChkData)) { os << "#"; os << " D=" << RosPrintBvi(fpExpect->DataValue(), dbase); - if (fpExpect->DataMask() != 0x0000) { + if (fpExpect->DataMask() != 0xffff) { os << "," << RosPrintBvi(fpExpect->DataMask(), dbase); } } else if (fpExpect->DataIsChecked()) { @@ -335,16 +348,14 @@ void RlinkCommand::Print(std::ostream& os, const RlinkContext& cntx, // status field os << " s=" << RosPrintBvi(fStatus, sbase); - uint8_t scval = fpExpect ? fpExpect->StatusValue() : cntx.StatusValue(); - uint8_t scmsk = fpExpect ? fpExpect->StatusMask() : cntx.StatusMask(); if (TestFlagAny(kFlagChkStat)) { os << "#"; - os << " S=" << RosPrintBvi(scval, sbase); - if (scmsk != 0x00) { - os << "," << RosPrintBvi(scmsk, sbase); + os << " S=" << RosPrintBvi(fExpectStatusVal, sbase); + if (fExpectStatusMsk != 0xff) { + os << "," << RosPrintBvi(fExpectStatusMsk, sbase); } } else { - os << ( scmsk != 0xff ? "!" : " " ); + os << (StatusIsChecked() ? (ExpectStatusSet() ? "|" : "!") : " " ); } if (TestFlagAny(kFlagDone)) { @@ -396,7 +407,7 @@ void RlinkCommand::Print(std::ostream& os, const RlinkContext& cntx, os << "\n FAIL d[" << RosPrintf(i,"d",4) << "]: " << RosPrintBvi(pdat[i], dbase) << "#" << " D=" << RosPrintBvi(evalvec[i], dbase); - if (i < emskvec.size() && emskvec[i]!=0x0000) { + if (i < emskvec.size() && emskvec[i]!=0xffff) { os << "," << RosPrintBvi(emskvec[i], dbase); } } @@ -450,8 +461,10 @@ void RlinkCommand::Dump(std::ostream& os, int ind, const char* text) const } os << endl; } + os << bl << " fExpectStatusVal:" << RosPrintBvi(fExpectStatusVal,0) << endl; + os << bl << " fExpectStatusMsk:" << RosPrintBvi(fExpectStatusMsk,0) << endl; if (fpExpect) fpExpect->Dump(os, ind+2, "fpExpect: "); - + return; } @@ -495,18 +508,21 @@ const Retro::RflagName* RlinkCommand::FlagNames() RlinkCommand& RlinkCommand::operator=(const RlinkCommand& rhs) { if (&rhs == this) return *this; - fRequest = rhs.fRequest; - fAddress = rhs.fAddress; - fData = rhs.fData; - fBlock = rhs.fBlock; - fpBlockExt = rhs.fpBlockExt; - fBlockExtSize = rhs.fBlockExtSize; - fBlockDone = rhs.fBlockDone; - fStatus = rhs.fStatus; - fFlags = rhs.fFlags; - fRcvSize = rhs.fRcvSize; + fRequest = rhs.fRequest; + fAddress = rhs.fAddress; + fData = rhs.fData; + fBlock = rhs.fBlock; + fpBlockExt = rhs.fpBlockExt; + fBlockExtSize = rhs.fBlockExtSize; + fBlockDone = rhs.fBlockDone; + fStatus = rhs.fStatus; + fFlags = rhs.fFlags; + fRcvSize = rhs.fRcvSize; + fExpectStatusSet = rhs.fExpectStatusSet; + fExpectStatusVal = rhs.fExpectStatusVal; + fExpectStatusMsk = rhs.fExpectStatusMsk; delete fpExpect; - fpExpect = rhs.fpExpect ? new RlinkCommandExpect(*rhs.fpExpect) : 0; + fpExpect = rhs.fpExpect ? new RlinkCommandExpect(*rhs.fpExpect) : 0; return *this; } diff --git a/tools/src/librlink/RlinkCommand.hpp b/tools/src/librlink/RlinkCommand.hpp index 10e4f85b..a4fa54cd 100644 --- a/tools/src/librlink/RlinkCommand.hpp +++ b/tools/src/librlink/RlinkCommand.hpp @@ -1,6 +1,6 @@ -// $Id: RlinkCommand.hpp 617 2014-12-21 14:18:53Z mueller $ +// $Id: RlinkCommand.hpp 661 2015-04-03 18:28:41Z mueller $ // -// Copyright 2011-2014 by Walter F.J. Mueller +// Copyright 2011-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-02 661 1.3 expect logic: add stat check, Print() without cntx // 2014-12-21 617 1.2.2 use kStat_M_RbTout for rbus timeout // 2014-12-20 616 1.2.1 add kFlagChkDone // 2014-12-06 609 1.2 new rlink v4 iface @@ -24,7 +25,7 @@ /*! \file - \version $Id: RlinkCommand.hpp 617 2014-12-21 14:18:53Z mueller $ + \version $Id: RlinkCommand.hpp 661 2015-04-03 18:28:41Z mueller $ \brief Declaration of class RlinkCommand. */ @@ -74,7 +75,10 @@ namespace Retro { void SetFlagBit(uint32_t mask); void ClearFlagBit(uint32_t mask); void SetRcvSize(size_t rsize); + void SetExpect(RlinkCommandExpect* pexp); + void SetExpectStatus(uint8_t stat, uint8_t statmsk=0xff); + void SetExpectStatusDefault(uint8_t stat=0, uint8_t statmsk=0x0); uint8_t Request() const; uint8_t Command() const; @@ -92,11 +96,17 @@ namespace Retro { bool TestFlagAny(uint32_t mask) const; bool TestFlagAll(uint32_t mask) const; size_t RcvSize() const; - RlinkCommandExpect* Expect() const; - void Print(std::ostream& os, const RlinkContext& cntx, - const RlinkAddrMap* pamap=0, size_t abase=16, - size_t dbase=16, size_t sbase=16) const; + RlinkCommandExpect* Expect() const; + uint8_t ExpectStatusValue() const; + uint8_t ExpectStatusMask() const; + bool ExpectStatusSet() const; + bool StatusCheck() const; + bool StatusIsChecked() const; + + void Print(std::ostream& os, const RlinkAddrMap* pamap=0, + size_t abase=16, size_t dbase=16, + size_t sbase=16) const; void Dump(std::ostream& os, int ind=0, const char* text=0) const; static const char* CommandName(uint8_t cmd); @@ -150,6 +160,9 @@ namespace Retro { uint8_t fStatus; //!< rlink command status uint32_t fFlags; //!< state bits size_t fRcvSize; //!< receive size for command + bool fExpectStatusSet; //!< stat chk set explicitely + uint8_t fExpectStatusVal; //!< status value + uint8_t fExpectStatusMsk; //!< status mask RlinkCommandExpect* fpExpect; //!< pointer to expect container }; diff --git a/tools/src/librlink/RlinkCommand.ipp b/tools/src/librlink/RlinkCommand.ipp index c5a7d2d6..69d9bd00 100644 --- a/tools/src/librlink/RlinkCommand.ipp +++ b/tools/src/librlink/RlinkCommand.ipp @@ -1,6 +1,6 @@ -// $Id: RlinkCommand.ipp 600 2014-11-02 22:33:02Z mueller $ +// $Id: RlinkCommand.ipp 661 2015-04-03 18:28:41Z mueller $ // -// Copyright 2011-2014 by Walter F.J. Mueller +// Copyright 2011-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-02 661 1.3 expect logic: add stat check, Print() without cntx // 2014-11-02 600 1.2 new rlink v4 iface // 2013-05-06 495 1.0.1 add RlinkContext to Print() args; drop oper<<() // 2011-03-27 374 1.0 Initial version @@ -21,7 +22,7 @@ /*! \file - \version $Id: RlinkCommand.ipp 600 2014-11-02 22:33:02Z mueller $ + \version $Id: RlinkCommand.ipp 661 2015-04-03 18:28:41Z mueller $ \brief Implemenation (inline) of class RlinkCommand. */ @@ -139,6 +140,28 @@ inline void RlinkCommand::SetRcvSize(size_t rsize) //------------------------------------------+----------------------------------- //! FIXME_docs +inline void RlinkCommand::SetExpectStatus(uint8_t stat, uint8_t statmsk) +{ + fExpectStatusSet = true; + fExpectStatusVal = stat; + fExpectStatusMsk = statmsk; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline void RlinkCommand::SetExpectStatusDefault(uint8_t stat, uint8_t statmsk) +{ + fExpectStatusSet = false; + fExpectStatusVal = stat; + fExpectStatusMsk = statmsk; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + inline uint8_t RlinkCommand::Request() const { return fRequest; @@ -272,5 +295,45 @@ inline RlinkCommandExpect* RlinkCommand::Expect() const return fpExpect; } +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline uint8_t RlinkCommand::ExpectStatusValue() const +{ + return fExpectStatusVal; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline uint8_t RlinkCommand::ExpectStatusMask() const +{ + return fExpectStatusMsk; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline bool RlinkCommand::ExpectStatusSet() const +{ + return fExpectStatusSet; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline bool RlinkCommand::StatusCheck() const +{ + return (fStatus & fExpectStatusMsk) == fExpectStatusVal; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline bool RlinkCommand::StatusIsChecked() const +{ + return fExpectStatusMsk != 0x0; +} + } // end namespace Retro diff --git a/tools/src/librlink/RlinkCommandExpect.cpp b/tools/src/librlink/RlinkCommandExpect.cpp index cd887b24..875ef064 100644 --- a/tools/src/librlink/RlinkCommandExpect.cpp +++ b/tools/src/librlink/RlinkCommandExpect.cpp @@ -1,6 +1,6 @@ -// $Id: RlinkCommandExpect.cpp 488 2013-02-16 18:49:47Z mueller $ +// $Id: RlinkCommandExpect.cpp 661 2015-04-03 18:28:41Z mueller $ // -// Copyright 2011- by Walter F.J. Mueller +// Copyright 2011-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-02 661 1.1 expect logic: remove stat from Expect, invert mask // 2011-11-28 434 1.0.1 Dump(): use proper cast for lp64 compatibility // 2011-03-12 368 1.0 Initial version // 2011-01-15 355 0.1 First draft @@ -20,7 +21,7 @@ /*! \file - \version $Id: RlinkCommandExpect.cpp 488 2013-02-16 18:49:47Z mueller $ + \version $Id: RlinkCommandExpect.cpp 661 2015-04-03 18:28:41Z mueller $ \brief Implemenation of class RlinkCommandExpect. */ @@ -49,10 +50,8 @@ namespace Retro { //! Default constructor RlinkCommandExpect::RlinkCommandExpect() - : fStatusVal(0), - fStatusMsk(0xff), - fDataVal(0), - fDataMsk(0xffff), + : fDataVal(0), + fDataMsk(0x0), fBlockVal(), fBlockMsk() {} @@ -60,23 +59,8 @@ RlinkCommandExpect::RlinkCommandExpect() //------------------------------------------+----------------------------------- //! FIXME_docs -RlinkCommandExpect::RlinkCommandExpect(uint8_t stat, uint8_t statmsk) - : fStatusVal(stat), - fStatusMsk(statmsk), - fDataVal(0), - fDataMsk(0xffff), - fBlockVal(), - fBlockMsk() -{} - -//------------------------------------------+----------------------------------- -//! FIXME_docs - -RlinkCommandExpect::RlinkCommandExpect(uint8_t stat, uint8_t statmsk, - uint16_t data, uint16_t datamsk) - : fStatusVal(stat), - fStatusMsk(statmsk), - fDataVal(data), +RlinkCommandExpect::RlinkCommandExpect(uint16_t data, uint16_t datamsk) + : fDataVal(data), fDataMsk(datamsk), fBlockVal(), fBlockMsk() @@ -85,12 +69,9 @@ RlinkCommandExpect::RlinkCommandExpect(uint8_t stat, uint8_t statmsk, //------------------------------------------+----------------------------------- //! FIXME_docs -RlinkCommandExpect::RlinkCommandExpect(uint8_t stat, uint8_t statmsk, - const std::vector& block) - : fStatusVal(stat), - fStatusMsk(statmsk), - fDataVal(0), - fDataMsk(0xffff), +RlinkCommandExpect::RlinkCommandExpect(const std::vector& block) + : fDataVal(0), + fDataMsk(0x0), fBlockVal(block), fBlockMsk() {} @@ -98,13 +79,10 @@ RlinkCommandExpect::RlinkCommandExpect(uint8_t stat, uint8_t statmsk, //------------------------------------------+----------------------------------- //! FIXME_docs -RlinkCommandExpect::RlinkCommandExpect(uint8_t stat, uint8_t statmsk, - const std::vector& block, +RlinkCommandExpect::RlinkCommandExpect(const std::vector& block, const std::vector& blockmsk) - : fStatusVal(stat), - fStatusMsk(statmsk), - fDataVal(0), - fDataMsk(0xffff), + : fDataVal(0), + fDataMsk(0x0), fBlockVal(block), fBlockMsk(blockmsk) {} @@ -122,8 +100,8 @@ bool RlinkCommandExpect::BlockCheck(size_t ind, uint16_t val) const { if (ind >= fBlockVal.size()) return true; uint16_t eval = fBlockVal[ind]; - uint16_t emsk = (ind < fBlockMsk.size()) ? fBlockMsk[ind] : 0x0000; - return (val|emsk) == (eval|emsk); + uint16_t emsk = (ind < fBlockMsk.size()) ? fBlockMsk[ind] : 0xffff; + return (val & emsk) == eval; } //------------------------------------------+----------------------------------- @@ -135,8 +113,8 @@ size_t RlinkCommandExpect::BlockCheck(const uint16_t* pval, size_t size) const for (size_t i=0; i= fBlockVal.size()) break; uint16_t eval = fBlockVal[i]; - uint16_t emsk = (i < fBlockMsk.size()) ? fBlockMsk[i] : 0x0000; - if ((pval[i]|emsk) != (eval|emsk)) nerr += 1; + uint16_t emsk = (i < fBlockMsk.size()) ? fBlockMsk[i] : 0xffff; + if ((pval[i] & emsk) != eval) nerr += 1; } return nerr; @@ -149,7 +127,7 @@ bool RlinkCommandExpect::BlockIsChecked(size_t ind) const { if (ind >= fBlockVal.size()) return false; if (ind >= fBlockMsk.size()) return true; - return fBlockMsk[ind] != 0xffff; + return fBlockMsk[ind] != 0x0; } //------------------------------------------+----------------------------------- @@ -160,8 +138,6 @@ void RlinkCommandExpect::Dump(std::ostream& os, int ind, const char* text) const RosFill bl(ind); os << bl << (text?text:"--") << "RlinkCommandExpect @ " << this << endl; - os << bl << " fStatusVal: " << RosPrintBvi(fStatusVal,0) << endl; - os << bl << " fStatusMsk: " << RosPrintBvi(fStatusMsk,0) << endl; os << bl << " fDataVal: " << RosPrintBvi(fDataVal,0) << endl; os << bl << " fDataMsk: " << RosPrintBvi(fDataMsk,0) << endl; os << bl << " fBlockVal.size: " << RosPrintf(fBlockVal.size(),"d",3) << endl; @@ -175,7 +151,7 @@ void RlinkCommandExpect::Dump(std::ostream& os, int ind, const char* text) const os << RosPrintBvi(fBlockVal[i],16); if (fBlockMsk.size()>0) { - if (i +// Copyright 2011-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-02 661 1.2 expect logic: remove stat from Expect, invert mask // 2014-12-20 616 1.1 add Done count methods (for rblk/wblk) // 2011-03-12 368 1.0 Initial version // 2011-01-15 355 0.1 First draft @@ -21,7 +22,7 @@ /*! \file - \version $Id: RlinkCommandExpect.hpp 616 2014-12-21 10:09:25Z mueller $ + \version $Id: RlinkCommandExpect.hpp 661 2015-04-03 18:28:41Z mueller $ \brief Declaration of class RlinkCommandExpect. */ @@ -37,38 +38,29 @@ namespace Retro { public: RlinkCommandExpect(); - explicit RlinkCommandExpect(uint8_t stat, uint8_t statmsk=0); - RlinkCommandExpect(uint8_t stat, uint8_t statmsk, - uint16_t data, uint16_t datamsk=0); - RlinkCommandExpect(uint8_t stat, uint8_t statmsk, - const std::vector& block); - RlinkCommandExpect(uint8_t stat, uint8_t statmsk, - const std::vector& block, + RlinkCommandExpect(uint16_t data, uint16_t datamsk=0xffff); + RlinkCommandExpect(const std::vector& block); + RlinkCommandExpect(const std::vector& block, const std::vector& blockmsk); ~RlinkCommandExpect(); - void SetStatus(uint8_t stat, uint8_t statmsk=0); void SetData(uint16_t data, uint16_t datamsk=0); void SetDone(uint16_t done, bool check=true); void SetBlock(const std::vector& block); void SetBlock(const std::vector& block, const std::vector& blockmsk); - uint8_t StatusValue() const; - uint8_t StatusMask() const; uint16_t DataValue() const; uint16_t DataMask() const; uint16_t DoneValue() const; const std::vector& BlockValue() const; const std::vector& BlockMask() const; - bool StatusCheck(uint8_t val) const; bool DataCheck(uint16_t val) const; bool DoneCheck(uint16_t val) const; bool BlockCheck(size_t ind, uint16_t val) const; size_t BlockCheck(const uint16_t* pval, size_t size) const; - bool StatusIsChecked() const; bool DataIsChecked() const; bool DoneIsChecked() const; bool BlockIsChecked(size_t ind) const; @@ -76,8 +68,6 @@ namespace Retro { void Dump(std::ostream& os, int ind=0, const char* text=0) const; protected: - uint8_t fStatusVal; //!< status value - uint8_t fStatusMsk; //!< status mask uint16_t fDataVal; //!< data value uint16_t fDataMsk; //!< data mask std::vector fBlockVal; //!< block value diff --git a/tools/src/librlink/RlinkCommandExpect.ipp b/tools/src/librlink/RlinkCommandExpect.ipp index 4f286459..d392430d 100644 --- a/tools/src/librlink/RlinkCommandExpect.ipp +++ b/tools/src/librlink/RlinkCommandExpect.ipp @@ -1,6 +1,6 @@ -// $Id: RlinkCommandExpect.ipp 616 2014-12-21 10:09:25Z mueller $ +// $Id: RlinkCommandExpect.ipp 661 2015-04-03 18:28:41Z mueller $ // -// Copyright 2011-2014 by Walter F.J. Mueller +// Copyright 2011-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-02 661 1.2 expect logic: remove stat from Expect, invert mask // 2014-12-20 616 1.1 add Done count methods (for rblk/wblk) // 2011-03-12 368 1.0 Initial version // 2011-01-15 355 0.1 First draft @@ -20,7 +21,7 @@ /*! \file - \version $Id: RlinkCommandExpect.ipp 616 2014-12-21 10:09:25Z mueller $ + \version $Id: RlinkCommandExpect.ipp 661 2015-04-03 18:28:41Z mueller $ \brief Implemenation (inline) of class RlinkCommandExpect. */ @@ -30,16 +31,6 @@ namespace Retro { //------------------------------------------+----------------------------------- //! FIXME_docs -inline void RlinkCommandExpect::SetStatus(uint8_t stat, uint8_t statmsk) -{ - fStatusVal = stat; - fStatusMsk = statmsk; - return; -} - -//------------------------------------------+----------------------------------- -//! FIXME_docs - inline void RlinkCommandExpect::SetData(uint16_t data, uint16_t datamsk) { fDataVal = data; @@ -53,7 +44,7 @@ inline void RlinkCommandExpect::SetData(uint16_t data, uint16_t datamsk) inline void RlinkCommandExpect::SetDone(uint16_t done, bool check) { fDataVal = done; - fDataMsk = check ? 0 : 0xffff; + fDataMsk = check ? 0xffff : 0x0; return; } @@ -81,22 +72,6 @@ inline void RlinkCommandExpect::SetBlock( //------------------------------------------+----------------------------------- //! FIXME_docs -inline uint8_t RlinkCommandExpect::StatusValue() const -{ - return fStatusVal; -} - -//------------------------------------------+----------------------------------- -//! FIXME_docs - -inline uint8_t RlinkCommandExpect::StatusMask() const -{ - return fStatusMsk; -} - -//------------------------------------------+----------------------------------- -//! FIXME_docs - inline uint16_t RlinkCommandExpect::DataValue() const { return fDataVal; @@ -137,17 +112,9 @@ inline const std::vector& RlinkCommandExpect::BlockMask() const //------------------------------------------+----------------------------------- //! FIXME_docs -inline bool RlinkCommandExpect::StatusCheck(uint8_t val) const -{ - return (val|fStatusMsk) == (fStatusVal|fStatusMsk); -} - -//------------------------------------------+----------------------------------- -//! FIXME_docs - inline bool RlinkCommandExpect::DataCheck(uint16_t val) const { - return (val|fDataMsk) == (fDataVal|fDataMsk); + return (val & fDataMsk) == fDataVal; } //------------------------------------------+----------------------------------- @@ -161,17 +128,9 @@ inline bool RlinkCommandExpect::DoneCheck(uint16_t val) const //------------------------------------------+----------------------------------- //! FIXME_docs -inline bool RlinkCommandExpect::StatusIsChecked() const -{ - return fStatusMsk != 0xff; -} - -//------------------------------------------+----------------------------------- -//! FIXME_docs - inline bool RlinkCommandExpect::DataIsChecked() const { - return fDataMsk != 0xffff; + return fDataMsk != 0x0; } //------------------------------------------+----------------------------------- @@ -179,7 +138,7 @@ inline bool RlinkCommandExpect::DataIsChecked() const inline bool RlinkCommandExpect::DoneIsChecked() const { - return fDataMsk == 0; + return fDataMsk != 0x0; } } // end namespace Retro diff --git a/tools/src/librlink/RlinkCommandList.cpp b/tools/src/librlink/RlinkCommandList.cpp index 013e9388..5c0153a9 100644 --- a/tools/src/librlink/RlinkCommandList.cpp +++ b/tools/src/librlink/RlinkCommandList.cpp @@ -1,6 +1,6 @@ -// $Id: RlinkCommandList.cpp 606 2014-11-24 07:08:51Z mueller $ +// $Id: RlinkCommandList.cpp 661 2015-04-03 18:28:41Z mueller $ // -// Copyright 2011-2014 by Walter F.J. Mueller +// Copyright 2011-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-02 661 1.3 expect logic: add SetLastExpect methods // 2014-11-23 606 1.2 new rlink v4 iface // 2014-08-02 576 1.1 rename LastExpect->SetLastExpect // 2013-05-06 495 1.0.3 add RlinkContext to Print() args @@ -24,7 +25,7 @@ /*! \file - \version $Id: RlinkCommandList.cpp 606 2014-11-24 07:08:51Z mueller $ + \version $Id: RlinkCommandList.cpp 661 2015-04-03 18:28:41Z mueller $ \brief Implemenation of class RlinkCommandList. */ @@ -200,13 +201,81 @@ size_t RlinkCommandList::AddInit(uint16_t addr, uint16_t data) //------------------------------------------+----------------------------------- //! FIXME_docs +void RlinkCommandList::SetLastExpectStatus(uint8_t stat, uint8_t statmsk) +{ + if (fList.empty()) + throw Rexception("RlinkCommandList::SetLastExpectStatus()", + "Bad state: list empty"); + fList.back()->SetExpectStatus(stat, statmsk); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void RlinkCommandList::SetLastExpectData(uint16_t data, uint16_t datamsk) +{ + if (fList.empty()) + throw Rexception("RlinkCommandList::SetLastExpectData()", + "Bad state: list empty"); + RlinkCommand& cmd = *fList.back(); + if (!cmd.Expect()) cmd.SetExpect(new RlinkCommandExpect()); + cmd.Expect()->SetData(data, datamsk); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void RlinkCommandList::SetLastExpectDone(uint16_t done) +{ + if (fList.empty()) + throw Rexception("RlinkCommandList::SetLastExpectDone()", + "Bad state: list empty"); + RlinkCommand& cmd = *fList.back(); + if (!cmd.Expect()) cmd.SetExpect(new RlinkCommandExpect()); + cmd.Expect()->SetDone(done); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void RlinkCommandList::SetLastExpectBlock(const std::vector& block) +{ + if (fList.empty()) + throw Rexception("RlinkCommandList::SetLastExpectBlock()", + "Bad state: list empty"); + RlinkCommand& cmd = *fList.back(); + if (!cmd.Expect()) cmd.SetExpect(new RlinkCommandExpect()); + cmd.Expect()->SetBlock(block); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + + void RlinkCommandList::SetLastExpectBlock(const std::vector& block, + const std::vector& blockmsk) +{ + if (fList.empty()) + throw Rexception("RlinkCommandList::SetLastExpectBlock()", + "Bad state: list empty"); + RlinkCommand& cmd = *fList.back(); + if (!cmd.Expect()) cmd.SetExpect(new RlinkCommandExpect()); + cmd.Expect()->SetBlock(block, blockmsk); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + void RlinkCommandList::SetLastExpect(RlinkCommandExpect* pexp) { - size_t ncmd = fList.size(); - if (ncmd == 0) + if (fList.empty()) throw Rexception("RlinkCommandList::SetLastExpect()", "Bad state: list empty"); - fList[ncmd-1]->SetExpect(pexp); + fList.back()->SetExpect(pexp); return; } @@ -224,12 +293,12 @@ void RlinkCommandList::Clear() //------------------------------------------+----------------------------------- //! FIXME_docs -void RlinkCommandList::Print(std::ostream& os, const RlinkContext& cntx, +void RlinkCommandList::Print(std::ostream& os, const RlinkAddrMap* pamap, size_t abase, size_t dbase, size_t sbase) const { foreach_ (RlinkCommand* pcmd, fList) { - pcmd->Print(os, cntx, pamap, abase, dbase, sbase); + pcmd->Print(os, pamap, abase, dbase, sbase); } return; } diff --git a/tools/src/librlink/RlinkCommandList.hpp b/tools/src/librlink/RlinkCommandList.hpp index c2222846..b192ed87 100644 --- a/tools/src/librlink/RlinkCommandList.hpp +++ b/tools/src/librlink/RlinkCommandList.hpp @@ -1,6 +1,6 @@ -// $Id: RlinkCommandList.hpp 606 2014-11-24 07:08:51Z mueller $ +// $Id: RlinkCommandList.hpp 661 2015-04-03 18:28:41Z mueller $ // -// Copyright 2011-2014 by Walter F.J. Mueller +// Copyright 2011-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-02 661 1.3 expect logic: add SetLastExpect methods // 2014-11-23 606 1.2 new rlink v4 iface // 2014-08-02 576 1.1 rename LastExpect->SetLastExpect // 2013-05-06 495 1.0.1 add RlinkContext to Print() args; drop oper<<() @@ -23,7 +24,7 @@ /*! \file - \version $Id: RlinkCommandList.hpp 606 2014-11-24 07:08:51Z mueller $ + \version $Id: RlinkCommandList.hpp 661 2015-04-03 18:28:41Z mueller $ \brief Declaration of class RlinkCommandList. */ @@ -62,6 +63,12 @@ namespace Retro { size_t AddAttn(); size_t AddInit(uint16_t addr, uint16_t data); + void SetLastExpectStatus(uint8_t stat, uint8_t statmsk=0xff); + void SetLastExpectData(uint16_t data, uint16_t datamsk=0xffff); + void SetLastExpectDone(uint16_t done); + void SetLastExpectBlock(const std::vector& block); + void SetLastExpectBlock(const std::vector& block, + const std::vector& blockmsk); void SetLastExpect(RlinkCommandExpect* exp); void ClearLaboIndex(); @@ -72,9 +79,9 @@ namespace Retro { void Clear(); size_t Size() const; - void Print(std::ostream& os, const RlinkContext& cntx, - const RlinkAddrMap* pamap=0, size_t abase=16, - size_t dbase=16, size_t sbase=16) const; + void Print(std::ostream& os, const RlinkAddrMap* pamap=0, + size_t abase=16, size_t dbase=16, + size_t sbase=16) const; void Dump(std::ostream& os, int ind=0, const char* text=0) const; RlinkCommandList& operator=(const RlinkCommandList& rhs); diff --git a/tools/src/librlink/RlinkConnect.cpp b/tools/src/librlink/RlinkConnect.cpp index 9ceb33fe..a05ae7dd 100644 --- a/tools/src/librlink/RlinkConnect.cpp +++ b/tools/src/librlink/RlinkConnect.cpp @@ -1,4 +1,4 @@ -// $Id: RlinkConnect.cpp 632 2015-01-11 12:30:03Z mueller $ +// $Id: RlinkConnect.cpp 679 2015-05-13 17:38:46Z mueller $ // // Copyright 2011-2015 by Walter F.J. Mueller // @@ -13,6 +13,9 @@ // // Revision History: // Date Rev Version Comment +// 2015-05-10 678 2.3.1 WaitAttn(): BUGFIX: return 0. (not -1.) if poll +// 2015-04-12 666 2.3 add LinkInit,LinkInitDone; transfer xon +// 2015-04-02 661 2.2 expect logic: stat expect in Command, invert mask // 2015-01-06 631 2.1 full rlink v4 implementation // 2014-12-10 611 2.0 re-organize for rlink v4 // 2014-08-26 587 1.5 start accept rlink v4 protocol (partially...) @@ -33,7 +36,7 @@ /*! \file - \version $Id: RlinkConnect.cpp 632 2015-01-11 12:30:03Z mueller $ + \version $Id: RlinkConnect.cpp 679 2015-05-13 17:38:46Z mueller $ \brief Implemenation of RlinkConnect. */ @@ -91,18 +94,20 @@ const uint16_t RlinkConnect::kRbufPrudentDelta; RlinkConnect::RlinkConnect() : fpPort(), + fLinkInitDeferred(false), + fLinkInitDone(false), fpServ(nullptr), fSndPkt(), fRcvPkt(), fContext(), fAddrMap(), fStats(), - fLogBaseAddr(16), - fLogBaseData(16), - fLogBaseStat(16), - fPrintLevel(0), - fDumpLevel(0), - fTraceLevel(0), + fLogBaseAddr(16), // addr default radix: hex + fLogBaseData(16), // data default radix: hex + fLogBaseStat(16), // stat default radix: hex + fPrintLevel(2), // default print: error and checks + fDumpLevel(0), // default dump: no + fTraceLevel(0), // default trace: no fspLog(new RlogFile(&cout)), fConnectMutex(), fAttnNotiPatt(0), @@ -111,7 +116,11 @@ RlinkConnect::RlinkConnect() fRbufSize(2048) { for (size_t i=0; i<8; i++) fSeqNumber[i] = 0; - + + fContext.SetStatus(0, RlinkCommand::kStat_M_RbTout | + RlinkCommand::kStat_M_RbNak | + RlinkCommand::kStat_M_RbErr); + // Statistic setup fStats.Define(kStatNExec, "NExec", "Exec() calls"); fStats.Define(kStatNExecPart, "NExecPart", "ExecPart() calls"); @@ -125,11 +134,12 @@ RlinkConnect::RlinkConnect() fStats.Define(kStatNInit, "NInit", "init commands"); fStats.Define(kStatNRblkWord, "NRblkWord", "words rcvd with rblk"); fStats.Define(kStatNWblkWord, "NWblkWord", "words send with wblk"); - fStats.Define(kStatNExpData, "NExpData", "Expect() for data defined"); - fStats.Define(kStatNExpDone, "NExpDone", "Expect() for done defined"); - fStats.Define(kStatNExpStat, "NExpStat", "Expect() for stat defined"); + fStats.Define(kStatNExpData, "NExpData", "expect for data defined"); + fStats.Define(kStatNExpDone, "NExpDone", "expect for done defined"); + fStats.Define(kStatNExpStat, "NExpStat", "expect for stat explicit"); + fStats.Define(kStatNNoExpStat,"NNoExpStat","no expect for stat"); fStats.Define(kStatNChkData, "NChkData", "expect data failed"); - fStats.Define(kStatNChkDone, "NChkData", "expect done failed"); + fStats.Define(kStatNChkDone, "NChkDone", "expect done failed"); fStats.Define(kStatNChkStat, "NChkStat", "expect stat failed"); fStats.Define(kStatNSndOob, "NSndOob", "SndOob() calls"); fStats.Define(kStatNErrMiss, "NErrMiss", "decode: missing data"); @@ -156,26 +166,22 @@ bool RlinkConnect::Open(const std::string& name, RerrMsg& emsg) fpPort.reset(RlinkPortFactory::Open(name, emsg)); if (!fpPort) return false; + fSndPkt.SetXonEscape(fpPort->XonEnable()); // transfer XON enable + fpPort->SetLogFile(fspLog); fpPort->SetTraceLevel(fTraceLevel); - RlinkCommandList clist; - clist.AddRreg(kRbaddr_RLSTAT); - clist.AddRreg(kRbaddr_RLID1); - clist.AddRreg(kRbaddr_RLID0); - - if (!Exec(clist, emsg)) { - Close(); - return false; + fLinkInitDone = false; + fRbufSize = 2048; // use minimum (2kB) as startup + fSysId = 0xffffffff; + + if (! fpPort->Url().FindOpt("noinit")) { + if (!LinkInit(emsg)) { + Close(); + return false; + } } - uint16_t rlstat = clist[0].Data(); - uint16_t rlid1 = clist[1].Data(); - uint16_t rlid0 = clist[2].Data(); - - fRbufSize = size_t(1) << (10 + (rlstat & kRLSTAT_M_RBSize)); - fSysId = uint32_t(rlid1)<<16 | uint32_t(rlid0); - return true; } @@ -198,6 +204,32 @@ void RlinkConnect::Close() return; } +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool RlinkConnect::LinkInit(RerrMsg& emsg) +{ + if (fLinkInitDone) return true; + + RlinkCommandList clist; + clist.AddRreg(kRbaddr_RLSTAT); + clist.AddRreg(kRbaddr_RLID1); + clist.AddRreg(kRbaddr_RLID0); + + if (!Exec(clist, emsg)) return false; + + fLinkInitDone = true; + + uint16_t rlstat = clist[0].Data(); + uint16_t rlid1 = clist[1].Data(); + uint16_t rlid0 = clist[2].Data(); + + fRbufSize = size_t(1) << (10 + (rlstat & kRLSTAT_M_RBSize)); + fSysId = uint32_t(rlid1)<<16 | uint32_t(rlid0); + + return true; +} + //------------------------------------------+----------------------------------- //! Indicates whether server is active. /*! @@ -276,6 +308,8 @@ bool RlinkConnect::Exec(RlinkCommandList& clist, RlinkContext& cntx, clist.ClearLaboIndex(); + uint8_t defstatval = cntx.StatusValue(); + uint8_t defstatmsk = cntx.StatusMask(); size_t size = clist.Size(); for (size_t i=0; iiend || iend>=clist.Size()) throw Rexception("RlinkConnect::ExecPart()", @@ -666,7 +706,7 @@ bool RlinkConnect::ExecPart(RlinkCommandList& clist, size_t ibeg, size_t iend, bool ok = ReadResponse(15., emsg); if (!ok) Rexception("RlinkConnect::ExecPart()","faulty response"); - int ncmd = DecodeResponse(clist, ibeg, iend, cntx); + int ncmd = DecodeResponse(clist, ibeg, iend); if (ncmd != int(iend-ibeg+1)) { clist.Dump(cout); throw Rexception("RlinkConnect::ExecPart()","incomplete response"); @@ -764,8 +804,8 @@ void RlinkConnect::EncodeRequest(RlinkCommandList& clist, size_t ibeg, //------------------------------------------+----------------------------------- //! FIXME_docs -int RlinkConnect::DecodeResponse(RlinkCommandList& clist, size_t ibeg, - size_t iend, RlinkContext& cntx) +int RlinkConnect::DecodeResponse(RlinkCommandList& clist, size_t ibeg, + size_t iend) { size_t ncmd = 0; @@ -872,7 +912,6 @@ int RlinkConnect::DecodeResponse(RlinkCommandList& clist, size_t ibeg, } else { if (expect.DataIsChecked()) fStats.Inc(kStatNExpData); } - if (expect.StatusIsChecked()) fStats.Inc(kStatNExpStat); if (ccode==RlinkCommand::kCmdRreg || ccode==RlinkCommand::kCmdLabo || @@ -894,19 +933,18 @@ int RlinkConnect::DecodeResponse(RlinkCommandList& clist, size_t ibeg, fStats.Inc(kStatNChkDone); cmd.SetFlagBit(RlinkCommand::kFlagChkDone); } - } - if (!expect.StatusCheck(cmd.Status())) { - fStats.Inc(kStatNChkStat); - cmd.SetFlagBit(RlinkCommand::kFlagChkStat); } - } else { // no expect, use context - if (!cntx.StatusCheck(cmd.Status())) { - fStats.Inc(kStatNChkStat); - cmd.SetFlagBit(RlinkCommand::kFlagChkStat); - } } // if (cmd.Expect()) + // status check, now independent of Expect object + if (cmd.ExpectStatusSet()) fStats.Inc(kStatNExpStat); + if (!cmd.StatusIsChecked()) fStats.Inc(kStatNNoExpStat); + if (!cmd.StatusCheck()) { + fStats.Inc(kStatNChkStat); + cmd.SetFlagBit(RlinkCommand::kFlagChkStat); + } + } // for (size_t i=ibeg; i<=iend; i++) // FIXME_code: check that all data is consumed !! diff --git a/tools/src/librlink/RlinkConnect.hpp b/tools/src/librlink/RlinkConnect.hpp index 5e993f4e..be07d296 100644 --- a/tools/src/librlink/RlinkConnect.hpp +++ b/tools/src/librlink/RlinkConnect.hpp @@ -1,4 +1,4 @@ -// $Id: RlinkConnect.hpp 632 2015-01-11 12:30:03Z mueller $ +// $Id: RlinkConnect.hpp 666 2015-04-12 21:17:54Z mueller $ // // Copyright 2011-2015 by Walter F.J. Mueller // @@ -13,6 +13,8 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-12 666 2.3 add LinkInit,LinkInitDone; transfer xon +// 2015-04-02 661 2.2 expect logic: stat expect in Command, invert mask // 2015-01-06 631 2.1 full rlink v4 implementation // 2014-12-25 621 2.0.2 Reorganize packet send/revd stats // 2014-12-20 616 2.0.1 add BlockDone expect checks @@ -35,7 +37,7 @@ /*! \file - \version $Id: RlinkConnect.hpp 632 2015-01-11 12:30:03Z mueller $ + \version $Id: RlinkConnect.hpp 666 2015-04-12 21:17:54Z mueller $ \brief Declaration of class \c RlinkConnect. */ @@ -80,6 +82,9 @@ namespace Retro { bool IsOpen() const; RlinkPort* Port() const; + bool LinkInit(RerrMsg& emsg); + bool LinkInitDone() const; + RlinkContext& Context(); void SetServer(RlinkServer* pserv); @@ -185,9 +190,10 @@ namespace Retro { kStatNInit, //!< init commands kStatNRblkWord, //!< words rcvd with rblk kStatNWblkWord, //!< words send with wblk - kStatNExpData, //!< Expect() for data defined - kStatNExpDone, //!< Expect() for done defined - kStatNExpStat, //!< Expect() for stat defined + kStatNExpData, //!< expect for data defined + kStatNExpDone, //!< expect for done defined + kStatNExpStat, //!< expect for stat explicit + kStatNNoExpStat, //!< no expect for stat kStatNChkData, //!< expect data failed kStatNChkDone, //!< expect done failed kStatNChkStat, //!< expect stat failed @@ -201,12 +207,12 @@ namespace Retro { protected: bool ExecPart(RlinkCommandList& clist, size_t ibeg, size_t iend, - RerrMsg& emsg, RlinkContext& cntx); + RerrMsg& emsg); void EncodeRequest(RlinkCommandList& clist, size_t ibeg, size_t iend); - int DecodeResponse(RlinkCommandList& clist, size_t ibeg, - size_t iend, RlinkContext& cntx); + int DecodeResponse(RlinkCommandList& clist, size_t ibeg, + size_t iend); bool DecodeAttnNotify(uint16_t& apat); bool ReadResponse(double timeout, RerrMsg& emsg); void AcceptResponse(); @@ -215,6 +221,8 @@ namespace Retro { protected: boost::scoped_ptr fpPort; //!< ptr to port + bool fLinkInitDeferred; //!< noinit attr seen on Open + bool fLinkInitDone; //!< LinkInit done RlinkServer* fpServ; //!< ptr to server (optional) uint8_t fSeqNumber[8]; //!< command sequence number RlinkPacketBufSnd fSndPkt; //!< send packet buffer diff --git a/tools/src/librlink/RlinkConnect.ipp b/tools/src/librlink/RlinkConnect.ipp index 28f324df..de5798d4 100644 --- a/tools/src/librlink/RlinkConnect.ipp +++ b/tools/src/librlink/RlinkConnect.ipp @@ -1,4 +1,4 @@ -// $Id: RlinkConnect.ipp 632 2015-01-11 12:30:03Z mueller $ +// $Id: RlinkConnect.ipp 666 2015-04-12 21:17:54Z mueller $ // // Copyright 2011-2015 by Walter F.J. Mueller // @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-12 666 2.2 add LinkInit,LinkInitDone; transfer xon // 2015-01-06 631 2.1 full rlink v4 implementation // 2013-03-05 495 1.2.1 add Exec() without emsg (will send emsg to LogFile) // 2013-02-23 492 1.2 use scoped_ptr for Port; Close allways allowed @@ -25,7 +26,7 @@ /*! \file - \version $Id: RlinkConnect.ipp 632 2015-01-11 12:30:03Z mueller $ + \version $Id: RlinkConnect.ipp 666 2015-04-12 21:17:54Z mueller $ \brief Implemenation (inline) of RlinkConnect. */ @@ -51,6 +52,14 @@ inline RlinkPort* RlinkConnect::Port() const //------------------------------------------+----------------------------------- //! FIXME_docs +inline bool RlinkConnect::LinkInitDone() const +{ + return fLinkInitDone; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + inline RlinkContext& RlinkConnect::Context() { return fContext; diff --git a/tools/src/librlink/RlinkContext.hpp b/tools/src/librlink/RlinkContext.hpp index 6734364b..b5da7e11 100644 --- a/tools/src/librlink/RlinkContext.hpp +++ b/tools/src/librlink/RlinkContext.hpp @@ -1,6 +1,6 @@ -// $Id: RlinkContext.hpp 492 2013-02-24 22:14:47Z mueller $ +// $Id: RlinkContext.hpp 661 2015-04-03 18:28:41Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,13 +13,14 @@ // // Revision History: // Date Rev Version Comment +// 2015-03-28 660 1.1 add SetStatus(Value|Mask)() // 2013-02-23 492 1.0 Initial version // --------------------------------------------------------------------------- /*! \file - \version $Id: RlinkContext.hpp 492 2013-02-24 22:14:47Z mueller $ + \version $Id: RlinkContext.hpp 661 2015-04-03 18:28:41Z mueller $ \brief Declaration of class RlinkContext. */ @@ -35,7 +36,10 @@ namespace Retro { RlinkContext(); ~RlinkContext(); - void SetStatus(uint8_t stat, uint8_t statmsk=0); + void SetStatus(uint8_t stat, uint8_t statmsk=0xff); + + void SetStatusValue(uint8_t stat); + void SetStatusMask(uint8_t statmsk); uint8_t StatusValue() const; uint8_t StatusMask() const; diff --git a/tools/src/librlink/RlinkContext.ipp b/tools/src/librlink/RlinkContext.ipp index 43f28b00..c02ecebf 100644 --- a/tools/src/librlink/RlinkContext.ipp +++ b/tools/src/librlink/RlinkContext.ipp @@ -1,6 +1,6 @@ -// $Id: RlinkContext.ipp 492 2013-02-24 22:14:47Z mueller $ +// $Id: RlinkContext.ipp 660 2015-03-29 22:10:16Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,12 +13,13 @@ // // Revision History: // Date Rev Version Comment +// 2015-03-28 660 1.1 add SetStatus(Value|Mask)() // 2013-02-23 492 1.0 Initial version // --------------------------------------------------------------------------- /*! \file - \version $Id: RlinkContext.ipp 492 2013-02-24 22:14:47Z mueller $ + \version $Id: RlinkContext.ipp 660 2015-03-29 22:10:16Z mueller $ \brief Implemenation (inline) of class RlinkContext. */ @@ -38,6 +39,24 @@ inline void RlinkContext::SetStatus(uint8_t stat, uint8_t statmsk) //------------------------------------------+----------------------------------- //! FIXME_docs +inline void RlinkContext::SetStatusValue(uint8_t stat) +{ + fStatusVal = stat; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline void RlinkContext::SetStatusMask(uint8_t statmsk) +{ + fStatusMsk = statmsk; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + inline uint8_t RlinkContext::StatusValue() const { return fStatusVal; diff --git a/tools/src/librlink/RlinkPacketBufSnd.cpp b/tools/src/librlink/RlinkPacketBufSnd.cpp index e817f1a8..523e4dd4 100644 --- a/tools/src/librlink/RlinkPacketBufSnd.cpp +++ b/tools/src/librlink/RlinkPacketBufSnd.cpp @@ -1,6 +1,6 @@ -// $Id: RlinkPacketBufSnd.cpp 621 2014-12-26 21:20:05Z mueller $ +// $Id: RlinkPacketBufSnd.cpp 666 2015-04-12 21:17:54Z mueller $ // -// Copyright 2014- by Walter F.J. Mueller +// Copyright 2014-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-11 666 1.1 handle xon/xoff escaping, add (Set)XonEscape() // 2014-12-25 621 1.0.1 Reorganize packet send/revd stats // 2014-11-15 604 1.0 Initial version // 2014-11-02 600 0.1 First draft (re-organize PacketBuf for rlink v4) @@ -20,7 +21,7 @@ /*! \file - \version $Id: RlinkPacketBufSnd.cpp 621 2014-12-26 21:20:05Z mueller $ + \version $Id: RlinkPacketBufSnd.cpp 666 2015-04-12 21:17:54Z mueller $ \brief Implemenation of class RlinkPacketBuf. */ @@ -47,11 +48,13 @@ namespace Retro { //! Default constructor RlinkPacketBufSnd::RlinkPacketBufSnd() - : fRawBuf() + : fXonEscape(false), + fRawBuf() { // Statistic setup fStats.Define(kStatNTxPktByt, "NTxPktByt", "Tx packet bytes send"); - fStats.Define(kStatNTxEsc, "NTxEsc", "Tx data escapes"); + fStats.Define(kStatNTxEsc, "NTxEsc", "Tx esc escapes"); + fStats.Define(kStatNTxXEsc, "NTxXEsc", "Tx xon escapes"); } //------------------------------------------+----------------------------------- @@ -88,7 +91,8 @@ void RlinkPacketBufSnd::PutWithCrc(const uint16_t* pdata, size_t count) bool RlinkPacketBufSnd::SndPacket(RlinkPort* port, RerrMsg& emsg) { - size_t nesc = 0; + size_t nesc = 0; + size_t nxesc = 0; fRawBuf.reserve(2*fPktBuf.size()+4); // max. size of raw data fRawBuf.clear(); @@ -99,16 +103,32 @@ bool RlinkPacketBufSnd::SndPacket(RlinkPort* port, RerrMsg& emsg) uint8_t* pi = fPktBuf.data(); for (size_t i=0; i - fStats.Inc(kStatNTxEsc , double(nesc)); + fStats.Inc(kStatNTxEsc, double(nesc)); + fStats.Inc(kStatNTxXEsc, double(nxesc)); bool sndok = SndRaw(port, emsg); if (sndok) fStats.Inc(kStatNTxPktByt, double(PktSize())); @@ -132,6 +152,8 @@ bool RlinkPacketBufSnd::SndOob(RlinkPort* port, uint16_t addr, uint16_t data, fRawBuf.push_back(uint8_t((data>>4) & 0x000f)); // DATA ( 7: 4) fRawBuf.push_back(uint8_t((data>>8) & 0x000f)); // DATA (11: 8) fRawBuf.push_back(uint8_t((data>>12) & 0x000f)); // DATA (15:12) + fRawBuf.push_back(0); // send two filler zero's to ensure that + fRawBuf.push_back(0); // comma handlers are in ground state return SndRaw(port, emsg); } @@ -194,6 +216,8 @@ void RlinkPacketBufSnd::Dump(std::ostream& os, int ind, const char* text) const RosFill bl(ind); os << bl << (text?text:"--") << "RlinkPacketBufSnd @ " << this << endl; + os << bl << " fXonEscape: " << fXonEscape << endl; + size_t rawbufsize = fRawBuf.size(); os << bl << " fRawBuf(size): " << RosPrintf(rawbufsize,"d",4); size_t ncol = max(1, (80-ind-4-6)/(2+1)); diff --git a/tools/src/librlink/RlinkPacketBufSnd.hpp b/tools/src/librlink/RlinkPacketBufSnd.hpp index 024b86fe..870a1983 100644 --- a/tools/src/librlink/RlinkPacketBufSnd.hpp +++ b/tools/src/librlink/RlinkPacketBufSnd.hpp @@ -1,6 +1,6 @@ -// $Id: RlinkPacketBufSnd.hpp 621 2014-12-26 21:20:05Z mueller $ +// $Id: RlinkPacketBufSnd.hpp 666 2015-04-12 21:17:54Z mueller $ // -// Copyright 2014- by Walter F.J. Mueller +// Copyright 2014-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-11 666 1.1 handle xon/xoff escaping, add (Set)XonEscape() // 2014-12-25 621 1.0.1 Reorganize packet send/revd stats // 2014-11-14 604 1.0 Initial version // 2014-11-02 600 0.1 First draft (re-organize PacketBuf for rlink v4) @@ -21,7 +22,7 @@ /*! \file - \version $Id: RlinkPacketBufSnd.hpp 621 2014-12-26 21:20:05Z mueller $ + \version $Id: RlinkPacketBufSnd.hpp 666 2015-04-12 21:17:54Z mueller $ \brief Declaration of class RlinkPacketBufSnd. */ @@ -39,6 +40,9 @@ namespace Retro { RlinkPacketBufSnd(); ~RlinkPacketBufSnd(); + void SetXonEscape(bool xon); + bool XonEscape() const; + void Init(); void PutWithCrc(uint8_t data); @@ -63,13 +67,15 @@ namespace Retro { // statistics counter indices enum stats { kStatNTxPktByt=0, //!< Tx packet bytes send - kStatNTxEsc //!< Tx data escapes + kStatNTxEsc, //!< Tx esc escapes + kStatNTxXEsc //!< Tx xon escapes }; protected: bool SndRaw(RlinkPort* port, RerrMsg& emsg); protected: + bool fXonEscape; //!< escape XON/XOFF std::vector fRawBuf; //!< raw data buffer }; diff --git a/tools/src/librlink/RlinkPacketBufSnd.ipp b/tools/src/librlink/RlinkPacketBufSnd.ipp index 88f15f82..12ae02da 100644 --- a/tools/src/librlink/RlinkPacketBufSnd.ipp +++ b/tools/src/librlink/RlinkPacketBufSnd.ipp @@ -1,6 +1,6 @@ -// $Id: RlinkPacketBufSnd.ipp 606 2014-11-24 07:08:51Z mueller $ +// $Id: RlinkPacketBufSnd.ipp 666 2015-04-12 21:17:54Z mueller $ // -// Copyright 2014- by Walter F.J. Mueller +// Copyright 2014-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,13 +13,14 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-11 666 1.1 handle xon/xoff escaping, add (Set)XonEscape() // 2014-11-08 602 1.0 Initial version // 2014-11-02 600 0.1 First draft (re-organize PacketBuf for rlink v4) // --------------------------------------------------------------------------- /*! \file - \version $Id: RlinkPacketBufSnd.ipp 606 2014-11-24 07:08:51Z mueller $ + \version $Id: RlinkPacketBufSnd.ipp 666 2015-04-12 21:17:54Z mueller $ \brief Implemenation (inline) of class RlinkPacketBuf. */ @@ -39,6 +40,23 @@ inline void RlinkPacketBufSnd::PutWithCrc(uint8_t data) //------------------------------------------+----------------------------------- //! FIXME_docs +inline void RlinkPacketBufSnd::SetXonEscape(bool xon) +{ + fXonEscape = xon; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline bool RlinkPacketBufSnd::XonEscape() const +{ + return fXonEscape; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + inline void RlinkPacketBufSnd::PutWithCrc(uint16_t data) { uint8_t datl = data & 0xff; diff --git a/tools/src/librlink/RlinkPort.cpp b/tools/src/librlink/RlinkPort.cpp index 91beb767..478f30f6 100644 --- a/tools/src/librlink/RlinkPort.cpp +++ b/tools/src/librlink/RlinkPort.cpp @@ -1,6 +1,6 @@ -// $Id: RlinkPort.cpp 632 2015-01-11 12:30:03Z mueller $ +// $Id: RlinkPort.cpp 666 2015-04-12 21:17:54Z mueller $ // -// Copyright 2011-2014 by Walter F.J. Mueller +// Copyright 2011-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-11 666 1.3 add fXon, XonEnable() // 2014-12-10 611 1.2.4 add time stamps for Read/Write for logs // 2014-11-29 607 1.2.3 BUGFIX: fix time handling on RawRead() // 2014-11-23 606 1.2.2 use Rtools::TimeOfDayAsDouble() @@ -30,7 +31,7 @@ /*! \file - \version $Id: RlinkPort.cpp 632 2015-01-11 12:30:03Z mueller $ + \version $Id: RlinkPort.cpp 666 2015-04-12 21:17:54Z mueller $ \brief Implemenation of RlinkPort. */ @@ -72,6 +73,7 @@ const int RlinkPort::kErr; RlinkPort::RlinkPort() : fIsOpen(false), fUrl(), + fXon(false), fFdRead(-1), fFdWrite(-1), fspLog(), @@ -295,6 +297,7 @@ void RlinkPort::Dump(std::ostream& os, int ind, const char* text) const os << bl << " fIsOpen: " << (int)fIsOpen << endl; fUrl.Dump(os, ind+2, "fUrl: "); + os << bl << " fXon: " << fXon << endl; os << bl << " fFdRead: " << fFdRead << endl; os << bl << " fFdWrite: " << fFdWrite << endl; os << bl << " fspLog: " << fspLog.get() << endl; diff --git a/tools/src/librlink/RlinkPort.hpp b/tools/src/librlink/RlinkPort.hpp index 1b0bcc93..60902b01 100644 --- a/tools/src/librlink/RlinkPort.hpp +++ b/tools/src/librlink/RlinkPort.hpp @@ -1,6 +1,6 @@ -// $Id: RlinkPort.hpp 632 2015-01-11 12:30:03Z mueller $ +// $Id: RlinkPort.hpp 666 2015-04-12 21:17:54Z mueller $ // -// Copyright 2011-2014 by Walter F.J. Mueller +// Copyright 2011-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-11 666 1.3 add fXon, XonEnable() // 2014-12-10 611 1.2.2 add time stamps for Read/Write for logs // 2013-05-01 513 1.2.1 fTraceLevel now uint32_t // 2013-02-23 492 1.2 use RparseUrl @@ -27,7 +28,7 @@ /*! \file - \version $Id: RlinkPort.hpp 632 2015-01-11 12:30:03Z mueller $ + \version $Id: RlinkPort.hpp 666 2015-04-12 21:17:54Z mueller $ \brief Declaration of class RlinkPort. */ @@ -66,6 +67,7 @@ namespace Retro { bool IsOpen() const; const RparseUrl& Url() const; + bool XonEnable() const; int FdRead() const; int FdWrite() const; @@ -101,6 +103,7 @@ namespace Retro { protected: bool fIsOpen; //!< is open flag RparseUrl fUrl; //!< parsed url + bool fXon; //!< xon attribute set int fFdRead; //!< fd for read int fFdWrite; //!< fd for write boost::shared_ptr fspLog; //!< log file ptr diff --git a/tools/src/librlink/RlinkPort.ipp b/tools/src/librlink/RlinkPort.ipp index 6e282915..8dd62fa8 100644 --- a/tools/src/librlink/RlinkPort.ipp +++ b/tools/src/librlink/RlinkPort.ipp @@ -1,6 +1,6 @@ -// $Id: RlinkPort.ipp 513 2013-05-01 14:02:06Z mueller $ +// $Id: RlinkPort.ipp 666 2015-04-12 21:17:54Z mueller $ // -// Copyright 2011-2013 by Walter F.J. Mueller +// Copyright 2011-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-11 666 1.3 add fXon, XonEnable() // 2013-05-01 513 1.2.1 fTraceLevel now uint32_t // 2013-02-23 492 1.2 use RparseUrl // 2013-02-22 491 1.1 use new RlogFile/RlogMsg interfaces @@ -22,7 +23,7 @@ /*! \file - \version $Id: RlinkPort.ipp 513 2013-05-01 14:02:06Z mueller $ + \version $Id: RlinkPort.ipp 666 2015-04-12 21:17:54Z mueller $ \brief Implemenation (inline) of RlinkPort. */ @@ -48,6 +49,14 @@ inline const Retro::RparseUrl& RlinkPort::Url() const //------------------------------------------+----------------------------------- //! FIXME_docs +inline bool RlinkPort::XonEnable() const +{ + return fXon; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + inline int RlinkPort::FdRead() const { return fFdRead; diff --git a/tools/src/librlink/RlinkPortCuff.cpp b/tools/src/librlink/RlinkPortCuff.cpp index c5e91ff2..519cca97 100644 --- a/tools/src/librlink/RlinkPortCuff.cpp +++ b/tools/src/librlink/RlinkPortCuff.cpp @@ -1,6 +1,6 @@ -// $Id: RlinkPortCuff.cpp 632 2015-01-11 12:30:03Z mueller $ +// $Id: RlinkPortCuff.cpp 666 2015-04-12 21:17:54Z mueller $ // -// Copyright 2012-2014 by Walter F.J. Mueller +// Copyright 2012-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-12 666 1.1.3 add noinit attribute // 2014-08-22 584 1.1.2 use nullptr // 2013-05-17 521 1.1.1 use Rtools::String2Long // 2013-02-23 492 1.1 use RparseUrl @@ -24,7 +25,7 @@ /*! \file - \version $Id: RlinkPortCuff.cpp 632 2015-01-11 12:30:03Z mueller $ + \version $Id: RlinkPortCuff.cpp 666 2015-04-12 21:17:54Z mueller $ \brief Implemenation of RlinkPortCuff. */ @@ -97,7 +98,7 @@ bool RlinkPortCuff::Open(const std::string& url, RerrMsg& emsg) if (IsOpen()) Close(); - if (!fUrl.Set(url, "|trace|", emsg)) return false; + if (!fUrl.Set(url, "|trace|noinit|", emsg)) return false; // initialize USB context irc = libusb_init(&fpUsbContext); diff --git a/tools/src/librlink/RlinkPortFifo.cpp b/tools/src/librlink/RlinkPortFifo.cpp index 206c0d9c..a25c2968 100644 --- a/tools/src/librlink/RlinkPortFifo.cpp +++ b/tools/src/librlink/RlinkPortFifo.cpp @@ -1,6 +1,6 @@ -// $Id: RlinkPortFifo.cpp 607 2014-11-30 20:02:48Z mueller $ +// $Id: RlinkPortFifo.cpp 666 2015-04-12 21:17:54Z mueller $ // -// Copyright 2011-2013 y Walter F.J. Mueller +// Copyright 2011-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-12 666 1.2 add xon,noinit attributes // 2013-02-23 492 1.1 use RparseUrl // 2011-03-27 374 1.0 Initial version // 2011-01-15 356 0.1 First draft @@ -20,7 +21,7 @@ /*! \file - \version $Id: RlinkPortFifo.cpp 607 2014-11-30 20:02:48Z mueller $ + \version $Id: RlinkPortFifo.cpp 666 2015-04-12 21:17:54Z mueller $ \brief Implemenation of RlinkPortFifo. */ @@ -64,7 +65,7 @@ bool RlinkPortFifo::Open(const std::string& url, RerrMsg& emsg) { if (IsOpen()) Close(); - if (!fUrl.Set(url, "|keep|", emsg)) return false; + if (!fUrl.Set(url, "|keep|xon|noinit|", emsg)) return false; // Note: _rx fifo must be opened before the _tx fifo, otherwise the test // bench might close with EOF on read prematurely (is a race condition). @@ -79,7 +80,8 @@ bool RlinkPortFifo::Open(const std::string& url, RerrMsg& emsg) return false; } - fIsOpen = true; + fXon = fUrl.FindOpt("xon"); + fIsOpen = true; return true; } diff --git a/tools/src/librlink/RlinkPortTerm.cpp b/tools/src/librlink/RlinkPortTerm.cpp index 33efe1a9..6c9656c1 100644 --- a/tools/src/librlink/RlinkPortTerm.cpp +++ b/tools/src/librlink/RlinkPortTerm.cpp @@ -1,4 +1,4 @@ -// $Id: RlinkPortTerm.cpp 641 2015-02-01 22:12:15Z mueller $ +// $Id: RlinkPortTerm.cpp 666 2015-04-12 21:17:54Z mueller $ // // Copyright 2011-2015 by Walter F.J. Mueller // @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-12 666 1.3 drop xon/xoff excaping; add noinit attribute // 2015-02-01 641 1.2 support custom baud rates (5M,6M,10M,12M) // 2013-02-23 492 1.1 use RparseUrl // 2011-12-18 440 1.0.4 add kStatNPort stats; Open(): autoadd /dev/tty, @@ -26,7 +27,7 @@ /*! \file - \version $Id: RlinkPortTerm.cpp 641 2015-02-01 22:12:15Z mueller $ + \version $Id: RlinkPortTerm.cpp 666 2015-04-12 21:17:54Z mueller $ \brief Implemenation of RlinkPortTerm. */ @@ -58,17 +59,13 @@ namespace Retro { // constants definitions const uint8_t RlinkPortTerm::kc_xon; const uint8_t RlinkPortTerm::kc_xoff; -const uint8_t RlinkPortTerm::kc_xesc; //------------------------------------------+----------------------------------- //! Default constructor RlinkPortTerm::RlinkPortTerm() : RlinkPort() -{ - fStats.Define(kStatNPortTxXesc, "NPortTxXesc", "Tx XESC escapes"); - fStats.Define(kStatNPortRxXesc, "NPortRxXesc", "Rx XESC escapes"); -} +{} //------------------------------------------+----------------------------------- //! Destructor @@ -85,7 +82,7 @@ bool RlinkPortTerm::Open(const std::string& url, RerrMsg& emsg) { Close(); - if (!fUrl.Set(url, "|baud=|break|cts|xon|", emsg)) return false; + if (!fUrl.Set(url, "|baud=|break|cts|xon|noinit|", emsg)) return false; // if path doesn't start with a '/' prepend a '/dev/tty' if (fUrl.Path().substr(0,1) != "/") { @@ -176,8 +173,7 @@ bool RlinkPortTerm::Open(const std::string& url, RerrMsg& emsg) bool use_cts = fUrl.FindOpt("cts"); bool use_xon = fUrl.FindOpt("xon"); - fUseXon = use_xon; - fPendXesc = false; + fXon = use_xon; fTiosNew = fTiosOld; @@ -318,78 +314,6 @@ void RlinkPortTerm::Close() //------------------------------------------+----------------------------------- //! FIXME_docs -int RlinkPortTerm::Read(uint8_t* buf, size_t size, double timeout, - RerrMsg& emsg) -{ - int irc; - if (fUseXon) { - uint8_t* po = buf; - if (fRxBuf.size() < size) fRxBuf.resize(size); - - // repeat read until at least one byte returned (or an error occurs) - // this avoids that the Read() returns with 0 in case only one byte is - // seen and this is a kc_xesc. At most two iterations possible because - // in 2nd iteration fPendXesc must be set and thus po pushed. - while (po == buf) { - irc = RlinkPort::Read(fRxBuf.data(), size, timeout, emsg); - if (irc <= 0) break; - uint8_t* pi = fRxBuf.data(); - for (int i=0; i +// Copyright 2011-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-11 666 1.1 drop xon/xoff excaping, now done in RlinkPacketBuf // 2011-12-18 440 1.0.2 add kStatNPort stats // 2011-12-11 438 1.0.1 Read(),Write(): added for xon handling, tcdrain(); // 2011-03-27 374 1.0 Initial version @@ -21,7 +22,7 @@ /*! \file - \version $Id: RlinkPortTerm.hpp 486 2013-02-10 22:34:43Z mueller $ + \version $Id: RlinkPortTerm.hpp 666 2015-04-12 21:17:54Z mueller $ \brief Declaration of class RlinkPortTerm. */ @@ -43,23 +44,12 @@ namespace Retro { virtual bool Open(const std::string& url, RerrMsg& emsg); virtual void Close(); - virtual int Read(uint8_t* buf, size_t size, double timeout, - RerrMsg& emsg); - virtual int Write(const uint8_t* buf, size_t size, RerrMsg& emsg); - + virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; // some constants (also defined in cpp) static const uint8_t kc_xon = 0x11; // XON char -> ^Q = hex 11 static const uint8_t kc_xoff = 0x13; // XOFF char -> ^S = hex 13 - static const uint8_t kc_xesc = 0x1b; // XESC char -> ^[ = ESC = hex 1B - - // statistics counter indices - enum stats { - kStatNPortTxXesc = RlinkPort::kDimStat, - kStatNPortRxXesc, - kDimStat - }; protected: void DumpTios(std::ostream& os, int ind, const std::string& name, @@ -68,10 +58,6 @@ namespace Retro { protected: struct termios fTiosOld; struct termios fTiosNew; - bool fUseXon; //!< xon attribute set - bool fPendXesc; //!< xesc pending - std::vector fTxBuf; //!< buffer to handle xesc - std::vector fRxBuf; //!< buffer to handle xesc }; } // end namespace Retro diff --git a/tools/src/librlink/RlinkServer.cpp b/tools/src/librlink/RlinkServer.cpp index 1f6f98ed..bc9484fd 100644 --- a/tools/src/librlink/RlinkServer.cpp +++ b/tools/src/librlink/RlinkServer.cpp @@ -1,4 +1,4 @@ -// $Id: RlinkServer.cpp 632 2015-01-11 12:30:03Z mueller $ +// $Id: RlinkServer.cpp 662 2015-04-05 08:02:54Z mueller $ // // Copyright 2013-2015 by Walter F.J. Mueller // @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-04 662 1.2 BUGFIX: fix race in Stop(), use UnStop() // 2015-01-10 632 2.2 Exec() without emsg now void, will throw // 2014-12-30 625 2.1 adopt to Rlink V4 attn logic // 2014-12-21 617 2.0.1 use kStat_M_RbTout for rbus timeout @@ -25,7 +26,7 @@ /*! \file - \version $Id: RlinkServer.cpp 632 2015-01-11 12:30:03Z mueller $ + \version $Id: RlinkServer.cpp 662 2015-04-05 08:02:54Z mueller $ \brief Implemenation of RlinkServer. */ @@ -67,10 +68,9 @@ RlinkServer::RlinkServer() fTraceLevel(0), fStats() { - fContext.SetStatus(0, - ~(RlinkCommand::kStat_M_RbTout | - RlinkCommand::kStat_M_RbNak | - RlinkCommand::kStat_M_RbErr)); + fContext.SetStatus(0, RlinkCommand::kStat_M_RbTout | + RlinkCommand::kStat_M_RbNak | + RlinkCommand::kStat_M_RbErr); fELoop.AddPollHandler(boost::bind(&RlinkServer::WakeupHandler, this, _1), fWakeupEvent, POLLIN); @@ -414,6 +414,7 @@ void RlinkServer::StartOrResume(bool resume) rlinkfd, POLLIN); // and start server thread + fELoop.UnStop(); fServerThread = boost::thread(boost::bind(&RlinkServerEventLoop::EventLoop, &fELoop)); diff --git a/tools/src/librlink/RlinkServerEventLoop.cpp b/tools/src/librlink/RlinkServerEventLoop.cpp index 82b2a759..9176f5e7 100644 --- a/tools/src/librlink/RlinkServerEventLoop.cpp +++ b/tools/src/librlink/RlinkServerEventLoop.cpp @@ -1,6 +1,6 @@ -// $Id: RlinkServerEventLoop.cpp 495 2013-03-06 17:13:48Z mueller $ +// $Id: RlinkServerEventLoop.cpp 662 2015-04-05 08:02:54Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-04 662 1.2 BUGFIX: fix race in Stop(), use StopPending() // 2013-03-05 495 1.1.1 add exception catcher to EventLoop // 2013-02-22 491 1.1 use new RlogFile/RlogMsg interfaces // 2013-01-12 474 1.0 Initial Version @@ -20,7 +21,7 @@ /*! \file - \version $Id: RlinkServerEventLoop.cpp 495 2013-03-06 17:13:48Z mueller $ + \version $Id: RlinkServerEventLoop.cpp 662 2015-04-05 08:02:54Z mueller $ \brief Implemenation of RlinkServerEventLoop. */ @@ -59,13 +60,12 @@ RlinkServerEventLoop::~RlinkServerEventLoop() void RlinkServerEventLoop::EventLoop() { - fLoopActive = true; fUpdatePoll = true; if (fspLog && fTraceLevel>0) fspLog->Write("eloop: starting", 'I'); try { - while (fLoopActive) { + while (!StopPending()) { int timeout = (fpServer->AttnPending() || fpServer->ActnPending()) ? 0 : -1; int irc = DoPoll(timeout); diff --git a/tools/src/librlinktpp/RtclRlinkConnect.cpp b/tools/src/librlinktpp/RtclRlinkConnect.cpp index 5e707926..1ce38b80 100644 --- a/tools/src/librlinktpp/RtclRlinkConnect.cpp +++ b/tools/src/librlinktpp/RtclRlinkConnect.cpp @@ -1,4 +1,4 @@ -// $Id: RtclRlinkConnect.cpp 631 2015-01-09 21:36:51Z mueller $ +// $Id: RtclRlinkConnect.cpp 676 2015-05-09 16:31:54Z mueller $ // // Copyright 2011-2015 by Walter F.J. Mueller // @@ -13,6 +13,11 @@ // // Revision History: // Date Rev Version Comment +// 2015-05-09 676 1.4.3 M_errcnt: add -increment; M_log: add -bare,-info.. +// 2015-04-19 668 1.4.2 M_wtlam: allow tout=0 for pending attn cleanup +// 2015-04-12 666 1.4.1 add M_init +// 2015-04-03 661 1.4 expect logic: drop estatdef, use LastExpect.. +// 2015-03-28 660 1.3.3 add stat* getter/setter; M_exec: add -estaterr ect // 2015-01-06 631 1.3.2 add M_get, M_set, remove M_config // 2014-12-20 616 1.3.1 M_exec: add -edone for BlockDone checking // 2014-12-06 609 1.3 new rlink v4 iface @@ -33,7 +38,7 @@ /*! \file - \version $Id: RtclRlinkConnect.cpp 631 2015-01-09 21:36:51Z mueller $ + \version $Id: RtclRlinkConnect.cpp 676 2015-05-09 16:31:54Z mueller $ \brief Implemenation of class RtclRlinkConnect. */ @@ -76,6 +81,7 @@ RtclRlinkConnect::RtclRlinkConnect(Tcl_Interp* interp, const char* name) { AddMeth("open", boost::bind(&RtclRlinkConnect::M_open, this, _1)); AddMeth("close", boost::bind(&RtclRlinkConnect::M_close, this, _1)); + AddMeth("init", boost::bind(&RtclRlinkConnect::M_init, this, _1)); AddMeth("exec", boost::bind(&RtclRlinkConnect::M_exec, this, _1)); AddMeth("amap", boost::bind(&RtclRlinkConnect::M_amap, this, _1)); AddMeth("errcnt", boost::bind(&RtclRlinkConnect::M_errcnt, this, _1)); @@ -94,7 +100,9 @@ RtclRlinkConnect::RtclRlinkConnect(Tcl_Interp* interp, const char* name) fCmdnameObj[i] = Tcl_NewStringObj(RlinkCommand::CommandName(i), -1); } - RlinkConnect* pobj = &Obj(); + // attributes of RlinkConnect + RlinkConnect* pobj = &Obj(); + fGets.Add ("baseaddr", boost::bind(&RlinkConnect::LogBaseAddr, pobj)); fGets.Add ("basedata", @@ -109,6 +117,9 @@ RtclRlinkConnect::RtclRlinkConnect(Tcl_Interp* interp, const char* name) boost::bind(&RlinkConnect::TraceLevel, pobj)); fGets.Add ("logfile", boost::bind(&RlinkConnect::LogFileName, pobj)); + + fGets.Add ("initdone", + boost::bind(&RlinkConnect::LinkInitDone, pobj)); fGets.Add ("sysid", boost::bind(&RlinkConnect::SysId, pobj)); fGets.Add ("rbufsize", @@ -132,6 +143,20 @@ RtclRlinkConnect::RtclRlinkConnect(Tcl_Interp* interp, const char* name) boost::bind(&RlinkConnect::SetTraceLevel, pobj, _1)); fSets.Add ("logfile", boost::bind(&RlinkConnect::SetLogFileName, pobj, _1)); + + // attributes of buildin RlinkContext + RlinkContext* pcntx = &Obj().Context(); + fGets.Add ("statchecked", + boost::bind(&RlinkContext::StatusIsChecked, pcntx)); + fGets.Add ("statvalue", + boost::bind(&RlinkContext::StatusValue, pcntx)); + fGets.Add ("statmask", + boost::bind(&RlinkContext::StatusMask, pcntx)); + + fSets.Add ("statvalue", + boost::bind(&RlinkContext::SetStatusValue, pcntx, _1)); + fSets.Add ("statmask", + boost::bind(&RlinkContext::SetStatusMask, pcntx, _1)); } //------------------------------------------+----------------------------------- @@ -174,10 +199,24 @@ int RtclRlinkConnect::M_close(RtclArgs& args) //------------------------------------------+----------------------------------- //! FIXME_docs +int RtclRlinkConnect::M_init(RtclArgs& args) +{ + if (!args.AllDone()) return kERR; + if (!Obj().IsOpen()) return args.Quit("-E: port not open"); + if (Obj().LinkInitDone()) return args.Quit("-E: already initialized"); + RerrMsg emsg; + if (!Obj().LinkInit(emsg)) return args.Quit(emsg); + return kOK; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + int RtclRlinkConnect::M_exec(RtclArgs& args) { static RtclNameSet optset("-rreg|-rblk|-wreg|-wblk|-labo|-attn|-init|" - "-edata|-edone|-estat|-estatdef|" + "-edata|-edone|-estat|" + "-estaterr|-estatnak|-estattout|" "-print|-dump|-rlist"); Tcl_Interp* interp = args.Interp(); @@ -192,9 +231,6 @@ int RtclRlinkConnect::M_exec(RtclArgs& args) string vardump; string varlist; - uint8_t estatdef_val = 0x00; - uint8_t estatdef_msk = 0xff; - while (args.NextOpt(opt, optset)) { size_t lsize = clist.Size(); @@ -245,62 +281,54 @@ int RtclRlinkConnect::M_exec(RtclArgs& args) } else if (opt == "-edata") { // -edata data ?mask -------------- if (!ClistNonEmpty(args, clist)) return kERR; - if (clist[lsize-1].Expect()==0) { - clist[lsize-1].SetExpect(new RlinkCommandExpect(estatdef_val, - estatdef_msk)); - } if (clist[lsize-1].Command() == RlinkCommand::kCmdRblk) { vector data; vector mask; size_t bsize = clist[lsize-1].BlockSize(); if (!args.GetArg("data", data, 0, bsize)) return kERR; if (!args.GetArg("??mask", mask, 0, bsize)) return kERR; - clist[lsize-1].Expect()->SetBlock(data, mask); + clist.SetLastExpectBlock(data, mask); } else { uint16_t data=0; - uint16_t mask=0; + uint16_t mask=0xffff; if (!args.GetArg("data", data)) return kERR; if (!args.GetArg("??mask", mask)) return kERR; - clist[lsize-1].Expect()->SetData(data, mask); + clist.SetLastExpectData(data, mask); } } else if (opt == "-edone") { // -edone done -------------------- if (!ClistNonEmpty(args, clist)) return kERR; uint16_t done=0; if (!args.GetArg("done", done)) return kERR; - if (clist[lsize-1].Expect()==0) { - clist[lsize-1].SetExpect(new RlinkCommandExpect(estatdef_val, - estatdef_msk)); - } uint8_t cmd = clist[lsize-1].Command(); if (cmd == RlinkCommand::kCmdRblk || cmd == RlinkCommand::kCmdWblk) { - clist[lsize-1].Expect()->SetDone(done); + clist.SetLastExpectDone(done); } else { return args.Quit("-E: -edone allowed only after -rblk,-wblk"); } - } else if (opt == "-estat") { // -estat ?stat ?mask ------------- + } else if (opt == "-estat") { // -estat stat ?mask -------------- if (!ClistNonEmpty(args, clist)) return kERR; uint8_t stat=0; - uint8_t mask=0; - if (!args.GetArg("??stat", stat)) return kERR; + uint8_t mask=0xff; + if (!args.GetArg("stat", stat)) return kERR; if (!args.GetArg("??mask", mask)) return kERR; - if (args.NOptMiss() == 2) mask = 0xff; - if (clist[lsize-1].Expect()==0) { - clist[lsize-1].SetExpect(new RlinkCommandExpect()); - } - clist[lsize-1].Expect()->SetStatus(stat, mask); - - } else if (opt == "-estatdef") { // -estatdef ?stat ?mask ----------- - uint8_t stat=0; - uint8_t mask=0; - if (!args.GetArg("??stat", stat)) return kERR; - if (!args.GetArg("??mask", mask)) return kERR; - if (args.NOptMiss() == 2) mask = 0xff; - estatdef_val = stat; - estatdef_msk = mask; + clist.SetLastExpectStatus(stat, mask); + } else if (opt == "-estaterr" || // -estaterr ---------------------- + opt == "-estatnak" || // -estatnak ---------------------- + opt == "-estattout") { // -estattout --------------------- + if (!ClistNonEmpty(args, clist)) return kERR; + uint8_t val = 0; + uint8_t msk = RlinkCommand::kStat_M_RbTout | + RlinkCommand::kStat_M_RbNak | + RlinkCommand::kStat_M_RbErr; + if (opt == "-estaterr") val = RlinkCommand::kStat_M_RbErr; + if (opt == "-estatnak") val = RlinkCommand::kStat_M_RbNak; + if (opt == "-estattout") val = RlinkCommand::kStat_M_RbTout; + clist.SetLastExpectStatus(val, msk); + } else if (opt == "-print") { // -print ?varRes ----------------- varprint = "-"; if (!args.GetArg("??varRes", varprint)) return kERR; @@ -312,17 +340,7 @@ int RtclRlinkConnect::M_exec(RtclArgs& args) if (!args.GetArg("??varRes", varlist)) return kERR; } - if (estatdef_msk != 0xff && // estatdef defined - lsize != clist.Size()) { // and cmd added to clist - for (size_t i=lsize; i= 3) { RlogMsg lmsg(Obj().LogFile()); - lmsg << "-- wtlam to=" << RosPrintf(tout, "f", 0,3) - << " T=" << RosPrintf(twait, "f", 0,3) - << " OK" << endl; + lmsg << "-- wtlam apat=" << RosPrintf(apat,"x0",4); + if (tout == 0.) { + lmsg << " to=0 harvest only"; + } else { + lmsg << " to=" << RosPrintf(tout, "f", 0,3) + << " T=" << RosPrintf(twait, "f", 0,3); + } + lmsg << " OK" << endl; } args.SetResult(twait); @@ -661,13 +687,29 @@ int RtclRlinkConnect::M_stats(RtclArgs& args) int RtclRlinkConnect::M_log(RtclArgs& args) { + static RtclNameSet optset("-bare|-info|-warn|-error|-fatal"); + string opt; + bool fbare = false; + char tag = 0; + while (args.NextOpt(opt, optset)) { + if (opt == "-bare") fbare = true; + if (opt == "-info") tag = 'I'; + if (opt == "-warn") tag = 'W'; + if (opt == "-error") tag = 'E'; + if (opt == "-fatal") tag = 'F'; + } + string msg; if (!args.GetArg("msg", msg)) return kERR; if (!args.AllDone()) return kERR; if (Obj().PrintLevel() != 0 || Obj().DumpLevel() != 0 || Obj().TraceLevel() != 0) { - Obj().LogFile().Write(string("# ") + msg); + if (tag || fbare) { + Obj().LogFile().Write(msg, tag); + } else { + Obj().LogFile().Write(string("# ") + msg); + } } return kOK; } @@ -810,7 +852,6 @@ bool RtclRlinkConnect::ConfigBase(RtclArgs& args, uint32_t& base) return true; } - //------------------------------------------+----------------------------------- //! FIXME_docs diff --git a/tools/src/librlinktpp/RtclRlinkConnect.hpp b/tools/src/librlinktpp/RtclRlinkConnect.hpp index 2f617dc3..97509ca7 100644 --- a/tools/src/librlinktpp/RtclRlinkConnect.hpp +++ b/tools/src/librlinktpp/RtclRlinkConnect.hpp @@ -1,4 +1,4 @@ -// $Id: RtclRlinkConnect.hpp 631 2015-01-09 21:36:51Z mueller $ +// $Id: RtclRlinkConnect.hpp 666 2015-04-12 21:17:54Z mueller $ // // Copyright 2011-2015 by Walter F.J. Mueller // @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-12 666 1.0.5 add M_init // 2015-01-06 631 1.0.4 add M_get, M_set, remove M_config // 2013-02-23 492 1.0.3 use RlogFile.Name(); use Context().ErrorCount() // 2013-01-06 473 1.0.2 add M_rawio @@ -23,7 +24,7 @@ /*! \file - \version $Id: RtclRlinkConnect.hpp 631 2015-01-09 21:36:51Z mueller $ + \version $Id: RtclRlinkConnect.hpp 666 2015-04-12 21:17:54Z mueller $ \brief Declaration of class RtclRlinkConnect. */ @@ -50,6 +51,7 @@ namespace Retro { protected: int M_open(RtclArgs& args); int M_close(RtclArgs& args); + int M_init(RtclArgs& args); int M_exec(RtclArgs& args); int M_amap(RtclArgs& args); int M_errcnt(RtclArgs& args); diff --git a/tools/src/librlinktpp/RtclRlinkServer.cpp b/tools/src/librlinktpp/RtclRlinkServer.cpp index fdcdb3fe..6f8e0248 100644 --- a/tools/src/librlinktpp/RtclRlinkServer.cpp +++ b/tools/src/librlinktpp/RtclRlinkServer.cpp @@ -1,6 +1,6 @@ -// $Id: RtclRlinkServer.cpp 632 2015-01-11 12:30:03Z mueller $ +// $Id: RtclRlinkServer.cpp 662 2015-04-05 08:02:54Z mueller $ // -// Copyright 2013-2014 by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-04 662 1.1 add M_get, M_set; remove 'server -trace' // 2014-08-22 584 1.0.6 use nullptr // 2013-05-01 513 1.0.5 TraceLevel now uint32_t // 2013-04-26 510 1.0.4 change M_attn, now -info instead of -show @@ -24,7 +25,7 @@ /*! \file - \version $Id: RtclRlinkServer.cpp 632 2015-01-11 12:30:03Z mueller $ + \version $Id: RtclRlinkServer.cpp 662 2015-04-05 08:02:54Z mueller $ \brief Implemenation of class RtclRlinkServer. */ @@ -63,14 +64,40 @@ namespace Retro { RtclRlinkServer::RtclRlinkServer(Tcl_Interp* interp, const char* name) : RtclProxyOwned("RlinkServer", interp, name, new RlinkServer()), - fspConn() + fspConn(), + fGets(), + fSets() { AddMeth("server", boost::bind(&RtclRlinkServer::M_server, this, _1)); AddMeth("attn", boost::bind(&RtclRlinkServer::M_attn, this, _1)); AddMeth("stats", boost::bind(&RtclRlinkServer::M_stats, this, _1)); AddMeth("print", boost::bind(&RtclRlinkServer::M_print, this, _1)); AddMeth("dump", boost::bind(&RtclRlinkServer::M_dump, this, _1)); + AddMeth("get", boost::bind(&RtclRlinkServer::M_get, this, _1)); + AddMeth("set", boost::bind(&RtclRlinkServer::M_set, this, _1)); AddMeth("$default", boost::bind(&RtclRlinkServer::M_default, this, _1)); + + // attributes of RlinkConnect + RlinkServer* pobj = &Obj(); + fGets.Add ("tracelevel", + boost::bind(&RlinkServer::TraceLevel, pobj)); + + fSets.Add ("tracelevel", + boost::bind(&RlinkServer::SetTraceLevel, pobj, _1)); + + // attributes of buildin RlinkContext + RlinkContext* pcntx = &Obj().Context(); + fGets.Add ("statchecked", + boost::bind(&RlinkContext::StatusIsChecked, pcntx)); + fGets.Add ("statvalue", + boost::bind(&RlinkContext::StatusValue, pcntx)); + fGets.Add ("statmask", + boost::bind(&RlinkContext::StatusMask, pcntx)); + + fSets.Add ("statvalue", + boost::bind(&RlinkContext::SetStatusValue, pcntx, _1)); + fSets.Add ("statmask", + boost::bind(&RlinkContext::SetStatusMask, pcntx, _1)); } //------------------------------------------+----------------------------------- @@ -111,7 +138,7 @@ int RtclRlinkServer::ClassCmdConfig(RtclArgs& args) int RtclRlinkServer::M_server(RtclArgs& args) { - static RtclNameSet optset("-start|-stop|-resume|-test|-trace"); + static RtclNameSet optset("-start|-stop|-resume|-test"); string opt; if (args.NextOpt(opt, optset)) { if (opt == "-start") { // server -start @@ -126,14 +153,6 @@ int RtclRlinkServer::M_server(RtclArgs& args) } else if (opt == "-test") { // server -test if (!args.AllDone()) return kERR; args.SetResult(Obj().IsActive()); - } else if (opt == "-trace") { // server -trace ... - uint32_t level; - if (!args.GetArg("?level", level)) return kERR; - if (args.NOptMiss()==0) { // server -trace level - Obj().SetTraceLevel(level); - } else { // server -trace - args.SetResult((int)Obj().TraceLevel()); - } } } else { // server @@ -283,6 +302,26 @@ int RtclRlinkServer::M_dump(RtclArgs& args) //------------------------------------------+----------------------------------- //! FIXME_docs +int RtclRlinkServer::M_get(RtclArgs& args) +{ + // synchronize with server thread (really needed ??) + boost::lock_guard lock(Obj().Connect()); + return fGets.M_get(args); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +int RtclRlinkServer::M_set(RtclArgs& args) +{ + // synchronize with server thread (really needed ??) + boost::lock_guard lock(Obj().Connect()); + return fSets.M_set(args); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + int RtclRlinkServer::M_default(RtclArgs& args) { if (!args.AllDone()) return kERR; diff --git a/tools/src/librlinktpp/RtclRlinkServer.hpp b/tools/src/librlinktpp/RtclRlinkServer.hpp index 533cdb97..2271be5c 100644 --- a/tools/src/librlinktpp/RtclRlinkServer.hpp +++ b/tools/src/librlinktpp/RtclRlinkServer.hpp @@ -1,6 +1,6 @@ -// $Id: RtclRlinkServer.hpp 486 2013-02-10 22:34:43Z mueller $ +// $Id: RtclRlinkServer.hpp 662 2015-04-05 08:02:54Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,13 +13,14 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-04 662 1.1 add M_get, M_set; remove 'server -trace' // 2013-02-05 482 1.0.1 add shared_ptr to RlinkConnect object // 2013-01-12 474 1.0 Initial version // --------------------------------------------------------------------------- /*! \file - \version $Id: RtclRlinkServer.hpp 486 2013-02-10 22:34:43Z mueller $ + \version $Id: RtclRlinkServer.hpp 662 2015-04-05 08:02:54Z mueller $ \brief Declaration of class RtclRlinkServer. */ @@ -33,7 +34,10 @@ #include "librtcltools/RtclOPtr.hpp" #include "librtcltools/RtclProxyOwned.hpp" +#include "librtcltools/RtclGetList.hpp" +#include "librtcltools/RtclSetList.hpp" #include "RtclAttnShuttle.hpp" + #include "librlink/RlinkServer.hpp" namespace Retro { @@ -53,6 +57,8 @@ namespace Retro { int M_stats(RtclArgs& args); int M_print(RtclArgs& args); int M_dump(RtclArgs& args); + int M_get(RtclArgs& args); + int M_set(RtclArgs& args); int M_default(RtclArgs& args); protected: @@ -61,6 +67,8 @@ namespace Retro { boost::shared_ptr fspConn; alist_t fAttnHdl; // // @@ -23,7 +23,7 @@ /*! \file - \version $Id: Rw11CntlDL11.cpp 632 2015-01-11 12:30:03Z mueller $ + \version $Id: Rw11CntlDL11.cpp 659 2015-03-22 23:15:51Z mueller $ \brief Implemenation of Rw11CntlDL11. */ @@ -111,10 +111,10 @@ void Rw11CntlDL11::Start() // add device register address ibus and rbus mappings // done here because now Cntl bound to Cpu and Cntl probed - Cpu().AllAddrMapInsert(Name()+".rcsr", Base() + kRCSR); - Cpu().AllAddrMapInsert(Name()+".rbuf", Base() + kRBUF); - Cpu().AllAddrMapInsert(Name()+".xcsr", Base() + kXCSR); - Cpu().AllAddrMapInsert(Name()+".xbuf", Base() + kXBUF); + Cpu().AllIAddrMapInsert(Name()+".rcsr", Base() + kRCSR); + Cpu().AllIAddrMapInsert(Name()+".rbuf", Base() + kRBUF); + Cpu().AllIAddrMapInsert(Name()+".xcsr", Base() + kXCSR); + Cpu().AllIAddrMapInsert(Name()+".xbuf", Base() + kXBUF); // setup primary info clist fPrimClist.Clear(); diff --git a/tools/src/librw11/Rw11CntlDL11.hpp b/tools/src/librw11/Rw11CntlDL11.hpp index 113c8703..26566c0c 100644 --- a/tools/src/librw11/Rw11CntlDL11.hpp +++ b/tools/src/librw11/Rw11CntlDL11.hpp @@ -1,4 +1,4 @@ -// $Id: Rw11CntlDL11.hpp 623 2014-12-29 19:11:40Z mueller $ +// $Id: Rw11CntlDL11.hpp 665 2015-04-07 07:13:49Z mueller $ // // Copyright 2013-2014 by Walter F.J. Mueller // @@ -22,7 +22,7 @@ /*! \file - \version $Id: Rw11CntlDL11.hpp 623 2014-12-29 19:11:40Z mueller $ + \version $Id: Rw11CntlDL11.hpp 665 2015-04-07 07:13:49Z mueller $ \brief Declaration of class Rw11CntlDL11. */ @@ -56,10 +56,10 @@ namespace Retro { static const uint16_t kIbaddr = 0177560; //!< DL11 default address static const int kLam = 1; //!< DL11 default lam - static const uint16_t kRCSR = 000; //!< RCSR register address offset - static const uint16_t kRBUF = 002; //!< RBUF register address offset - static const uint16_t kXCSR = 004; //!< XCSR register address offset - static const uint16_t kXBUF = 006; //!< XBUF register address offset + static const uint16_t kRCSR = 000; //!< RCSR reg offset + static const uint16_t kRBUF = 002; //!< RBUF reg offset + static const uint16_t kXCSR = 004; //!< XCSR reg offset + static const uint16_t kXBUF = 006; //!< XBUF reg offset static const uint16_t kProbeOff = kRCSR; //!< probe address offset (rcsr) static const bool kProbeInt = true; //!< probe int active diff --git a/tools/src/librw11/Rw11CntlLP11.cpp b/tools/src/librw11/Rw11CntlLP11.cpp index 0593ab61..4378cb8f 100644 --- a/tools/src/librw11/Rw11CntlLP11.cpp +++ b/tools/src/librw11/Rw11CntlLP11.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11CntlLP11.cpp 625 2014-12-30 16:17:45Z mueller $ +// $Id: Rw11CntlLP11.cpp 659 2015-03-22 23:15:51Z mueller $ // // Copyright 2013-2014 by Walter F.J. Mueller // @@ -21,7 +21,7 @@ /*! \file - \version $Id: Rw11CntlLP11.cpp 625 2014-12-30 16:17:45Z mueller $ + \version $Id: Rw11CntlLP11.cpp 659 2015-03-22 23:15:51Z mueller $ \brief Implemenation of Rw11CntlLP11. */ @@ -101,8 +101,8 @@ void Rw11CntlLP11::Start() // add device register address ibus and rbus mappings // done here because now Cntl bound to Cpu and Cntl probed - Cpu().AllAddrMapInsert(Name()+".csr", Base() + kCSR); - Cpu().AllAddrMapInsert(Name()+".buf", Base() + kBUF); + Cpu().AllIAddrMapInsert(Name()+".csr", Base() + kCSR); + Cpu().AllIAddrMapInsert(Name()+".buf", Base() + kBUF); // setup primary info clist fPrimClist.Clear(); diff --git a/tools/src/librw11/Rw11CntlLP11.hpp b/tools/src/librw11/Rw11CntlLP11.hpp index 2c88090f..589ff1c1 100644 --- a/tools/src/librw11/Rw11CntlLP11.hpp +++ b/tools/src/librw11/Rw11CntlLP11.hpp @@ -1,4 +1,4 @@ -// $Id: Rw11CntlLP11.hpp 623 2014-12-29 19:11:40Z mueller $ +// $Id: Rw11CntlLP11.hpp 665 2015-04-07 07:13:49Z mueller $ // // Copyright 2013-2014 by Walter F.J. Mueller // @@ -20,7 +20,7 @@ /*! \file - \version $Id: Rw11CntlLP11.hpp 623 2014-12-29 19:11:40Z mueller $ + \version $Id: Rw11CntlLP11.hpp 665 2015-04-07 07:13:49Z mueller $ \brief Declaration of class Rw11CntlLP11. */ @@ -50,8 +50,8 @@ namespace Retro { static const uint16_t kIbaddr = 0177514; //!< LP11 default address static const int kLam = 8; //!< LP11 default lam - static const uint16_t kCSR = 000; //!< CSR register address offset - static const uint16_t kBUF = 002; //!< BUF register address offset + static const uint16_t kCSR = 000; //!< CSR reg offset + static const uint16_t kBUF = 002; //!< BUF reg offset static const uint16_t kProbeOff = kCSR; //!< probe address offset (rcsr) static const bool kProbeInt = true; //!< probe int active diff --git a/tools/src/librw11/Rw11CntlPC11.cpp b/tools/src/librw11/Rw11CntlPC11.cpp index 2c74e192..09f7890a 100644 --- a/tools/src/librw11/Rw11CntlPC11.cpp +++ b/tools/src/librw11/Rw11CntlPC11.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11CntlPC11.cpp 625 2014-12-30 16:17:45Z mueller $ +// $Id: Rw11CntlPC11.cpp 659 2015-03-22 23:15:51Z mueller $ // // Copyright 2013-2014 by Walter F.J. Mueller // @@ -20,7 +20,7 @@ /*! \file - \version $Id: Rw11CntlPC11.cpp 625 2014-12-30 16:17:45Z mueller $ + \version $Id: Rw11CntlPC11.cpp 659 2015-03-22 23:15:51Z mueller $ \brief Implemenation of Rw11CntlPC11. */ @@ -109,10 +109,10 @@ void Rw11CntlPC11::Start() // add device register address ibus and rbus mappings // done here because now Cntl bound to Cpu and Cntl probed - Cpu().AllAddrMapInsert(Name()+".rcsr", Base() + kRCSR); - Cpu().AllAddrMapInsert(Name()+".rbuf", Base() + kRBUF); - Cpu().AllAddrMapInsert(Name()+".pcsr", Base() + kPCSR); - Cpu().AllAddrMapInsert(Name()+".pbuf", Base() + kPBUF); + Cpu().AllIAddrMapInsert(Name()+".rcsr", Base() + kRCSR); + Cpu().AllIAddrMapInsert(Name()+".rbuf", Base() + kRBUF); + Cpu().AllIAddrMapInsert(Name()+".pcsr", Base() + kPCSR); + Cpu().AllIAddrMapInsert(Name()+".pbuf", Base() + kPBUF); // setup primary info clist fPrimClist.Clear(); diff --git a/tools/src/librw11/Rw11CntlPC11.hpp b/tools/src/librw11/Rw11CntlPC11.hpp index b1901655..76509224 100644 --- a/tools/src/librw11/Rw11CntlPC11.hpp +++ b/tools/src/librw11/Rw11CntlPC11.hpp @@ -1,4 +1,4 @@ -// $Id: Rw11CntlPC11.hpp 623 2014-12-29 19:11:40Z mueller $ +// $Id: Rw11CntlPC11.hpp 665 2015-04-07 07:13:49Z mueller $ // // Copyright 2013-2014 by Walter F.J. Mueller // @@ -20,7 +20,7 @@ /*! \file - \version $Id: Rw11CntlPC11.hpp 623 2014-12-29 19:11:40Z mueller $ + \version $Id: Rw11CntlPC11.hpp 665 2015-04-07 07:13:49Z mueller $ \brief Declaration of class Rw11CntlPC11. */ @@ -53,10 +53,10 @@ namespace Retro { static const uint16_t kIbaddr = 0177550; //!< PC11 default address static const int kLam = 10; //!< PC11 default lam - static const uint16_t kRCSR = 000; //!< RCSR register address offset - static const uint16_t kRBUF = 002; //!< RBUF register address offset - static const uint16_t kPCSR = 004; //!< PCSR register address offset - static const uint16_t kPBUF = 006; //!< PBUF register address offset + static const uint16_t kRCSR = 000; //!< RCSR reg offset + static const uint16_t kRBUF = 002; //!< RBUF reg offset + static const uint16_t kPCSR = 004; //!< PCSR reg offset + static const uint16_t kPBUF = 006; //!< PBUF reg offset static const uint16_t kUnit_PR = 0; // +// Other credits: +// the boot code is from the simh project and Copyright Robert M Supnik +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-14 680 1.0 Initial version +// 2015-03-21 659 0.1 First draft +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11CntlRHRP.cpp 680 2015-05-14 13:29:46Z mueller $ + \brief Implemenation of Rw11CntlRHRP. +*/ + +#include "boost/bind.hpp" +#include "boost/foreach.hpp" +#define foreach_ BOOST_FOREACH + +#include "librtools/RosFill.hpp" +#include "librtools/RosPrintBvi.hpp" +#include "librtools/RosPrintf.hpp" +#include "librtools/Rexception.hpp" +#include "librtools/RlogMsg.hpp" + +#include "Rw11CntlRHRP.hpp" + +using namespace std; + +/*! + \class Retro::Rw11CntlRHRP + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +// constants definitions + +const uint16_t Rw11CntlRHRP::kIbaddr; +const int Rw11CntlRHRP::kLam; + +const uint16_t Rw11CntlRHRP::kRPCS1; +const uint16_t Rw11CntlRHRP::kRPWC; +const uint16_t Rw11CntlRHRP::kRPBA; +const uint16_t Rw11CntlRHRP::kRPDA; +const uint16_t Rw11CntlRHRP::kRPCS2; +const uint16_t Rw11CntlRHRP::kRPDS; +const uint16_t Rw11CntlRHRP::kRPER1; +const uint16_t Rw11CntlRHRP::kRPAS; +const uint16_t Rw11CntlRHRP::kRPLA; +const uint16_t Rw11CntlRHRP::kRPDB; +const uint16_t Rw11CntlRHRP::kRPMR1; +const uint16_t Rw11CntlRHRP::kRPDT; +const uint16_t Rw11CntlRHRP::kRPSN; +const uint16_t Rw11CntlRHRP::kRPOF; +const uint16_t Rw11CntlRHRP::kRPDC; +const uint16_t Rw11CntlRHRP::kRxM13; +const uint16_t Rw11CntlRHRP::kRxM14; +const uint16_t Rw11CntlRHRP::kRxM15; +const uint16_t Rw11CntlRHRP::kRPEC1; +const uint16_t Rw11CntlRHRP::kRPEC2; +const uint16_t Rw11CntlRHRP::kRPBAE; +const uint16_t Rw11CntlRHRP::kRPCS3; + +const uint16_t Rw11CntlRHRP::kProbeOff; +const bool Rw11CntlRHRP::kProbeInt; +const bool Rw11CntlRHRP::kProbeRem; + +const uint16_t Rw11CntlRHRP::kRPCS1_M_SC; +const uint16_t Rw11CntlRHRP::kRPCS1_M_TRE; +const uint16_t Rw11CntlRHRP::kRPCS1_M_DVA; +const uint16_t Rw11CntlRHRP::kRPCS1_M_BAE; +const uint16_t Rw11CntlRHRP::kRPCS1_V_BAE; +const uint16_t Rw11CntlRHRP::kRPCS1_B_BAE; +const uint16_t Rw11CntlRHRP::kRPCS1_M_RDY; +const uint16_t Rw11CntlRHRP::kRPCS1_M_IE; +const uint16_t Rw11CntlRHRP::kRPCS1_V_FUNC; +const uint16_t Rw11CntlRHRP::kRPCS1_B_FUNC; +const uint16_t Rw11CntlRHRP::kRPCS1_M_GO; + +const uint16_t Rw11CntlRHRP::kFUNC_WCD; +const uint16_t Rw11CntlRHRP::kFUNC_WCHD; +const uint16_t Rw11CntlRHRP::kFUNC_WRITE; +const uint16_t Rw11CntlRHRP::kFUNC_WHD; +const uint16_t Rw11CntlRHRP::kFUNC_READ; +const uint16_t Rw11CntlRHRP::kFUNC_RHD; + +const uint16_t Rw11CntlRHRP::kRFUNC_WUNIT; +const uint16_t Rw11CntlRHRP::kRFUNC_CUNIT; +const uint16_t Rw11CntlRHRP::kRFUNC_DONE; +const uint16_t Rw11CntlRHRP::kRFUNC_WIDLY; + +const uint16_t Rw11CntlRHRP::kRPCS1_V_RUNIT; +const uint16_t Rw11CntlRHRP::kRPCS1_B_RUNIT; +const uint16_t Rw11CntlRHRP::kRPCS1_M_RATA; +const uint16_t Rw11CntlRHRP::kRPCS1_V_RIDLY; +const uint16_t Rw11CntlRHRP::kRPCS1_B_RIDLY; + +const uint16_t Rw11CntlRHRP::kRPDA_V_TA; +const uint16_t Rw11CntlRHRP::kRPDA_B_TA; +const uint16_t Rw11CntlRHRP::kRPDA_B_SA; + +const uint16_t Rw11CntlRHRP::kRPCS2_M_RWCO; +const uint16_t Rw11CntlRHRP::kRPCS2_M_WCE; +const uint16_t Rw11CntlRHRP::kRPCS2_M_NED; +const uint16_t Rw11CntlRHRP::kRPCS2_M_NEM; +const uint16_t Rw11CntlRHRP::kRPCS2_M_PGE; +const uint16_t Rw11CntlRHRP::kRPCS2_M_MXF; +const uint16_t Rw11CntlRHRP::kRPCS2_M_OR; +const uint16_t Rw11CntlRHRP::kRPCS2_M_IR; +const uint16_t Rw11CntlRHRP::kRPCS2_M_CLR; +const uint16_t Rw11CntlRHRP::kRPCS2_M_PAT; +const uint16_t Rw11CntlRHRP::kRPCS2_M_BAI; +const uint16_t Rw11CntlRHRP::kRPCS2_M_UNIT2; +const uint16_t Rw11CntlRHRP::kRPCS2_B_UNIT; + +const uint16_t Rw11CntlRHRP::kRPDS_M_ATA; +const uint16_t Rw11CntlRHRP::kRPDS_M_ERP; +const uint16_t Rw11CntlRHRP::kRPDS_M_MOL; +const uint16_t Rw11CntlRHRP::kRPDS_M_WRL; +const uint16_t Rw11CntlRHRP::kRPDS_M_LBT; +const uint16_t Rw11CntlRHRP::kRPDS_M_DPR; +const uint16_t Rw11CntlRHRP::kRPDS_M_DRY; +const uint16_t Rw11CntlRHRP::kRPDS_M_VV; +const uint16_t Rw11CntlRHRP::kRPDS_M_OM ; + +const uint16_t Rw11CntlRHRP::kRPER1_M_UNS; +const uint16_t Rw11CntlRHRP::kRPER1_M_WLE; +const uint16_t Rw11CntlRHRP::kRPER1_M_IAE; +const uint16_t Rw11CntlRHRP::kRPER1_M_AOE; +const uint16_t Rw11CntlRHRP::kRPER1_M_RMR; +const uint16_t Rw11CntlRHRP::kRPER1_M_ILF; + +const uint16_t Rw11CntlRHRP::kRPDC_B_CA; + +const uint16_t Rw11CntlRHRP::kRPCS3_M_IE; +const uint16_t Rw11CntlRHRP::kRPCS3_M_RSEARDONE; +const uint16_t Rw11CntlRHRP::kRPCS3_M_RPACKDONE; +const uint16_t Rw11CntlRHRP::kRPCS3_M_RPOREDONE; +const uint16_t Rw11CntlRHRP::kRPCS3_M_RSEEKDONE; + +//------------------------------------------+----------------------------------- +//! Default constructor + +Rw11CntlRHRP::Rw11CntlRHRP() + : Rw11CntlBase("rhrp"), + fPC_rpcs1(0), + fPC_rpcs2(0), + fPC_rpcs3(0), + fPC_rpwc(0), + fPC_rpba(0), + fPC_rpbae(0), + fPC_cunit(0), + fPC_rpds(0), + fPC_rpda(0), + fPC_rpdc(0), + fRd_rpcs1(0), + fRd_rpcs2(0), + fRd_rpcs3(0), + fRd_rpwc(0), + fRd_rpba(0), + fRd_rpbae(0), + fRd_rpds(0), + fRd_rpda(0), + fRd_rpdc(0), + fRd_addr(0), + fRd_lba(0), + fRd_nwrd(0), + fRd_fu(0), + fRd_ovr(false), + fRdma(this, + boost::bind(&Rw11CntlRHRP::RdmaPreExecCB, this, _1, _2, _3, _4), + boost::bind(&Rw11CntlRHRP::RdmaPostExecCB, this, _1, _2, _3, _4)) +{ + // must be here because Units have a back-ptr (not available at Rw11CntlBase) + for (size_t i=0; i set MOL + rpds |= kRPDS_M_ERP; // -> clear ER1 via ERP=1 + if (unit.WProt()) rpds |= kRPDS_M_WRL; // in case write protected + } + if ((unit.Rpds() ^ rpds) & kRPDS_M_MOL) { // mol state change ? + rpds |= kRPDS_M_ATA; // cause attentions + rpds |= kRPDS_M_VV; // reset volume valid + } + } + + unit.SetRpds(rpds); // remember new DS + cpu.AddWibr(clist, fBase+kRPCS1, // setup unit + (ind << kRPCS1_V_RUNIT) | + (kRFUNC_WUNIT << kRPCS1_V_FUNC) ); + cpu.AddWibr(clist, fBase+kRPDT, unit.Rpdt()); // setup DT + cpu.AddWibr(clist, fBase+kRPDS, rpds); // setup DS + Server().Exec(clist); + + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool Rw11CntlRHRP::BootCode(size_t unit, std::vector& code, + uint16_t& aload, uint16_t& astart) +{ + uint16_t kBOOT_START = 02000; + uint16_t bootcode[] = { // rh/rp boot loader - from simh pdp11_rp.c (v3.9) + 0042102, // "BD" + 0012706, kBOOT_START, // mov #boot_start, sp + 0012700, uint16_t(unit), // mov #unit, r0 + 0012701, 0176700, // mov #RPCS1, r1 + 0012761, 0000040, 0000010, // mov #CS2_CLR, 10(r1) ; reset + 0010061, 0000010, // mov r0, 10(r1) ; set unit + 0012711, 0000021, // mov #RIP+GO, (r1) ; pack ack + 0012761, 0010000, 0000032, // mov #FMT16B, 32(r1) ; 16b mode + 0012761, 0177000, 0000002, // mov #-512., 2(r1) ; set wc + 0005061, 0000004, // clr 4(r1) ; clr ba + 0005061, 0000006, // clr 6(r1) ; clr da + 0005061, 0000034, // clr 34(r1) ; clr cyl + 0012711, 0000071, // mov #READ+GO, (r1) ; read + 0105711, // tstb (r1) ; wait + 0100376, // bpl .-2 + 0005002, // clr R2 + 0005003, // clr R3 + 0012704, uint16_t(kBOOT_START+020), // mov #start+020, r4 + 0005005, // clr R5 + 0105011, // clrb (r1) + 0005007 // clr PC + }; + + code.clear(); + foreach_ (uint16_t& w, bootcode) code.push_back(w); + aload = kBOOT_START; + astart = kBOOT_START+2; + return true; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11CntlRHRP::Dump(std::ostream& os, int ind, const char* text) const +{ + RosFill bl(ind); + os << bl << (text?text:"--") << "Rw11CntlRHRP @ " << this << endl; + os << bl << " fPC_rpcs1: " << RosPrintf(fPC_rpcs1,"d",6) << endl; + os << bl << " fPC_rpcs2: " << RosPrintf(fPC_rpcs2,"d",6) << endl; + os << bl << " fPC_rpcs3: " << RosPrintf(fPC_rpcs3,"d",6) << endl; + os << bl << " fPC_rpwc: " << RosPrintf(fPC_rpwc,"d",6) << endl; + os << bl << " fPC_rpba: " << RosPrintf(fPC_rpba,"d",6) << endl; + os << bl << " fPC_rpbae: " << RosPrintf(fPC_rpbae,"d",6) << endl; + os << bl << " fPC_cunit: " << RosPrintf(fPC_cunit,"d",6) << endl; + os << bl << " fPC_rpds: " << RosPrintf(fPC_rpds,"d",6) << endl; + os << bl << " fPC_rpda: " << RosPrintf(fPC_rpda,"d",6) << endl; + os << bl << " fPC_rpdc: " << RosPrintf(fPC_rpdc,"d",6) << endl; + os << bl << " fRd_rpcs1: " << RosPrintBvi(fRd_rpcs1) << endl; + os << bl << " fRd_rpcs2: " << RosPrintBvi(fRd_rpcs2) << endl; + os << bl << " fRd_rpcs3: " << RosPrintBvi(fRd_rpcs3) << endl; + os << bl << " fRd_rpwc: " << RosPrintBvi(fRd_rpwc) << endl; + os << bl << " fRd_rpba: " << RosPrintBvi(fRd_rpba) << endl; + os << bl << " fRd_rpbae: " << RosPrintBvi(fRd_rpbae) << endl; + os << bl << " fRd_rpds: " << RosPrintBvi(fRd_rpds) << endl; + os << bl << " fRd_rpda: " << RosPrintBvi(fRd_rpda) << endl; + os << bl << " fRd_rpdc: " << RosPrintBvi(fRd_rpdc) << endl; + os << bl << " fRd_addr: " << RosPrintBvi(fRd_addr,8,22) << endl; + os << bl << " fRd_lba: " << RosPrintf(fRd_lba,"d",6) << endl; + os << bl << " fRd_nwrd: " << RosPrintf(fRd_nwrd,"d",6) << endl; + os << bl << " fRd_fu: " << RosPrintf(fRd_fu,"d",6) << endl; + os << bl << " fRd_ovr: " << fRd_ovr << endl; + fRdma.Dump(os, ind+2, "fRdma: "); + Rw11CntlBase::Dump(os, ind, " ^"); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +int Rw11CntlRHRP::AttnHandler(RlinkServer::AttnArgs& args) +{ + fStats.Inc(kStatNAttnHdl); + Server().GetAttnInfo(args, fPrimClist); + + uint16_t rpcs1 = fPrimClist[fPC_rpcs1].Data(); + uint16_t rpcs2 = fPrimClist[fPC_rpcs2].Data(); + uint16_t rpcs3 = fPrimClist[fPC_rpcs3].Data(); + uint16_t rpwc = fPrimClist[fPC_rpwc ].Data(); + uint16_t rpba = fPrimClist[fPC_rpba ].Data(); + uint16_t rpbae = fPrimClist[fPC_rpbae].Data(); + uint16_t rpds = fPrimClist[fPC_rpds ].Data(); + uint16_t rpda = fPrimClist[fPC_rpda ].Data(); + uint16_t rpdc = fPrimClist[fPC_rpdc ].Data(); + + uint16_t unum = rpcs2 & kRPCS2_B_UNIT; + uint16_t fu = (rpcs1>>kRPCS1_V_FUNC) & kRPCS1_B_FUNC; + + uint32_t addr = uint32_t(rpbae)<<16 | uint32_t(rpba); + + uint16_t sa = rpda & kRPDA_B_SA; + uint16_t ta = (rpda>>kRPDA_V_TA) & kRPDA_B_TA; + uint16_t ca = rpdc & kRPDC_B_CA; + + uint32_t nwrd = (~uint32_t(rpwc)&0xffff) + 1; // transfer size in words + + // all 4 units are always available, but check anyway + if (unum > NUnit()) + throw Rexception("Rw11CntlRHRP::AttnHandler","Bad state: unum > NUnit()"); + + Rw11UnitRHRP& unit = *fspUnit[unum]; + //Rw11Cpu& cpu = Cpu(); + RlinkCommandList clist; + + uint32_t lba = unit.Chs2Lba(ca,ta,sa); + uint32_t nblk = unit.Nwrd2Nblk(nwrd); + + if (fTraceLevel>0) { + RlogMsg lmsg(LogFile()); + static const char* fumnemo[32] = + {"00 ","01 ","02 ","03 ","04 ","05 ","06 ","07 ", // 00--- + "10 ","11 ","12 ","13 ","14 ","15 ","16 ","17 ", // 01--- + "20 ","21 ","22 ","23 ","wc ","wch","26 ","27 ", // 10--- + "wr ","wrh","32 ","33 ","rd ","rdh","36 ","37 "}; // 11--- + lmsg << "-I RHRP" + << " fu=" << fumnemo[fu&037] + << " cs=" << RosPrintBvi(rpcs1,8) + << "," << RosPrintBvi(rpcs2,8) + << " ad=" << RosPrintBvi(addr,8,22) + << " pa=" << unum + << "," << RosPrintf(ca,"d",3) + << "," << RosPrintf(ta,"d",2) + << "," << RosPrintf(sa,"d",2) + << " la,nw=" << RosPrintf(lba,"d",6) + << ","; + if (nwrd==65536) lmsg << " (0)"; else lmsg << RosPrintf(nwrd,"d",5); + } + + // handle cs3 done flags, just count them + if (rpcs3 & kRPCS3_M_RSEARDONE) fStats.Inc(kStatNFuncSear); + if (rpcs3 & kRPCS3_M_RPOREDONE) fStats.Inc(kStatNFuncPore); + if (rpcs3 & kRPCS3_M_RPACKDONE) fStats.Inc(kStatNFuncPack); + if (rpcs3 & kRPCS3_M_RSEEKDONE) fStats.Inc(kStatNFuncSeek); + + // check for overrun (read/write beyond last track + // if found, truncate request length + bool ovr = lba + nblk > unit.NBlock(); + if (ovr) nwrd = (unit.NBlock()-lba) * (unit.BlockSize()/2); + + // remember request parameters for call back and error exit handling + + fRd_rpcs1 = rpcs1; + fRd_rpcs2 = rpcs2; + fRd_rpcs3 = rpcs3; + fRd_rpwc = rpwc; + fRd_rpba = rpba; + fRd_rpbae = rpbae; + fRd_rpds = rpds; + fRd_rpda = rpda; + fRd_rpdc = rpdc; + fRd_addr = addr; + fRd_lba = lba; + fRd_nwrd = nwrd; + fRd_fu = fu; + fRd_ovr = ovr; + + // check for general abort conditions + // note: only 'data transfer' functions handled via backend + // SEEK and others are done in ibdr_rhrp autonomously + + // not attached --> signal drive unsave status + if (! unit.Virt()) { // not attached + AddErrorExit(clist, kRPER1_M_UNS); // signal UNS (drive unsafe) + Server().Exec(clist); // doit + return 0; + } + + // invalid disk address + if (ca > unit.NCylinder() || ta > unit.NHead() || sa > unit.NSector()) { + AddErrorExit(clist, kRPER1_M_IAE); // signal IAE (invalid address err) + Server().Exec(clist); // doit + return 0; + } + + // now handle the functions + if (fu == kFUNC_WRITE) { // Write ------------------------- + fStats.Inc(kStatNFuncWrite); + if (unit.WProt()) { // write on write locked drive ? + AddErrorExit(clist, kRPER1_M_WLE); // signal WLE (write lock error) + } else { + fRdma.QueueDiskWrite(addr, nwrd, Rw11Cpu::kCPAH_M_22BIT, lba, &unit); + } + + } else if (fu == kFUNC_WCD) { // Write Check ------------------- + fStats.Inc(kStatNFuncWchk ); + fRdma.QueueDiskWriteCheck(addr, nwrd, Rw11Cpu::kCPAH_M_22BIT, lba, &unit); + + } else if (fu == kFUNC_READ ) { // Read -------------------------- + fStats.Inc(kStatNFuncRead); + fRdma.QueueDiskRead(addr, nwrd, Rw11Cpu::kCPAH_M_22BIT, lba, &unit); + + } else { + // FIXME: handle other special functions (currently simply error out !!) + AddErrorExit(clist, kRPER1_M_ILF); // signal ILF (invalid function) + Server().Exec(clist); // doit + return 0; + } + + if (clist.Size()) { // if handled directly + Server().Exec(clist); // doit + } + + return 0; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11CntlRHRP::RdmaPreExecCB(int stat, size_t nwdone, size_t nwnext, + RlinkCommandList& clist) +{ + // if last chunk and not doing WCD add a labo and normal exit csr update + if (stat == Rw11Rdma::kStatusBusyLast && fRd_fu != kFUNC_WCD) { + clist.AddLabo(); + AddNormalExit(clist, nwdone+nwnext, 0, 0); + } + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11CntlRHRP::RdmaPostExecCB(int stat, size_t ndone, + RlinkCommandList& clist, size_t ncmd) +{ + if (stat == Rw11Rdma::kStatusBusy) return; + + uint16_t rper1 = 0; + uint16_t rpcs2 = 0; + + if (fRd_fu == kFUNC_WCD) { + size_t nwcok = fRdma.WriteCheck(ndone); + if (nwcok != ndone) { // if mismatch found + rpcs2 = kRPCS2_M_WCE; + if (ndone & 0x1) rpcs2 = kRPCS2_M_RWCO; // failed in odd word ! + ndone = nwcok; // truncate word count + } + } + + // handle Rdma aborts + if (stat == Rw11Rdma::kStatusFailRdma) rpcs2 = kRPCS2_M_NEM; + + // check for fused csr updates + if (clist.Size() > ncmd) { + uint8_t ccode = clist[ncmd].Command(); + uint16_t cdata = clist[ncmd].Data(); + if (ccode != RlinkCommand::kCmdLabo || (rper1 != 0 && cdata == 0)) + throw Rexception("Rw11CntlRHRP::RdmaPostExecCB", + "Bad state: Labo not found or missed abort"); + if (cdata == 0) return; + } + + // finally to RHRP register update + RlinkCommandList clist1; + AddNormalExit(clist1, ndone, rper1, rpcs2); + Server().Exec(clist1); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11CntlRHRP::AddErrorExit(RlinkCommandList& clist, uint16_t rper1) +{ + Rw11Cpu& cpu = Cpu(); + + cpu.AddWibr(clist, fBase+kRPCS1, (kRFUNC_CUNIT<1) { + RlogMsg lmsg(LogFile()); + lmsg << "-I RHRP" + << " err " + << " cs1=" << RosPrintBvi(fRd_rpcs1,8) + << " er1=" << RosPrintBvi(rper1,2,16); + } + + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11CntlRHRP::AddNormalExit(RlinkCommandList& clist, size_t ndone, + uint16_t rper1, uint16_t rpcs2) +{ + Rw11Cpu& cpu = Cpu(); + uint16_t unum = fRd_rpcs2 & kRPCS2_B_UNIT; + Rw11UnitRHRP& unit = *fspUnit[unum]; + + size_t nblk = unit.Nwrd2Nblk(ndone); + uint32_t addr = fRd_addr + 2*ndone; + size_t lba = fRd_lba + nblk; + + uint16_t ba = addr & 0177776; // get lower 16 bits + uint16_t bae = (addr>>16) & 077; // get upper 6 bits + + uint16_t sa; + uint16_t ta; + uint16_t ca; + unit.Lba2Chs(lba, ca,ta,sa); + uint16_t da = (ta<1) { + RlogMsg lmsg(LogFile()); + if (rper1 || rpcs2) { + lmsg << "-I RHRP" + << " err " + << " er1=" << RosPrintBvi(rper1,2,16) + << " cs2=" << RosPrintBvi(rpcs2,2,8) + << endl; + } + lmsg << "-I RHRP" + << (rper1==0 ? " ok " :" err ") + << " we=" << RosPrintBvi(wc,8) << "," << RosPrintBvi(rper1,8) + << " ad=" << RosPrintBvi(addr,8,22) + << " pa=" << unum + << "," << RosPrintf(ca,"d",3) + << "," << RosPrintf(ta,"d",2) + << "," << RosPrintf(sa,"d",2) + << " ca,da=" << RosPrintBvi(ca,8,10) << "," << RosPrintBvi(da,8); + } + + return; +} + + +} // end namespace Retro diff --git a/tools/src/librw11/Rw11CntlRHRP.hpp b/tools/src/librw11/Rw11CntlRHRP.hpp new file mode 100644 index 00000000..034746d5 --- /dev/null +++ b/tools/src/librw11/Rw11CntlRHRP.hpp @@ -0,0 +1,221 @@ +// $Id: Rw11CntlRHRP.hpp 680 2015-05-14 13:29:46Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-14 680 1.0 Initial version +// 2015-03-21 659 0.1 First draft +// --------------------------------------------------------------------------- + + +/*! + \file + \version $Id: Rw11CntlRHRP.hpp 680 2015-05-14 13:29:46Z mueller $ + \brief Declaration of class Rw11CntlRHRP. +*/ + +#ifndef included_Retro_Rw11CntlRHRP +#define included_Retro_Rw11CntlRHRP 1 + +#include "Rw11CntlBase.hpp" +#include "Rw11UnitRHRP.hpp" +#include "Rw11RdmaDisk.hpp" + +namespace Retro { + + class Rw11CntlRHRP : public Rw11CntlBase { + public: + + Rw11CntlRHRP(); + ~Rw11CntlRHRP(); + + void Config(const std::string& name, uint16_t base, int lam); + + virtual void Start(); + + virtual bool BootCode(size_t unit, std::vector& code, + uint16_t& aload, uint16_t& astart); + + virtual void UnitSetup(size_t ind); + + void SetChunkSize(size_t chunk); + size_t ChunkSize() const; + + const Rstats& RdmaStats() const; + + virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; + + // some constants (also defined in cpp) + static const uint16_t kIbaddr = 0176700; //!< RHRP default address + static const int kLam = 6; //!< RHRP default lam + + static const uint16_t kRPCS1 = 000; //!< RPCS1 reg offset + static const uint16_t kRPWC = 002; //!< RPWC reg offset + static const uint16_t kRPBA = 004; //!< RPBA reg offset + static const uint16_t kRPDA = 006; //!< RPDA reg offset + static const uint16_t kRPCS2 = 010; //!< RPCS2 reg offset + static const uint16_t kRPDS = 012; //!< RPDS reg offset + static const uint16_t kRPER1 = 014; //!< RPER1 reg offset + static const uint16_t kRPAS = 016; //!< RPAS reg offset + static const uint16_t kRPLA = 020; //!< RPLA reg offset + static const uint16_t kRPDB = 022; //!< RPDB reg offset + static const uint16_t kRPMR1 = 024; //!< RPMR1 reg offset + static const uint16_t kRPDT = 026; //!< RPDT reg offset + static const uint16_t kRPSN = 030; //!< RPSN reg offset + static const uint16_t kRPOF = 032; //!< RPOF reg offset + static const uint16_t kRPDC = 034; //!< RPDC reg offset + static const uint16_t kRxM13 = 036; //!< MB reg 13 reg offset + static const uint16_t kRxM14 = 040; //!< MB reg 14 reg offset + static const uint16_t kRxM15 = 042; //!< MB reg 15 reg offset + static const uint16_t kRPEC1 = 044; //!< RPEC1 reg offset + static const uint16_t kRPEC2 = 046; //!< RPEC2 reg offset + static const uint16_t kRPBAE = 050; //!< RPBAE reg offset + static const uint16_t kRPCS3 = 052; //!< RPCS3 reg offset + + static const uint16_t kProbeOff = kRPCS2;//!< probe address offset (rxcs2) + static const bool kProbeInt = true; //!< probe int active + static const bool kProbeRem = true; //!< probr rem active + + static const uint16_t kRPCS1_M_SC = kWBit15; + static const uint16_t kRPCS1_M_TRE = kWBit14; + static const uint16_t kRPCS1_M_DVA = kWBit11; + static const uint16_t kRPCS1_M_BAE = 001400; + static const uint16_t kRPCS1_V_BAE = 8; + static const uint16_t kRPCS1_B_BAE = 0003; + static const uint16_t kRPCS1_M_RDY = kWBit07; + static const uint16_t kRPCS1_M_IE = kWBit06; + static const uint16_t kRPCS1_V_FUNC = 1; + static const uint16_t kRPCS1_B_FUNC = 0037; + static const uint16_t kRPCS1_M_GO = kWBit00; + + // only function codes handled in backend are defined + static const uint16_t kFUNC_WCD = 024; //!< func: write chk data + static const uint16_t kFUNC_WCHD = 025; //!< func: write chk head&data + static const uint16_t kFUNC_WRITE = 030; //!< func: write + static const uint16_t kFUNC_WHD = 031; //!< func: write head&data + static const uint16_t kFUNC_READ = 034; //!< func: read + static const uint16_t kFUNC_RHD = 035; //!< func: read head&data + // remote function codes + static const uint16_t kRFUNC_WUNIT = 001; //!< rfunc: write runit + static const uint16_t kRFUNC_CUNIT = 002; //!< rfunc: copy funit->runit + static const uint16_t kRFUNC_DONE = 003; //!< rfunc: done (set rdy) + static const uint16_t kRFUNC_WIDLY = 004; //!< rfunc: write idly + + // cs1 usage or rem func=wunit + static const uint16_t kRPCS1_V_RUNIT = 8; + static const uint16_t kRPCS1_B_RUNIT = 0003; + // cs1 usage or rem func=done + static const uint16_t kRPCS1_M_RATA = kWBit08; + // cs1 usage or rem func=widly + static const uint16_t kRPCS1_V_RIDLY = 8; + static const uint16_t kRPCS1_B_RIDLY = 0377; + + static const uint16_t kRPDA_V_TA = 8; + static const uint16_t kRPDA_B_TA = 0037; + static const uint16_t kRPDA_B_SA = 0077; + + static const uint16_t kRPCS2_M_RWCO = kWBit15; + static const uint16_t kRPCS2_M_WCE = kWBit14; + static const uint16_t kRPCS2_M_NED = kWBit12; + static const uint16_t kRPCS2_M_NEM = kWBit11; + static const uint16_t kRPCS2_M_PGE = kWBit10; + static const uint16_t kRPCS2_M_MXF = kWBit09; + static const uint16_t kRPCS2_M_OR = kWBit07; + static const uint16_t kRPCS2_M_IR = kWBit06; + static const uint16_t kRPCS2_M_CLR = kWBit05; + static const uint16_t kRPCS2_M_PAT = kWBit04; + static const uint16_t kRPCS2_M_BAI = kWBit03; + static const uint16_t kRPCS2_M_UNIT2 = kWBit02; + static const uint16_t kRPCS2_B_UNIT = 0003; + + static const uint16_t kRPDS_M_ATA = kWBit15; + static const uint16_t kRPDS_M_ERP = kWBit14; + static const uint16_t kRPDS_M_MOL = kWBit12; + static const uint16_t kRPDS_M_WRL = kWBit11; + static const uint16_t kRPDS_M_LBT = kWBit10; + static const uint16_t kRPDS_M_DPR = kWBit08; + static const uint16_t kRPDS_M_DRY = kWBit07; + static const uint16_t kRPDS_M_VV = kWBit06; + static const uint16_t kRPDS_M_OM = kWBit00; + + static const uint16_t kRPER1_M_UNS = kWBit14; + static const uint16_t kRPER1_M_WLE = kWBit11; + static const uint16_t kRPER1_M_IAE = kWBit10; + static const uint16_t kRPER1_M_AOE = kWBit09; + static const uint16_t kRPER1_M_RMR = kWBit02; + static const uint16_t kRPER1_M_ILF = kWBit00; + + static const uint16_t kRPDC_B_CA = 01777; + + static const uint16_t kRPCS3_M_IE = kWBit06; + static const uint16_t kRPCS3_M_RSEARDONE = kWBit03; + static const uint16_t kRPCS3_M_RPACKDONE = kWBit02; + static const uint16_t kRPCS3_M_RPOREDONE = kWBit01; + static const uint16_t kRPCS3_M_RSEEKDONE = kWBit00; + + // statistics counter indices + enum stats { + kStatNFuncWchk = Rw11Cntl::kDimStat, + kStatNFuncWrite, + kStatNFuncRead, + kStatNFuncSear, + kStatNFuncPack, + kStatNFuncPore, + kStatNFuncSeek, + kDimStat + }; + + protected: + int AttnHandler(RlinkServer::AttnArgs& args); + void RdmaPreExecCB(int stat, size_t nwdone, size_t nwnext, + RlinkCommandList& clist); + void RdmaPostExecCB(int stat, size_t ndone, + RlinkCommandList& clist, size_t ncmd); + void AddErrorExit(RlinkCommandList& clist, uint16_t rper1); + void AddNormalExit(RlinkCommandList& clist, size_t ndone, + uint16_t rper1=0, uint16_t rpcs2=0); + + protected: + size_t fPC_rpcs1; //!< PrimClist: rpcs1 index + size_t fPC_rpcs2; //!< PrimClist: rpcs2 index + size_t fPC_rpcs3; //!< PrimClist: rpcs3 index + size_t fPC_rpwc; //!< PrimClist: rpwc index + size_t fPC_rpba; //!< PrimClist: rpba index + size_t fPC_rpbae; //!< PrimClist: rpbae index + size_t fPC_cunit; //!< PrimClist: copy unit + size_t fPC_rpds; //!< PrimClist: rpds index + size_t fPC_rpda; //!< PrimClist: rpda index + size_t fPC_rpdc; //!< PrimClist: rpdc index + + uint16_t fRd_rpcs1; //!< Rdma: request rpcs1 + uint16_t fRd_rpcs2; //!< Rdma: request rpcs2 + uint16_t fRd_rpcs3; //!< Rdma: request rpcs3 + uint16_t fRd_rpwc; //!< Rdma: request rpwc + uint16_t fRd_rpba; //!< Rdma: request rpba + uint16_t fRd_rpbae; //!< Rdma: request rpbae + uint16_t fRd_rpds; //!< Rdma: request rpds + uint16_t fRd_rpda; //!< Rdma: request rpda + uint16_t fRd_rpdc; //!< Rdma: request rpdc + uint32_t fRd_addr; //!< Rdma: current addr + uint32_t fRd_lba; //!< Rdma: current lba + uint32_t fRd_nwrd; //!< Rdma: current nwrd + uint16_t fRd_fu; //!< Rdma: request fu code + bool fRd_ovr; //!< Rdma: overrun condition found + Rw11RdmaDisk fRdma; //!< Rdma controller + }; + +} // end namespace Retro + +#include "Rw11CntlRHRP.ipp" + +#endif diff --git a/tools/src/librw11/Rw11CntlRHRP.ipp b/tools/src/librw11/Rw11CntlRHRP.ipp new file mode 100644 index 00000000..e38bcdc9 --- /dev/null +++ b/tools/src/librw11/Rw11CntlRHRP.ipp @@ -0,0 +1,56 @@ +// $Id: Rw11CntlRHRP.ipp 680 2015-05-14 13:29:46Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-14 680 1.0 Initial version +// 2015-03-21 659 0.1 First draft +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11CntlRHRP.ipp 680 2015-05-14 13:29:46Z mueller $ + \brief Implemenation (inline) of Rw11CntlRHRP. +*/ + + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline void Rw11CntlRHRP::SetChunkSize(size_t chunk) +{ + fRdma.SetChunkSize(chunk); + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline size_t Rw11CntlRHRP::ChunkSize() const +{ + return fRdma.ChunkSize(); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline const Rstats& Rw11CntlRHRP::RdmaStats() const +{ + return fRdma.Stats(); +} + + +} // end namespace Retro diff --git a/tools/src/librw11/Rw11CntlRK11.cpp b/tools/src/librw11/Rw11CntlRK11.cpp index 336c1f5c..ffbfcccb 100644 --- a/tools/src/librw11/Rw11CntlRK11.cpp +++ b/tools/src/librw11/Rw11CntlRK11.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11CntlRK11.cpp 647 2015-02-17 22:35:36Z mueller $ +// $Id: Rw11CntlRK11.cpp 669 2015-04-26 21:20:32Z mueller $ // // Copyright 2013-2015 by Walter F.J. Mueller // Other credits: @@ -26,7 +26,7 @@ /*! \file - \version $Id: Rw11CntlRK11.cpp 647 2015-02-17 22:35:36Z mueller $ + \version $Id: Rw11CntlRK11.cpp 669 2015-04-26 21:20:32Z mueller $ \brief Implemenation of Rw11CntlRK11. */ @@ -194,13 +194,13 @@ void Rw11CntlRK11::Start() // add device register address ibus and rbus mappings // done here because now Cntl bound to Cpu and Cntl probed - Cpu().AllAddrMapInsert(Name()+".ds", Base() + kRKDS); - Cpu().AllAddrMapInsert(Name()+".er", Base() + kRKER); - Cpu().AllAddrMapInsert(Name()+".cs", Base() + kRKCS); - Cpu().AllAddrMapInsert(Name()+".wc", Base() + kRKWC); - Cpu().AllAddrMapInsert(Name()+".ba", Base() + kRKBA); - Cpu().AllAddrMapInsert(Name()+".da", Base() + kRKDA); - Cpu().AllAddrMapInsert(Name()+".mr", Base() + kRKMR); + Cpu().AllIAddrMapInsert(Name()+".ds", Base() + kRKDS); + Cpu().AllIAddrMapInsert(Name()+".er", Base() + kRKER); + Cpu().AllIAddrMapInsert(Name()+".cs", Base() + kRKCS); + Cpu().AllIAddrMapInsert(Name()+".wc", Base() + kRKWC); + Cpu().AllIAddrMapInsert(Name()+".ba", Base() + kRKBA); + Cpu().AllIAddrMapInsert(Name()+".da", Base() + kRKDA); + Cpu().AllIAddrMapInsert(Name()+".mr", Base() + kRKMR); // setup primary info clist fPrimClist.Clear(); @@ -364,11 +364,11 @@ int Rw11CntlRK11::AttnHandler(RlinkServer::AttnArgs& args) << " da=" << RosPrintBvi(rkda,8) << " ad=" << RosPrintBvi(addr,8,18) << " fu=" << fumnemo[fu&0x7] - << " dchs=" << dr + << " pa=" << dr << "," << RosPrintf(cy,"d",3) << "," << hd << "," << RosPrintf(se,"d",2) - << " lba,nw=" << RosPrintf(lba,"d",4) + << " la,nw=" << RosPrintf(lba,"d",4) << "," << RosPrintf(nwrd,"d",5); } @@ -425,7 +425,7 @@ int Rw11CntlRK11::AttnHandler(RlinkServer::AttnArgs& args) AddErrorExit(clist, rker); } else { fRdma.QueueDiskWrite(addr, nwrd, - Rw11Cpu::kCp_ah_m_22bit|Rw11Cpu::kCp_ah_m_ubmap, + Rw11Cpu::kCPAH_M_22BIT|Rw11Cpu::kCPAH_M_UBMAP, lba, &unit); } @@ -438,7 +438,7 @@ int Rw11CntlRK11::AttnHandler(RlinkServer::AttnArgs& args) AddErrorExit(clist, rker); } else { fRdma.QueueDiskRead(addr, nwrd, - Rw11Cpu::kCp_ah_m_22bit|Rw11Cpu::kCp_ah_m_ubmap, + Rw11Cpu::kCPAH_M_22BIT|Rw11Cpu::kCPAH_M_UBMAP, lba, &unit); } @@ -451,7 +451,7 @@ int Rw11CntlRK11::AttnHandler(RlinkServer::AttnArgs& args) AddErrorExit(clist, rker); } else { fRdma.QueueDiskWriteCheck(addr, nwrd, - Rw11Cpu::kCp_ah_m_22bit|Rw11Cpu::kCp_ah_m_ubmap, + Rw11Cpu::kCPAH_M_22BIT|Rw11Cpu::kCPAH_M_UBMAP, lba, &unit); } diff --git a/tools/src/librw11/Rw11CntlRK11.hpp b/tools/src/librw11/Rw11CntlRK11.hpp index 95d91e25..10cbe122 100644 --- a/tools/src/librw11/Rw11CntlRK11.hpp +++ b/tools/src/librw11/Rw11CntlRK11.hpp @@ -1,4 +1,4 @@ -// $Id: Rw11CntlRK11.hpp 647 2015-02-17 22:35:36Z mueller $ +// $Id: Rw11CntlRK11.hpp 665 2015-04-07 07:13:49Z mueller $ // // Copyright 2013-2015 by Walter F.J. Mueller // @@ -23,7 +23,7 @@ /*! \file - \version $Id: Rw11CntlRK11.hpp 647 2015-02-17 22:35:36Z mueller $ + \version $Id: Rw11CntlRK11.hpp 665 2015-04-07 07:13:49Z mueller $ \brief Declaration of class Rw11CntlRK11. */ @@ -62,13 +62,13 @@ namespace Retro { static const uint16_t kIbaddr = 0177400; //!< RK11 default address static const int kLam = 4; //!< RK11 default lam - static const uint16_t kRKDS = 000; //!< RKDS register address offset - static const uint16_t kRKER = 002; //!< RKER register address offset - static const uint16_t kRKCS = 004; //!< RKCS register address offset - static const uint16_t kRKWC = 006; //!< RKWC register address offset - static const uint16_t kRKBA = 010; //!< RKBA register address offset - static const uint16_t kRKDA = 012; //!< RKDA register address offset - static const uint16_t kRKMR = 014; //!< RKMR register address offset + static const uint16_t kRKDS = 000; //!< RKDS reg offset + static const uint16_t kRKER = 002; //!< RKER reg offset + static const uint16_t kRKCS = 004; //!< RKCS reg offset + static const uint16_t kRKWC = 006; //!< RKWC reg offset + static const uint16_t kRKBA = 010; //!< RKBA reg offset + static const uint16_t kRKDA = 012; //!< RKDA reg offset + static const uint16_t kRKMR = 014; //!< RKMR reg offset static const uint16_t kProbeOff = kRKCS; //!< probe address offset (rkcs) static const bool kProbeInt = true; //!< probe int active diff --git a/tools/src/librw11/Rw11CntlRL11.cpp b/tools/src/librw11/Rw11CntlRL11.cpp index 4ea9f3db..22cb9461 100644 --- a/tools/src/librw11/Rw11CntlRL11.cpp +++ b/tools/src/librw11/Rw11CntlRL11.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11CntlRL11.cpp 655 2015-03-04 20:35:21Z mueller $ +// $Id: Rw11CntlRL11.cpp 669 2015-04-26 21:20:32Z mueller $ // // Copyright 2014-2015 by Walter F.J. Mueller // Other credits: @@ -23,7 +23,7 @@ /*! \file - \version $Id: Rw11CntlRL11.cpp 655 2015-03-04 20:35:21Z mueller $ + \version $Id: Rw11CntlRL11.cpp 669 2015-04-26 21:20:32Z mueller $ \brief Implemenation of Rw11CntlRL11. */ @@ -233,10 +233,10 @@ void Rw11CntlRL11::Start() // add device register address ibus and rbus mappings // done here because now Cntl bound to Cpu and Cntl probed - Cpu().AllAddrMapInsert(Name()+".cs", Base() + kRLCS); - Cpu().AllAddrMapInsert(Name()+".ba", Base() + kRLBA); - Cpu().AllAddrMapInsert(Name()+".da", Base() + kRLDA); - Cpu().AllAddrMapInsert(Name()+".mp", Base() + kRLMP); + Cpu().AllIAddrMapInsert(Name()+".cs", Base() + kRLCS); + Cpu().AllIAddrMapInsert(Name()+".ba", Base() + kRLBA); + Cpu().AllIAddrMapInsert(Name()+".da", Base() + kRLDA); + Cpu().AllIAddrMapInsert(Name()+".mp", Base() + kRLMP); // setup primary info clist fPrimClist.Clear(); @@ -269,8 +269,8 @@ void Rw11CntlRL11::UnitSetup(size_t ind) RlinkCommandList clist; // only two mayor drive states are used - // on: st=lock; ho=1; bh=1; co=0; wl=? ( file connected) - // off: st=load; ho=0; bh=1; co=1; (no file connected) + // on: st=lock; ho=1; bh=1; co=0; wl=? ( file attached) + // off: st=load; ho=0; bh=1; co=1; (no file attached) uint16_t sta = 0; if (unit.Type() == "rl02") // is it RL02 @@ -430,11 +430,11 @@ int Rw11CntlRL11::AttnHandler(RlinkServer::AttnArgs& args) << " da=" << RosPrintBvi(rlda,8) << " ad=" << RosPrintBvi(addr,8,18) << " fu=" << fumnemo[fu&0x7] - << " ds=" << ds + << " pa=" << ds << "," << RosPrintf(ca,"d",3) << "," << hs << "," << RosPrintf(sa,"d",2) - << " lba,nw=" << RosPrintf(lba,"d",5) + << " la,nw=" << RosPrintf(lba,"d",5) << ","; if (nwrd==65536) lmsg << " (0)"; else lmsg << RosPrintf(nwrd,"d",4); if (ovr) lmsg << "!"; @@ -527,14 +527,14 @@ int Rw11CntlRL11::AttnHandler(RlinkServer::AttnArgs& args) AddErrorExit(clist, kERR_M_DE); } else { fRdma.QueueDiskWrite(addr, nwrd, - Rw11Cpu::kCp_ah_m_22bit|Rw11Cpu::kCp_ah_m_ubmap, + Rw11Cpu::kCPAH_M_22BIT|Rw11Cpu::kCPAH_M_UBMAP, lba, &unit); } } else if (fu == kFUNC_WCHK) { // Write Check ------------------- fStats.Inc(kStatNFuncWchk ); fRdma.QueueDiskWriteCheck(addr, nwrd, - Rw11Cpu::kCp_ah_m_22bit|Rw11Cpu::kCp_ah_m_ubmap, + Rw11Cpu::kCPAH_M_22BIT|Rw11Cpu::kCPAH_M_UBMAP, lba, &unit); } else if (fu == kFUNC_READ || // Read or @@ -542,7 +542,7 @@ int Rw11CntlRL11::AttnHandler(RlinkServer::AttnArgs& args) fStats.Inc(fu==kFUNC_READ ? kStatNFuncRead : kStatNFuncRnhc); fRdma.QueueDiskRead(addr, nwrd, - Rw11Cpu::kCp_ah_m_22bit|Rw11Cpu::kCp_ah_m_ubmap, + Rw11Cpu::kCPAH_M_22BIT|Rw11Cpu::kCPAH_M_UBMAP, lba, &unit); } diff --git a/tools/src/librw11/Rw11CntlRL11.hpp b/tools/src/librw11/Rw11CntlRL11.hpp index 82c343dd..c779b803 100644 --- a/tools/src/librw11/Rw11CntlRL11.hpp +++ b/tools/src/librw11/Rw11CntlRL11.hpp @@ -1,4 +1,4 @@ -// $Id: Rw11CntlRL11.hpp 653 2015-03-01 12:53:01Z mueller $ +// $Id: Rw11CntlRL11.hpp 665 2015-04-07 07:13:49Z mueller $ // // Copyright 2014-2015 by Walter F.J. Mueller // @@ -20,7 +20,7 @@ /*! \file - \version $Id: Rw11CntlRL11.hpp 653 2015-03-01 12:53:01Z mueller $ + \version $Id: Rw11CntlRL11.hpp 665 2015-04-07 07:13:49Z mueller $ \brief Declaration of class Rw11CntlRL11. */ @@ -59,10 +59,10 @@ namespace Retro { static const uint16_t kIbaddr = 0174400; //!< RL11 default address static const int kLam = 5; //!< RL11 default lam - static const uint16_t kRLCS = 000; //!< RLCS register address offset - static const uint16_t kRLBA = 002; //!< RLBA register address offset - static const uint16_t kRLDA = 004; //!< RLDA register address offset - static const uint16_t kRLMP = 006; //!< RLMP register address offset + static const uint16_t kRLCS = 000; //!< RLCS reg offset + static const uint16_t kRLBA = 002; //!< RLBA reg offset + static const uint16_t kRLDA = 004; //!< RLDA reg offset + static const uint16_t kRLMP = 006; //!< RLMP reg offset static const uint16_t kProbeOff = kRLCS; //!< probe address offset (rlcs) static const bool kProbeInt = true; //!< probe int active diff --git a/tools/src/librw11/Rw11Cpu.cpp b/tools/src/librw11/Rw11Cpu.cpp index fce9ab2f..5c86ac94 100644 --- a/tools/src/librw11/Rw11Cpu.cpp +++ b/tools/src/librw11/Rw11Cpu.cpp @@ -1,6 +1,6 @@ -// $Id: Rw11Cpu.cpp 632 2015-01-11 12:30:03Z mueller $ +// $Id: Rw11Cpu.cpp 675 2015-05-08 21:05:08Z mueller $ // -// Copyright 2013-2014 by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,10 @@ // // Revision History: // Date Rev Version Comment +// 2015-05-08 675 1.2.3 w11a start/stop/suspend overhaul +// 2015-04-25 668 1.2.2 add AddRbibr(), AddWbibr() +// 2015-04-03 661 1.2.1 add kStat_M_* defs +// 2015-03-21 659 1.2 add RAddrMap // 2015-01-01 626 1.1 Adopt for rlink v4 and 4k ibus window // 2014-12-21 617 1.0.3 use kStat_M_RbTout for rbus timeout // 2014-08-02 576 1.0.2 adopt rename of LastExpect->SetLastExpect @@ -23,7 +27,7 @@ /*! \file - \version $Id: Rw11Cpu.cpp 632 2015-01-11 12:30:03Z mueller $ + \version $Id: Rw11Cpu.cpp 675 2015-05-08 21:05:08Z mueller $ \brief Implemenation of Rw11Cpu. */ #include @@ -58,52 +62,60 @@ namespace Retro { //------------------------------------------+----------------------------------- // constants definitions -const uint16_t Rw11Cpu::kCp_addr_conf; -const uint16_t Rw11Cpu::kCp_addr_cntl; -const uint16_t Rw11Cpu::kCp_addr_stat; -const uint16_t Rw11Cpu::kCp_addr_psw; -const uint16_t Rw11Cpu::kCp_addr_al; -const uint16_t Rw11Cpu::kCp_addr_ah; -const uint16_t Rw11Cpu::kCp_addr_mem; -const uint16_t Rw11Cpu::kCp_addr_memi; -const uint16_t Rw11Cpu::kCp_addr_r0; -const uint16_t Rw11Cpu::kCp_addr_pc; -const uint16_t Rw11Cpu::kCp_addr_membe; +const uint16_t Rw11Cpu::kCPCONF; +const uint16_t Rw11Cpu::kCPCNTL; +const uint16_t Rw11Cpu::kCPSTAT; +const uint16_t Rw11Cpu::kCPPSW; +const uint16_t Rw11Cpu::kCPAL; +const uint16_t Rw11Cpu::kCPAH; +const uint16_t Rw11Cpu::kCPMEM; +const uint16_t Rw11Cpu::kCPMEMI; +const uint16_t Rw11Cpu::kCPR0; +const uint16_t Rw11Cpu::kCPPC; +const uint16_t Rw11Cpu::kCPMEMBE; -const uint16_t Rw11Cpu::kCp_func_noop; -const uint16_t Rw11Cpu::kCp_func_start; -const uint16_t Rw11Cpu::kCp_func_stop; -const uint16_t Rw11Cpu::kCp_func_cont; -const uint16_t Rw11Cpu::kCp_func_step; -const uint16_t Rw11Cpu::kCp_func_reset; +const uint16_t Rw11Cpu::kCPFUNC_NOOP; +const uint16_t Rw11Cpu::kCPFUNC_START; +const uint16_t Rw11Cpu::kCPFUNC_STOP; +const uint16_t Rw11Cpu::kCPFUNC_STEP; +const uint16_t Rw11Cpu::kCPFUNC_CRESET; +const uint16_t Rw11Cpu::kCPFUNC_BRESET; +const uint16_t Rw11Cpu::kCPFUNC_SUSPEND; +const uint16_t Rw11Cpu::kCPFUNC_RESUME; -const uint16_t Rw11Cpu::kCp_stat_m_cpurust; -const uint16_t Rw11Cpu::kCp_stat_v_cpurust; -const uint16_t Rw11Cpu::kCp_stat_b_cpurust; -const uint16_t Rw11Cpu::kCp_stat_m_cpuhalt; -const uint16_t Rw11Cpu::kCp_stat_m_cpugo; -const uint16_t Rw11Cpu::kCp_stat_m_cmdmerr; -const uint16_t Rw11Cpu::kCp_stat_m_cmderr; +const uint16_t Rw11Cpu::kCPSTAT_M_SuspExt; +const uint16_t Rw11Cpu::kCPSTAT_M_SuspInt; +const uint16_t Rw11Cpu::kCPSTAT_M_CpuRust; +const uint16_t Rw11Cpu::kCPSTAT_V_CpuRust; +const uint16_t Rw11Cpu::kCPSTAT_B_CpuRust; +const uint16_t Rw11Cpu::kCPSTAT_M_CpuSusp; +const uint16_t Rw11Cpu::kCPSTAT_M_CpuGo; +const uint16_t Rw11Cpu::kCPSTAT_M_CmdMErr; +const uint16_t Rw11Cpu::kCPSTAT_M_CmdErr; -const uint16_t Rw11Cpu::kCp_cpurust_init; -const uint16_t Rw11Cpu::kCp_cpurust_halt; -const uint16_t Rw11Cpu::kCp_cpurust_reset; -const uint16_t Rw11Cpu::kCp_cpurust_stop; -const uint16_t Rw11Cpu::kCp_cpurust_step; -const uint16_t Rw11Cpu::kCp_cpurust_susp; -const uint16_t Rw11Cpu::kCp_cpurust_runs; -const uint16_t Rw11Cpu::kCp_cpurust_vecfet; -const uint16_t Rw11Cpu::kCp_cpurust_recrsv; -const uint16_t Rw11Cpu::kCp_cpurust_sfail; -const uint16_t Rw11Cpu::kCp_cpurust_vfail; +const uint16_t Rw11Cpu::kCPURUST_INIT; +const uint16_t Rw11Cpu::kCPURUST_HALT; +const uint16_t Rw11Cpu::kCPURUST_RESET; +const uint16_t Rw11Cpu::kCPURUST_STOP; +const uint16_t Rw11Cpu::kCPURUST_STEP; +const uint16_t Rw11Cpu::kCPURUST_SUSP; +const uint16_t Rw11Cpu::kCPURUST_RUNS; +const uint16_t Rw11Cpu::kCPURUST_VECFET; +const uint16_t Rw11Cpu::kCPURUST_RECRSV; +const uint16_t Rw11Cpu::kCPURUST_SFAIL; +const uint16_t Rw11Cpu::kCPURUST_VFAIL; -const uint16_t Rw11Cpu::kCp_ah_m_addr; -const uint16_t Rw11Cpu::kCp_ah_m_22bit; -const uint16_t Rw11Cpu::kCp_ah_m_ubmap; +const uint16_t Rw11Cpu::kCPAH_M_ADDR; +const uint16_t Rw11Cpu::kCPAH_M_22BIT; +const uint16_t Rw11Cpu::kCPAH_M_UBMAP; -const uint16_t Rw11Cpu::kCp_membe_m_stick; -const uint16_t Rw11Cpu::kCp_membe_m_be; - +const uint16_t Rw11Cpu::kCPMEMBE_M_STICK; +const uint16_t Rw11Cpu::kCPMEMBE_M_BE; + +const uint8_t Rw11Cpu::kStat_M_CmdErr; +const uint8_t Rw11Cpu::kStat_M_CmdMErr; +const uint8_t Rw11Cpu::kStat_M_CpuHalt; +const uint8_t Rw11Cpu::kStat_M_CpuGo; //------------------------------------------+----------------------------------- //! Constructor @@ -120,6 +132,7 @@ Rw11Cpu::Rw11Cpu(const std::string& type) fCpuGoCond(), fCntlMap(), fIAddrMap(), + fRAddrMap(), fStats() {} @@ -136,70 +149,66 @@ void Rw11Cpu::Setup(Rw11* pw11) { fpW11 = pw11; // add control port address rbus mappings - // name base: 'cn.', where n is cpu index - string cbase = "c"; - cbase += '0'+Index(); - cbase += '.'; - Connect().AddrMapInsert(cbase+"conf", Base()+kCp_addr_conf); - Connect().AddrMapInsert(cbase+"cntl", Base()+kCp_addr_cntl); - Connect().AddrMapInsert(cbase+"stat", Base()+kCp_addr_stat); - Connect().AddrMapInsert(cbase+"psw" , Base()+kCp_addr_psw); - Connect().AddrMapInsert(cbase+"al" , Base()+kCp_addr_al); - Connect().AddrMapInsert(cbase+"ah" , Base()+kCp_addr_ah); - Connect().AddrMapInsert(cbase+"mem" , Base()+kCp_addr_mem); - Connect().AddrMapInsert(cbase+"memi", Base()+kCp_addr_memi); - Connect().AddrMapInsert(cbase+"r0" , Base()+kCp_addr_r0); - Connect().AddrMapInsert(cbase+"r1" , Base()+kCp_addr_r0+1); - Connect().AddrMapInsert(cbase+"r2" , Base()+kCp_addr_r0+2); - Connect().AddrMapInsert(cbase+"r3" , Base()+kCp_addr_r0+3); - Connect().AddrMapInsert(cbase+"r4" , Base()+kCp_addr_r0+4); - Connect().AddrMapInsert(cbase+"r5" , Base()+kCp_addr_r0+5); - Connect().AddrMapInsert(cbase+"sp" , Base()+kCp_addr_r0+6); - Connect().AddrMapInsert(cbase+"pc" , Base()+kCp_addr_r0+7); - Connect().AddrMapInsert(cbase+"membe",Base()+kCp_addr_membe); + AllRAddrMapInsert("conf" , Base()+kCPCONF); + AllRAddrMapInsert("cntl" , Base()+kCPCNTL); + AllRAddrMapInsert("stat" , Base()+kCPSTAT); + AllRAddrMapInsert("psw" , Base()+kCPPSW); + AllRAddrMapInsert("al" , Base()+kCPAL); + AllRAddrMapInsert("ah" , Base()+kCPAH); + AllRAddrMapInsert("mem" , Base()+kCPMEM); + AllRAddrMapInsert("memi" , Base()+kCPMEMI); + AllRAddrMapInsert("r0" , Base()+kCPR0); + AllRAddrMapInsert("r1" , Base()+kCPR0+1); + AllRAddrMapInsert("r2" , Base()+kCPR0+2); + AllRAddrMapInsert("r3" , Base()+kCPR0+3); + AllRAddrMapInsert("r4" , Base()+kCPR0+4); + AllRAddrMapInsert("r5" , Base()+kCPR0+5); + AllRAddrMapInsert("sp" , Base()+kCPR0+6); + AllRAddrMapInsert("pc" , Base()+kCPR0+7); + AllRAddrMapInsert("membe",Base()+kCPMEMBE); // add cpu register address ibus and rbus mappings - AllAddrMapInsert("psw" , 0177776); - AllAddrMapInsert("stklim" , 0177774); - AllAddrMapInsert("pirq" , 0177772); - AllAddrMapInsert("mbrk" , 0177770); - AllAddrMapInsert("cpuerr" , 0177766); - AllAddrMapInsert("sysid" , 0177764); - AllAddrMapInsert("hisize" , 0177762); - AllAddrMapInsert("losize" , 0177760); + AllIAddrMapInsert("psw" , 0177776); + AllIAddrMapInsert("stklim" , 0177774); + AllIAddrMapInsert("pirq" , 0177772); + AllIAddrMapInsert("mbrk" , 0177770); + AllIAddrMapInsert("cpuerr" , 0177766); + AllIAddrMapInsert("sysid" , 0177764); + AllIAddrMapInsert("hisize" , 0177762); + AllIAddrMapInsert("losize" , 0177760); - AllAddrMapInsert("hm" , 0177752); - AllAddrMapInsert("maint" , 0177750); - AllAddrMapInsert("cntrl" , 0177746); - AllAddrMapInsert("syserr" , 0177744); - AllAddrMapInsert("hiaddr" , 0177742); - AllAddrMapInsert("loaddr" , 0177740); + AllIAddrMapInsert("hm" , 0177752); + AllIAddrMapInsert("maint" , 0177750); + AllIAddrMapInsert("cntrl" , 0177746); + AllIAddrMapInsert("syserr" , 0177744); + AllIAddrMapInsert("hiaddr" , 0177742); + AllIAddrMapInsert("loaddr" , 0177740); - AllAddrMapInsert("ssr2" , 0177576); - AllAddrMapInsert("ssr1" , 0177574); - AllAddrMapInsert("ssr0" , 0177572); + AllIAddrMapInsert("ssr2" , 0177576); + AllIAddrMapInsert("ssr1" , 0177574); + AllIAddrMapInsert("ssr0" , 0177572); - AllAddrMapInsert("sdreg" , 0177570); + AllIAddrMapInsert("sdreg" , 0177570); - AllAddrMapInsert("ssr3" , 0172516); + AllIAddrMapInsert("ssr3" , 0172516); // add mmu segment register files string sdr = "sdr"; string sar = "sar"; for (char i=0; i<8; i++) { char ichar = '0'+i; - AllAddrMapInsert(sdr+"ki."+ichar, 0172300+2*i); - AllAddrMapInsert(sdr+"kd."+ichar, 0172320+2*i); - AllAddrMapInsert(sar+"ki."+ichar, 0172340+2*i); - AllAddrMapInsert(sar+"kd."+ichar, 0172360+2*i); - AllAddrMapInsert(sdr+"si."+ichar, 0172200+2*i); - AllAddrMapInsert(sdr+"sd."+ichar, 0172220+2*i); - AllAddrMapInsert(sar+"si."+ichar, 0172240+2*i); - AllAddrMapInsert(sar+"sd."+ichar, 0172260+2*i); - AllAddrMapInsert(sdr+"ui."+ichar, 0177600+2*i); - AllAddrMapInsert(sdr+"ud."+ichar, 0177620+2*i); - AllAddrMapInsert(sar+"ui."+ichar, 0177640+2*i); - AllAddrMapInsert(sar+"ud."+ichar, 0177660+2*i); + AllIAddrMapInsert(sdr+"ki."+ichar, 0172300+2*i); + AllIAddrMapInsert(sdr+"kd."+ichar, 0172320+2*i); + AllIAddrMapInsert(sar+"ki."+ichar, 0172340+2*i); + AllIAddrMapInsert(sar+"kd."+ichar, 0172360+2*i); + AllIAddrMapInsert(sdr+"si."+ichar, 0172200+2*i); + AllIAddrMapInsert(sdr+"sd."+ichar, 0172220+2*i); + AllIAddrMapInsert(sar+"si."+ichar, 0172240+2*i); + AllIAddrMapInsert(sar+"sd."+ichar, 0172260+2*i); + AllIAddrMapInsert(sdr+"ui."+ichar, 0177600+2*i); + AllIAddrMapInsert(sdr+"ud."+ichar, 0177620+2*i); + AllIAddrMapInsert(sar+"ui."+ichar, 0177640+2*i); + AllIAddrMapInsert(sar+"ud."+ichar, 0177660+2*i); } return; @@ -289,9 +298,9 @@ std::string Rw11Cpu::NextCntlName(const std::string& base) const int Rw11Cpu::AddMembe(RlinkCommandList& clist, uint16_t be, bool stick) { - uint16_t data = be & kCp_membe_m_be; - if (stick) data |= kCp_membe_m_stick; - return clist.AddWreg(fBase+kCp_addr_membe, data); + uint16_t data = be & kCPMEMBE_M_BE; + if (stick) data |= kCPMEMBE_M_STICK; + return clist.AddWreg(fBase+kCPMEMBE, data); } //------------------------------------------+----------------------------------- @@ -316,16 +325,37 @@ int Rw11Cpu::AddWibr(RlinkCommandList& clist, uint16_t ibaddr, uint16_t data) return clist.AddWreg(IbusRemoteAddr(ibaddr), data); } +//------------------------------------------+----------------------------------- +//! FIXME_docs +int Rw11Cpu::AddRbibr(RlinkCommandList& clist, uint16_t ibaddr, size_t size) +{ + if ((ibaddr & 0160001) != 0160000) + throw Rexception("Rw11Cpu::AddRbibr", "ibaddr out of IO page or odd"); + + return clist.AddRblk(IbusRemoteAddr(ibaddr), size); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs +int Rw11Cpu::AddWbibr(RlinkCommandList& clist, uint16_t ibaddr, + std::vector block) +{ + if ((ibaddr & 0160001) != 0160000) + throw Rexception("Rw11Cpu::AddWbibr", "ibaddr out of IO page or odd"); + + return clist.AddWblk(IbusRemoteAddr(ibaddr), block); +} + //------------------------------------------+----------------------------------- //! FIXME_docs int Rw11Cpu::AddLalh(RlinkCommandList& clist, uint32_t addr, uint16_t mode) { uint16_t al = uint16_t(addr); - uint16_t ah = uint16_t(addr>>16) & kCp_ah_m_addr; - ah |= mode & (kCp_ah_m_22bit|kCp_ah_m_ubmap); - int ind = clist.AddWreg(fBase+kCp_addr_al, al); - clist.AddWreg(fBase+kCp_addr_ah, ah); + uint16_t ah = uint16_t(addr>>16) & kCPAH_M_ADDR; + ah |= mode & (kCPAH_M_22BIT|kCPAH_M_UBMAP); + int ind = clist.AddWreg(fBase+kCPAL, al); + clist.AddWreg(fBase+kCPAH, ah); return ind; } @@ -343,7 +373,7 @@ int Rw11Cpu::AddRMem(RlinkCommandList& clist, uint32_t addr, uint16_t* buf, int ind = AddLalh(clist, addr, mode); while (size > 0) { size_t bsize = (size>blkmax) ? blkmax : size; - clist.AddRblk(fBase+kCp_addr_memi, buf, bsize); + clist.AddRblk(fBase+kCPMEMI, buf, bsize); buf += bsize; size -= bsize; } @@ -365,7 +395,7 @@ int Rw11Cpu::AddWMem(RlinkCommandList& clist, uint32_t addr, int ind = AddLalh(clist, addr, mode); while (size > 0) { size_t bsize = (size>blkmax) ? blkmax : size; - clist.AddWblk(fBase+kCp_addr_memi, buf, bsize); + clist.AddWblk(fBase+kCPMEMI, buf, bsize); buf += bsize; size -= bsize; } @@ -384,8 +414,8 @@ bool Rw11Cpu::MemRead(uint16_t addr, std::vector& data, while (nword>ndone) { size_t nblk = min(blkmax, nword-ndone); RlinkCommandList clist; - clist.AddWreg(fBase+kCp_addr_al, addr+2*ndone); - clist.AddRblk(fBase+kCp_addr_memi, data.data()+ndone, nblk); + clist.AddWreg(fBase+kCPAL, addr+2*ndone); + clist.AddRblk(fBase+kCPMEMI, data.data()+ndone, nblk); if (!Server().Exec(clist, emsg)) return false; ndone += nblk; } @@ -404,8 +434,8 @@ bool Rw11Cpu::MemWrite(uint16_t addr, const std::vector& data, while (nword>ndone) { size_t nblk = min(blkmax, nword-ndone); RlinkCommandList clist; - clist.AddWreg(fBase+kCp_addr_al, addr+2*ndone); - clist.AddWblk(fBase+kCp_addr_memi, data.data()+ndone, nblk); + clist.AddWreg(fBase+kCPAL, addr+2*ndone); + clist.AddWblk(fBase+kCPMEMI, data.data()+ndone, nblk); if (!Server().Exec(clist, emsg)) return false; ndone += nblk; } @@ -426,13 +456,13 @@ bool Rw11Cpu::ProbeCntl(Rw11Probe& dsc) int iib = -1; int irb = -1; if (dsc.fProbeInt) { - clist.AddWreg(fBase+kCp_addr_al, dsc.fAddr); - iib = clist.AddRreg(fBase+kCp_addr_mem); - clist.SetLastExpect(new RlinkCommandExpect(0,0xff)); // disable stat check + clist.AddWreg(fBase+kCPAL, dsc.fAddr); + iib = clist.AddRreg(fBase+kCPMEM); + clist.SetLastExpectStatus(0,0); // disable stat check } if (dsc.fProbeRem) { irb = AddRibr(clist, dsc.fAddr); - clist.SetLastExpect(new RlinkCommandExpect(0,0xff)); // disable stat check + clist.SetLastExpectStatus(0,0); // disable stat check } Server().Exec(clist); @@ -678,8 +708,10 @@ bool Rw11Cpu::Boot(const std::string& uname, RerrMsg& emsg) if (!MemWrite(aload, code, emsg)) return false; RlinkCommandList clist; - clist.AddWreg(fBase+kCp_addr_pc, astart); - clist.AddWreg(fBase+kCp_addr_cntl, kCp_func_start); + clist.AddWreg(fBase+kCPCNTL, kCPFUNC_STOP); // stop, just in case + clist.AddWreg(fBase+kCPCNTL, kCPFUNC_CRESET); // init cpu and bus + clist.AddWreg(fBase+kCPPC, astart); // load PC + clist.AddWreg(fBase+kCPCNTL, kCPFUNC_START); // and start SetCpuGoUp(); if (!Server().Exec(clist, emsg)) return false; @@ -703,7 +735,7 @@ void Rw11Cpu::SetCpuGoUp() void Rw11Cpu::SetCpuGoDown(uint16_t stat) { - if ((stat & kCp_stat_m_cpugo) == 0) { + if ((stat & kCPSTAT_M_CpuGo) == 0) { boost::lock_guard lock(fCpuGoMutex); fCpuGo = false; fCpuStat = stat; @@ -732,14 +764,36 @@ double Rw11Cpu::WaitCpuGoDown(double tout) //------------------------------------------+----------------------------------- //! FIXME_docs -void Rw11Cpu::AllAddrMapInsert(const std::string& name, uint16_t ibaddr) +void Rw11Cpu::AllIAddrMapInsert(const std::string& name, uint16_t ibaddr) { - string rbname = "i"; - rbname += '0'+Index(); - rbname += '.'; - rbname += name; - Connect().AddrMapInsert(rbname, IbusRemoteAddr(ibaddr)); IAddrMapInsert(name, ibaddr); + uint16_t rbaddr = IbusRemoteAddr(ibaddr); + RAddrMapInsert(name, rbaddr); + + // add ix. to name in common Connect AddrMap to keep name unique + string cname = "i"; + cname += '0'+Index(); + cname += '.'; + cname += name; + Connect().AddrMapInsert(cname, rbaddr); + + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11Cpu::AllRAddrMapInsert(const std::string& name, uint16_t rbaddr) +{ + RAddrMapInsert(name, rbaddr); + + // add cx. to name in common Connect AddrMap to keep name unique + string cname = "c"; + cname += '0'+Index(); + cname += '.'; + cname += name; + Connect().AddrMapInsert(cname, rbaddr); + return; } @@ -749,7 +803,7 @@ void Rw11Cpu::AllAddrMapInsert(const std::string& name, uint16_t ibaddr) void Rw11Cpu::W11AttnHandler() { RlinkCommandList clist; - clist.AddRreg(fBase+kCp_addr_stat); + clist.AddRreg(fBase+kCPSTAT); Server().Exec(clist); SetCpuGoDown(clist[0].Data()); return; @@ -776,6 +830,7 @@ void Rw11Cpu::Dump(std::ostream& os, int ind, const char* text) const << " : " << it->second << endl; } fIAddrMap.Dump(os, ind+2, "fIAddrMap: "); + fRAddrMap.Dump(os, ind+2, "fRAddrMap: "); fStats.Dump(os, ind+2, "fStats: "); return; } diff --git a/tools/src/librw11/Rw11Cpu.hpp b/tools/src/librw11/Rw11Cpu.hpp index c09ae926..37719c89 100644 --- a/tools/src/librw11/Rw11Cpu.hpp +++ b/tools/src/librw11/Rw11Cpu.hpp @@ -1,4 +1,4 @@ -// $Id: Rw11Cpu.hpp 626 2015-01-03 14:41:37Z mueller $ +// $Id: Rw11Cpu.hpp 675 2015-05-08 21:05:08Z mueller $ // // Copyright 2013-2015 by Walter F.J. Mueller // @@ -13,6 +13,10 @@ // // Revision History: // Date Rev Version Comment +// 2015-05-08 675 1.2.3 w11a start/stop/suspend overhaul +// 2015-04-25 668 1.2.2 add AddRbibr(), AddWbibr() +// 2015-04-03 661 1.2.1 add kStat_M_* defs +// 2015-03-21 659 1.2 add RAddrMap; add AllRAddrMapInsert(); // 2015-01-01 626 1.1 Adopt for rlink v4 and 4k ibus window; add IAddrMap // 2013-04-14 506 1.0.1 add AddLalh(),AddRMem(),AddWMem() // 2013-04-12 504 1.0 Initial version @@ -22,7 +26,7 @@ /*! \file - \version $Id: Rw11Cpu.hpp 626 2015-01-03 14:41:37Z mueller $ + \version $Id: Rw11Cpu.hpp 675 2015-05-08 21:05:08Z mueller $ \brief Declaration of class Rw11Cpu. */ @@ -88,15 +92,20 @@ namespace Retro { int AddWibr(RlinkCommandList& clist, uint16_t ibaddr, uint16_t data); + int AddRbibr(RlinkCommandList& clist, uint16_t ibaddr, + size_t size); + int AddWbibr(RlinkCommandList& clist, uint16_t ibaddr, + std::vector block); + int AddLalh(RlinkCommandList& clist, uint32_t addr, - uint16_t mode=kCp_ah_m_22bit); + uint16_t mode=kCPAH_M_22BIT); int AddRMem(RlinkCommandList& clist, uint32_t addr, uint16_t* buf, size_t size, - uint16_t mode=kCp_ah_m_22bit, + uint16_t mode=kCPAH_M_22BIT, bool singleblk=false); int AddWMem(RlinkCommandList& clist, uint32_t addr, const uint16_t* buf, size_t size, - uint16_t mode=kCp_ah_m_22bit, + uint16_t mode=kCPAH_M_22BIT, bool singleblk=false); bool MemRead(uint16_t addr, std::vector& data, @@ -117,7 +126,8 @@ namespace Retro { uint16_t CpuStat() const; uint16_t IbusRemoteAddr(uint16_t ibaddr) const; - void AllAddrMapInsert(const std::string& name, uint16_t ibaddr); + void AllIAddrMapInsert(const std::string& name, uint16_t ibaddr); + void AllRAddrMapInsert(const std::string& name, uint16_t rbaddr); bool IAddrMapInsert(const std::string& name, uint16_t ibaddr); bool IAddrMapErase(const std::string& name); @@ -125,57 +135,73 @@ namespace Retro { void IAddrMapClear(); const RlinkAddrMap& IAddrMap() const; + bool RAddrMapInsert(const std::string& name, uint16_t rbaddr); + bool RAddrMapErase(const std::string& name); + bool RAddrMapErase(uint16_t rbaddr); + void RAddrMapClear(); + const RlinkAddrMap& RAddrMap() const; + void W11AttnHandler(); const Rstats& Stats() const; virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; // some constants (also defined in cpp) - static const uint16_t kCp_addr_conf = 0x0000; //!< - static const uint16_t kCp_addr_cntl = 0x0001; //!< - static const uint16_t kCp_addr_stat = 0x0002; //!< - static const uint16_t kCp_addr_psw = 0x0003; //!< - static const uint16_t kCp_addr_al = 0x0004; //!< - static const uint16_t kCp_addr_ah = 0x0005; //!< - static const uint16_t kCp_addr_mem = 0x0006; //!< - static const uint16_t kCp_addr_memi = 0x0007; //!< - static const uint16_t kCp_addr_r0 = 0x0008; //!< - static const uint16_t kCp_addr_pc = 0x000f; //!< - static const uint16_t kCp_addr_membe = 0x0010; //!< + static const uint16_t kCPCONF = 0x0000; //!< CPCONF reg offset + static const uint16_t kCPCNTL = 0x0001; //!< CPADDR reg offset + static const uint16_t kCPSTAT = 0x0002; //!< CPSTAT reg offset + static const uint16_t kCPPSW = 0x0003; //!< CPPSW reg offset + static const uint16_t kCPAL = 0x0004; //!< CPAL reg offset + static const uint16_t kCPAH = 0x0005; //!< CPAH reg offset + static const uint16_t kCPMEM = 0x0006; //!< CPMEM reg offset + static const uint16_t kCPMEMI = 0x0007; //!< CPMEMI reg offset + static const uint16_t kCPR0 = 0x0008; //!< CPR0 reg offset + static const uint16_t kCPPC = 0x000f; //!< CPPC reg offset + static const uint16_t kCPMEMBE = 0x0010; //!< CPMEMBE reg offset - static const uint16_t kCp_func_noop = 0x0000; //!< - static const uint16_t kCp_func_start = 0x0001; //!< - static const uint16_t kCp_func_stop = 0x0002; //!< - static const uint16_t kCp_func_cont = 0x0003; //!< - static const uint16_t kCp_func_step = 0x0004; //!< - static const uint16_t kCp_func_reset = 0x000f; //!< + static const uint16_t kCPFUNC_NOOP = 0x0000; //!< + static const uint16_t kCPFUNC_START = 0x0001; //!< + static const uint16_t kCPFUNC_STOP = 0x0002; //!< + static const uint16_t kCPFUNC_STEP = 0x0003; //!< + static const uint16_t kCPFUNC_CRESET = 0x0004; //!< + static const uint16_t kCPFUNC_BRESET = 0x0005; //!< + static const uint16_t kCPFUNC_SUSPEND = 0x0006; //!< + static const uint16_t kCPFUNC_RESUME = 0x0007; //!< - static const uint16_t kCp_stat_m_cpurust = 0x00f0; //!< - static const uint16_t kCp_stat_v_cpurust = 4; //!< - static const uint16_t kCp_stat_b_cpurust = 0x000f; //!< - static const uint16_t kCp_stat_m_cpuhalt = kWBit03; //!< - static const uint16_t kCp_stat_m_cpugo = kWBit02; //!< - static const uint16_t kCp_stat_m_cmdmerr = kWBit01; //!< - static const uint16_t kCp_stat_m_cmderr = kWBit00; //!< + static const uint16_t kCPSTAT_M_SuspExt = kWBit09; //!< + static const uint16_t kCPSTAT_M_SuspInt = kWBit08; //!< + static const uint16_t kCPSTAT_M_CpuRust = 0x00f0; //!< + static const uint16_t kCPSTAT_V_CpuRust = 4; //!< + static const uint16_t kCPSTAT_B_CpuRust = 0x000f; //!< + static const uint16_t kCPSTAT_M_CpuSusp = kWBit03; //!< + static const uint16_t kCPSTAT_M_CpuGo = kWBit02; //!< + static const uint16_t kCPSTAT_M_CmdMErr = kWBit01; //!< + static const uint16_t kCPSTAT_M_CmdErr = kWBit00; //!< - static const uint16_t kCp_cpurust_init = 0x0; //!< cpu in init state - static const uint16_t kCp_cpurust_halt = 0x1; //!< cpu executed HALT - static const uint16_t kCp_cpurust_reset = 0x2; //!< cpu was reset - static const uint16_t kCp_cpurust_stop = 0x3; //!< cpu was stopped - static const uint16_t kCp_cpurust_step = 0x4; //!< cpu was stepped - static const uint16_t kCp_cpurust_susp = 0x5; //!< cpu was suspended - static const uint16_t kCp_cpurust_runs = 0x7; //!< cpu running - static const uint16_t kCp_cpurust_vecfet = 0x8; //!< vector fetch halt - static const uint16_t kCp_cpurust_recrsv = 0x9; //!< rec red-stack halt - static const uint16_t kCp_cpurust_sfail = 0xa; //!< sequencer failure - static const uint16_t kCp_cpurust_vfail = 0xb; //!< vmbox failure + static const uint16_t kCPURUST_INIT = 0x0; //!< cpu in init state + static const uint16_t kCPURUST_HALT = 0x1; //!< cpu executed HALT + static const uint16_t kCPURUST_RESET = 0x2; //!< cpu was reset + static const uint16_t kCPURUST_STOP = 0x3; //!< cpu was stopped + static const uint16_t kCPURUST_STEP = 0x4; //!< cpu was stepped + static const uint16_t kCPURUST_SUSP = 0x5; //!< cpu was suspended + static const uint16_t kCPURUST_RUNS = 0x7; //!< cpu running + static const uint16_t kCPURUST_VECFET = 0x8; //!< vector fetch halt + static const uint16_t kCPURUST_RECRSV = 0x9; //!< rec red-stack halt + static const uint16_t kCPURUST_SFAIL = 0xa; //!< sequencer failure + static const uint16_t kCPURUST_VFAIL = 0xb; //!< vmbox failure - static const uint16_t kCp_ah_m_addr = 0x003f; //!< - static const uint16_t kCp_ah_m_22bit = kWBit06; //!< - static const uint16_t kCp_ah_m_ubmap = kWBit07; //!< + static const uint16_t kCPAH_M_ADDR = 0x003f; //!< + static const uint16_t kCPAH_M_22BIT = kWBit06; //!< + static const uint16_t kCPAH_M_UBMAP = kWBit07; //!< - static const uint16_t kCp_membe_m_stick = kWBit02; //!< - static const uint16_t kCp_membe_m_be = 0x0003; //!< + static const uint16_t kCPMEMBE_M_STICK = kWBit02; //!< + static const uint16_t kCPMEMBE_M_BE = 0x0003; //!< + + // defs for the four status bits defined by w11 rbus iface + static const uint8_t kStat_M_CmdErr = kBBit07; //!< stat: cmderr flag + static const uint8_t kStat_M_CmdMErr = kBBit06; //!< stat: cmdmerr flag + static const uint8_t kStat_M_CpuHalt = kBBit05; //!< stat: cpuhalt flag + static const uint8_t kStat_M_CpuGo = kBBit04; //!< stat: cpugo flag private: Rw11Cpu() {} //!< default ctor blocker @@ -192,6 +218,7 @@ namespace Retro { boost::condition_variable fCpuGoCond; cmap_t fCntlMap; //!< name->cntl map RlinkAddrMap fIAddrMap; //!< ibus name<->address mapping + RlinkAddrMap fRAddrMap; //!< rbus name<->address mapping Rstats fStats; //!< statistics }; diff --git a/tools/src/librw11/Rw11Cpu.ipp b/tools/src/librw11/Rw11Cpu.ipp index 54edba5e..235c45f6 100644 --- a/tools/src/librw11/Rw11Cpu.ipp +++ b/tools/src/librw11/Rw11Cpu.ipp @@ -1,6 +1,6 @@ -// $Id: Rw11Cpu.ipp 621 2014-12-26 21:20:05Z mueller $ +// $Id: Rw11Cpu.ipp 659 2015-03-22 23:15:51Z mueller $ // -// Copyright 2013-2014 by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-03-21 659 1.2 add RAddrMap // 2014-12-25 621 1.1 Adopt for 4k word ibus window; add IAddrMap // 2013-04-12 504 1.0 Initial version // 2013-01-27 478 0.1 First draft @@ -20,7 +21,7 @@ /*! \file - \version $Id: Rw11Cpu.ipp 621 2014-12-26 21:20:05Z mueller $ + \version $Id: Rw11Cpu.ipp 659 2015-03-22 23:15:51Z mueller $ \brief Implemenation (inline) of Rw11Cpu. */ @@ -158,6 +159,46 @@ inline const RlinkAddrMap& Rw11Cpu::IAddrMap() const //------------------------------------------+----------------------------------- //! FIXME_docs +inline bool Rw11Cpu::RAddrMapInsert(const std::string& name, uint16_t ibaddr) +{ + return fRAddrMap.Insert(name, ibaddr); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline bool Rw11Cpu::RAddrMapErase(const std::string& name) +{ + return fRAddrMap.Erase(name); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline bool Rw11Cpu::RAddrMapErase(uint16_t ibaddr) +{ + return fRAddrMap.Erase(ibaddr); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline void Rw11Cpu::RAddrMapClear() +{ + return fRAddrMap.Clear(); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline const RlinkAddrMap& Rw11Cpu::RAddrMap() const +{ + return fRAddrMap; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + inline const Rstats& Rw11Cpu::Stats() const { return fStats; diff --git a/tools/src/librw11/Rw11Unit.cpp b/tools/src/librw11/Rw11Unit.cpp index bc473c75..6e71aa84 100644 --- a/tools/src/librw11/Rw11Unit.cpp +++ b/tools/src/librw11/Rw11Unit.cpp @@ -1,6 +1,6 @@ -// $Id: Rw11Unit.cpp 515 2013-05-04 17:28:59Z mueller $ +// $Id: Rw11Unit.cpp 680 2015-05-14 13:29:46Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-05-13 680 1.1.1 add Enabled() // 2013-05-03 515 1.1 use AttachDone(),DetachCleanup(),DetachDone() // 2013-03-06 495 1.0 Initial version // 2013-02-13 488 0.1 First draft @@ -20,7 +21,7 @@ /*! \file - \version $Id: Rw11Unit.cpp 515 2013-05-04 17:28:59Z mueller $ + \version $Id: Rw11Unit.cpp 680 2015-05-14 13:29:46Z mueller $ \brief Implemenation of Rw11Unit. */ @@ -57,6 +58,14 @@ Rw11Unit::~Rw11Unit() //------------------------------------------+----------------------------------- //! FIXME_docs +bool Rw11Unit::Enabled() const +{ + return true; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + bool Rw11Unit::Attach(const std::string& url, RerrMsg& emsg) { emsg.Init("Rw11Unit::Attach","attach not available for this device type"); diff --git a/tools/src/librw11/Rw11Unit.hpp b/tools/src/librw11/Rw11Unit.hpp index 296e911e..4e264eab 100644 --- a/tools/src/librw11/Rw11Unit.hpp +++ b/tools/src/librw11/Rw11Unit.hpp @@ -1,6 +1,6 @@ -// $Id: Rw11Unit.hpp 515 2013-05-04 17:28:59Z mueller $ +// $Id: Rw11Unit.hpp 680 2015-05-14 13:29:46Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-05-13 680 1.1.1 add Enabled() // 2013-05-03 515 1.1 use AttachDone(),DetachCleanup(),DetachDone() // 2013-05-01 513 1.0.1 add fAttachOpts, (Set)AttachOpts() // 2013-03-06 495 1.0 Initial version @@ -22,7 +23,7 @@ /*! \file - \version $Id: Rw11Unit.hpp 515 2013-05-04 17:28:59Z mueller $ + \version $Id: Rw11Unit.hpp 680 2015-05-14 13:29:46Z mueller $ \brief Declaration of class Rw11Unit. */ @@ -61,6 +62,8 @@ namespace Retro { RlinkConnect& Connect() const; RlogFile& LogFile() const; + virtual bool Enabled() const; + virtual bool Attach(const std::string& url, RerrMsg& emsg); virtual void Detach(); diff --git a/tools/src/librw11/Rw11UnitDisk.cpp b/tools/src/librw11/Rw11UnitDisk.cpp index 0b9321ec..ceb59359 100644 --- a/tools/src/librw11/Rw11UnitDisk.cpp +++ b/tools/src/librw11/Rw11UnitDisk.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11UnitDisk.cpp 561 2014-06-09 17:22:50Z mueller $ +// $Id: Rw11UnitDisk.cpp 659 2015-03-22 23:15:51Z mueller $ // // Copyright 2013- by Walter F.J. Mueller // @@ -13,13 +13,14 @@ // // Revision History: // Date Rev Version Comment +// 2015-03-21 659 1.0.1 add fEnabled, Enabled() // 2013-04-19 507 1.0 Initial version // 2013-02-19 490 0.1 First draft // --------------------------------------------------------------------------- /*! \file - \version $Id: Rw11UnitDisk.cpp 561 2014-06-09 17:22:50Z mueller $ + \version $Id: Rw11UnitDisk.cpp 659 2015-03-22 23:15:51Z mueller $ \brief Implemenation of Rw11UnitDisk. */ @@ -43,6 +44,7 @@ namespace Retro { Rw11UnitDisk::Rw11UnitDisk(Rw11Cntl* pcntl, size_t index) : Rw11UnitVirt(pcntl, index), fType(), + fEnabled(false), fNCyl(0), fNHead(0), fNSect(0), @@ -101,6 +103,7 @@ void Rw11UnitDisk::Dump(std::ostream& os, int ind, const char* text) const RosFill bl(ind); os << bl << (text?text:"--") << "Rw11UnitDisk @ " << this << endl; os << bl << " fType: " << fType << endl; + os << bl << " fEnabled: " << fEnabled << endl; os << bl << " fNCyl: " << fNCyl << endl; os << bl << " fNHead: " << fNHead << endl; os << bl << " fNSect: " << fNSect << endl; diff --git a/tools/src/librw11/Rw11UnitDisk.hpp b/tools/src/librw11/Rw11UnitDisk.hpp index 5ca3d487..ac1b1dab 100644 --- a/tools/src/librw11/Rw11UnitDisk.hpp +++ b/tools/src/librw11/Rw11UnitDisk.hpp @@ -1,4 +1,4 @@ -// $Id: Rw11UnitDisk.hpp 647 2015-02-17 22:35:36Z mueller $ +// $Id: Rw11UnitDisk.hpp 680 2015-05-14 13:29:46Z mueller $ // // Copyright 2013-2015 by Walter F.J. Mueller // @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-03-21 659 1.0.2 add fEnabled, Enabled() // 2015-02-18 647 1.0.1 add Nwrd2Nblk() // 2013-04-19 507 1.0 Initial version // 2013-02-19 490 0.1 First draft @@ -21,7 +22,7 @@ /*! \file - \version $Id: Rw11UnitDisk.hpp 647 2015-02-17 22:35:36Z mueller $ + \version $Id: Rw11UnitDisk.hpp 680 2015-05-14 13:29:46Z mueller $ \brief Declaration of class Rw11UnitDisk. */ @@ -42,6 +43,7 @@ namespace Retro { virtual void SetType(const std::string& type); const std::string& Type() const; + virtual bool Enabled() const; size_t NCylinder() const; size_t NHead() const; size_t NSector() const; @@ -64,13 +66,14 @@ namespace Retro { virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; protected: - std::string fType; - size_t fNCyl; - size_t fNHead; - size_t fNSect; - size_t fBlksize; - size_t fNBlock; - bool fWProt; + std::string fType; //!< drive type + bool fEnabled; //!< unit enabled + size_t fNCyl; //!< # cylinder + size_t fNHead; //!< # heads (aka surfaces) + size_t fNSect; //!< # sectors + size_t fBlksize; //!< block size (in bytes) + size_t fNBlock; //!< # blocks + bool fWProt; //!< unit write protected }; } // end namespace Retro diff --git a/tools/src/librw11/Rw11UnitDisk.ipp b/tools/src/librw11/Rw11UnitDisk.ipp index 0743ce8c..ce3bb910 100644 --- a/tools/src/librw11/Rw11UnitDisk.ipp +++ b/tools/src/librw11/Rw11UnitDisk.ipp @@ -1,4 +1,4 @@ -// $Id: Rw11UnitDisk.ipp 647 2015-02-17 22:35:36Z mueller $ +// $Id: Rw11UnitDisk.ipp 659 2015-03-22 23:15:51Z mueller $ // // Copyright 2013-2015 by Walter F.J. Mueller // @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-03-21 659 1.0.2 add fEnabled, Enabled() // 2015-02-18 647 1.0.1 add Nwrd2Nblk() // 2013-04-19 507 1.0 Initial version // 2013-02-19 490 0.1 First draft @@ -20,7 +21,7 @@ /*! \file - \version $Id: Rw11UnitDisk.ipp 647 2015-02-17 22:35:36Z mueller $ + \version $Id: Rw11UnitDisk.ipp 659 2015-03-22 23:15:51Z mueller $ \brief Implemenation (inline) of Rw11UnitDisk. */ @@ -38,6 +39,14 @@ inline const std::string& Rw11UnitDisk::Type() const //------------------------------------------+----------------------------------- //! FIXME_docs +inline bool Rw11UnitDisk::Enabled() const +{ + return fEnabled; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + inline size_t Rw11UnitDisk::NCylinder() const { return fNCyl; diff --git a/tools/src/librw11/Rw11UnitRHRP.cpp b/tools/src/librw11/Rw11UnitRHRP.cpp new file mode 100644 index 00000000..a382182b --- /dev/null +++ b/tools/src/librw11/Rw11UnitRHRP.cpp @@ -0,0 +1,148 @@ +// $Id: Rw11UnitRHRP.cpp 680 2015-05-14 13:29:46Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-14 680 1.0 Initial version +// 2015-03-21 659 0.1 First draft +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11UnitRHRP.cpp 680 2015-05-14 13:29:46Z mueller $ + \brief Implemenation of Rw11UnitRHRP. +*/ + +#include "boost/bind.hpp" + +#include "librtools/Rexception.hpp" +#include "librtools/RosFill.hpp" +#include "Rw11CntlRHRP.hpp" + +#include "Rw11UnitRHRP.hpp" + +using namespace std; + +/*! + \class Retro::Rw11UnitRHRP + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +// constants definitions + +const uint16_t Rw11UnitRHRP::kDTE_M_RM; +const uint16_t Rw11UnitRHRP::kDTE_RP04; +const uint16_t Rw11UnitRHRP::kDTE_RP06; +const uint16_t Rw11UnitRHRP::kDTE_RM03; +const uint16_t Rw11UnitRHRP::kDTE_RM80; +const uint16_t Rw11UnitRHRP::kDTE_RM05; +const uint16_t Rw11UnitRHRP::kDTE_RP07; + +//------------------------------------------+----------------------------------- +//! Constructor + +Rw11UnitRHRP::Rw11UnitRHRP(Rw11CntlRHRP* pcntl, size_t index) + : Rw11UnitDiskBase(pcntl, index), + fRpdt(0), + fRpds(0) +{ + // setup disk geometry: default off + fType = "off"; + fEnabled = false; + fBlksize = 512; +} + +//------------------------------------------+----------------------------------- +//! Destructor + +Rw11UnitRHRP::~Rw11UnitRHRP() +{} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11UnitRHRP::SetType(const std::string& type) +{ + if (Virt()) { + throw Rexception("Rw11UnitRHRP::SetType", + string("Bad state: file attached")); + } + + if (type == "off") { + fRpdt = 0; + fNCyl = 0; + fNHead = 0; + fNSect = 0; + } else if (type == "rp04") { + fRpdt = kDTE_RP04; + fNCyl = 411; + fNHead = 19; + fNSect = 22; + } else if (type == "rp06") { + fRpdt = kDTE_RP06; + fNCyl = 815; + fNHead = 19; + fNSect = 22; + } else if (type == "rm03") { + fRpdt = kDTE_RM03; + fNCyl = 823; + fNHead = 5; + fNSect = 32; + } else if (type == "rm80") { + fRpdt = kDTE_RM80; + fNCyl = 559; + fNHead = 14; + fNSect = 31; + } else if (type == "rm05") { + fRpdt = kDTE_RM05; + fNCyl = 823; + fNHead = 19; + fNSect = 32; + } else if (type == "rp07") { + fRpdt = kDTE_RP07; + fNCyl = 630; + fNHead = 32; + fNSect = 50; + } else { + throw Rexception("Rw11UnitRHRP::SetType", + string("Bad args: only off or rp04,rp06,rm03,rm80,rm05,rp07 supported")); + } + + fType = type; + fEnabled = fNCyl != 0; + fNBlock = fNCyl*fNHead*fNSect; + + Cntl().UnitSetup(Index()); // update hardware + + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +void Rw11UnitRHRP::Dump(std::ostream& os, int ind, const char* text) const +{ + RosFill bl(ind); + os << bl << (text?text:"--") << "Rw11UnitRHRP @ " << this << endl; + os << bl << " fRpdt: " << RosPrintf(fRpdt,"o",6) << endl; + os << bl << " fRpds: " << RosPrintf(fRpds,"o",6) << endl; + + Rw11UnitDiskBase::Dump(os, ind, " ^"); + return; +} + +} // end namespace Retro diff --git a/tools/src/librw11/Rw11UnitRHRP.hpp b/tools/src/librw11/Rw11UnitRHRP.hpp new file mode 100644 index 00000000..83ada863 --- /dev/null +++ b/tools/src/librw11/Rw11UnitRHRP.hpp @@ -0,0 +1,68 @@ +// $Id: Rw11UnitRHRP.hpp 680 2015-05-14 13:29:46Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-14 680 1.0 Initial version +// 2015-03-21 659 0.1 First draft +// --------------------------------------------------------------------------- + + +/*! + \file + \version $Id: Rw11UnitRHRP.hpp 680 2015-05-14 13:29:46Z mueller $ + \brief Declaration of class Rw11UnitRHRP. +*/ + +#ifndef included_Retro_Rw11UnitRHRP +#define included_Retro_Rw11UnitRHRP 1 + +#include "Rw11UnitDiskBase.hpp" + +namespace Retro { + + class Rw11CntlRHRP; // forw decl to avoid circular incl + + class Rw11UnitRHRP : public Rw11UnitDiskBase { + public: + Rw11UnitRHRP(Rw11CntlRHRP* pcntl, size_t index); + ~Rw11UnitRHRP(); + + virtual void SetType(const std::string& type); + uint16_t Rpdt() const; + bool IsRmType() const; + + void SetRpds(uint16_t rpds); + uint16_t Rpds() const; + + virtual void Dump(std::ostream& os, int ind=0, const char* text=0) const; + + // some constants (also defined in cpp) + static const uint16_t kDTE_M_RM = kWBit02; //!< rm type flag + static const uint16_t kDTE_RP04 = 00; //!< drive type of RP04 rm=0 + static const uint16_t kDTE_RP06 = 01; //!< drive type of RP06 rm=0 + static const uint16_t kDTE_RM03 = 04; //!< drive type of RM03 rm=1 + static const uint16_t kDTE_RM80 = 05; //!< drive type of RM80 rm=1 + static const uint16_t kDTE_RM05 = 06; //!< drive type of RM05 rm=1 + static const uint16_t kDTE_RP07 = 07; //!< drive type of RP07 rm=1 + + protected: + uint16_t fRpdt; //!< drive type (encoded) + uint16_t fRpds; //!< drive status + }; + +} // end namespace Retro + +#include "Rw11UnitRHRP.ipp" + +#endif diff --git a/tools/src/librw11/Rw11UnitRHRP.ipp b/tools/src/librw11/Rw11UnitRHRP.ipp new file mode 100644 index 00000000..5cb06dbd --- /dev/null +++ b/tools/src/librw11/Rw11UnitRHRP.ipp @@ -0,0 +1,69 @@ +// $Id: Rw11UnitRHRP.ipp 680 2015-05-14 13:29:46Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-14 680 1.0 Initial version +// 2015-03-21 659 0.1 First draft +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: Rw11UnitRHRP.ipp 680 2015-05-14 13:29:46Z mueller $ + \brief Implemenation (inline) of Rw11UnitRHRP. +*/ + +#include "Rw11UnitRHRP.hpp" + +/*! + \class Retro::Rw11UnitRHRP + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline uint16_t Rw11UnitRHRP::Rpdt() const +{ + return fRpdt; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline bool Rw11UnitRHRP::IsRmType() const +{ + return fRpdt & kDTE_M_RM; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline void Rw11UnitRHRP::SetRpds(uint16_t rpds) +{ + fRpds = rpds; + return; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +inline uint16_t Rw11UnitRHRP::Rpds() const +{ + return fRpds; +} + +} // end namespace Retro diff --git a/tools/src/librw11/Rw11UnitRK11.cpp b/tools/src/librw11/Rw11UnitRK11.cpp index e7a53c3e..b15e2515 100644 --- a/tools/src/librw11/Rw11UnitRK11.cpp +++ b/tools/src/librw11/Rw11UnitRK11.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11UnitRK11.cpp 509 2013-04-21 20:46:20Z mueller $ +// $Id: Rw11UnitRK11.cpp 659 2015-03-22 23:15:51Z mueller $ // // Copyright 2013- by Walter F.J. Mueller // @@ -19,7 +19,7 @@ /*! \file - \version $Id: Rw11UnitRK11.cpp 509 2013-04-21 20:46:20Z mueller $ + \version $Id: Rw11UnitRK11.cpp 659 2015-03-22 23:15:51Z mueller $ \brief Implemenation of Rw11UnitRK11. */ @@ -49,6 +49,7 @@ Rw11UnitRK11::Rw11UnitRK11(Rw11CntlRK11* pcntl, size_t index) { // setup disk geometry: only rk05 supported, no rk05f ! fType = "rk05"; + fEnabled = true; fNCyl = 203; fNHead = 2; fNSect = 12; diff --git a/tools/src/librw11/Rw11UnitRL11.cpp b/tools/src/librw11/Rw11UnitRL11.cpp index 12a28d43..f531ac8e 100644 --- a/tools/src/librw11/Rw11UnitRL11.cpp +++ b/tools/src/librw11/Rw11UnitRL11.cpp @@ -1,4 +1,4 @@ -// $Id: Rw11UnitRL11.cpp 653 2015-03-01 12:53:01Z mueller $ +// $Id: Rw11UnitRL11.cpp 659 2015-03-22 23:15:51Z mueller $ // // Copyright 2014- by Walter F.J. Mueller // @@ -13,12 +13,13 @@ // // Revision History: // Date Rev Version Comment +// 2015-03-21 659 1.0.1 BUGFIX: SetType(): set fType; // 2014-06-08 561 1.0 Initial version // --------------------------------------------------------------------------- /*! \file - \version $Id: Rw11UnitRL11.cpp 653 2015-03-01 12:53:01Z mueller $ + \version $Id: Rw11UnitRL11.cpp 659 2015-03-22 23:15:51Z mueller $ \brief Implemenation of Rw11UnitRL11. */ @@ -50,6 +51,7 @@ Rw11UnitRL11::Rw11UnitRL11(Rw11CntlRL11* pcntl, size_t index) { // setup disk geometry: rl01 and rl02 supported, default rl02 fType = "rl02"; + fEnabled = true; fNCyl = 512; fNHead = 2; fNSect = 40; @@ -81,6 +83,8 @@ void Rw11UnitRL11::SetType(const std::string& type) throw Rexception("Rw11UnitRL11::SetType", string("Bad args: only types 'rl01' and 'rl02' supported")); } + + fType = type; fNBlock = fNCyl*fNHead*fNSect; return; } diff --git a/tools/src/librw11/Rw11UnitVirt.ipp b/tools/src/librw11/Rw11UnitVirt.ipp index c2e80bda..d015759e 100644 --- a/tools/src/librw11/Rw11UnitVirt.ipp +++ b/tools/src/librw11/Rw11UnitVirt.ipp @@ -1,6 +1,6 @@ -// $Id: Rw11UnitVirt.ipp 600 2014-11-02 22:33:02Z mueller $ +// $Id: Rw11UnitVirt.ipp 680 2015-05-14 13:29:46Z mueller $ // -// Copyright 2013-2014 by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-05-13 680 1.2 Attach(): check for Enabled() // 2014-11-02 600 1.1.1 add (bool) cast, needed in 4.8.2 // 2013-05-03 515 1.1 use AttachDone(),DetachCleanup(),DetachDone() // 2013-03-03 494 1.0 Initial version @@ -21,7 +22,7 @@ /*! \file - \version $Id: Rw11UnitVirt.ipp 600 2014-11-02 22:33:02Z mueller $ + \version $Id: Rw11UnitVirt.ipp 680 2015-05-14 13:29:46Z mueller $ \brief Implemenation (inline) of Rw11UnitVirt. */ @@ -73,6 +74,10 @@ inline bool Rw11UnitVirt::Attach(const std::string& url, RerrMsg& emsg) // synchronize with server thread boost::lock_guard lock(Connect()); if (fpVirt) Detach(); + if (!Enabled()) { + emsg.Init("Rw11UnitVirt::Attach","unit not enabled"); + return false; + } fpVirt.reset(TV::New(url, this, emsg)); if (fpVirt) AttachDone(); return (bool)fpVirt; diff --git a/tools/src/librwxxtpp/Makefile b/tools/src/librwxxtpp/Makefile index 7911ac55..d454a6a9 100644 --- a/tools/src/librwxxtpp/Makefile +++ b/tools/src/librwxxtpp/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 602 2014-11-08 21:42:47Z mueller $ +# $Id: Makefile 664 2015-04-06 12:02:17Z mueller $ # # Revision History: # Date Rev Version Comment @@ -37,6 +37,7 @@ OBJ_all += RtclRw11CntlLP11.o RtclRw11UnitLP11.o OBJ_all += RtclRw11CntlPC11.o RtclRw11UnitPC11.o OBJ_all += RtclRw11CntlRK11.o RtclRw11UnitRK11.o OBJ_all += RtclRw11CntlRL11.o RtclRw11UnitRL11.o +OBJ_all += RtclRw11CntlRHRP.o RtclRw11UnitRHRP.o # DEP_all = $(OBJ_all:.o=.dep) # diff --git a/tools/src/librwxxtpp/RtclRw11.cpp b/tools/src/librwxxtpp/RtclRw11.cpp index b10f5509..639c5476 100644 --- a/tools/src/librwxxtpp/RtclRw11.cpp +++ b/tools/src/librwxxtpp/RtclRw11.cpp @@ -1,6 +1,6 @@ -// $Id: RtclRw11.cpp 632 2015-01-11 12:30:03Z mueller $ +// $Id: RtclRw11.cpp 660 2015-03-29 22:10:16Z mueller $ // -// Copyright 2013-2014 by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-03-28 660 1.0.1 add M_get // 2014-12-25 621 1.1 adopt to 4k word ibus window // 2013-03-06 495 1.0 Initial version // 2013-01-27 478 0.1 First Draft @@ -20,7 +21,7 @@ /*! \file - \version $Id: RtclRw11.cpp 632 2015-01-11 12:30:03Z mueller $ + \version $Id: RtclRw11.cpp 660 2015-03-29 22:10:16Z mueller $ \brief Implemenation of class RtclRw11. */ @@ -55,11 +56,17 @@ namespace Retro { RtclRw11::RtclRw11(Tcl_Interp* interp, const char* name) : RtclProxyOwned("Rw11", interp, name, new Rw11()), - fspServ() + fspServ(), + fGets() { + AddMeth("get", boost::bind(&RtclRw11::M_get, this, _1)); AddMeth("start", boost::bind(&RtclRw11::M_start, this, _1)); AddMeth("dump", boost::bind(&RtclRw11::M_dump, this, _1)); AddMeth("$default", boost::bind(&RtclRw11::M_default, this, _1)); + + Rw11* pobj = &Obj(); + fGets.Add ("started",boost::bind(&Rw11::IsStarted, pobj)); + } //------------------------------------------+----------------------------------- @@ -115,10 +122,20 @@ int RtclRw11::ClassCmdConfig(RtclArgs& args) //------------------------------------------+----------------------------------- //! FIXME_docs +int RtclRw11::M_get(RtclArgs& args) +{ + // synchronize with server thread + boost::lock_guard lock(Obj().Connect()); + return fGets.M_get(args); +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + int RtclRw11::M_start(RtclArgs& args) { if (!args.AllDone()) return kERR; - if (Obj().IsStarted()) return args.Quit("already started"); + if (Obj().IsStarted()) return args.Quit("-E: already started"); Obj().Start(); return kOK; } diff --git a/tools/src/librwxxtpp/RtclRw11.hpp b/tools/src/librwxxtpp/RtclRw11.hpp index 9032fa1c..33e999ba 100644 --- a/tools/src/librwxxtpp/RtclRw11.hpp +++ b/tools/src/librwxxtpp/RtclRw11.hpp @@ -1,6 +1,6 @@ -// $Id: RtclRw11.hpp 504 2013-04-13 15:37:24Z mueller $ +// $Id: RtclRw11.hpp 660 2015-03-29 22:10:16Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,13 +13,14 @@ // // Revision History: // Date Rev Version Comment +// 2015-03-28 660 1.0.1 add M_get // 2013-03-06 495 1.0 Initial version // 2013-01-27 478 0.1 First draft // --------------------------------------------------------------------------- /*! \file - \version $Id: RtclRw11.hpp 504 2013-04-13 15:37:24Z mueller $ + \version $Id: RtclRw11.hpp 660 2015-03-29 22:10:16Z mueller $ \brief Declaration of class RtclRw11. */ @@ -32,6 +33,7 @@ #include "boost/shared_ptr.hpp" #include "librtcltools/RtclProxyOwned.hpp" +#include "librtcltools/RtclGetList.hpp" #include "librlink/RlinkServer.hpp" #include "librw11/Rw11.hpp" @@ -46,12 +48,14 @@ namespace Retro { virtual int ClassCmdConfig(RtclArgs& args); protected: + int M_get(RtclArgs& args); int M_start(RtclArgs& args); int M_dump(RtclArgs& args); int M_default(RtclArgs& args); protected: boost::shared_ptr fspServ; + RtclGetList fGets; }; } // end namespace Retro diff --git a/tools/src/librwxxtpp/RtclRw11Cntl.cpp b/tools/src/librwxxtpp/RtclRw11Cntl.cpp index 9a420dcb..5b034927 100644 --- a/tools/src/librwxxtpp/RtclRw11Cntl.cpp +++ b/tools/src/librwxxtpp/RtclRw11Cntl.cpp @@ -1,6 +1,6 @@ -// $Id: RtclRw11Cntl.cpp 504 2013-04-13 15:37:24Z mueller $ +// $Id: RtclRw11Cntl.cpp 660 2015-03-29 22:10:16Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,13 +13,14 @@ // // Revision History: // Date Rev Version Comment +// 2015-03-27 660 1.0.1 add M_start // 2013-03-06 495 1.0 Initial version // 2013-02-08 484 0.1 First draft // --------------------------------------------------------------------------- /*! \file - \version $Id: RtclRw11Cntl.cpp 504 2013-04-13 15:37:24Z mueller $ + \version $Id: RtclRw11Cntl.cpp 660 2015-03-29 22:10:16Z mueller $ \brief Implemenation of RtclRw11Cntl. */ @@ -51,6 +52,7 @@ RtclRw11Cntl::RtclRw11Cntl(const std::string& type) AddMeth("get", boost::bind(&RtclRw11Cntl::M_get, this, _1)); AddMeth("set", boost::bind(&RtclRw11Cntl::M_set, this, _1)); AddMeth("probe", boost::bind(&RtclRw11Cntl::M_probe, this, _1)); + AddMeth("start", boost::bind(&RtclRw11Cntl::M_start, this, _1)); AddMeth("stats", boost::bind(&RtclRw11Cntl::M_stats, this, _1)); AddMeth("dump", boost::bind(&RtclRw11Cntl::M_dump, this, _1)); AddMeth("$default", boost::bind(&RtclRw11Cntl::M_default, this, _1)); @@ -95,6 +97,17 @@ int RtclRw11Cntl::M_probe(RtclArgs& args) //------------------------------------------+----------------------------------- //! FIXME_docs +int RtclRw11Cntl::M_start(RtclArgs& args) +{ + if (!args.AllDone()) return kERR; + Obj().Probe(); + Obj().Start(); + return kOK; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + int RtclRw11Cntl::M_stats(RtclArgs& args) { RtclStats::Context cntx; diff --git a/tools/src/librwxxtpp/RtclRw11Cntl.hpp b/tools/src/librwxxtpp/RtclRw11Cntl.hpp index 8eccf71c..9914ed61 100644 --- a/tools/src/librwxxtpp/RtclRw11Cntl.hpp +++ b/tools/src/librwxxtpp/RtclRw11Cntl.hpp @@ -1,4 +1,4 @@ -// $Id: RtclRw11Cntl.hpp 627 2015-01-04 11:36:37Z mueller $ +// $Id: RtclRw11Cntl.hpp 660 2015-03-29 22:10:16Z mueller $ // // Copyright 2013-2015 by Walter F.J. Mueller // @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-03-27 660 1.1.1 add M_start // 2015-01-03 627 1.1 M_stats now virtual // 2013-03-06 495 1.0 Initial version // 2013-02-08 484 0.1 First draft @@ -21,7 +22,7 @@ /*! \file - \version $Id: RtclRw11Cntl.hpp 627 2015-01-04 11:36:37Z mueller $ + \version $Id: RtclRw11Cntl.hpp 660 2015-03-29 22:10:16Z mueller $ \brief Declaration of class RtclRw11Cntl. */ @@ -53,6 +54,7 @@ namespace Retro { int M_get(RtclArgs& args); int M_set(RtclArgs& args); int M_probe(RtclArgs& args); + int M_start(RtclArgs& args); virtual int M_stats(RtclArgs& args); int M_dump(RtclArgs& args); int M_default(RtclArgs& args); diff --git a/tools/src/librwxxtpp/RtclRw11CntlFactory.cpp b/tools/src/librwxxtpp/RtclRw11CntlFactory.cpp index b6779ea2..b3571a47 100644 --- a/tools/src/librwxxtpp/RtclRw11CntlFactory.cpp +++ b/tools/src/librwxxtpp/RtclRw11CntlFactory.cpp @@ -1,4 +1,4 @@ -// $Id: RtclRw11CntlFactory.cpp 630 2015-01-04 22:43:32Z mueller $ +// $Id: RtclRw11CntlFactory.cpp 664 2015-04-06 12:02:17Z mueller $ // // Copyright 2013-2015 by Walter F.J. Mueller // @@ -13,6 +13,7 @@ // // Revision History: // Date Rev Version Comment +// 2015-03-21 659 1.1.3 add RPRM (later renamed to RHRP) // 2015-01-04 630 1.1.2 RL11 back in // 2014-06-27 565 1.1.1 temporarily hide RL11 // 2014-06-08 561 1.1.0 add RL11 @@ -23,7 +24,7 @@ /*! \file - \version $Id: RtclRw11CntlFactory.cpp 630 2015-01-04 22:43:32Z mueller $ + \version $Id: RtclRw11CntlFactory.cpp 664 2015-04-06 12:02:17Z mueller $ \brief Implemenation of global function RtclRw11CntlFactory. */ @@ -34,6 +35,7 @@ #include "RtclRw11CntlDL11.hpp" #include "RtclRw11CntlRK11.hpp" #include "RtclRw11CntlRL11.hpp" +#include "RtclRw11CntlRHRP.hpp" #include "RtclRw11CntlLP11.hpp" #include "RtclRw11CntlPC11.hpp" @@ -66,6 +68,11 @@ int RtclRw11CntlFactory(RtclArgs& args, RtclRw11Cpu& cpu) if(pobj->FactoryCmdConfig(args, cpu) != TCL_OK) return TCL_ERROR; pobj.release(); + } else if (type == "rhrp") { // rhrp -------------------------- + unique_ptr pobj(new RtclRw11CntlRHRP()); + if(pobj->FactoryCmdConfig(args, cpu) != TCL_OK) return TCL_ERROR; + pobj.release(); + } else if (type == "lp11") { // lp11 -------------------------- unique_ptr pobj(new RtclRw11CntlLP11()); if(pobj->FactoryCmdConfig(args, cpu) != TCL_OK) return TCL_ERROR; diff --git a/tools/src/librwxxtpp/RtclRw11CntlRHRP.cpp b/tools/src/librwxxtpp/RtclRw11CntlRHRP.cpp new file mode 100644 index 00000000..dac54c95 --- /dev/null +++ b/tools/src/librwxxtpp/RtclRw11CntlRHRP.cpp @@ -0,0 +1,112 @@ +// $Id: RtclRw11CntlRHRP.cpp 680 2015-05-14 13:29:46Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-14 680 1.0 Initial version +// 2015-03-21 659 0.1 First draft +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: RtclRw11CntlRHRP.cpp 680 2015-05-14 13:29:46Z mueller $ + \brief Implemenation of RtclRw11CntlRHRP. +*/ + +#include "librtcltools/RtclNameSet.hpp" + +#include "RtclRw11CntlRHRP.hpp" +#include "RtclRw11UnitRHRP.hpp" + +using namespace std; + +/*! + \class Retro::RtclRw11CntlRHRP + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! Constructor + +RtclRw11CntlRHRP::RtclRw11CntlRHRP() + : RtclRw11CntlBase("Rw11CntlRHRP") +{ + Rw11CntlRHRP* pobj = &Obj(); + fGets.Add ("chunksize", + boost::bind(&Rw11CntlRHRP::ChunkSize, pobj)); + fSets.Add ("chunksize", + boost::bind(&Rw11CntlRHRP::SetChunkSize, pobj, _1)); +} + +//------------------------------------------+----------------------------------- +//! Destructor + +RtclRw11CntlRHRP::~RtclRw11CntlRHRP() +{} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + +int RtclRw11CntlRHRP::FactoryCmdConfig(RtclArgs& args, RtclRw11Cpu& cpu) +{ + static RtclNameSet optset("-base|-lam"); + + string cntlname(cpu.Obj().NextCntlName("rp")); + string cntlcmd = cpu.CommandName() + cntlname; + + uint16_t base = Rw11CntlRHRP::kIbaddr; + int lam = Rw11CntlRHRP::kLam; + + string opt; + while (args.NextOpt(opt, optset)) { + if (opt == "-base") { + if (!args.GetArg("base", base, 0177776, 0160000)) return kERR; + } else if (opt == "-lam") { + if (!args.GetArg("lam", lam, 0, 15)) return kERR; + } + } + if (!args.AllDone()) return kERR; + + // configure controller + Obj().Config(cntlname, base, lam); + + // install in CPU + cpu.Obj().AddCntl(dynamic_pointer_cast(ObjSPtr())); + // finally create tcl command + CreateObjectCmd(args.Interp(), cntlcmd.c_str()); + + // and create unit commands + for (size_t i=0; i +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-14 680 1.0 Initial version +// 2015-03-21 659 0.1 First draft +// --------------------------------------------------------------------------- + + +/*! + \file + \version $Id: RtclRw11CntlRHRP.hpp 680 2015-05-14 13:29:46Z mueller $ + \brief Declaration of class RtclRw11CntlRHRP. +*/ + +#ifndef included_Retro_RtclRw11CntlRHRP +#define included_Retro_RtclRw11CntlRHRP 1 + +#include "RtclRw11CntlBase.hpp" +#include "librw11/Rw11CntlRHRP.hpp" + +namespace Retro { + + class RtclRw11CntlRHRP : public RtclRw11CntlBase { + public: + RtclRw11CntlRHRP(); + ~RtclRw11CntlRHRP(); + + virtual int FactoryCmdConfig(RtclArgs& args, RtclRw11Cpu& cpu); + + protected: + virtual int M_stats(RtclArgs& args); + }; + +} // end namespace Retro + +//#include "RtclRw11CntlRHRP.ipp" + +#endif diff --git a/tools/src/librwxxtpp/RtclRw11Cpu.cpp b/tools/src/librwxxtpp/RtclRw11Cpu.cpp index c1dc5563..2620ece4 100644 --- a/tools/src/librwxxtpp/RtclRw11Cpu.cpp +++ b/tools/src/librwxxtpp/RtclRw11Cpu.cpp @@ -1,6 +1,6 @@ -// $Id: RtclRw11Cpu.cpp 631 2015-01-09 21:36:51Z mueller $ +// $Id: RtclRw11Cpu.cpp 675 2015-05-08 21:05:08Z mueller $ // -// Copyright 2013-2014 by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,12 @@ // // Revision History: // Date Rev Version Comment +// 2015-05-04 674 1.2.2 w11a start/stop/suspend overhaul +// 2015-04-25 668 1.2.1 M_cp: add -rbibr, wbibr; GetRAddr: drop odd check +// 2015-04-03 661 1.2 expect logic: drop estatdef, use LastExpect.. +// 2015-03-28 660 1.1.4 M_cp: add -estat(err|nak|tout) +// 2015-03-21 659 1.1.3 rename M_amap->M_imap; add M_rmap; add GetRAddr() +// add -rreg,...,-init and -[rw]ma // 2014-12-29 623 1.1.2 add M_amap; M_cp: add -print and -dump // 2014-12-20 616 1.1.1 M_cp: add -edone for BlockDone checking // 2014-11-30 607 1.1 new rlink v4 iface @@ -27,7 +33,7 @@ /*! \file - \version $Id: RtclRw11Cpu.cpp 631 2015-01-09 21:36:51Z mueller $ + \version $Id: RtclRw11Cpu.cpp 675 2015-05-08 21:05:08Z mueller $ \brief Implemenation of RtclRw11Cpu. */ @@ -80,7 +86,8 @@ RtclRw11Cpu::RtclRw11Cpu(const std::string& type) fSets() { AddMeth("add", boost::bind(&RtclRw11Cpu::M_add, this, _1)); - AddMeth("amap", boost::bind(&RtclRw11Cpu::M_amap, this, _1)); + AddMeth("imap", boost::bind(&RtclRw11Cpu::M_imap, this, _1)); + AddMeth("rmap", boost::bind(&RtclRw11Cpu::M_rmap, this, _1)); AddMeth("cp", boost::bind(&RtclRw11Cpu::M_cp, this, _1)); AddMeth("wtcpu", boost::bind(&RtclRw11Cpu::M_wtcpu, this, _1)); AddMeth("deposit", boost::bind(&RtclRw11Cpu::M_deposit, this, _1)); @@ -114,7 +121,7 @@ int RtclRw11Cpu::M_add(RtclArgs& args) //------------------------------------------+----------------------------------- //! FIXME_docs -int RtclRw11Cpu::M_amap(RtclArgs& args) +int RtclRw11Cpu::M_imap(RtclArgs& args) { static RtclNameSet optset("-name|-testname|-testaddr|-insert|-erase|-print"); @@ -125,7 +132,7 @@ int RtclRw11Cpu::M_amap(RtclArgs& args) uint16_t addr=0; if (args.NextOpt(opt, optset)) { - if (opt == "-name") { // amap -name addr + if (opt == "-name") { // imap -name addr if (!args.GetArg("addr", addr)) return kERR; if (!args.AllDone()) return kERR; string tstname; @@ -136,19 +143,19 @@ int RtclRw11Cpu::M_amap(RtclArgs& args) "' not mapped"); } - } else if (opt == "-testname") { // amap -testname name + } else if (opt == "-testname") { // imap -testname name if (!args.GetArg("name", name)) return kERR; if (!args.AllDone()) return kERR; uint16_t tstaddr; args.SetResult(int(addrmap.Find(name, tstaddr))); - } else if (opt == "-testaddr") { // amap -testaddr addr + } else if (opt == "-testaddr") { // imap -testaddr addr if (!args.GetArg("addr", addr)) return kERR; if (!args.AllDone()) return kERR; string tstname; args.SetResult(int(addrmap.Find(addr, tstname))); - } else if (opt == "-insert") { // amap -insert name addr + } else if (opt == "-insert") { // imap -insert name addr uint16_t tstaddr; string tstname; int tstint; @@ -166,13 +173,13 @@ int RtclRw11Cpu::M_amap(RtclArgs& args) args.PeekArgString(-1) + "'"); Obj().IAddrMapInsert(name, addr); - } else if (opt == "-erase") { // amap -erase name + } else if (opt == "-erase") { // imap -erase name if (!args.GetArg("name", name)) return kERR; if (!args.AllDone()) return kERR; if (!Obj().IAddrMapErase(name)) return args.Quit(string("-E: no mapping defined for '") + name + "'"); - } else if (opt == "-print") { // amap -print + } else if (opt == "-print") { // imap -print if (!args.AllDone()) return kERR; ostringstream sos; addrmap.Print(sos); @@ -182,7 +189,7 @@ int RtclRw11Cpu::M_amap(RtclArgs& args) } else { if (!args.OptValid()) return kERR; if (!args.GetArg("?name", name)) return kERR; - if (args.NOptMiss()==0) { // amap name + if (args.NOptMiss()==0) { // imap name uint16_t tstaddr; if(addrmap.Find(name, tstaddr)) { args.SetResult(int(tstaddr)); @@ -190,7 +197,7 @@ int RtclRw11Cpu::M_amap(RtclArgs& args) return args.Quit(string("-E: no mapping defined for '") + name + "'"); } - } else { // amap + } else { // imap RtclOPtr plist(Tcl_NewListObj(0, nullptr)); const RlinkAddrMap::amap_t amap = addrmap.Amap(); for (RlinkAddrMap::amap_cit_t it=amap.begin(); it!=amap.end(); it++) { @@ -209,19 +216,123 @@ int RtclRw11Cpu::M_amap(RtclArgs& args) //------------------------------------------+----------------------------------- //! FIXME_docs +int RtclRw11Cpu::M_rmap(RtclArgs& args) +{ + static RtclNameSet optset("-name|-testname|-testaddr|-insert|-erase|-print"); + + const RlinkAddrMap& lmap = Obj().RAddrMap(); // local map + const RlinkAddrMap& cmap = Connect().AddrMap(); // common map + + string opt; + string name; + uint16_t addr=0; + + if (args.NextOpt(opt, optset)) { + if (opt == "-name") { // rmap -name addr + if (!args.GetArg("addr", addr)) return kERR; + if (!args.AllDone()) return kERR; + string tstname; + if(lmap.Find(addr, tstname)) { + args.SetResult(tstname); + } else if(cmap.Find(addr, tstname)) { + args.SetResult(tstname); + } else { + return args.Quit(string("-E: address '") + args.PeekArgString(-1) + + "' not mapped"); + } + + } else if (opt == "-testname") { // rmap -testname name + if (!args.GetArg("name", name)) return kERR; + if (!args.AllDone()) return kERR; + uint16_t tstaddr; + args.SetResult(int(lmap.Find(name, tstaddr))); + + } else if (opt == "-testaddr") { // rmap -testaddr addr + if (!args.GetArg("addr", addr)) return kERR; + if (!args.AllDone()) return kERR; + string tstname; + args.SetResult(int(lmap.Find(addr, tstname))); + + } else if (opt == "-insert") { // rmap -insert name addr + uint16_t tstaddr; + string tstname; + int tstint; + if (!args.GetArg("name", name)) return kERR; + // enforce that the name is not a valid representation of an int + if (Tcl_GetIntFromObj(nullptr, args[args.NDone()-1], &tstint) == kOK) + return args.Quit(string("-E: name should not look like an int but '")+ + name + "' does"); + if (!args.GetArg("addr", addr)) return kERR; + if (!args.AllDone()) return kERR; + if (lmap.Find(name, tstaddr)) + return args.Quit(string("-E: mapping already defined for '")+name+"'"); + if (lmap.Find(addr, tstname)) + return args.Quit(string("-E: mapping already defined for address '") + + args.PeekArgString(-1) + "'"); + Obj().RAddrMapInsert(name, addr); + + } else if (opt == "-erase") { // rmap -erase name + if (!args.GetArg("name", name)) return kERR; + if (!args.AllDone()) return kERR; + if (!Obj().RAddrMapErase(name)) + return args.Quit(string("-E: no mapping defined for '") + name + "'"); + + } else if (opt == "-print") { // rmap -print + if (!args.AllDone()) return kERR; + ostringstream sos; + lmap.Print(sos); + args.AppendResultLines(sos); + } + + } else { + if (!args.OptValid()) return kERR; + if (!args.GetArg("?name", name)) return kERR; + if (args.NOptMiss()==0) { // rmap name + uint16_t tstaddr; + if(lmap.Find(name, tstaddr)) { + args.SetResult(int(tstaddr)); + } else if(cmap.Find(name, tstaddr)) { + args.SetResult(int(tstaddr)); + } else { + return args.Quit(string("-E: no mapping defined for '") + name + "'"); + } + + } else { // rmap + RtclOPtr plist(Tcl_NewListObj(0, nullptr)); + const RlinkAddrMap::amap_t amap = lmap.Amap(); + for (RlinkAddrMap::amap_cit_t it=amap.begin(); it!=amap.end(); it++) { + Tcl_Obj* tpair[2]; + tpair[0] = Tcl_NewIntObj(it->first); + tpair[1] = Tcl_NewStringObj((it->second).c_str(),(it->second).length()); + Tcl_ListObjAppendElement(nullptr, plist, Tcl_NewListObj(2, tpair)); + } + args.SetResult(plist); + } + } + + return kOK; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + int RtclRw11Cpu::M_cp(RtclArgs& args) { - static RtclNameSet optset("-rr|-rr0|-rr1|-rr2|-rr3|-rr4|-rr5|-rr6|-rr7|" + static RtclNameSet optset("-rreg|-rblk|-wreg|-wblk|-labo|-attn|-init|" + "-rr|-rr0|-rr1|-rr2|-rr3|-rr4|-rr5|-rr6|-rr7|" "-wr|-wr0|-wr1|-wr2|-wr3|-wr4|-wr5|-wr6|-wr7|" "-rsp|-rpc|-wsp|-wpc|" "-rps|-wps|" "-ral|-rah|-wal|-wah|-wa|" - "-rm|-rmi|-wm|-wmi|-brm|-bwm|" - "-stapc|-start|-stop|-continue|-step|-reset|" - "-rmembe|-wmembe|-ribr|-wibr|" + "-rm|-rmi|-rma|-wm|-wmi|-wma|-brm|-bwm|" + "-start|-stop|-step|-creset|-breset|" + "-suspend|-resume|" + "-stapc|" + "-rmembe|-wmembe|-ribr|-rbibr|-wibr|-wbibr|" "-rconf|-rstat|" - "-edata|-edone|-estat|-estatdef|" - "-print|-dump|"); + "-edata|-edone|-estat|" + "-estaterr|-estatnak|-estattout|" + "-print|-dump"); Tcl_Interp* interp = args.Interp(); @@ -234,9 +345,6 @@ int RtclRw11Cpu::M_cp(RtclArgs& args) string varprint; string vardump; - uint8_t estatdef_val = 0x00; - uint8_t estatdef_msk = 0xff; - bool setcpugo = false; while (args.NextOpt(opt, optset)) { @@ -250,58 +358,107 @@ int RtclRw11Cpu::M_cp(RtclArgs& args) int regnum = 0; if (opt.substr(0,3) == "-rr" || opt.substr(0,3) == "-wr" ) { - if (opt.length() == 3) { + if (opt.length() == 3) { // -rr n or -wr n option if (!args.GetArg("regnum", regnum, 0, 7)) return kERR; - } else { + } else if (opt.length() == 4 && opt[3] >= '0' && opt[3] <= '7') { regnum = opt[3] - '0'; - regnum &= 0x7; // to be sure... + opt = opt.substr(0,3); } - opt = opt.substr(0,3); } - if (opt == "-rr") { // -rr* ?varData ?varStat -------- + if (opt == "-rreg") { // -rreg addr ?varData ?varStat --- + uint16_t addr; + if (!GetRAddr(args, addr)) return kERR; if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; - clist.AddRreg(base + Rw11Cpu::kCp_addr_r0 + regnum); + clist.AddRreg(addr); + + } else if (opt == "-rblk") { // -rblk addr size ?varData ?varStat + uint16_t addr; + int32_t bsize; + if (!GetRAddr(args, addr)) return kERR; + if (!args.GetArg("bsize", bsize, 1, Connect().BlockSizeMax())) return kERR; + if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; + if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; + clist.AddRblk(addr, (size_t) bsize); + + } else if (opt == "-wreg") { // -wreg addr data ?varStat ------- + uint16_t addr; + uint16_t data; + if (!GetRAddr(args, addr)) return kERR; + if (!args.GetArg("data", data)) return kERR; + if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; + clist.AddWreg(addr, data); + + } else if (opt == "-wblk") { // -wblk addr block ?varStat ------ + uint16_t addr; + vector block; + if (!GetRAddr(args, addr)) return kERR; + if (!args.GetArg("data", block, 1, Connect().BlockSizeMax())) return kERR; + if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; + clist.AddWblk(addr, block); + + } else if (opt == "-labo") { // -labo varData ?varStat --------- + if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; + if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; + clist.AddLabo(); + + } else if (opt == "-attn") { // -attn varData ?varStat --------- + if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; + if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; + clist.AddAttn(); + + } else if (opt == "-init") { // -init addr data ?varStat ------- + uint16_t addr; + uint16_t data; + if (!GetRAddr(args, addr)) return kERR; + if (!args.GetArg("data", data)) return kERR; + if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; + clist.AddInit(addr, data); + + } else if (opt == "-rr") { // -rr* ?varData ?varStat -------- + if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; + if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; + clist.AddRreg(base + Rw11Cpu::kCPR0 + regnum); } else if (opt == "-wr") { // -wr* data ?varStat ------------ uint16_t data; if (!args.GetArg("data", data)) return kERR; if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; - clist.AddWreg(base + Rw11Cpu::kCp_addr_r0 + regnum, data); + clist.AddWreg(base + Rw11Cpu::kCPR0 + regnum, data); } else if (opt == "-rps") { // -rps ?varData ?varStat -------- if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; - clist.AddRreg(base + Rw11Cpu::kCp_addr_psw); + clist.AddRreg(base + Rw11Cpu::kCPPSW); } else if (opt == "-wps") { // -wps data ?varStat ------------ uint16_t data; if (!args.GetArg("data", data)) return kERR; if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; - clist.AddWreg(base + Rw11Cpu::kCp_addr_psw, data); + clist.AddWreg(base + Rw11Cpu::kCPPSW, data); } else if (opt == "-ral") { // -ral ?varData ?varStat -------- if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; - clist.AddRreg(base + Rw11Cpu::kCp_addr_al); + clist.AddRreg(base + Rw11Cpu::kCPAL); } else if (opt == "-rah") { // -rah ?varData ?varStat -------- if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; - clist.AddRreg(base + Rw11Cpu::kCp_addr_ah); + clist.AddRreg(base + Rw11Cpu::kCPAH); } else if (opt == "-wal") { // -wal data ?varStat ------------ - uint16_t data; - if (!args.GetArg("al", data)) return kERR; + uint16_t ibaddr; + if (!GetIAddr(args, ibaddr)) return kERR; if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; - clist.AddWreg(base + Rw11Cpu::kCp_addr_al, data); + clist.AddWreg(base + Rw11Cpu::kCPAL, ibaddr); } else if (opt == "-wah") { // -wah data ?varStat ------------ uint16_t data; if (!args.GetArg("ah", data)) return kERR; if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; - clist.AddWreg(base + Rw11Cpu::kCp_addr_ah, data); + clist.AddWreg(base + Rw11Cpu::kCPAH, data); } else if (opt == "-wa") { // -wa addr ?varStat [-p22 -ubm]-- uint32_t addr; @@ -314,78 +471,106 @@ int RtclRw11Cpu::M_cp(RtclArgs& args) while (args.NextSubOpt(subopt, suboptset)>=0) { // loop for sub-options if (!args.OptValid()) return kERR; if (subopt == "-p22") { // -p22 - ah |= Rw11Cpu::kCp_ah_m_22bit; + ah |= Rw11Cpu::kCPAH_M_22BIT; } else if (subopt == "-ubm") { // -ubm - ah |= Rw11Cpu::kCp_ah_m_ubmap; + ah |= Rw11Cpu::kCPAH_M_UBMAP; } } - clist.AddWreg(base + Rw11Cpu::kCp_addr_al, al); - if (ah!=0) clist.AddWreg(base + Rw11Cpu::kCp_addr_ah, ah); + clist.AddWreg(base + Rw11Cpu::kCPAL, al); + if (ah!=0) clist.AddWreg(base + Rw11Cpu::kCPAH, ah); } else if (opt == "-rm" || // -rm(i) ?varData ?varStat ------ opt == "-rmi") { - uint16_t addr = opt=="-rm" ? Rw11Cpu::kCp_addr_mem : - Rw11Cpu::kCp_addr_memi; + uint16_t addr = opt=="-rm" ? Rw11Cpu::kCPMEM : + Rw11Cpu::kCPMEMI; if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; clist.AddRreg(base + addr); + } else if (opt == "-rma") { // -rma addr ?varData ?varStat --- + uint16_t ibaddr; + if (!GetIAddr(args, ibaddr)) return kERR; + // bind expects to memi access, which is second command + if (!GetVarName(args, "??varData", lsize+1, vardata)) return kERR; + if (!GetVarName(args, "??varStat", lsize+1, varstat)) return kERR; + clist.AddWreg(base + Rw11Cpu::kCPAL, ibaddr); + clist.AddRreg(base + Rw11Cpu::kCPMEMI); + } else if (opt == "-wm" || // -wm(i) data ?varStat - opt == "-wmi") { - uint16_t addr = opt=="-wm" ? Rw11Cpu::kCp_addr_mem : - Rw11Cpu::kCp_addr_memi; + uint16_t addr = opt=="-wm" ? Rw11Cpu::kCPMEM : + Rw11Cpu::kCPMEMI; uint16_t data; if (!args.GetArg("data", data)) return kERR; if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; clist.AddWreg(base + addr, data); + } else if (opt == "-wma") { // -wma addr data ?varStat ------- + uint16_t ibaddr; + uint16_t data; + if (!GetIAddr(args, ibaddr)) return kERR; + if (!args.GetArg("data", data)) return kERR; + // bind expects to memi access, which is second command + if (!GetVarName(args, "??varStat", lsize+1, varstat)) return kERR; + clist.AddWreg(base + Rw11Cpu::kCPAL, ibaddr); + clist.AddWreg(base + Rw11Cpu::kCPMEMI, data); + } else if (opt == "-brm") { // -brm size ?varData ?varStat --- int32_t bsize; if (!args.GetArg("bsize", bsize, 1, 256)) return kERR; if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; - clist.AddRblk(base + Rw11Cpu::kCp_addr_memi, (size_t) bsize); + clist.AddRblk(base + Rw11Cpu::kCPMEMI, (size_t) bsize); } else if (opt == "-bwm") { // -bwm block ?varStat ----------- vector block; if (!args.GetArg("data", block, 1, 256)) return kERR; if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; - clist.AddWblk(base + Rw11Cpu::kCp_addr_memi, block); + clist.AddWblk(base + Rw11Cpu::kCPMEMI, block); - } else if (opt == "-stapc") { // -stapc addr ?varStat ---------- - uint16_t data; - if (!args.GetArg("data", data)) return kERR; - if (!GetVarName(args, "??varStat", lsize+1, varstat)) return kERR; - clist.AddWreg(base + Rw11Cpu::kCp_addr_pc, data); - clist.AddWreg(base + Rw11Cpu::kCp_addr_cntl, Rw11Cpu::kCp_func_start); - setcpugo = true; - } else if (opt == "-start") { // -start ?varStat --------------- if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; - clist.AddWreg(base + Rw11Cpu::kCp_addr_cntl, Rw11Cpu::kCp_func_start); + clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_START); setcpugo = true; } else if (opt == "-stop") { // -stop ?varStat ---------------- if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; - clist.AddWreg(base + Rw11Cpu::kCp_addr_cntl, Rw11Cpu::kCp_func_stop); - - } else if (opt == "-continue") { // -continue ?varStat ------------ - if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; - clist.AddWreg(base + Rw11Cpu::kCp_addr_cntl, Rw11Cpu::kCp_func_cont); - setcpugo = true; + clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_STOP); } else if (opt == "-step") { // -step ?varStat ---------------- if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; - clist.AddWreg(base + Rw11Cpu::kCp_addr_cntl, Rw11Cpu::kCp_func_step); + clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_STEP); - } else if (opt == "-reset") { // -reset ?varStat --------------- + } else if (opt == "-creset") { // -creset ?varStat -------------- if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; - clist.AddWreg(base + Rw11Cpu::kCp_addr_cntl, Rw11Cpu::kCp_func_reset); + clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_CRESET); + + } else if (opt == "-breset") { // -breset ?varStat -------------- + if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; + clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_BRESET); + + } else if (opt == "-suspend") { // -suspend ?varStat ------------- + if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; + clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_SUSPEND); + + } else if (opt == "-resume") { // -resume ?varStat -------------- + if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; + clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_RESUME); + + } else if (opt == "-stapc") { // -stapc addr ?varStat ---------- + uint16_t data; + if (!args.GetArg("data", data)) return kERR; + if (!GetVarName(args, "??varStat", lsize+1, varstat)) return kERR; + clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_STOP); + clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_CRESET); + clist.AddWreg(base + Rw11Cpu::kCPPC, data); + clist.AddWreg(base + Rw11Cpu::kCPCNTL, Rw11Cpu::kCPFUNC_START); + setcpugo = true; } else if (opt == "-rmembe") { // -rmembe ?varData ?varStat ------ if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; - clist.AddRreg(base + Rw11Cpu::kCp_addr_membe); + clist.AddRreg(base + Rw11Cpu::kCPMEMBE); } else if (opt == "-wmembe") { // -wmembe be ?varStat [-stick] - uint16_t be; @@ -403,14 +588,23 @@ int RtclRw11Cpu::M_cp(RtclArgs& args) } Obj().AddMembe(clist, be, stick); - } else if (opt == "-ribr") { // -ribr off ?varData ?varStat ---- + } else if (opt == "-ribr") { // -ribr iba ?varData ?varStat ---- uint16_t ibaddr; if (!GetIAddr(args, ibaddr)) return kERR; if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; Obj().AddRibr(clist, ibaddr); - } else if (opt == "-wibr") { // -wibr off data ?varStat -------- + } else if (opt == "-rbibr") { // -rbibr iba size ?varData ?varStat + uint16_t ibaddr; + int32_t bsize; + if (!GetIAddr(args, ibaddr)) return kERR; + if (!args.GetArg("bsize", bsize, 1, Connect().BlockSizeMax())) return kERR; + if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; + if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; + Obj().AddRbibr(clist, ibaddr, (size_t) bsize); + + } else if (opt == "-wibr") { // -wibr iba data ?varStat -------- uint16_t ibaddr; uint16_t data; if (!GetIAddr(args, ibaddr)) return kERR; @@ -418,77 +612,80 @@ int RtclRw11Cpu::M_cp(RtclArgs& args) if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; Obj().AddWibr(clist, ibaddr, data); + } else if (opt == "-wbibr") { // -wbibr iba block data ?varStat - + uint16_t ibaddr; + vector block; + if (!GetIAddr(args, ibaddr)) return kERR; + if (!args.GetArg("data", block, 1, Connect().BlockSizeMax())) return kERR; + if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; + Obj().AddWbibr(clist, ibaddr, block); + } else if (opt == "-rconf") { // -rconf ?varData ?varStat ------ if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; - clist.AddRreg(base + Rw11Cpu::kCp_addr_conf); + clist.AddRreg(base + Rw11Cpu::kCPCONF); } else if (opt == "-rstat") { // -rstat ?varData ?varStat ------ if (!GetVarName(args, "??varData", lsize, vardata)) return kERR; if (!GetVarName(args, "??varStat", lsize, varstat)) return kERR; - clist.AddRreg(base + Rw11Cpu::kCp_addr_stat); + clist.AddRreg(base + Rw11Cpu::kCPSTAT); } else if (opt == "-edata") { // -edata data ?mask -------------- - if (lsize == 0) - return args.Quit("-E: -edata not allowed on empty command list"); - if (clist[lsize-1].Expect()==0) { - clist[lsize-1].SetExpect(new RlinkCommandExpect(estatdef_val, - estatdef_msk)); - } + if (!ClistNonEmpty(args, clist)) return kERR; if (clist[lsize-1].Command() == RlinkCommand::kCmdRblk) { vector data; vector mask; size_t bsize = clist[lsize-1].BlockSize(); if (!args.GetArg("data", data, 0, bsize)) return kERR; if (!args.GetArg("??mask", mask, 0, bsize)) return kERR; - clist[lsize-1].Expect()->SetBlock(data, mask); + clist.SetLastExpectBlock(data, mask); } else { uint16_t data=0; - uint16_t mask=0; + uint16_t mask=0xffff; if (!args.GetArg("data", data)) return kERR; if (!args.GetArg("??mask", mask)) return kERR; - clist[lsize-1].Expect()->SetData(data, mask); + clist.SetLastExpectData(data, mask); } } else if (opt == "-edone") { // -edone done -------------------- - if (lsize == 0) - return args.Quit("-E: -edone not allowed on empty command list"); + if (!ClistNonEmpty(args, clist)) return kERR; uint16_t done=0; if (!args.GetArg("done", done)) return kERR; - if (clist[lsize-1].Expect()==0) { - clist[lsize-1].SetExpect(new RlinkCommandExpect(estatdef_val, - estatdef_msk)); - } uint8_t cmd = clist[lsize-1].Command(); if (cmd == RlinkCommand::kCmdRblk || cmd == RlinkCommand::kCmdWblk) { - clist[lsize-1].Expect()->SetDone(done); + clist.SetLastExpectDone(done); } else { return args.Quit("-E: -edone allowed only after -rblk,-wblk"); } - } else if (opt == "-estat") { // -estat ?stat ?mask ------------- - if (lsize == 0) - return args.Quit("-E: -estat not allowed on empty command list"); + } else if (opt == "-estat") { // -estat stat ?mask -------------- + if (!ClistNonEmpty(args, clist)) return kERR; uint8_t stat=0; - uint8_t mask=0; - if (!args.GetArg("??stat", stat)) return kERR; + uint8_t mask=0xff; + if (!args.GetArg("stat", stat)) return kERR; if (!args.GetArg("??mask", mask)) return kERR; - if (args.NOptMiss() == 2) mask = 0xff; - if (clist[lsize-1].Expect()==0) { - clist[lsize-1].SetExpect(new RlinkCommandExpect()); + clist.SetLastExpectStatus(stat, mask); + + } else if (opt == "-estaterr" || // -estaterr ---------------------- + opt == "-estatnak" || // -estatnak ---------------------- + opt == "-estattout" || // -estattout --------------------- + opt == "-estatmerr") { // -estatmerr --------------------- + if (!ClistNonEmpty(args, clist)) return kERR; + uint8_t val = 0; + uint8_t msk = RlinkCommand::kStat_M_RbTout | + RlinkCommand::kStat_M_RbNak | + RlinkCommand::kStat_M_RbErr; + if (opt == "-estaterr") val = RlinkCommand::kStat_M_RbErr; + if (opt == "-estatnak") val = RlinkCommand::kStat_M_RbNak; + if (opt == "-estattout") val = RlinkCommand::kStat_M_RbTout; + if (opt == "-estatmerr") { + val = Rw11Cpu::kStat_M_CmdMErr; + msk |= Rw11Cpu::kStat_M_CmdMErr | + Rw11Cpu::kStat_M_CmdErr; } - clist[lsize-1].Expect()->SetStatus(stat, mask); - - } else if (opt == "-estatdef") { // -estatdef ?stat ?mask ----------- - uint8_t stat=0; - uint8_t mask=0; - if (!args.GetArg("??stat", stat)) return kERR; - if (!args.GetArg("??mask", mask)) return kERR; - if (args.NOptMiss() == 2) mask = 0xff; - estatdef_val = stat; - estatdef_msk = mask; - + clist.SetLastExpectStatus(val, msk); + } else if (opt == "-print") { // -print ?varRes ----------------- varprint = "-"; if (!args.GetArg("??varRes", varprint)) return kERR; @@ -497,17 +694,7 @@ int RtclRw11Cpu::M_cp(RtclArgs& args) if (!args.GetArg("??varRes", vardump)) return kERR; } - if (estatdef_msk != 0xff && // estatdef defined - lsize != clist.Size()) { // and cmd added to clist - for (size_t i=lsize; i lock(Connect()); RlinkCommandList clist; - clist.AddWreg(base + Rw11Cpu::kCp_addr_al, 0177572); - clist.AddRblk(base + Rw11Cpu::kCp_addr_memi, mmr, 3); - clist.AddWreg(base + Rw11Cpu::kCp_addr_al, 0172516); - clist.AddRblk(base + Rw11Cpu::kCp_addr_memi, mmr+3, 1); + clist.AddWreg(base + Rw11Cpu::kCPAL, 0177572); + clist.AddRblk(base + Rw11Cpu::kCPMEMI, mmr, 3); + clist.AddWreg(base + Rw11Cpu::kCPAL, 0172516); + clist.AddRblk(base + Rw11Cpu::kCPMEMI, mmr+3, 1); if (!Server().Exec(clist, emsg)) return args.Quit(emsg); clist.Clear(); - clist.AddWreg(base + Rw11Cpu::kCp_addr_al, 0172300); - clist.AddRblk(base + Rw11Cpu::kCp_addr_memi, asr[0], 32); - clist.AddWreg(base + Rw11Cpu::kCp_addr_al, 0172200); - clist.AddRblk(base + Rw11Cpu::kCp_addr_memi, asr[1], 32); - clist.AddWreg(base + Rw11Cpu::kCp_addr_al, 0177600); - clist.AddRblk(base + Rw11Cpu::kCp_addr_memi, asr[2], 32); + clist.AddWreg(base + Rw11Cpu::kCPAL, 0172300); + clist.AddRblk(base + Rw11Cpu::kCPMEMI, asr[0], 32); + clist.AddWreg(base + Rw11Cpu::kCPAL, 0172200); + clist.AddRblk(base + Rw11Cpu::kCPMEMI, asr[1], 32); + clist.AddWreg(base + Rw11Cpu::kCPAL, 0177600); + clist.AddRblk(base + Rw11Cpu::kCPMEMI, asr[2], 32); if (!Server().Exec(clist, emsg)) return args.Quit(emsg); } uint16_t mmr1_0_reg = (mmr[1] ) & 07; @@ -1164,8 +1351,8 @@ int RtclRw11Cpu::M_show(RtclArgs& args) } else if (opt == "-ubmap") { uint16_t ubmap[64]; RlinkCommandList clist; - clist.AddWreg(base + Rw11Cpu::kCp_addr_al, 0170200); - clist.AddRblk(base + Rw11Cpu::kCp_addr_memi, ubmap, 64); + clist.AddWreg(base + Rw11Cpu::kCPAL, 0170200); + clist.AddRblk(base + Rw11Cpu::kCPMEMI, ubmap, 64); if (!Server().Exec(clist, emsg)) return args.Quit(emsg); sos << "unibus map:" << endl; for (size_t i = 0; i<=7; i++) { @@ -1287,6 +1474,43 @@ bool RtclRw11Cpu::GetIAddr(RtclArgs& args, uint16_t& ibaddr) //------------------------------------------+----------------------------------- //! FIXME_docs +bool RtclRw11Cpu::GetRAddr(RtclArgs& args, uint16_t& rbaddr) +{ + Tcl_Obj* pobj=0; + if (!args.GetArg("rbaddr", pobj)) return kERR; + + int tstint; + // if a number is given.. + if (Tcl_GetIntFromObj(nullptr, pobj, &tstint) == kOK) { + if (tstint >= 0 && tstint <= 0xffff) { + rbaddr = (uint16_t)tstint; + } else { + args.AppendResult("-E: value '", Tcl_GetString(pobj), + "' for 'addr' out of range 0...0xffff", + nullptr); + return false; + } + // if a name is given + } else { + string name(Tcl_GetString(pobj)); + uint16_t tstaddr; + if (Obj().RAddrMap().Find(name, tstaddr)) { + rbaddr = tstaddr; + } else if (Connect().AddrMap().Find(name, tstaddr)) { + rbaddr = tstaddr; + } else { + args.AppendResult("-E: no address mapping known for '", + Tcl_GetString(pobj), "'", nullptr); + return false; + } + } + + return true; +} + +//------------------------------------------+----------------------------------- +//! FIXME_docs + bool RtclRw11Cpu::GetVarName(RtclArgs& args, const char* argname, size_t nind, std::vector& varname) @@ -1307,4 +1531,17 @@ bool RtclRw11Cpu::GetVarName(RtclArgs& args, const char* argname, return true; } +//------------------------------------------+----------------------------------- +//! FIXME_docs + +bool RtclRw11Cpu::ClistNonEmpty(RtclArgs& args, const RlinkCommandList& clist) +{ + if (clist.Size() == 0) { + args.AppendResult("-E: -edata, -edone, or -estat " + "not allowed on empty command list", nullptr); + return false; + } + return true; +} + } // end namespace Retro diff --git a/tools/src/librwxxtpp/RtclRw11Cpu.hpp b/tools/src/librwxxtpp/RtclRw11Cpu.hpp index 136e7612..e8906767 100644 --- a/tools/src/librwxxtpp/RtclRw11Cpu.hpp +++ b/tools/src/librwxxtpp/RtclRw11Cpu.hpp @@ -1,6 +1,6 @@ -// $Id: RtclRw11Cpu.hpp 621 2014-12-26 21:20:05Z mueller $ +// $Id: RtclRw11Cpu.hpp 661 2015-04-03 18:28:41Z mueller $ // -// Copyright 2013-2014 by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,6 +13,8 @@ // // Revision History: // Date Rev Version Comment +// 2015-04-03 661 1.0.4 add ClistNonEmpty() +// 2015-03-21 659 1.0.3 rename M_amap->M_imap; add M_rmap; add GetRAddr() // 2014-12-25 621 1.0.2 add M_amap // 2013-04-26 511 1.0.1 add M_show // 2013-04-02 502 1.0 Initial version @@ -22,7 +24,7 @@ /*! \file - \version $Id: RtclRw11Cpu.hpp 621 2014-12-26 21:20:05Z mueller $ + \version $Id: RtclRw11Cpu.hpp 661 2015-04-03 18:28:41Z mueller $ \brief Declaration of class RtclRw11Cpu. */ @@ -52,7 +54,8 @@ namespace Retro { protected: int M_add(RtclArgs& args); - int M_amap(RtclArgs& args); + int M_imap(RtclArgs& args); + int M_rmap(RtclArgs& args); int M_cp(RtclArgs& args); int M_wtcpu(RtclArgs& args); int M_deposit(RtclArgs& args); @@ -74,8 +77,11 @@ namespace Retro { RlinkConnect& Connect(); bool GetIAddr(RtclArgs& args, uint16_t& ibaddr); + bool GetRAddr(RtclArgs& args, uint16_t& rbaddr); bool GetVarName(RtclArgs& args, const char* argname, size_t nind, std::vector& varname); + bool ClistNonEmpty(RtclArgs& args, + const RlinkCommandList& clist); protected: RtclGetList fGets; diff --git a/tools/src/librwxxtpp/RtclRw11UnitBase.ipp b/tools/src/librwxxtpp/RtclRw11UnitBase.ipp index 6ac293ea..c6672fd4 100644 --- a/tools/src/librwxxtpp/RtclRw11UnitBase.ipp +++ b/tools/src/librwxxtpp/RtclRw11UnitBase.ipp @@ -1,6 +1,6 @@ -// $Id: RtclRw11UnitBase.ipp 504 2013-04-13 15:37:24Z mueller $ +// $Id: RtclRw11UnitBase.ipp 680 2015-05-14 13:29:46Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,13 +13,14 @@ // // Revision History: // Date Rev Version Comment +// 2015-05-14 680 1.1 fGets: add enabled (moved from RtclRw11UnitDisk) // 2013-03-06 495 1.0 Initial version // 2013-02-16 488 0.1 First draft // --------------------------------------------------------------------------- /*! \file - \version $Id: RtclRw11UnitBase.ipp 504 2013-04-13 15:37:24Z mueller $ + \version $Id: RtclRw11UnitBase.ipp 680 2015-05-14 13:29:46Z mueller $ \brief Implemenation (all inline) of RtclRw11UnitBase. */ @@ -44,8 +45,9 @@ inline RtclRw11UnitBase::RtclRw11UnitBase(const std::string& type, { AddMeth("stats", boost::bind(&RtclRw11UnitBase::M_stats, this, _1)); TO* pobj = fspObj.get(); - fGets.Add ("index", boost::bind(&TO::Index, pobj)); - fGets.Add ("name", boost::bind(&TO::Name, pobj)); + fGets.Add ("index", boost::bind(&TO::Index, pobj)); + fGets.Add ("name", boost::bind(&TO::Name, pobj)); + fGets.Add ("enabled", boost::bind(&TO::Enabled, pobj)); } //------------------------------------------+----------------------------------- diff --git a/tools/src/librwxxtpp/RtclRw11UnitDisk.cpp b/tools/src/librwxxtpp/RtclRw11UnitDisk.cpp index 21c502fb..98edc5c5 100644 --- a/tools/src/librwxxtpp/RtclRw11UnitDisk.cpp +++ b/tools/src/librwxxtpp/RtclRw11UnitDisk.cpp @@ -1,6 +1,6 @@ -// $Id: RtclRw11UnitDisk.cpp 509 2013-04-21 20:46:20Z mueller $ +// $Id: RtclRw11UnitDisk.cpp 680 2015-05-14 13:29:46Z mueller $ // -// Copyright 2013- by Walter F.J. Mueller +// Copyright 2013-2015 by Walter F.J. Mueller // // This program is free software; you may redistribute and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -13,13 +13,15 @@ // // Revision History: // Date Rev Version Comment +// 2015-05-14 680 1.1.1 fGets: remove enabled, now in RtclRw11UnitBase +// 2015-03-21 659 1.1 fGets: add enabled // 2013-04-19 507 1.0 Initial version // 2013-02-22 490 0.1 First draft // --------------------------------------------------------------------------- /*! \file - \version $Id: RtclRw11UnitDisk.cpp 509 2013-04-21 20:46:20Z mueller $ + \version $Id: RtclRw11UnitDisk.cpp 680 2015-05-14 13:29:46Z mueller $ \brief Implemenation of RtclRw11UnitDisk. */ diff --git a/tools/src/librwxxtpp/RtclRw11UnitRHRP.cpp b/tools/src/librwxxtpp/RtclRw11UnitRHRP.cpp new file mode 100644 index 00000000..625458ca --- /dev/null +++ b/tools/src/librwxxtpp/RtclRw11UnitRHRP.cpp @@ -0,0 +1,56 @@ +// $Id: RtclRw11UnitRHRP.cpp 680 2015-05-14 13:29:46Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-14 680 1.0 Initial version +// 2015-03-21 659 0.1 First draft +// --------------------------------------------------------------------------- + +/*! + \file + \version $Id: RtclRw11UnitRHRP.cpp 680 2015-05-14 13:29:46Z mueller $ + \brief Implemenation of RtclRw11UnitRHRP. +*/ + +#include "RtclRw11UnitRHRP.hpp" + +using namespace std; + +/*! + \class Retro::RtclRw11UnitRHRP + \brief FIXME_docs +*/ + +// all method definitions in namespace Retro +namespace Retro { + +//------------------------------------------+----------------------------------- +//! Constructor + +RtclRw11UnitRHRP::RtclRw11UnitRHRP( + Tcl_Interp* interp, const std::string& unitcmd, + const boost::shared_ptr& spunit) + : RtclRw11UnitBase("Rw11UnitRHRP", spunit), + RtclRw11UnitDisk(this, spunit.get()) +{ + CreateObjectCmd(interp, unitcmd.c_str()); +} + +//------------------------------------------+----------------------------------- +//! Destructor + +RtclRw11UnitRHRP::~RtclRw11UnitRHRP() +{} + +} // end namespace Retro diff --git a/tools/src/librwxxtpp/RtclRw11UnitRHRP.hpp b/tools/src/librwxxtpp/RtclRw11UnitRHRP.hpp new file mode 100644 index 00000000..65e93ffd --- /dev/null +++ b/tools/src/librwxxtpp/RtclRw11UnitRHRP.hpp @@ -0,0 +1,53 @@ +// $Id: RtclRw11UnitRHRP.hpp 680 2015-05-14 13:29:46Z mueller $ +// +// Copyright 2015- by Walter F.J. Mueller +// +// This program is free software; you may redistribute and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation, either version 2, or at your option any later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for complete details. +// +// Revision History: +// Date Rev Version Comment +// 2015-05-14 680 1.0 Initial version +// 2015-03-21 659 0.1 First draft +// --------------------------------------------------------------------------- + + +/*! + \file + \version $Id: RtclRw11UnitRHRP.hpp 680 2015-05-14 13:29:46Z mueller $ + \brief Declaration of class RtclRw11UnitRHRP. +*/ + +#ifndef included_Retro_RtclRw11UnitRHRP +#define included_Retro_RtclRw11UnitRHRP 1 + +#include "librw11/Rw11UnitRHRP.hpp" +#include "librw11/Rw11CntlRHRP.hpp" + +#include "RtclRw11UnitDisk.hpp" +#include "RtclRw11UnitBase.hpp" + +namespace Retro { + + class RtclRw11UnitRHRP : public RtclRw11UnitBase, + public RtclRw11UnitDisk { + public: + RtclRw11UnitRHRP(Tcl_Interp* interp, + const std::string& unitcmd, + const boost::shared_ptr& spunit); + ~RtclRw11UnitRHRP(); + + protected: + }; + +} // end namespace Retro + +//#include "RtclRw11UnitRHRP.ipp" + +#endif diff --git a/tools/tbench/rhrp_all.dat b/tools/tbench/rhrp_all.dat new file mode 100644 index 00000000..91757a04 --- /dev/null +++ b/tools/tbench/rhrp_all.dat @@ -0,0 +1,8 @@ +# $Id: rhrp_all.dat 668 2015-04-25 14:31:19Z mueller $ +# +## steering file for all rhrp tests +# +test_rhrp_basics.tcl +test_rhrp_regs.tcl +test_rhrp_func_reg.tcl +test_rhrp_int.tcl diff --git a/tools/tbench/test_cp_cpubasics.tcl b/tools/tbench/test_cp_cpubasics.tcl index daeb6a4a..77edbc55 100644 --- a/tools/tbench/test_cp_cpubasics.tcl +++ b/tools/tbench/test_cp_cpubasics.tcl @@ -1,21 +1,24 @@ -# $Id: test_cp_cpubasics.tcl 552 2014-03-02 23:02:00Z mueller $ +# $Id: test_cp_cpubasics.tcl 676 2015-05-09 16:31:54Z mueller $ # -# Copyright 2013- by Walter F.J. Mueller +# Copyright 2013-2015 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory # # Revision History: # Date Rev Version Comment +# 2015-05-09 676 1.1 w11a start/stop/suspend overhaul # 2013-03-31 502 1.0 Initial version # # Test very basic cpu interface gymnastics # 1. load code via ldasm -# 2. execute code via -start, -stapc, -continue +# 2. execute code via -start, -stapc # 3. single step code via -step +# 4. verify -suspend, -resume # # ---------------------------------------------------------------------------- -rlc log "test_cp_cpubasics: Test very basic cpu interface gymnastics" -rlc log " load code via lsasm" +rlc log "test_cp_cpubasics: Test very basic cpu interface gymnastics ---------" +rlc log " A1: start/stop/step basics --------------------------------" +rlc log " load simple linear code via lsasm" # $cpu ldasm -lst lst -sym sym { @@ -27,11 +30,11 @@ start: inc r2 stop: } -rlc log " read back and check" +rlc log " read back and check" $cpu cp -wal $sym(start) \ -brm 4 -edata {0005202 0005202 0005202 0000000} -rlc log " execute via -start" +rlc log " execute via -start" $cpu cp -wr2 00000 \ -wpc $sym(start) \ -start @@ -39,29 +42,93 @@ $cpu wtcpu -reset 1.0 $cpu cp -rr2 -edata 00003 \ -rpc -edata $sym(stop) -rlc log " execute via -stapc" +rlc log " execute via -stapc" $cpu cp -wr2 00100 \ -stapc $sym(start) $cpu wtcpu -reset 1.0 $cpu cp -rr2 -edata 00103 \ -rpc -edata $sym(stop) -rlc log " execute via -continue" -$cpu cp -wr2 00200 \ - -wpc $sym(start) \ - -continue -$cpu wtcpu -reset 1.0 -$cpu cp -rr2 -edata 00203 \ - -rpc -edata $sym(stop) - -rlc log " execute via -step" -$cpu cp -wr2 00300 \ +rlc log " execute via -step" +$cpu cp -wr2 00300 \ -wpc $sym(start) -$cpu cp -step -rpc -edata [expr {$sym(start)+002}] \ - -rr2 -edata 00301 -rstat -edata 000100 -$cpu cp -step -rpc -edata [expr {$sym(start)+004}] \ - -rr2 -edata 00302 -rstat -edata 000100 -$cpu cp -step -rpc -edata [expr {$sym(start)+006}] \ - -rr2 -edata 00303 -rstat -edata 000100 -$cpu cp -step -rpc -edata [expr {$sym(start)+010}] \ - -rr2 -edata 00303 -rstat -edata 000030 +$cpu cp -step \ + -rpc -edata [expr {$sym(start)+002}] \ + -rr2 -edata 00301 \ + -rstat -edata 000100 +$cpu cp -step \ + -rpc -edata [expr {$sym(start)+004}] \ + -rr2 -edata 00302 \ + -rstat -edata 000100 +$cpu cp -step \ + -rpc -edata [expr {$sym(start)+006}] \ + -rr2 -edata 00303 \ + -rstat -edata 000100 +$cpu cp -step \ + -rpc -edata [expr {$sym(start)+010}] \ + -rr2 -edata 00303 \ + -rstat -edata 000020 + +rlc log " A2: suspend/resume basics; cpugo,cpususp flags ------------" +# define tmpproc for r2 increment checks +proc tmpproc_checkr2inc {val} { + set emsg "" + if {$val == 0} { + set emsg "FAIL: r2 change zero" + rlc errcnt -inc + } + rlc log -bare ".. r2 increment $val $emsg" +} + +# +rlc log " load simple loop code via lsasm" +$cpu ldasm -lst lst -sym sym { + . = 1000 +start: inc r2 + br start +stop: +} + +set statgo [regbld rw11::STAT cpugo] +set statgosu [regbld rw11::STAT cpususp cpugo] + +rlc log " execute via -stapc, check cpugo and that r2 increments" +$cpu cp -wr2 00000 \ + -stapc $sym(start) \ + -rr2 rr2_1 -estat $statgo \ + -rr2 rr2_2 -estat $statgo +tmpproc_checkr2inc $rr2_1 +tmpproc_checkr2inc [expr {$rr2_2 - $rr2_1}] + +rlc log " suspend, check cpususp=1 and that r2 doesn't increment" +$cpu cp -suspend \ + -wr2 00000 \ + -rr2 -edata 0 -estat $statgosu \ + -rr2 -edata 0 -estat $statgosu + +rlc log " resume, check cpususp=0 and that r2 increments again" +$cpu cp -resume \ + -rr2 rr2_1 -estat $statgo \ + -rr2 rr2_2 -estat $statgo +tmpproc_checkr2inc $rr2_1 +tmpproc_checkr2inc [expr {$rr2_2 - $rr2_1}] + +rlc log " suspend than step, two steps should inc r2 once" +$cpu cp -suspend \ + -wr2 00000 \ + -step \ + -step \ + -rr2 -edata 1 \ + -step \ + -step \ + -rr2 -edata 2 + +rlc log " stop while suspended, check cpugo=0,cpususp=1,attn=1; harvest attn" +$cpu cp -stop -estat [regbld rw11::STAT cpususp attn] +$cpu wtcpu -reset 1.0 + +rlc log " creset, check cpususp=0" +# Note: creset still has cpususp stat flag set because it clears with one +# cycle delay. So do -estat after next command +$cpu cp -creset \ + -rr2 -estat 0 diff --git a/tools/tbench/test_cp_gpr.tcl b/tools/tbench/test_cp_gpr.tcl index e58b0ffe..76106b0d 100644 --- a/tools/tbench/test_cp_gpr.tcl +++ b/tools/tbench/test_cp_gpr.tcl @@ -1,4 +1,4 @@ -# $Id: test_cp_gpr.tcl 552 2014-03-02 23:02:00Z mueller $ +# $Id: test_cp_gpr.tcl 676 2015-05-09 16:31:54Z mueller $ # # Copyright 2013- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory @@ -14,7 +14,7 @@ # # ---------------------------------------------------------------------------- -rlc log "test_cp_gpr: test cp access to general purpose registers" +rlc log "test_cp_gpr: test cp access to general purpose registers ------------" rlc log " write set 0" $cpu cp -wps 0000000 $cpu cp -wr0 0000001 \ diff --git a/tools/tbench/test_cp_ibrbasics.tcl b/tools/tbench/test_cp_ibrbasics.tcl index 9cf2b137..361d669d 100644 --- a/tools/tbench/test_cp_ibrbasics.tcl +++ b/tools/tbench/test_cp_ibrbasics.tcl @@ -1,4 +1,4 @@ -# $Id: test_cp_ibrbasics.tcl 621 2014-12-26 21:20:05Z mueller $ +# $Id: test_cp_ibrbasics.tcl 676 2015-05-09 16:31:54Z mueller $ # # Copyright 2014- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory @@ -13,7 +13,7 @@ # # ---------------------------------------------------------------------------- -rlc log "test_cp_ibrbasics: Test very basic ibus interface gymnastics" +rlc log "test_cp_ibrbasics: Test very basic ibus interface gymnastics --------" rlc log " write/read ibus space (MMU SAR SM I regs) via bwm/brm" $cpu cp -wal 0172240 \ diff --git a/tools/tbench/test_cp_membasics.tcl b/tools/tbench/test_cp_membasics.tcl index 6b6b75bd..68cf50f6 100644 --- a/tools/tbench/test_cp_membasics.tcl +++ b/tools/tbench/test_cp_membasics.tcl @@ -1,4 +1,4 @@ -# $Id: test_cp_membasics.tcl 621 2014-12-26 21:20:05Z mueller $ +# $Id: test_cp_membasics.tcl 676 2015-05-09 16:31:54Z mueller $ # # Copyright 2014- by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory @@ -14,7 +14,7 @@ # # ---------------------------------------------------------------------------- -rlc log "test_cp_membasics: Test very basic memory interface gymnastics" +rlc log "test_cp_membasics: Test very basic memory interface gymnastics ------" # -------------------------------------------------------------------- rlc log " write/read address register" diff --git a/tools/tbench/test_cp_psw.tcl b/tools/tbench/test_cp_psw.tcl index 8136763e..ea11b577 100644 --- a/tools/tbench/test_cp_psw.tcl +++ b/tools/tbench/test_cp_psw.tcl @@ -1,4 +1,4 @@ -# $Id: test_cp_psw.tcl 621 2014-12-26 21:20:05Z mueller $ +# $Id: test_cp_psw.tcl 676 2015-05-09 16:31:54Z mueller $ # # Copyright 2013-2014 by Walter F.J. Mueller # License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory @@ -18,7 +18,7 @@ # # ---------------------------------------------------------------------------- -rlc log "test_cp_psw: test psw access via all methods" +rlc log "test_cp_psw: test psw access via all methods ------------------------" rlc log " write/read via cp" foreach w { 000000 000017 } { $cpu cp -wps $w \ diff --git a/tools/tbench/test_rhrp_basics.tcl b/tools/tbench/test_rhrp_basics.tcl new file mode 100644 index 00000000..24a0501d --- /dev/null +++ b/tools/tbench/test_rhrp_basics.tcl @@ -0,0 +1,200 @@ +# $Id: test_rhrp_basics.tcl 667 2015-04-18 20:16:05Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-03-29 660 1.0 Initial version +# +# Test basic access +# 1. ibus/rbus ack (for cs1:cs3) and no ack (cs3+2) +# 2. unit enable/disable and cs2.ned response +# 3. drive type logic +# 4. readability of all regs (enabled and diabled unit, check cs2.ned) + +# ---------------------------------------------------------------------------- +rlc log "test_rhrp_basics: basic access tests --------------------------------" +rlc log " setup context" +package require ibd_rhrp +ibd_rhrp::setup + +rlc set statmask $rw11::STAT_DEFMASK +rlc set statvalue 0 + +rlc log " A1: test that cs1,cs3 give ack, cs3+2 gives no ack --------" + +set iaddrfail [expr {[cpu0 imap rpa.cs3] + 2}] + +rlc log " A1.1: rem read cs1,cs3,cs3+1 -----------------------" + +$cpu cp -ribr rpa.cs1 \ + -ribr rpa.cs3 \ + -ribr $iaddrfail -estaterr + +rlc log " A1.2: loc read cs1,cs3,cs3+1 -----------------------" + +$cpu cp -rma rpa.cs1 \ + -rma rpa.cs3 \ + -rma $iaddrfail -estaterr + +rlc log " A2: test unit enable, dt and cs2.ned ----------------------" +rlc log " A2.1: disable unit 0 -------------------------------" + +# +# select rem and loc unit 0; disable unit +$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \ + -wibr rpa.ds [regbld ibd_rhrp::DS {dpr 0}] \ + -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] + +rlc log " A2.2: check dt read and cs2.ned --------------------" +set cs2ned [regbld ibd_rhrp::CS2 ned] +$cpu cp -wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ + -rma rpa.dt \ + -rma rpa.cs2 -edata $cs2ned $cs2ned + +rlc log " A2.3: enable unit 0 as RP06; check cs2.ned, dt -----" + +# check for cs2.ned=0 response on dt read (after cs1.tre=1) +# unit 0 selected rem and loc from previous section +$cpu cp -wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1}] \ + -wibr rpa.dt $ibd_rhrp::DTE_RP06 \ + -wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ + -rma rpa.dt -edata $ibd_rhrp::DT_RP06 \ + -rma rpa.cs2 -edata 0 $cs2ned + +rlc log " A3: set drive types, check proper dt response -------------" + +# dte dt +set tbl [list $ibd_rhrp::DTE_RP04 $ibd_rhrp::DT_RP04 \ + $ibd_rhrp::DTE_RP06 $ibd_rhrp::DT_RP06 \ + $ibd_rhrp::DTE_RM04 $ibd_rhrp::DT_RM04 \ + $ibd_rhrp::DTE_RM80 $ibd_rhrp::DT_RM80 \ + $ibd_rhrp::DTE_RM05 $ibd_rhrp::DT_RM05 \ + $ibd_rhrp::DTE_RP07 $ibd_rhrp::DT_RP07 ] + +# unit 0 enabled and selected rem and loc from previous section +foreach {dte dt} $tbl { + $cpu cp -wibr rpa.dt $dte \ + -ribr rpa.dt -edata $dte \ + -rma rpa.dt -edata $dt +} + +rlc log " A4: check unit selection and that units are distinct ------" + +rlc log " A4.1: setup units: 0: RP04 1:off 2:RP06 3:off ------" + +# unit dpr dte dt +set tbl [list 0 1 $ibd_rhrp::DTE_RP04 $ibd_rhrp::DT_RP04 \ + 1 0 0 0 \ + 2 1 $ibd_rhrp::DTE_RP06 $ibd_rhrp::DT_RP06 \ + 3 0 0 0] + +foreach {unit dpr dte dt} $tbl { + $cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit $unit] \ + -wibr rpa.ds [regbld ibd_rhrp::DS [list dpr $dpr]] \ + -wibr rpa.dt $dte +} + +rlc log " A4.2: readback dt rem and loc; check cs2.ned -------" + +set dsmsk [regbld ibd_rhrp::DS dpr] +set cs2msk [regbld ibd_rhrp::CS2 ned {unit 3}] +foreach {unit dpr dte dt} $tbl { + set dsval [regbld ibd_rhrp::DS [list dpr $dpr]] + set cs2val [regbld ibd_rhrp::CS2 [list ned [expr {1-$dpr}]] [list unit $unit]] + $cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit $unit] \ + -ribr rpa.ds -edata $dsval $dsmsk \ + -ribr rpa.dt -edata $dte \ + -wma rpa.cs2 [regbld ibd_rhrp::CS2 [list unit $unit]] \ + -wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ + -rma rpa.dt -edata $dt \ + -rma rpa.cs2 -edata $cs2val $cs2msk +} + +rlc log " A5: check cs2.ned for all regs on disabled unit -----------" + +# use setting from last section: drive 0 on, drive 1 off +# addr mb +set tbl [list rpa.cs1 1 \ + rpa.wc 0 \ + rpa.ba 0 \ + rpa.da 1 \ + rpa.cs2 0 \ + rpa.ds 1 \ + rpa.er1 1 \ + rpa.as 1 \ + rpa.la 1 \ + rpa.db 0 \ + rpa.mr1 1 \ + rpa.dt 1 \ + rpa.sn 1 \ + rpa.of 1 \ + rpa.dc 1 \ + rpa.m13 1 \ + rpa.m14 1 \ + rpa.m15 1 \ + rpa.ec1 1 \ + rpa.ec2 1 \ + rpa.bae 0 \ + rpa.cs3 0 \ + ] + +# Note: First unit 1 (enabled) selected, and cs1.tre=1 done +# Than unit 1 (disabled) selected, and registered read +# This ensures that cs2.ned is really cleared, because a cs1.tre=1 +# write while a disabled drive is selected will clear and set ned !! +set cs2msk [regbld ibd_rhrp::CS2 ned {unit -1}] +foreach {addr mb} $tbl { + set cs2val [regbld ibd_rhrp::CS2 [list ned $mb] {unit 1}] + $cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ + -wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ + -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ + -rma $addr \ + -rma rpa.cs2 -edata $cs2val $cs2msk +} + +rlc log " A6: check cs2.ned for all regs on enable unit -------------" + +# select drive 0 (on); cs1.tre=1; read all regs; check cs2 at end once (sticky) +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 [list unit 0]] \ + -wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ + -rma rpa.cs1 \ + -rma rpa.wc \ + -rma rpa.ba \ + -rma rpa.da + +$cpu cp -rma rpa.cs2 \ + -rma rpa.ds \ + -rma rpa.er1 \ + -rma rpa.as \ + -rma rpa.la \ + -rma rpa.db \ + -rma rpa.mr1 + +$cpu cp -rma rpa.dt \ + -rma rpa.sn \ + -rma rpa.of \ + -rma rpa.dc \ + -rma rpa.m13 \ + -rma rpa.m14 \ + -rma rpa.m15 + +$cpu cp -rma rpa.ec1 \ + -rma rpa.ec2 \ + -rma rpa.bae \ + -rma rpa.cs3 \ + -rma rpa.cs2 -edata 0 [regbld ibd_rhrp::CS2 ned] + +rlc log " A7: check that unit 3-7 are loc selectable, but off -------" +rlc log " A7.1: loc read dt for unit 3-7 ; check cs2.unit+ned" + +set cs2msk [regbld ibd_rhrp::CS2 ned {unit -1}] +foreach {unit} {4 5 6 7} { + set cs2val [regbld ibd_rhrp::CS2 ned [list unit $unit]] + $cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 [list unit $unit]] \ + -wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ + -rma rpa.dt -edata 0 \ + -rma rpa.cs2 -edata $cs2val $cs2msk +} + diff --git a/tools/tbench/test_rhrp_func_reg.tcl b/tools/tbench/test_rhrp_func_reg.tcl new file mode 100644 index 00000000..c4ebc754 --- /dev/null +++ b/tools/tbench/test_rhrp_func_reg.tcl @@ -0,0 +1,149 @@ +# $Id: test_rhrp_func_reg.tcl 668 2015-04-25 14:31:19Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-03-29 660 1.0 Initial version +# +# Test functions - register level +# A: + +# ---------------------------------------------------------------------------- +rlc log "test_rhrp_func_reg: test functions - register level -----------------" +rlc log " setup: unit 0:RP06(mol), 1:RM05(mol,wrl), 2: RP07(mol=0), 3: off" +package require ibd_rhrp +ibd_rhrp::setup + +rlc set statmask $rw11::STAT_DEFMASK +rlc set statvalue 0 + +# configure drives +$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \ + -wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1} mol] \ + -wibr rpa.dt $ibd_rhrp::DTE_RP06 \ + -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \ + -wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1} mol wrl] \ + -wibr rpa.dt $ibd_rhrp::DTE_RM05 \ + -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 2] \ + -wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1}] \ + -wibr rpa.dt $ibd_rhrp::DTE_RP07 \ + -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 3] \ + -wibr rpa.ds [regbld ibd_rhrp::DS {dpr 0}] + +# setup system: select unit 0; clr errors (cs1.tre and func=dclr); clear ATs +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ + -wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ + -wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_DCLR] \ + -wma rpa.as [regbld ibd_rhrp::AS u3 u2 u1 u0] \ + -rma rpa.ds -edata [regbld ibd_rhrp::DS dpr mol dry] + +# -- Section A -- function basics -------------------------------------------- +rlc log " A -- function basics ----------------------------------------------" +rlc log " A1: test cs1 func basics ----------------------------------" +rlc log " A1.1a: func noop; check no as ----------------------" + +set dsmsk [regbld ibd_rhrp::DS ata dpr] + +$cpu cp -wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_NOOP] \ + -rma rpa.as -edata 0x0 \ + -rma rpa.ds -edata [regbld ibd_rhrp::DS dpr] $dsmsk + +rlc log " A2.1a: test invalid function (037) -----------------" + +$cpu cp -wma rpa.cs1 [ibd_rhrp::cs1_func 037] + +rlc log " A2.1b: check as,er1.ilf,ds.ata; clear as; recheck --" + +$cpu cp -rma rpa.as -edata [regbld ibd_rhrp::AS u0] \ + -rma rpa.er1 -edata [regbld ibd_rhrp::ER1 ilf] \ + -rma rpa.ds -edata [regbld ibd_rhrp::DS ata dpr] $dsmsk \ + -wma rpa.as [regbld ibd_rhrp::AS u0] \ + -rma rpa.as -edata 0x0 \ + -rma rpa.ds -edata [regbld ibd_rhrp::DS dpr] $dsmsk + +rlc log " A2.2a: func dclr; check no as and er1 clear --------" + +$cpu cp -wma rpa.as [regbld ibd_rhrp::AS u3 u2 u1 u0] \ + -wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_DCLR] \ + -rma rpa.as -edata 0x0 \ + -rma rpa.er1 -edata 0x0 + +# -- Section B -- state functions -------------------------------------------- +rlc log " B -- state functions ----------------------------------------------" + +# -- Section C -- seek functions --------------------------------------------- +rlc log " C -- seek functions -----------------------------------------------" + +# -- Section D -- transfer functions ----------------------------------------- +rlc log " D -- transfer functions -------------------------------------------" +rlc log " D1: test func read sequence -------------------------------" +rlc log " D1.1: issue func with ie=0 ---------------------------" + +# discard pending attn to be on save side +rlc wtlam 0. +rlc exec -attn + +set attnmsk [expr {1<<$ibd_rhrp::ANUM}] + +set ba 0x1000 +set wc [expr {0xffff & (-256)}] +set da [regbld ibd_rhrp::DA {ta 2} {sa 1}] +set dc 0x0003 + +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ + -wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ + -wma rpa.ba $ba \ + -wma rpa.bae 0x0 \ + -wma rpa.wc $wc \ + -wma rpa.da $da \ + -wma rpa.dc $dc \ + -wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_READ] + +rlc log " D1.2: loc status check: cs1.rdy=0, ds.dry=0 ----------" + +$cpu cp -rma rpa.cs1 -edata 0 [regbld ibd_rhrp::CS1 rdy] \ + -rma rpa.ds -edata 0 [regbld ibd_rhrp::DS dry] + +rlc log " D1.3: rem status check: attn + state -----------------" + +rlc exec -attn -edata $attnmsk + +# check rdy=0 ie=0 func=read +set cs1val [regbld ibd_rhrp::CS1 [list func $ibd_rhrp::FUNC_READ]] +set cs1msk [regbld ibd_rhrp::CS1 rdy ie {func -1}] +# expect ds mol=1 dpr=1 dry=0 +set dsval [regbld ibd_rhrp::DS mol dpr] + +$cpu cp -wibr rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::RFUNC_CUNIT] \ + -ribr rpa.cs1 -edata $cs1val $cs1msk \ + -ribr rpa.ba -edata $ba \ + -ribr rpa.bae -edata 0x0 \ + -ribr rpa.wc -edata $wc \ + -ribr rpa.da -edata $da \ + -ribr rpa.dc -edata $dc \ + -ribr rpa.ds -edata $dsval + +rlc log " D1.4: rem send response ------------------------------" + +set ba [expr {0xffff & (-$wc)}] +set da [regbld ibd_rhrp::DA {ta 2} {sa 2}] + +$cpu cp -wibr rpa.ba $ba \ + -wibr rpa.wc 0x0 \ + -wibr rpa.da $da \ + -wibr rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::RFUNC_DONE] + +rlc log " D1.5: loc check: cs1.rdy=1, ds.dry=1 -----------------" + +# expect cs1 sc=0 tre=0 dva=1 rdy=1 ie=0 func=read go=0 +set cs1val [regbld ibd_rhrp::CS1 dva rdy [list func $ibd_rhrp::FUNC_READ]] +# expect ds ata=0 mol=1 dpr=1 dry=1 +set dsval [regbld ibd_rhrp::DS mol dpr dry] + +$cpu cp -rma rpa.cs1 -edata $cs1val \ + -rma rpa.ba -edata $ba \ + -rma rpa.wc -edata 0x0 \ + -rma rpa.da -edata $da \ + -rma rpa.ds -edata $dsval diff --git a/tools/tbench/test_rhrp_int.tcl b/tools/tbench/test_rhrp_int.tcl new file mode 100644 index 00000000..82439e33 --- /dev/null +++ b/tools/tbench/test_rhrp_int.tcl @@ -0,0 +1,490 @@ +# $Id: test_rhrp_int.tcl 678 2015-05-10 16:23:02Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-05-04 674 1.1 w11a start/stop/suspend overhaul +# 2015-03-29 667 1.0 Initial version +# +# Test interrupt response +# A: + +# ---------------------------------------------------------------------------- +rlc log "test_rhrp_int: test interrupt response ------------------------------" +rlc log " setup: unit 0:RP06(mol), 1:RM05(mol,wrl), 2: RP07(mol=0), 3: off" +package require ibd_rhrp +ibd_rhrp::setup + +rlc set statmask $rw11::STAT_DEFMASK +rlc set statvalue 0 + +# configure drives +$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \ + -wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1} mol] \ + -wibr rpa.dt $ibd_rhrp::DTE_RP06 \ + -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \ + -wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1} mol wrl] \ + -wibr rpa.dt $ibd_rhrp::DTE_RM05 \ + -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 2] \ + -wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1}] \ + -wibr rpa.dt $ibd_rhrp::DTE_RP07 \ + -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 3] \ + -wibr rpa.ds [regbld ibd_rhrp::DS {dpr 0}] + +# clear errors: cs1.tre=1 via unit 0 +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ + -wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ + -wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_DCLR] \ + -wma rpa.as [regbld ibd_rhrp::AS u3 u2 u1 u0] \ + -rma rpa.ds -edata [regbld ibd_rhrp::DS dpr mol dry] + +# load test code +$cpu ldasm -lst lst -sym sym { + .include |lib/defs_cpu.mac| + .include |lib/defs_rp.mac| +; + .include |lib/vec_cpucatch.mac| +; + . = 000254 ; setup RHRP interrupt vector +v..rp: .word vh.rp + .word cp.pr7 +; + . = 1000 ; data area +stack: +ibuf: .blkw 4. ; input buffer +rint: .word 0 ; reinterrupt +; +icnt: .word 0 ; interrupt count +pcnt: .word 0 ; poll count +obuf: .blkw 6. ; output buffer +fbuf: .blkw 5. ; final buffer +; + . = 2000 ; code area +start: spl 7 ; lock out interrupts + clr icnt ; clear counters + clr pcnt +; + mov #obuf,r0 ; clear obuf + clr (r0)+ + clr (r0)+ + clr (r0)+ + clr (r0)+ + clr (r0)+ + clr (r0)+ + clr r5 ; r5 used to time int delay +; + mov #ibuf,r0 ; setup regs from ibuf + mov (r0)+,@#rp.cs2 ; cs2 + mov (r0)+,@#rp.da ; da + mov (r0)+,@#rp.dc ; dc + mov (r0)+,@#rp.cs1 ; cs1 + spl 0 ; allow interrupts +; + inc r5 ; time int delay, up to 10 instructions + inc r5 + inc r5 + inc r5 + inc r5 + inc r5 + inc r5 + inc r5 + inc r5 + inc r5 +; +poll: inc pcnt ; count polls + tstb @#rp.cs1 ; check cs1 rdy + bpl poll ; if rdy=0 keep polling + tst icnt ; did we have an interrupt ? + bne 1$ ; +; + mov #obuf,r0 ; store regs in obuf + mov @#rp.cs1,(r0)+ ; cs1 + mov @#rp.cs2,(r0)+ ; cs2 + mov @#rp.er1,(r0)+ ; er1 + mov @#rp.ds,(r0)+ ; ds + mov @#rp.as,(r0)+ ; as +; +1$: tst rint ; re-interrupt wanted ? + bne 2$ ; + mov #377,@#rp.as ; if not, cancel all attentions + clr rint +; +2$: bit #rp.erp,@#rp.ds ; ds.erp = 1 ? any controller errors ? + beq 3$ + mov #,@#rp.cs1 ; than do drive clear +; +3$: bit #rp.tre,@#rp.cs1 ; cs1.tre = 1 ? any transfer errors ? + beq 4$ + mov #rp.tre,@#rp.cs1 ; if yes, clear them with tre=1 write +; +4$: mov #fbuf,r0 ; store final regs in fbuf + mov @#rp.cs1,(r0)+ ; cs1 + mov @#rp.cs2,(r0)+ ; cs2 + mov @#rp.er1,(r0)+ ; er1 + mov @#rp.ds,(r0)+ ; ds + mov @#rp.as,(r0)+ ; as + + halt ; halt if done +stop: +; + clr pcnt ; clear pcnt again + mov #obuf,r0 ; clear obuf again + clr (r0)+ + clr (r0)+ + clr (r0)+ + clr (r0)+ + clr (r0)+ + clr (r0)+ +; + mov #rp.ie,@#rp.cs1 ; re-enable interrupt + br poll + +; RHRP interrupt handler +vh.rp: mov #obuf,r0 ; store regs in obuf + mov @#rp.cs1,(r0)+ ; cs1 + mov @#rp.cs2,(r0)+ ; cs2 + mov @#rp.er1,(r0)+ ; er1 + mov @#rp.ds,(r0)+ ; ds + mov @#rp.as,r1 ; + mov r1,(r0)+ ; as + mov r5,(r0)+ ; int delay +; +1$: tst icnt ; test first interrupt + beq 2$ ; if yes quit + mov r1,@#rp.as ; if not, clear as +2$: inc icnt ; count interrupts + rti ; and return +} + +##puts $lst + +# define tmpproc for readback checks +proc tmpproc_dotest {cpu symName opts} { + upvar 1 $symName sym + + set tout 10.; # FIXME_code: parameter ?? + +# setup defs hash, first defaults, than write over concrete run values + array set defs { i.cs2 0 \ + i.da 0 \ + i.dc 0 \ + i.cs1 0 \ + i.idly 0 \ + o.cs1 0 \ + o.cs2 0 \ + o.er1 0 \ + o.ds 0 \ + o.as 0 \ + o.itim 10 \ + o.icnt 0 \ + o.pcnt 1 \ + or.cs1 0 \ + or.cs2 0 \ + or.er1 0 \ + or.ds 0 \ + or.as 0 \ + or.icnt 0 \ + or.pcnt 1 \ + do.rint 0 \ + do.lam 0 + } + array set defs $opts + + # build ibuf + set ibuf [list $defs(i.cs2) $defs(i.da) $defs(i.dc) $defs(i.cs1) \ + $defs(do.rint)] + + # setup idly, write ibuf, setup stack, and start cpu at start: + $cpu cp -wibr rpa.cs1 [regbld ibd_rhrp::RCS1 \ + [list val $defs(i.idly)] \ + [list func $ibd_rhrp::RFUNC_WIDLY] ] \ + -wal $sym(ibuf) \ + -bwm $ibuf \ + -wsp $sym(stack) \ + -stapc $sym(start) + + # here do minimal lam handling (harvest + send DONE) + if {$defs(do.lam)} { + rlc wtlam $tout apat + $cpu cp -attn \ + -wibr rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::RFUNC_DONE] + } + + $cpu wtcpu -reset $tout + + # determine regs after cleanup + set cs1msk [rutil::com16 [regbld ibd_rhrp::CS1 {func -1}]] + set fcs2 [expr {$defs(o.cs2) & 0x00ff}]; # cs1.tre clears upper byte ! + set fer1 0 + if {!$defs(do.rint)} { # no reinterrupt, ata clear by cpu + set fcs1 [expr {$defs(o.cs1) & ~[regbld ibd_rhrp::CS1 sc tre {func -1}] }] + set fds [expr {$defs(o.ds) & ~[regbld ibd_rhrp::DS ata erp] }] + set fas 0 + } else { # reinterrupt, ata still pending + set fcs1 [expr {$defs(o.cs1) & ~[regbld ibd_rhrp::CS1 tre {func -1}] }] + set fds [expr {$defs(o.ds) & ~[regbld ibd_rhrp::DS erp] }] + set fas $defs(o.as) + } + $cpu cp -rpc -edata $sym(stop) \ + -rsp -edata $sym(stack) \ + -wal $sym(icnt) \ + -rmi -edata $defs(o.icnt) \ + -rmi \ + -rmi -edata $defs(o.cs1) \ + -rmi -edata $defs(o.cs2) \ + -rmi -edata $defs(o.er1) \ + -rmi -edata $defs(o.ds) \ + -rmi -edata $defs(o.as) \ + -rmi -edata $defs(o.itim) \ + -rmi -edata $fcs1 $cs1msk \ + -rmi -edata $fcs2 \ + -rmi -edata $fer1 \ + -rmi -edata $fds \ + -rmi -edata $fas + + if {!$defs(do.rint)} return ""; + + $cpu cp -start + + $cpu wtcpu -reset $tout + + # determine regs after cleanup + set fcs1 [expr {$defs(or.cs1) & ~[regbld ibd_rhrp::CS1 sc] }] + set fcs2 $defs(or.cs2) + set fer1 0 + set fds [expr {$defs(or.ds) & ~[regbld ibd_rhrp::DS ata] }] + set fas 0 + + $cpu cp -rpc -edata $sym(stop) \ + -rsp -edata $sym(stack) \ + -wal $sym(icnt) \ + -rmi -edata $defs(or.icnt) \ + -rmi \ + -rmi -edata $defs(or.cs1) \ + -rmi -edata $defs(or.cs2) \ + -rmi -edata $defs(or.er1) \ + -rmi -edata $defs(or.ds) \ + -rmi -edata $defs(or.as) \ + -rmi \ + -rmi -edata $fcs1 \ + -rmi -edata $fcs2 \ + -rmi -edata $fer1 \ + -rmi -edata $fds \ + -rmi -edata $fas + + return "" +} + +# discard pending attn to be on save side +rlc wtlam 0. +rlc exec -attn + +# -- Section A --------------------------------------------------------------- +rlc log " A -- function basics ----------------------------------------------" +rlc log " A1: test rdy and ie logic ---------------------------------" +rlc log " A1.1 set cs1.ie=1 alone -> no interrupt ------------" + +# Note: no interrupt, so ie stays on ! +set opts [list \ + i.cs1 [regbld ibd_rhrp::CS1 ie] \ + o.icnt 0 \ + o.cs1 [regbld ibd_rhrp::CS1 dva rdy ie] \ + o.cs2 [regbld ibd_rhrp::CS2 or ir] \ + o.er1 0 \ + o.ds [regbld ibd_rhrp::DS mol dpr dry] \ + o.as 0 \ + o.itim 0 + ] +tmpproc_dotest $cpu sym $opts + +rlc log " A1.2 set cs1.ie=1 with rdy=1 -> software interrupt -" + +# Note: interrupt, so ie switched off again ! +set opts [list \ + i.cs1 [regbld ibd_rhrp::CS1 rdy ie] \ + o.icnt 1 \ + o.cs1 [regbld ibd_rhrp::CS1 dva rdy] \ + o.cs2 [regbld ibd_rhrp::CS2 or ir] \ + o.er1 0 \ + o.ds [regbld ibd_rhrp::DS mol dpr dry] \ + o.as 0 \ + o.itim 1 + ] + +tmpproc_dotest $cpu sym $opts + +rlc log " A2: test state functions: iff no, as yes ------------------" +rlc log " A2.1 noop function ---------------------------------" + +set opts [list \ + i.cs1 [regbld ibd_rhrp::CS1 ie go] \ + o.cs1 [regbld ibd_rhrp::CS1 ie dva rdy] \ + o.cs2 [regbld ibd_rhrp::CS2 or ir] \ + o.er1 0 \ + o.ds [regbld ibd_rhrp::DS mol dpr dry] \ + o.as 0 \ + o.itim 0 + ] +tmpproc_dotest $cpu sym $opts + +rlc log " A2.2 pack acknowledge function (sets ds.vv=1) ------" + +set rbcs1func [list func $ibd_rhrp::FUNC_PACK] +set opts [list \ + i.cs1 [regbld ibd_rhrp::CS1 $rbcs1func ie go] \ + o.cs1 [regbld ibd_rhrp::CS1 dva rdy ie $rbcs1func] \ + o.cs2 [regbld ibd_rhrp::CS2 or ir] \ + o.er1 0 \ + o.ds [regbld ibd_rhrp::DS mol dpr dry vv] \ + o.as 0 \ + o.itim 0 + ] +tmpproc_dotest $cpu sym $opts + +rlc log " A3: test seek type functions: iff no, as yes --------------" + +rlc log " A3.1 seek function, ie=0, valid da,dc---------------" + +# check that cs1.sc=1, ds.ata=1, and as.u0=1 +set rbcs1func [list func $ibd_rhrp::FUNC_SEEK] +set opts [list \ + i.cs1 [regbld ibd_rhrp::CS1 $rbcs1func go] \ + o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \ + o.cs2 [regbld ibd_rhrp::CS2 or ir] \ + o.er1 0 \ + o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \ + o.as [regbld ibd_rhrp::AS u0] \ + o.itim 0 + ] +tmpproc_dotest $cpu sym $opts + +rlc log " A3.2 seek function, valid da,dc, idly=0 ------------" + +# check re-interrupt too +set rbcs1func [list func $ibd_rhrp::FUNC_SEEK] +set opts [list \ + i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \ + i.dc 814 \ + i.idly 0 \ + o.icnt 1 \ + o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \ + o.cs2 [regbld ibd_rhrp::CS2 or ir] \ + o.er1 0 \ + o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \ + o.as [regbld ibd_rhrp::AS u0] \ + o.itim 1 \ + do.rint 1 \ + or.icnt 2 \ + or.cs1 [regbld ibd_rhrp::CS1 sc dva rdy] \ + or.cs2 [regbld ibd_rhrp::CS2 or ir] \ + or.er1 0 \ + or.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \ + or.as [regbld ibd_rhrp::AS u0] + ] +tmpproc_dotest $cpu sym $opts + +rlc log " A3.3 seek function, invalid dc ---------------------" + +set rbcs1func [list func $ibd_rhrp::FUNC_SEEK] +set opts [list \ + i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \ + i.dc 815 \ + o.icnt 1 \ + o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \ + o.cs2 [regbld ibd_rhrp::CS2 or ir] \ + o.er1 [regbld ibd_rhrp::ER1 iae] \ + o.ds [regbld ibd_rhrp::DS ata erp mol dpr dry vv] \ + o.as [regbld ibd_rhrp::AS u0] \ + o.itim 1 + ] +tmpproc_dotest $cpu sym $opts + +rlc log " A3.4 search function, valid da,dc, idly=0 ----------" + +set rbcs1func [list func $ibd_rhrp::FUNC_SEAR] +set opts [list \ + i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \ + i.dc 0 \ + i.da [regbld ibd_rhrp::DA {ta 0} {sa 21}] \ + i.idly 0 \ + o.icnt 1 \ + o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \ + o.cs2 [regbld ibd_rhrp::CS2 or ir] \ + o.er1 0 \ + o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \ + o.as [regbld ibd_rhrp::AS u0] \ + o.itim 1 + ] +tmpproc_dotest $cpu sym $opts + +rlc log " A3.5 search function, valid da,dc, idly=2 ----------" + +set rbcs1func [list func $ibd_rhrp::FUNC_SEAR] +set opts [list \ + i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \ + i.dc 0 \ + i.da [regbld ibd_rhrp::DA {ta 0} {sa 21}] \ + i.idly 2 \ + o.icnt 1 \ + o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \ + o.cs2 [regbld ibd_rhrp::CS2 or ir] \ + o.er1 0 \ + o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \ + o.as [regbld ibd_rhrp::AS u0] \ + o.itim 3 + ] +tmpproc_dotest $cpu sym $opts + +rlc log " A3.5 search function, valid da,dc, idly=8 ----------" + +set rbcs1func [list func $ibd_rhrp::FUNC_SEAR] +set opts [list \ + i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \ + i.dc 0 \ + i.da [regbld ibd_rhrp::DA {ta 0} {sa 21}] \ + i.idly 8 \ + o.icnt 1 \ + o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \ + o.cs2 [regbld ibd_rhrp::CS2 or ir] \ + o.er1 0 \ + o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \ + o.as [regbld ibd_rhrp::AS u0] \ + o.itim 9 + ] +tmpproc_dotest $cpu sym $opts + +rlc log " A3.5 search function, invalid sa, idly=8 -----------" +# Note: idly is 8, but error ata's come immediately !! + +set rbcs1func [list func $ibd_rhrp::FUNC_SEAR] +set opts [list \ + i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \ + i.dc 0 \ + i.da [regbld ibd_rhrp::DA {ta 0} {sa 22}] \ + i.idly 8 \ + o.icnt 1 \ + o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \ + o.cs2 [regbld ibd_rhrp::CS2 or ir] \ + o.er1 [regbld ibd_rhrp::ER1 iae] \ + o.ds [regbld ibd_rhrp::DS ata erp mol dpr dry vv] \ + o.as [regbld ibd_rhrp::AS u0] \ + o.itim 1 + ] +tmpproc_dotest $cpu sym $opts + +rlc log " A4: test transfer functions: iff yes, as no ---------------" +rlc log " A4.1 read function, valid da,dc --------------------" + +set rbcs1func [list func $ibd_rhrp::FUNC_READ] +set opts [list \ + i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \ + o.icnt 1 \ + o.cs1 [regbld ibd_rhrp::CS1 dva rdy $rbcs1func] \ + o.cs2 [regbld ibd_rhrp::CS2 or ir] \ + o.ds [regbld ibd_rhrp::DS mol dpr dry vv] \ + do.lam 1 + ] +tmpproc_dotest $cpu sym $opts + diff --git a/tools/tbench/test_rhrp_regs.tcl b/tools/tbench/test_rhrp_regs.tcl new file mode 100644 index 00000000..00c12a7c --- /dev/null +++ b/tools/tbench/test_rhrp_regs.tcl @@ -0,0 +1,426 @@ +# $Id: test_rhrp_regs.tcl 678 2015-05-10 16:23:02Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Revision History: +# Date Rev Version Comment +# 2015-03-29 660 1.0 Initial version +# +# Test register response +# A: test ba, bae, cs1.bae, wc and db (cntl regs) +# B: test da, dc (and cc for RP typ) +# C: test of,mr1,mr2(for RM typ); test NI regs: er2,er3,ec1,ec2 +# D: test hr (for RM typ); ensure unit distinct +# E: test cs2.clr +# F: test er1 + +# ---------------------------------------------------------------------------- +rlc log "test_rhrp_regs: test register response ------------------------------" +rlc log " setup context; unit 0:RP06, 1:RM05, 2: RP07, 3: off" +package require ibd_rhrp +ibd_rhrp::setup + +rlc set statmask $rw11::STAT_DEFMASK +rlc set statvalue 0 + +# configure drives +$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \ + -wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1}] \ + -wibr rpa.dt $ibd_rhrp::DTE_RP06 \ + -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \ + -wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1}] \ + -wibr rpa.dt $ibd_rhrp::DTE_RM05 \ + -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 2] \ + -wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1}] \ + -wibr rpa.dt $ibd_rhrp::DTE_RP07 \ + -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 3] \ + -wibr rpa.ds [regbld ibd_rhrp::DS {dpr 0}] + +# clear errors: cs1.tre=1 via unit 0 +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ + -wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] + +# -- Section A --------------------------------------------------------------- +rlc log " A1: test ba,bae and cs1.bae -------------------------------" +rlc log " A1.1: loc write ba, read loc and rem ---------------" + +$cpu cp -wma rpa.ba 0xffff \ + -rma rpa.ba -edata 0xfffe \ + -ribr rpa.ba -edata 0xfffe \ + -wma rpa.ba 0x0 \ + -rma rpa.ba -edata 0x0 \ + -ribr rpa.ba -edata 0x0 + +rlc log " A1.2: rem write ba, read loc and rem ---------------" + +$cpu cp -wibr rpa.ba 0x12ef \ + -ribr rpa.ba -edata 0x12ee \ + -rma rpa.ba -edata 0x12ee \ + -wibr rpa.ba 0x0 \ + -ribr rpa.ba -edata 0x0 \ + -rma rpa.ba -edata 0x0 + +rlc log " A1.3: loc write bae, read l+r bae+cs1.bae ----------" + +set cs1msk [regbld ibd_rhrp::CS1 {bae -1}] +foreach bae {077 071 000} { + set cs1val [regbld ibd_rhrp::CS1 [list bae [expr {$bae & 03}]]] + $cpu cp -wma rpa.bae $bae \ + -rma rpa.bae -edata $bae \ + -rma rpa.cs1 -edata $cs1val $cs1msk \ + -ribr rpa.bae -edata $bae \ + -ribr rpa.cs1 -edata $cs1val $cs1msk +} + +rlc log " A1.4: rem write bae, read l+r bae+cs1.bae ----------" + +foreach bae {077 071 000} { + set cs1val [regbld ibd_rhrp::CS1 [list bae [expr {$bae & 03}]]] + $cpu cp -wibr rpa.bae $bae \ + -ribr rpa.bae -edata $bae \ + -ribr rpa.cs1 -edata $cs1val $cs1msk \ + -rma rpa.bae -edata $bae \ + -rma rpa.cs1 -edata $cs1val $cs1msk +} + +rlc log " A1.5: loc write cs1.bae, read l+r bae+cs1.bae ------" + +$cpu cp -wibr rpa.bae 070; # set 3 lbs of bae + +foreach cs1bae {03 01 00} { + set cs1val [regbld ibd_rhrp::CS1 [list bae $cs1bae]] + set bae [expr {070 | $cs1bae}] + $cpu cp -wma rpa.cs1 $cs1val \ + -rma rpa.bae -edata $bae \ + -rma rpa.cs1 -edata $cs1val $cs1msk \ + -ribr rpa.bae -edata $bae \ + -ribr rpa.cs1 -edata $cs1val $cs1msk +} + +# Note: cs1.bae can only be loc written ! +# No need to do this via rem, use bae !! +# therefore no 'rem write cs1.bae' test + +rlc log " A1.6: loc write cs1.func, read loc, ensure distinct " + +set funcu0 [regbld ibd_rhrp::CS1 {func 001}] +set funcu1 [regbld ibd_rhrp::CS1 {func 025}] +set funcu2 [regbld ibd_rhrp::CS1 {func 037}] +set funcmsk [regbld ibd_rhrp::CS1 {func -1}] + +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ + -wma rpa.cs1 $funcu0 \ + -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ + -wma rpa.cs1 $funcu1 \ + -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ + -wma rpa.cs1 $funcu2 + +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ + -rma rpa.cs1 -edata $funcu0 $funcmsk \ + -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ + -rma rpa.cs1 -edata $funcu1 $funcmsk \ + -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ + -rma rpa.cs1 -edata $funcu2 $funcmsk + +# Note: rem read of cs1.func always gives func frozen a go for xfer function ! +# therefore no rem read cs1.func test here + +rlc log " A2: test wc; ensure wc,ba distinct ------------------------" +rlc log " A2.1: loc write wc,ba, read loc and rem ------------" + +foreach {wc ba} {0xdead 0x1234 0xbeaf 0x5678} { + $cpu cp -wma rpa.wc $wc \ + -wma rpa.ba $ba \ + -rma rpa.wc -edata $wc \ + -rma rpa.ba -edata $ba \ + -ribr rpa.wc -edata $wc \ + -ribr rpa.ba -edata $ba +} + +rlc log " A2.2: rem write wc,ba, read loc and rem ------------" + +foreach {wc ba} {0x4321 0x3456 0x5432 0x1234} { + $cpu cp -wibr rpa.wc $wc \ + -wibr rpa.ba $ba \ + -ribr rpa.wc -edata $wc \ + -ribr rpa.ba -edata $ba \ + -rma rpa.wc -edata $wc \ + -rma rpa.ba -edata $ba +} + +rlc log " A3: test db; check cs2.or,ir; ensure ba,dt distinct --" + +set cs2msk [regbld ibd_rhrp::CS2 or ir {unit -1}] +set cs2val [regbld ibd_rhrp::CS2 or ir {unit 0}] + +# clear cs2 -> set unit 0; later check that or,ir set, and unit 0 +# only loc tested; rem side irrelevant +foreach {db ba} {0xdead 0x1234 0xbeaf 0x5678} { + $cpu cp -wma rpa.cs2 0 \ + -wma rpa.db $db \ + -wma rpa.ba $ba \ + -rma rpa.cs2 -edata $cs2val $cs2msk \ + -rma rpa.db -edata $db \ + -rma rpa.ba -edata $ba +} + +# -- Section B --------------------------------------------------------------- +rlc log " B1: test da,dc; ensure unit distinct; check cc ------------" + +# define tmpproc for readback checks +proc tmpproc_checkdadc {cpu tbl} { + foreach {unit ta sa dc} $tbl { + set da [regbld ibd_rhrp::DA [list ta $ta] [list sa $sa]] + $cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 [list unit $unit]] \ + -rma rpa.da -edata $da \ + -rma rpa.dc -edata $dc \ + -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit $unit] \ + -ribr rpa.da -edata $da \ + -ribr rpa.dc -edata $dc + } +} + +rlc log " B1.1: loc setup ------------------------------------" + +# unit ta sa dc +# 5b 6b 10b +set tbl { 0 007 006 00123 \ + 1 013 031 00345 \ + 2 037 077 01777 + } + +foreach {unit ta sa dc} $tbl { + $cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 [list unit $unit]] \ + -wma rpa.da [regbld ibd_rhrp::DA [list ta $ta] [list sa $sa]] \ + -wma rpa.dc $dc +} + +rlc log " B1.2: loc+rem readback -----------------------------" +tmpproc_checkdadc $cpu $tbl + +rlc log " B1.3: check cc for unit 0 (RP06) -------------------" +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ + -rma rpa.m13 -edata 00123 + +rlc log " B1.4: rem setup ------------------------------------" + +# unit ta sa dc +# 5b 6b 10b +set tbl { 0 005 004 00234 \ + 1 020 077 00456 \ + 2 032 023 01070 + } + +foreach {unit ta sa dc} $tbl { + $cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit $unit] \ + -wibr rpa.da [regbld ibd_rhrp::DA [list ta $ta] [list sa $sa]] \ + -wibr rpa.dc $dc +} + +rlc log " B1.5: loc+rem readback -----------------------------" +tmpproc_checkdadc $cpu $tbl + +rlc log " B1.6: check cc for unit 0 (RP06) -------------------" +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ + -rma rpa.m13 -edata 00234 + +# -- Section C --------------------------------------------------------------- +rlc log " C1: test of,mr1,mr2(for RM typ); test NI regs: er2,er3,ec1,ec2" + +# test fmt,eci,hci flags (NI, but stored), also off for RP +set of_0 [regbld ibd_rhrp::OF fmt {odi 1} {off -1}] +set of_1 [regbld ibd_rhrp::OF eci {odi 0}] +set of_2 [regbld ibd_rhrp::OF hci {odi 0}] + +set mr1_0 0x7700 +set mr1_1 0x7701 +set mr1_2 0x7702 + +set mr2_1 0x6601 +set mr2_2 0x6602 + +set da_0 [regbld ibd_rhrp::DA {ta 010} {sa 022}] +set da_1 [regbld ibd_rhrp::DA {ta 011} {sa 021}] +set da_2 [regbld ibd_rhrp::DA {ta 012} {sa 020}] + +set dc_0 0x40 +set dc_1 0x41 +set dc_2 0x42 + +rlc log " C1.1: loc write da,mr1,of,dc (mr2 for RM) ----------" +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ + -wma rpa.da $da_0 \ + -wma rpa.mr1 $mr1_0 \ + -wma rpa.of $of_0 \ + -wma rpa.dc $dc_0 + +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ + -wma rpa.da $da_1 \ + -wma rpa.mr1 $mr1_1 \ + -wma rpa.of $of_1 \ + -wma rpa.dc $dc_1 \ + -wma rpa.m14 $mr2_1 + +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ + -wma rpa.da $da_2 \ + -wma rpa.mr1 $mr1_2 \ + -wma rpa.of $of_2 \ + -wma rpa.dc $dc_2 \ + -wma rpa.m14 $mr2_2 + +rlc log " C1.2: loc read da,mr1,of,dc (mr2 for RM) -----------" +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ + -rma rpa.da -edata $da_0 \ + -rma rpa.mr1 -edata $mr1_0 \ + -rma rpa.of -edata $of_0 \ + -rma rpa.dc -edata $dc_0 + +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ + -rma rpa.da -edata $da_1 \ + -rma rpa.mr1 -edata $mr1_1 \ + -rma rpa.of -edata $of_1 \ + -rma rpa.dc -edata $dc_1 \ + -rma rpa.m14 -edata $mr2_1 + +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ + -rma rpa.da -edata $da_2 \ + -rma rpa.mr1 -edata $mr1_2 \ + -rma rpa.of -edata $of_2 \ + -rma rpa.dc -edata $dc_2 \ + -rma rpa.m14 -edata $mr2_2 + +rlc log " C2.1: loc write er2,er3,ec1,ec2 --------------------" + +# unit 0: RP typ -> m14 is er2; m15 is er3 +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ + -wma rpa.m14 0xaa00 \ + -wma rpa.m15 0xaa10 \ + -wma rpa.ec1 0xaa20 \ + -wma rpa.ec1 0xaa30 + +# unit 1+2: RM typ -> m15 is er2 +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ + -wma rpa.m15 0xaa11 \ + -wma rpa.ec1 0xaa21 \ + -wma rpa.ec1 0xaa31 +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ + -wma rpa.m15 0xaa12 \ + -wma rpa.ec1 0xaa22 \ + -wma rpa.ec1 0xaa32 + +rlc log " C2.1: loc read er2,er3,ec1,ec2 (NI -> =0!) ---------" + +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ + -rma rpa.m14 -edata 0x0 \ + -rma rpa.m15 -edata 0x0 \ + -rma rpa.ec1 -edata 0x0 \ + -rma rpa.ec1 -edata 0x0 + +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ + -rma rpa.m15 -edata 0x0 \ + -rma rpa.ec1 -edata 0x0 \ + -rma rpa.ec1 -edata 0x0 +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ + -rma rpa.m15 -edata 0x0 \ + -rma rpa.ec1 -edata 0x0 \ + -rma rpa.ec1 -edata 0x0 + +# -- Section D --------------------------------------------------------------- +rlc log " D1: test hr (for RM typ); ensure unit distinct ------------" + +# test unit 1+2, they are RM typ (RM05 and RP07) + +set da [regbld ibd_rhrp::DA {ta 005} {sa 023}]; # some da +set dc 00456; # some dc + +rlc log " D1.1: write da(1) and dc(2) ------------------------" +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ + -wma rpa.da $da \ + -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ + -wma rpa.da $dc + +rlc log " D1.2: check hr(1) and hr(2) ------------------------" +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ + -rma rpa.m13 -edata [rutil::com16 $da] \ + -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ + -rma rpa.m13 -edata [rutil::com16 $dc] + +rlc log " D1.3: write da(2) and dc(1) ------------------------" +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ + -wma rpa.da $da \ + -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ + -wma rpa.da $dc + +rlc log " D1.4: check hr(1) and hr(2) ------------------------" +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ + -rma rpa.m13 -edata [rutil::com16 $dc] \ + -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ + -rma rpa.m13 -edata [rutil::com16 $da] + +# FIXME: add code to check hr response for all mb reg writes + +# -- Section E --------------------------------------------------------------- +rlc log " E1: test rem er1 write; clear via func=dclr ---------------" +rlc log " E1.1: rem er1 set uns,iae,aoe,ilf; loc readback ----" + +set er1msk [regbld ibd_rhrp::ER1 uns iae aoe ilf] + +# use unit 1 +$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \ + -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] + +$cpu cp -rma rpa.er1 -edata 0x0 \ + -wibr rpa.er1 [regbld ibd_rhrp::ER1 uns] \ + -rma rpa.er1 -edata [regbld ibd_rhrp::ER1 uns] $er1msk \ + -wibr rpa.er1 [regbld ibd_rhrp::ER1 iae] \ + -rma rpa.er1 -edata [regbld ibd_rhrp::ER1 uns iae] $er1msk \ + -wibr rpa.er1 [regbld ibd_rhrp::ER1 aoe] \ + -rma rpa.er1 -edata [regbld ibd_rhrp::ER1 uns iae aoe] $er1msk \ + -wibr rpa.er1 [regbld ibd_rhrp::ER1 ilf] \ + -rma rpa.er1 -edata [regbld ibd_rhrp::ER1 uns iae aoe ilf] $er1msk + +rlc log " E1.2: clear er1 via func=dclr ----------------------" + +$cpu cp -wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_DCLR] \ + -rma rpa.er1 -edata 0x0 + +rlc log " E1.3: rem er1 set in different units ---------------" + +$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \ + -wibr rpa.er1 [regbld ibd_rhrp::ER1 iae] \ + -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \ + -wibr rpa.er1 [regbld ibd_rhrp::ER1 aoe] \ + -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 2] \ + -wibr rpa.er1 [regbld ibd_rhrp::ER1 ilf] + +rlc log " E1.4: loc readback, show er1 is distinct -----------" + +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ + -rma rpa.er1 -edata [regbld ibd_rhrp::ER1 iae] $er1msk \ + -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ + -rma rpa.er1 -edata [regbld ibd_rhrp::ER1 aoe] $er1msk \ + -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ + -rma rpa.er1 -edata [regbld ibd_rhrp::ER1 ilf] $er1msk + +rlc log " E1.5: show func=dclr distinct ----------------------" + +# clear unit 1, that that 1 clr and 0+2 untouched +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ + -wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_DCLR] \ + -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ + -rma rpa.er1 -edata [regbld ibd_rhrp::ER1 iae] $er1msk \ + -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ + -rma rpa.er1 -edata 0x0 \ + -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ + -rma rpa.er1 -edata [regbld ibd_rhrp::ER1 ilf] $er1msk + +rlc log " E1.6: clear er1 in remaining units -----------------" + +# unit 0+2 still have er1 bits set from previous test +$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ + -wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_DCLR] \ + -rma rpa.er1 -edata 0x0 \ + -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ + -wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_DCLR] \ + -rma rpa.er1 -edata 0x0 diff --git a/tools/tcl/ibd_ibmon/.cvsignore b/tools/tcl/ibd_ibmon/.cvsignore new file mode 100644 index 00000000..fc959ab2 --- /dev/null +++ b/tools/tcl/ibd_ibmon/.cvsignore @@ -0,0 +1 @@ +pkgIndex.tcl diff --git a/tools/tcl/ibd_ibmon/util.tcl b/tools/tcl/ibd_ibmon/util.tcl new file mode 100644 index 00000000..3fae6050 --- /dev/null +++ b/tools/tcl/ibd_ibmon/util.tcl @@ -0,0 +1,282 @@ +# $Id: util.tcl 668 2015-04-25 14:31:19Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# +# This program is free software; you may redistribute and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation, either version 2, or at your option any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for complete details. +# +# Revision History: +# Date Rev Version Comment +# 2015-04-25 668 1.0 Initial version +# + +package provide ibd_ibmon 1.0 + +package require rutil +package require rlink + +namespace eval ibd_ibmon { + # + # setup register descriptions for ibd_ibmon + # + regdsc CNTL {conena 5} {remena 4} {locena 3} {wena 2} {stop 1} {start 0} + regdsc STAT {bsize 15 3} {wrap 0} + regdsc ADDR {laddr 15 14} {waddr 1 2} + # + regdsc DAT3 {burst 15} {tout 14} {nak 13} {ack 12} \ + {busy 11} {we 9} {rmw 8} {ndlymsb 7 8} + regdsc DAT2 {ndlylsb 15 6} {nbusy 9 10} + regdsc DAT0 {be1 15} {be0 14} {racc 13} {addr 12 12} {cacc 0} + # + # 'pseudo register', describes 1st word in return list element of read proc + # all flag bits from DAT3 and DAT0 + regdsc FLAGS {burst 11} {tout 10} {nak 9} {ack 8} \ + {busy 7} {cacc 5} {racc 4} {rmw 3} {be1 2} {be0 1} {we 0} + # + # setup: amap definitions for rbd_rbmon + # + proc setup {{cpu "cpu0"} {base 0160000}} { + $cpu imap -insert im.cntl [expr {$base + 000}] + $cpu imap -insert im.stat [expr {$base + 002}] + $cpu imap -insert im.hilim [expr {$base + 004}] + $cpu imap -insert im.lolim [expr {$base + 006}] + $cpu imap -insert im.addr [expr {$base + 010}] + $cpu imap -insert im.data [expr {$base + 012}] + } + # + # init: reset rbd_rbmon (stop, reset alim) + # + proc init {{cpu "cpu0"}} { + $cpu cp \ + -wibr im.cntl [regbld ibd_ibmon::CNTL stop] \ + -wibr im.hilim 0177776 \ + -wibr im.lolim 0160000 \ + -wibr im.addr 0x0000 + } + # + # start: start the rbmon + # + proc start {{cpu "cpu0"} {opts {}}} { + array set defs { conena 1 remena 1 locena 1 wena 1 } + array set defs $opts + $cpu cp -wibr im.cntl [regbld ibd_ibmon::CNTL start \ + [list wena $defs(wena)] \ + [list locena $defs(locena)] \ + [list remena $defs(remena)] \ + [list conena $defs(conena)] \ + ] + } + # + # stop: stop the rbmon + # + proc stop {{cpu "cpu0"}} { + $cpu cp -wibr im.cntl [regbld ibd_ibmon::CNTL stop] + } + # + # read: read nent last entries (by default all) + # + proc read {{cpu "cpu0"} {nent -1}} { + $cpu cp -ribr im.addr raddr \ + -ribr im.stat rstat + + set bsize [regget ibd_ibmon::STAT(bsize) $rstat] + set amax [expr {( 512 << $bsize ) - 1}] + if {$nent == -1} { set nent $amax } + + set laddr [regget ibd_ibmon::ADDR(laddr) $raddr] + set nval $laddr + if {[regget ibd_ibmon::STAT(wrap) $rstat]} { set nval $amax } + + if {$nent > $nval} {set nent $nval} + if {$nent == 0} { return {} } + + set caddr [expr {( $laddr - $nent ) & $amax}] + $cpu cp -wibr im.addr [regbld ibd_ibmon::ADDR [list laddr $caddr]] + + set rval {} + + set nrest $nent + while {$nrest > 0} { + set nblk [expr {$nrest << 2}] + if {$nblk > 256} {set nblk 256} + set iaddr [$cpu imap im.data] + $cpu cp -rbibr $iaddr $nblk rawdat + + foreach {d0 d1 d2 d3} $rawdat { + set d3burst [regget ibd_ibmon::DAT3(burst) $d3] + set d3tout [regget ibd_ibmon::DAT3(tout) $d3] + set d3nak [regget ibd_ibmon::DAT3(nak) $d3] + set d3ack [regget ibd_ibmon::DAT3(ack) $d3] + set d3busy [regget ibd_ibmon::DAT3(busy) $d3] + set d3we [regget ibd_ibmon::DAT3(we) $d3] + set d3rmw [regget ibd_ibmon::DAT3(rmw) $d3] + set d0be1 [regget ibd_ibmon::DAT0(be1) $d0] + set d0be0 [regget ibd_ibmon::DAT0(be0) $d0] + set d0racc [regget ibd_ibmon::DAT0(racc) $d0] + set d0addr [regget ibd_ibmon::DAT0(addr) $d0] + set d0cacc [regget ibd_ibmon::DAT0(cacc) $d0] + + set eflag [regbld ibd_ibmon::FLAGS \ + [list burst $d3burst] \ + [list tout $d3tout] \ + [list nak $d3nak] \ + [list ack $d3ack] \ + [list busy $d3busy] \ + [list cacc $d0cacc] \ + [list racc $d0racc] \ + [list rmw $d3rmw] \ + [list be1 $d0be1] \ + [list be0 $d0be0] \ + [list we $d3we] \ + ] + + set edelay [expr {( [regget ibd_ibmon::DAT3(ndlymsb) $d3] << 6 ) | + [regget ibd_ibmon::DAT2(ndlylsb) $d2] }] + set enbusy [regget ibd_ibmon::DAT2(nbusy) $d2] + set edata $d1 + set eaddr [expr {0160000 | ($d0addr<<1)}] + lappend rval [list $eflag $eaddr $edata $edelay $enbusy] + } + + set nrest [expr {$nrest - ( $nblk >> 2 ) }] + } + + $cpu cp -wibr im.addr $raddr + + return $rval + } + # + # print: print ibmon data (optionally also read them) + # + proc print {{cpu "cpu0"} {mondat -1}} { + + if {[llength $mondat] == 1} { + set ele [lindex $mondat 0] + if {[llength $ele] == 1} { + set nent [lindex $ele 0] + set mondat [read $cpu $nent] + } + } + + set rval {} + set edlymax 16383 + + set eind [expr {1 - [llength $mondat] }] + append rval \ + " ind addr data delay nbsy btnab-crm10w acc-mode" + + set mtout [regbld ibd_ibmon::FLAGS tout ] + set mnak [regbld ibd_ibmon::FLAGS nak ] + set mack [regbld ibd_ibmon::FLAGS ack ] + set mbusy [regbld ibd_ibmon::FLAGS busy ] + set mcacc [regbld ibd_ibmon::FLAGS cacc ] + set mracc [regbld ibd_ibmon::FLAGS racc ] + set mrmw [regbld ibd_ibmon::FLAGS rmw ] + set mbe1 [regbld ibd_ibmon::FLAGS be1 ] + set mbe0 [regbld ibd_ibmon::FLAGS be0 ] + set mwe [regbld ibd_ibmon::FLAGS we ] + + foreach {ele} $mondat { + foreach {eflag eaddr edata edly enbusy} $ele { break } + + set ftout [expr {$eflag & $mtout} ] + set fnak [expr {$eflag & $mnak} ] + set fack [expr {$eflag & $mack} ] + set fbusy [expr {$eflag & $mbusy} ] + set fcacc [expr {$eflag & $mcacc} ] + set fracc [expr {$eflag & $mracc} ] + set frmw [expr {$eflag & $mrmw} ] + set fbe1 [expr {$eflag & $mbe1} ] + set fbe0 [expr {$eflag & $mbe0} ] + set fwe [expr {$eflag & $mwe} ] + + set prw "r" + set pmod " " + set pwe1 " " + set pwe0 " " + + if {$fwe } { + set prw "w" + set pwe1 "0" + set pwe0 "0" + if {$fbe1} { set pwe1 "1"} + if {$fbe0} { set pwe0 "1"} + } + if {$frmw} { set pmod "m"} + + set prmw "$pmod$prw$pwe1$pwe0" + set pacc "loc" + if {$fcacc} { set pacc "con"} + if {$fracc} { set pacc "rem"} + + set pedly [expr {$edly!=$edlymax ? [format "%5d" $edly] : " --"}] + set ename [format "%6.6o" $eaddr] + set comment "" + if {$fnak} {append comment " NAK=1!"} + if {$ftout} {append comment " TOUT=1!"} + if {[$cpu imap -testaddr $eaddr]} {set ename [$cpu imap -name $eaddr]} + append rval [format \ + "\n%5d %-10s %6.6o %5s %4d %s %s %s %s" \ + $eind $ename $edata $pedly $enbusy [pbvi b12 $eflag] \ + $prmw $pacc $comment] + incr eind + } + + return $rval + } + + # + # raw_edata: prepare edata lists for raw data reads in tests + # args is list of {eflag eaddr edata enbusy} sublists + + proc raw_edata {edat emsk args} { + upvar $edat uedat + upvar $emsk uemsk + set uedat {} + set uemsk {} + + set m3 [rutil::com16 [regbld ibd_ibmon::DAT3 {ndlymsb -1}]]; # all but ndly + set m2 [rutil::com16 [regbld ibd_ibmon::DAT2 {ndlylsb -1}]]; # all but ndly + set m1 0xffff + set m0 0xffff + + foreach line $args { + foreach {eflags eaddr edata enbusy} $line { break } + set d3 [regbld ibd_ibmon::DAT3 [list flags $eflags]] + set d2 [regbld ibd_ibmon::DAT2 [list nbusy $enbusy]] + if {$edata ne ""} { + set m1 0xffff + set d1 $edata + } else { + set m1 0x0000 + set d1 0x0000 + } + set d0 $eaddr + + lappend uedat $d0 $d1 $d2 $d3 + lappend uemsk $m0 $m1 $m2 $m3 + } + + return "" + } + + # + # raw_check: check raw data against expect values prepared by raw_edata + # + proc raw_check {{cpu "cpu0"} edat emsk} { + + $cpu cp \ + -ribr im.addr -edata [llength $edat] \ + -wibr im.addr 0 \ + -rbibr im.data [llength $edat] -edata $edat $emsk \ + -ribr im.addr -edata [llength $edat] + return "" + } + +} diff --git a/tools/tcl/ibd_rhrp/.cvsignore b/tools/tcl/ibd_rhrp/.cvsignore new file mode 100644 index 00000000..fc959ab2 --- /dev/null +++ b/tools/tcl/ibd_rhrp/.cvsignore @@ -0,0 +1 @@ +pkgIndex.tcl diff --git a/tools/tcl/ibd_rhrp/util.tcl b/tools/tcl/ibd_rhrp/util.tcl new file mode 100644 index 00000000..884860eb --- /dev/null +++ b/tools/tcl/ibd_rhrp/util.tcl @@ -0,0 +1,165 @@ +# $Id: util.tcl 678 2015-05-10 16:23:02Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# +# This program is free software; you may redistribute and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation, either version 2, or at your option any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for complete details. +# +# Revision History: +# Date Rev Version Comment +# 2015-03-21 659 1.0 Initial version +# + +package provide ibd_rhrp 1.0 + +package require rlink +package require rw11 + +namespace eval ibd_rhrp { + # + # setup register descriptions for ibd_rhrp --------------------------------- + # + regdsc CS1 {sc 15} {tre 14} {dva 11} {bae 9 2} \ + {rdy 7} {ie 6} {func 5 5} {go 0} + variable FUNC_NOOP [bvi b5 "00000"] + variable FUNC_UNL [bvi b5 "00001"] + variable FUNC_SEEK [bvi b5 "00010"] + variable FUNC_RECAL [bvi b5 "00011"] + variable FUNC_DCLR [bvi b5 "00100"] + variable FUNC_PORE [bvi b5 "00101"] + variable FUNC_OFFS [bvi b5 "00110"] + variable FUNC_RETC [bvi b5 "00111"] + variable FUNC_PRES [bvi b5 "01000"] + variable FUNC_PACK [bvi b5 "01001"] + variable FUNC_SEAR [bvi b5 "01100"] + variable FUNC_WCD [bvi b5 "10100"] + variable FUNC_WCHD [bvi b5 "10101"] + variable FUNC_WRITE [bvi b5 "11000"] + variable FUNC_WHD [bvi b5 "11001"] + variable FUNC_READ [bvi b5 "11100"] + variable FUNC_RHD [bvi b5 "11101"] + + regdsc RCS1 {val 15 8} {func 5 5} {go 0} + variable RFUNC_WUNIT [bvi b5 "00001"] + variable RFUNC_CUNIT [bvi b5 "00010"] + variable RFUNC_DONE [bvi b5 "00011"] + variable RFUNC_WIDLY [bvi b5 "00100"] + + regdsc DA {ta 12 5 2d} {sa 5 6 2d} + regdsc CS2 {wce 14} {ned 12} {nem 11} {pge 10} {or 7} {ir 6} \ + {clr 5} {pat 4} {bai 3} {unit 2 3 d} + regdsc DS {ata 15} {erp 14} {mol 12} {wrl 11} {lbt 10} {dpr 8} {dry 7} {vv 6} + regdsc ER1 {uns 14} {iae 10} {aoe 9} {rmr 2} {ilf 0} + regdsc AS {u3 3} {u2 2} {u1 1} {u0 0} + regdsc LA {sc 11 6 2d} + regdsc OF {fmt 12} {eci 11} {hci 10} {odi 7} {off 6 7} + + variable DTE_RP04 [bvi b3 "000"] + variable DTE_RP06 [bvi b3 "001"] + variable DTE_RM04 [bvi b3 "100"] + variable DTE_RM80 [bvi b3 "101"] + variable DTE_RM05 [bvi b3 "110"] + variable DTE_RP07 [bvi b3 "111"] + + variable DT_RP04 020020 + variable DT_RP06 020022 + variable DT_RM04 020024 + variable DT_RM80 020026 + variable DT_RM05 020027 + variable DT_RP07 020042 + + regdsc SN {d3 15 4 d} {d2 11 4 d} {d1 7 4 d} {d0 3 4 d} + regdsc OF {odi 7} + regdsc DC {dc 9 10 d} + + regdsc CS3 {ie 6} + + variable ANUM 6 + + # + # setup: create controller with default attributes ------------------------- + # + proc setup {{cpu "cpu0"}} { + return [rw11::setup_cntl $cpu "rhrp" "rpa"] + } + + # + # rcs1_wunit: value for rem CS1 WUNIT function ----------------------------- + # + proc rcs1_wunit {unit} { + return [regbld ibd_rhrp::RCS1 [list val $unit] \ + [list func $ibd_rhrp::RFUNC_WUNIT] ] + } + + # + # cs1_func: value for loc CS1 function start ------------------------------- + # + proc cs1_func {func {ie 0} {bae 0}} { + return [regbld ibd_rhrp::CS1 [list bae $bae] [list ie $ie] \ + [list func $func] {go 1}] + } + + # + # rdump: register dump - rem view ------------------------------------------ + # + proc rdump {{cpu "cpu0"} {unit 0}} { + set rval {} + $cpu cp -ribr "rpa.cs1" cs1 \ + -ribr "rpa.wc" wc \ + -ribr "rpa.ba" ba \ + -ribr "rpa.cs2" cs2 \ + -ribr "rpa.bae" bae \ + -ribr "rpa.cs3" cs3 + + if {$wc} { + set fwc [format "%d" [expr {64 * 1024 - $wc}]] + } else { + set fwc "(0)" + } + + append rval "Controller registers:" + append rval [format "\n cs1: %6.6o %s" $cs1 [regtxt ibd_rhrp::CS1 $cs1]] + append rval [format "\n cs2: %6.6o %s" $cs2 [regtxt ibd_rhrp::CS2 $cs2]] + append rval [format "\n cs3: %6.6o %s" $cs3 [regtxt ibd_rhrp::CS3 $cs3]] + append rval [format "\n wc: %6.6o nw=%s" $wc $fwc] + append rval [format "\n ba: %6.6o" $ba] + append rval [format "\n bae: %6.6o ea=%8.8o" $bae [expr {($bae<<16)|$ba}] ] + + $cpu cp -wibr "rpa.cs1" [rcs1_wunit $unit] \ + -ribr "rpa.da" da \ + -ribr "rpa.ds" ds \ + -ribr "rpa.er1" er1 \ + -ribr "rpa.as" as \ + -ribr "rpa.la" la \ + -ribr "rpa.mr1" mr1 \ + -ribr "rpa.dt" dt \ + -ribr "rpa.sn" sn \ + -ribr "rpa.of" of \ + -ribr "rpa.dc" dc + + append rval "\nUnit $unit registers:" + append rval [format "\n da: %6.6o %s" $da [regtxt ibd_rhrp::DA $da ]] + append rval [format "\n ds: %6.6o %s" $ds [regtxt ibd_rhrp::DS $ds ]] + append rval [format "\n er1: %6.6o %s" $er1 [regtxt ibd_rhrp::ER1 $er1]] + append rval [format "\n as: %6.6o as:%s" $as [pbvi b4 $as]] + append rval [format "\n la: %6.6o %s" $la [regtxt ibd_rhrp::LA $la ]] + append rval [format "\n mr1: %6.6o " $mr1 ] + append rval [format "\n dt: %6.6o " $dt ] + set snd3 [regget ibd_rhrp::SN(d3) $sn] + set snd2 [regget ibd_rhrp::SN(d2) $sn] + set snd1 [regget ibd_rhrp::SN(d1) $sn] + set snd0 [regget ibd_rhrp::SN(d0) $sn] + set sntxt [format "%d%d%d%d" $snd3 $snd2 $snd1 $snd0] + append rval [format "\n sn: %6.6o sn=%s" $sn $sntxt] + append rval [format "\n of: %6.6o %s" $of [regtxt ibd_rhrp::OF $of ]] + append rval [format "\n dc: %6.6o dc:%s" $dc [format "%3d" $dc]] + + return $rval + } +} diff --git a/tools/tcl/rbemon/test_regs.tcl b/tools/tcl/rbemon/test_regs.tcl index a9f49f20..659b93d8 100644 --- a/tools/tcl/rbemon/test_regs.tcl +++ b/tools/tcl/rbemon/test_regs.tcl @@ -1,6 +1,6 @@ -# $Id: test_regs.tcl 516 2013-05-05 21:24:52Z mueller $ +# $Id: test_regs.tcl 661 2015-04-03 18:28:41Z mueller $ # -# Copyright 2011-2013 by Walter F.J. Mueller +# Copyright 2011-2015 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-04-03 661 1.1 drop estatdef, use estaterr; fix test 4 # 2011-12-18 440 1.0.1 increase npoll in "CNTL.clr->0" test # 2011-04-02 375 1.0 Initial version # @@ -28,8 +29,6 @@ namespace eval rbemon { # Basic tests with rbd_eyemon registers # proc test_regs {} { - set esdval 0x00 - set esdmsk [regbld rlink::STAT {stat -1}] # set errcnt 0 rlc errcnt -clear @@ -41,7 +40,7 @@ namespace eval rbemon { # ensure that last value 0x0 -> go=0 foreach val [list [regbld rbemon::CNTL ena01] [regbld rbemon::CNTL ena10] \ [regbld rbemon::CNTL go] 0x0 ] { - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg em.cntl $val \ -rreg em.cntl -edata $val } @@ -49,7 +48,7 @@ namespace eval rbemon { #------------------------------------------------------------------------- rlc log " test 1b: write/read rdiv" foreach val [list [regbld rbemon::RDIV {rdiv -1}] 0x0 ] { - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg em.rdiv $val \ -rreg em.rdiv -edata $val } @@ -58,7 +57,7 @@ namespace eval rbemon { rlc log " test 1c: write/read addr" set amax [regget rbemon::ADDR(addr) -1] foreach addr [list 0x1 $amax 0x0] { - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg em.addr $addr \ -rreg em.addr -edata $addr } @@ -66,7 +65,7 @@ namespace eval rbemon { #------------------------------------------------------------------------- rlc log " test 2: verify addr increments on data reads" foreach addr [list 0x0 0x011 [expr {$amax - 1}]] { - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg em.addr $addr \ -rreg em.data \ -rreg em.addr -edata [expr {( $addr + 1 ) & $amax}] \ @@ -77,20 +76,17 @@ namespace eval rbemon { #------------------------------------------------------------------------- rlc log " test 3: verify rberr on DATA write and DATE read if in go state" rlc exec \ - -wreg em.data 0x0000 -estat [regbld rlink::STAT rberr] $esdmsk \ - -wreg em.cntl [regbld rbemon::CNTL go] -estat $esdval $esdmsk \ - -rreg em.data -estat [regbld rlink::STAT rberr] $esdmsk + -wreg em.data 0x0000 -estaterr \ + -wreg em.cntl [regbld rbemon::CNTL go] \ + -rreg em.data -estaterr # #------------------------------------------------------------------------- rlc log " test 4: verify that CNTL.clr returns to 0" - set npoll 48 - set edat {} - set emsk {} - for {set i 0} {$i < $npoll} {incr i} { lappend edat 0x0000 } - for {set i 1} {$i < $npoll} {incr i} { lappend emsk 0xffff } - rlc exec -estatdef $esdval $esdmsk \ + set npoll 64; # wait 64 rbus cycles, than test + rlc exec \ -wreg em.cntl [regbld rbemon::CNTL clr] \ - -rblk em.cntl $npoll -edata $edat $emsk + -rblk em.cntl $npoll \ + -rreg em.cntl -edata 0x0 # incr errcnt [rlc errcnt -clear] return $errcnt diff --git a/tools/tcl/rbmoni/test_rbtest.tcl b/tools/tcl/rbmoni/test_rbtest.tcl index dedb6370..922d5ae6 100644 --- a/tools/tcl/rbmoni/test_rbtest.tcl +++ b/tools/tcl/rbmoni/test_rbtest.tcl @@ -1,6 +1,6 @@ -# $Id: test_rbtest.tcl 619 2014-12-23 13:17:41Z mueller $ +# $Id: test_rbtest.tcl 661 2015-04-03 18:28:41Z mueller $ # -# Copyright 2011-2014 by Walter F.J. Mueller +# Copyright 2011-2015 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-04-03 661 2.1 drop estatdef; fix test 5 (wrong regs accessed) # 2014-12-22 619 2.0 adopt to new rbd_rbmon and rlink v4 # 2011-03-27 374 1.0 Initial version # 2011-03-13 369 0.1 First Draft @@ -30,8 +31,6 @@ namespace eval rbmoni { # Basic tests with rbtester registers # proc test_rbtest {{print 0}} { - set esdval 0x00 - set esdmsk [regbld rlink::STAT {stat -1}] # set errcnt 0 rlc errcnt -clear @@ -57,7 +56,7 @@ namespace eval rbmoni { set vtedata 0x1234 # write/read te.stat and te.data with rbmoni on; check that 4 lines aquired - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg rm.cntl [regbld rbmoni::CNTL start] \ -wreg te.stat $vtestat \ -wreg te.data $vtedata \ @@ -79,7 +78,7 @@ namespace eval rbmoni { # #------------------------------------------------------------------------- rlc log " test 1a: read all in one rblk" - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg rm.addr 0x0000 \ -rblk rm.data 16 -edata $edat $emsk \ -rreg rm.addr -edata 16 @@ -89,7 +88,7 @@ namespace eval rbmoni { rlc log " test 1b: random address with rreg" foreach addr {0x1 0x3 0x5 0x7 0x6 0x4 0x2 0x0 \ 0x9 0xb 0xd 0xf 0xe 0xc 0xa 0x8} { - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg rm.addr $addr \ -rreg rm.data -edata [lindex $edat $addr] [lindex $emsk $addr] \ -rreg rm.addr -edata [expr {$addr + 1}] @@ -100,7 +99,7 @@ namespace eval rbmoni { rlc log " test 1c: random address with rblk length 2" foreach addr {0x1 0x3 0x5 0x7 0x6 0x4 0x2 0x0 \ 0x9 0xb 0xd 0xe 0xc 0xa 0x8} { - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg rm.addr $addr \ -rblk rm.data 2 -edata [lrange $edat $addr [expr {$addr + 1}] ] \ [lrange $emsk $addr [expr {$addr + 1}] ] \ @@ -117,7 +116,7 @@ namespace eval rbmoni { [list [regbld rbmoni::FLAGS ack ] $atedata $vtedata 0] # rbmoni::start - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.data $vtedata \ -rreg te.data -edata $vtedata rbmoni::stop @@ -139,7 +138,7 @@ namespace eval rbmoni { [list [regbld rbmoni::FLAGS ack we] $atecntl 0 0] # rbmoni::start - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.cntl $nbusy_1 \ -wreg te.data $vtedata \ -wreg te.cntl $nbusy_4 \ @@ -163,7 +162,7 @@ namespace eval rbmoni { [list [regbld rbmoni::FLAGS ack we] $atecntl 0 0] # rbmoni::start - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.cntl $vtecntl \ -wreg te.data $vtedata -estat [regbld rlink::STAT rbtout] \ -rreg te.data -edata 0x5555 -estat [regbld rlink::STAT rbtout] \ @@ -182,7 +181,7 @@ namespace eval rbmoni { [list [regbld rbmoni::FLAGS nak ] $atelnak {} 0] # rbmoni::start - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.lnak $vtelnak -estat [regbld rlink::STAT rbnak] \ -rreg te.lnak -estat [regbld rlink::STAT rbnak] rbmoni::stop @@ -202,7 +201,7 @@ namespace eval rbmoni { [list [regbld rbmoni::FLAGS ack we] $atecntl 0 0] # rbmoni::start - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.cntl $vtecntl \ -wreg te.lnak $vtelnak -estat [regbld rlink::STAT rbnak] \ -rreg te.lnak -estat [regbld rlink::STAT rbnak] \ @@ -222,7 +221,7 @@ namespace eval rbmoni { [list [regbld rbmoni::FLAGS ack err ] $atefifo {} 0] # rbmoni::start - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.fifo $vtefifo \ -rreg te.fifo -edata $vtefifo \ -rreg te.fifo -estat [regbld rlink::STAT rberr] @@ -244,11 +243,11 @@ namespace eval rbmoni { [list [regbld rbmoni::FLAGS ack we] $atecntl 0 0] # rbmoni::start - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.cntl $vtecntl \ -wreg te.fifo $vtefifo \ -rreg te.fifo -edata $vtefifo \ - -rreg te.fifo -estat [regbld rlink::STAT rberr] \ + -rreg te.fifo -estaterr \ -wreg te.cntl 0x0 rbmoni::stop if {$print} {puts [print]} @@ -266,7 +265,7 @@ namespace eval rbmoni { [list [regbld rbmoni::FLAGS ack ] $atecntl 0 0] # rbmoni::start - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.cntl $vtecntl \ -init te.cntl $vteinit \ -rreg te.cntl -edata 0 @@ -293,7 +292,7 @@ namespace eval rbmoni { [list [regbld rbmoni::FLAGS nak init] $atecntl $vteinit 0] # rbmoni::start - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -init te.cntl $vteinit \ -wblk te.fifo $vtefifo \ -wreg te.cntl $nbusy_2 \ @@ -310,7 +309,7 @@ namespace eval rbmoni { rlc exec -wreg rm.lolim $atencyc \ -wreg rm.hilim $atedinc - # now access all regs, but only ncyc,data,dinc should be recorded + # now access all regs (except attn,lnak), but only ncyc,data,dinc recorded raw_edata edat emsk \ [list [regbld rbmoni::FLAGS ack ] $atencyc 0x0001 0] \ [list [regbld rbmoni::FLAGS ack we] $atedata 0x2345 0] \ @@ -320,14 +319,12 @@ namespace eval rbmoni { rbmoni::start rlc exec -rreg te.cntl \ -rreg te.stat \ - -rreg te.attn \ -rreg te.ncyc \ -wreg te.data 0x2345 \ -wreg te.fifo 0xbeaf \ -rreg te.dinc -edata 0x2345 \ -rreg te.fifo -edata 0xbeaf \ - -rreg te.data -edata 0x2346 \ - -rreg te.lnak + -rreg te.data -edata 0x2346 rbmoni::stop if {$print} {puts [print]} raw_check $edat $emsk diff --git a/tools/tcl/rbmoni/test_regs.tcl b/tools/tcl/rbmoni/test_regs.tcl index 71d40f30..e4019793 100644 --- a/tools/tcl/rbmoni/test_regs.tcl +++ b/tools/tcl/rbmoni/test_regs.tcl @@ -1,6 +1,6 @@ -# $Id: test_regs.tcl 622 2014-12-28 20:45:26Z mueller $ +# $Id: test_regs.tcl 661 2015-04-03 18:28:41Z mueller $ # -# Copyright 2011- by Walter F.J. Mueller +# Copyright 2011-2015 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-04-03 661 2.1 drop estatdef (stat err check default now) # 2014-12-27 622 2.0 rbd_rbmon reorganized, supports now 16 bit addresses # 2011-03-27 374 1.0 Initial version # 2011-03-13 369 0.1 First Draft @@ -29,8 +30,6 @@ namespace eval rbmoni { # Basic tests with rbtester registers # proc test_regs {} { - set esdval 0x00 - set esdmsk [regbld rlink::STAT {stat -1}] # set errcnt 0 rlc errcnt -clear @@ -39,7 +38,7 @@ namespace eval rbmoni { # #------------------------------------------------------------------------- rlc log " test 1: write/read cntl" - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg rm.cntl [regbld rbmoni::CNTL start] \ -rreg rm.cntl -edata [regbld rbmoni::CNTL start] \ -wreg rm.cntl [regbld rbmoni::CNTL stop] \ @@ -51,7 +50,7 @@ namespace eval rbmoni { # #------------------------------------------------------------------------- rlc log " test 2: read stat" - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -rreg rm.stat rstat set bsize [regget rbmoni::STAT(bsize) $rstat] set amax [expr {( 512 << $bsize ) - 1}] @@ -60,7 +59,7 @@ namespace eval rbmoni { rlc log " test 3: write/read hilim/lolim" foreach {lolim hilim} {0xffff 0x0000 \ 0x0000 0xfffb} { - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg rm.lolim $lolim -wreg rm.hilim $hilim \ -rreg rm.lolim -edata $lolim -rreg rm.hilim -edata $hilim } @@ -69,14 +68,14 @@ namespace eval rbmoni { rlc log " test 4: write/read addr" foreach {laddr waddr} [list 0x0000 0 0x0000 3 $amax 0 $amax 3] { set addr [regbld rbmoni::ADDR [list laddr $laddr] [list waddr $waddr]] - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg rm.addr $addr \ -rreg rm.addr -edata $addr } # #------------------------------------------------------------------------- rlc log " test 5: verify that cntl.go 0->1 clear addr" - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg rm.cntl [regbld rbmoni::CNTL stop] \ -rreg rm.cntl -edata 0x0 \ -wreg rm.addr [regbld rbmoni::ADDR [list laddr $amax]] \ diff --git a/tools/tcl/rbmoni/util.tcl b/tools/tcl/rbmoni/util.tcl index f3690e5a..9188ae1d 100644 --- a/tools/tcl/rbmoni/util.tcl +++ b/tools/tcl/rbmoni/util.tcl @@ -1,6 +1,6 @@ -# $Id: util.tcl 619 2014-12-23 13:17:41Z mueller $ +# $Id: util.tcl 661 2015-04-03 18:28:41Z mueller $ # -# Copyright 2011-2014 by Walter F.J. Mueller +# Copyright 2011-2015 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-04-03 661 3.1 drop estatdef; invert mask in raw_edata # 2014-12-23 619 3.0 rbd_rbmon reorganized, supports now 16 bit addresses # 2014-11-09 603 2.0 use rlink v4 address layout # 2011-03-27 374 1.0 Initial version @@ -217,20 +218,20 @@ namespace eval rbmoni { set uedat {} set uemsk {} - set m3 [regbld rbmoni::DAT3 {ndlymsb -1}] - set m2 [regbld rbmoni::DAT2 {ndlylsb -1}] - set m1 0 - set m0 0 + set m3 [rutil::com16 [regbld rbmoni::DAT3 {ndlymsb -1}]]; # all but ndlymsb + set m2 [rutil::com16 [regbld rbmoni::DAT2 {ndlylsb -1}]]; # all but ndlylsb + set m1 0xffff + set m0 0xffff foreach line $args { foreach {eflags eaddr edata enbusy} $line { break } set d3 [regbld rbmoni::DAT3 [list flags $eflags]] set d2 [regbld rbmoni::DAT2 [list nbusy $enbusy]] if {$edata ne ""} { - set m1 0x0000 + set m1 0xffff set d1 $edata } else { - set m1 0xffff + set m1 0x0000 set d1 0x0000 } set d0 $eaddr @@ -247,7 +248,7 @@ namespace eval rbmoni { # proc raw_check {edat emsk} { - rlc exec -estatdef 0x0 [regbld rlink::STAT {stat -1}] \ + rlc exec \ -rreg rm.addr -edata [llength $edat] \ -wreg rm.addr 0 \ -rblk rm.data [llength $edat] -edata $edat $emsk \ diff --git a/tools/tcl/rbtest/test_all.tcl b/tools/tcl/rbtest/test_all.tcl index 0220f9df..d2aa0b19 100644 --- a/tools/tcl/rbtest/test_all.tcl +++ b/tools/tcl/rbtest/test_all.tcl @@ -1,6 +1,6 @@ -# $Id: test_all.tcl 375 2011-04-02 07:56:47Z mueller $ +# $Id: test_all.tcl 662 2015-04-05 08:02:54Z mueller $ # -# Copyright 2011- by Walter F.J. Mueller +# Copyright 2011-2015 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-04-03 662 1.1 add test_labo # 2011-03-27 374 1.0 Initial version # 2011-03-13 369 0.1 First draft # @@ -28,6 +29,7 @@ namespace eval rbtest { set errcnt 0 incr errcnt [rbtest::test_data] incr errcnt [rbtest::test_fifo] + incr errcnt [rbtest::test_labo] incr errcnt [rbtest::test_stat $statmsk] incr errcnt [rbtest::test_attn $attnmsk] return $errcnt diff --git a/tools/tcl/rbtest/test_attn.tcl b/tools/tcl/rbtest/test_attn.tcl index 760cc690..854cc2bf 100644 --- a/tools/tcl/rbtest/test_attn.tcl +++ b/tools/tcl/rbtest/test_attn.tcl @@ -1,6 +1,6 @@ -# $Id: test_attn.tcl 603 2014-11-09 22:50:26Z mueller $ +# $Id: test_attn.tcl 661 2015-04-03 18:28:41Z mueller $ # -# Copyright 2011-2014 by Walter F.J. Mueller +# Copyright 2011-2015 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-04-03 661 2.1 drop estatdef (stat err check default now) # 2014-11-09 603 2.0 use rlink v4 address layout and iface # 2011-03-27 374 1.0 Initial version # 2011-03-20 372 0.1 First Draft @@ -32,9 +33,6 @@ namespace eval rbtest { # quit if nothing to do... if {$attnmsk == 0} {return 0} # - set esdval 0x00 - set esdmsk [regbld rlink::STAT {stat -1} attn] - # set apats {} for {set i 0} {$i < 16} {incr i} { set apat [expr {1 << $i}] @@ -52,7 +50,7 @@ namespace eval rbtest { #------------------------------------------------------------------------- rlc log " test 1: verify connection of attn bits" foreach apat $apats { - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.attn $apat \ -rreg te.cntl -estat [regbld rlink::STAT attn] \ -attn -edata $apat \ @@ -63,9 +61,9 @@ namespace eval rbtest { #------------------------------------------------------------------------- rlc log " test 2: verify that attn flags accumulate" foreach apat $apats { - rlc exec -wreg te.attn $apat -estat $esdval $esdmsk + rlc exec -wreg te.attn $apat } - rlc exec -attn -edata $attnmsk -estat $esdval $esdmsk + rlc exec -attn -edata $attnmsk # #------------------------------------------------------------------------- diff --git a/tools/tcl/rbtest/test_data.tcl b/tools/tcl/rbtest/test_data.tcl index 641b633e..3f4dea01 100644 --- a/tools/tcl/rbtest/test_data.tcl +++ b/tools/tcl/rbtest/test_data.tcl @@ -1,6 +1,6 @@ -# $Id: test_data.tcl 617 2014-12-21 14:18:53Z mueller $ +# $Id: test_data.tcl 661 2015-04-03 18:28:41Z mueller $ # -# Copyright 2011-2014 by Walter F.J. Mueller +# Copyright 2011-2015 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-04-03 661 2.1 drop estatdef, use estattout # 2014-12-21 617 2.0.1 use rbtout stat bit for timeout # 2014-11-09 603 2.0 use rlink v4 address layout and iface # 2011-03-27 374 1.0 Initial version @@ -32,8 +33,6 @@ namespace eval rbtest { # rbd_tester is embedded in the design (e.g. stat and attn connections) # proc test_data {} { - set esdval 0x00 - set esdmsk [regbld rlink::STAT {stat -1}] # set errcnt 0 rlc errcnt -clear @@ -50,14 +49,14 @@ namespace eval rbtest { te.stat 0x0000 0x0000 \ te.data 0xffff 0xffff \ te.data 0x0000 0x0000 ] { - rlc exec -wreg $addr $valw -estat $esdval $esdmsk - rlc exec -rreg $addr -edata $valr -estat $esdval $esdmsk + rlc exec -wreg $addr $valw + rlc exec -rreg $addr -edata $valr } # # rlc log " test 1b: as test 1a, use clists, check cntl,stat,data distinct" foreach {valc vals vald} [list 0x1 0x2 0x3 0x0 0x0 0x0] { - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.cntl $valc \ -wreg te.stat $vals \ -wreg te.data $vald \ @@ -68,19 +67,19 @@ namespace eval rbtest { # #------------------------------------------------------------------------- rlc log " test 2: verify that large nbusy causes timeout" - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.data 0xdead \ -rreg te.data -edata 0xdead \ -wreg te.cntl [regbld rbtest::CNTL {nbusy 0x3ff}] \ - -wreg te.data 0xbeaf -estat [regbld rlink::STAT rbtout] $esdmsk \ - -rreg te.data -estat [regbld rlink::STAT rbtout] $esdmsk \ + -wreg te.data 0xbeaf -estattout \ + -rreg te.data -estattout \ -wreg te.cntl 0x0000 \ - -rreg te.data -edata 0xdead -edata 0xdead + -rreg te.data -edata 0xdead # # ------------------------------------------------------------------------- rlc log " test 3a: verify that init 001 clears cntl,stat and not data" set valc [regbld rbtest::CNTL {nbusy 1}] - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.cntl $valc \ -wreg te.stat 0x0002 \ -wreg te.data 0x1234 \ @@ -90,7 +89,7 @@ namespace eval rbtest { -wreg te.data 0x1234 rlc log " test 3b: verify that init 010 clears data and not cntl,stat" set valc [regbld rbtest::CNTL {nbusy 2}] - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.cntl $valc \ -wreg te.stat 0x0003 \ -wreg te.data 0x4321 \ @@ -99,7 +98,7 @@ namespace eval rbtest { -rreg te.stat -edata 0x0003 \ -wreg te.data 0x0 rlc log " test 3c: verify that init 011 clears data and cntl,stat" - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.cntl [regbld rbtest::CNTL {nbusy 3}] \ -wreg te.stat 0x0004 \ -wreg te.data 0xabcd \ @@ -112,7 +111,7 @@ namespace eval rbtest { rlc log " test 4: test that te.ncyc returns # of cycles for te.data w&r" foreach nbusy {0x03 0x07 0x0f 0x1f 0x00} { set valc [regbld rbtest::CNTL [list nbusy $nbusy]] - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.cntl $valc \ -wreg te.data [expr {$nbusy | ( $nbusy << 8 ) }] \ -rreg te.ncyc -edata [expr {$nbusy + 1 }] \ diff --git a/tools/tcl/rbtest/test_fifo.tcl b/tools/tcl/rbtest/test_fifo.tcl index 6232f9ee..bea20cd3 100644 --- a/tools/tcl/rbtest/test_fifo.tcl +++ b/tools/tcl/rbtest/test_fifo.tcl @@ -1,6 +1,6 @@ -# $Id: test_fifo.tcl 603 2014-11-09 22:50:26Z mueller $ +# $Id: test_fifo.tcl 662 2015-04-05 08:02:54Z mueller $ # -# Copyright 2011-2014 by Walter F.J. Mueller +# Copyright 2011-2015 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-04-03 661 2.1 drop estatdef; use estaterr # 2014-11-09 603 2.0 use rlink v4 address layout and iface # 2011-03-27 374 1.0 Initial version # 2011-03-13 369 0.1 First draft @@ -29,8 +30,6 @@ namespace eval rbtest { # Basic tests with cntl and fifo registers. # proc test_fifo {} { - set esdval 0x00 - set esdmsk [regbld rlink::STAT {stat -1}] # set errcnt 0 rlc errcnt -clear @@ -42,11 +41,11 @@ namespace eval rbtest { #------------------------------------------------------------------------- rlc log " test 1: fifo write/read with wreg/rreg" # single word - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.fifo 0x0000 \ - -rreg te.fifo -estat 0x0000 + -rreg te.fifo -estat 0x00 # three words - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.fifo 0xdead \ -wreg te.fifo 0xbeaf \ -wreg te.fifo 0x1234 \ @@ -55,24 +54,24 @@ namespace eval rbtest { -rreg te.fifo -edata 0x1234 # #------------------------------------------------------------------------- - rlc log " test 2: fifo write/read with wblk/rblk" + rlc log " test 2: fifo write/read with wblk/rblk and -edone" # two words set blk {0x1111 0x2222} - rlc exec -estatdef $esdval $esdmsk \ - -wblk te.fifo $blk \ - -rblk te.fifo [llength $blk] -edata $blk + rlc exec \ + -wblk te.fifo $blk -edone [llength $blk] \ + -rblk te.fifo [llength $blk] -edata $blk -edone [llength $blk] # six words set blk {0x3333 0x4444 0x5555 0x6666 0x7777 0x8888} - rlc exec -estatdef $esdval $esdmsk \ - -wblk te.fifo $blk \ - -rblk te.fifo [llength $blk] -edata $blk + rlc exec \ + -wblk te.fifo $blk -edone [llength $blk] \ + -rblk te.fifo [llength $blk] -edata $blk -edone [llength $blk] # #------------------------------------------------------------------------- - rlc log " test 3a: fifo read error (write 3, read 4)" + rlc log " test 3a: fifo read error (write 3, read 4) and -edone" set blk {0xdead 0xbeaf 0x1234} - rlc exec -estatdef $esdval $esdmsk \ - -wblk te.fifo $blk \ - -rblk te.fifo 4 -edata $blk -estat [regbld rlink::STAT rberr] $esdmsk + rlc exec \ + -wblk te.fifo $blk -edone [llength $blk] \ + -rblk te.fifo 4 -edata $blk -edone 3 -estaterr # # rlc log " test 3b: fifo write error (write 17, read 16)" @@ -80,21 +79,21 @@ namespace eval rbtest { for { set i 0 } { $i < 17 } { incr i } { lappend blk [expr {$i | ( $i << 8 ) }] } - rlc exec -estatdef $esdval $esdmsk \ - -wblk te.fifo $blk -estat [regbld rlink::STAT rberr] $esdmsk \ - -rblk te.fifo 16 -edata [lrange $blk 0 15] + rlc exec \ + -wblk te.fifo $blk -edone 16 -estaterr \ + -rblk te.fifo 16 -edata [lrange $blk 0 15] -edone 16 # #------------------------------------------------------------------------- rlc log " test 4a: verify that init 100 clears fifo and not cntl&data" # check fifo empty; write a value; clear fifo via init; check fifo empty # check that cntl and data not affected - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.cntl [regbld rbtest::CNTL {nbusy 0x1}] \ -wreg te.data 0x1234 \ - -rreg te.fifo -estat [regbld rlink::STAT rberr] $esdmsk \ + -rreg te.fifo -estaterr \ -wreg te.fifo 0x4321 \ -init te.cntl [regbld rbtest::INIT fifo] \ - -rreg te.fifo -estat [regbld rlink::STAT rberr] $esdmsk \ + -rreg te.fifo -estaterr \ -rreg te.cntl -edata [regbld rbtest::CNTL {nbusy 0x1}] \ -rreg te.data -edata 0x1234 # @@ -102,7 +101,7 @@ namespace eval rbtest { rlc log " test 6: test that te.ncyc returns # of cycles for te.fifo w&r" foreach nbusy {0x03 0x07 0x0f 0x1f 0x00} { set valc [regbld rbtest::CNTL [list nbusy $nbusy]] - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.cntl $valc \ -wreg te.fifo [expr {$nbusy | ( $nbusy << 8 ) }] \ -rreg te.ncyc -edata [expr {$nbusy + 1 }] \ @@ -118,7 +117,7 @@ namespace eval rbtest { set bcode [expr {32 * $i + 2 * $j}] lappend blk [expr {( $bcode << 8 ) | ( $bcode + 1 )}] } - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wblk te.fifo $blk \ -rblk te.fifo [llength $blk] -edata $blk } diff --git a/tools/tcl/rbtest/test_labo.tcl b/tools/tcl/rbtest/test_labo.tcl new file mode 100644 index 00000000..b5268d3b --- /dev/null +++ b/tools/tcl/rbtest/test_labo.tcl @@ -0,0 +1,175 @@ +# $Id: test_labo.tcl 662 2015-04-05 08:02:54Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# +# This program is free software; you may redistribute and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation, either version 2, or at your option any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for complete details. +# +# Revision History: +# Date Rev Version Comment +# 2015-04-03 662 1.0 Initial version +# + +package provide rbtest 1.0 + +package require rutiltpp +package require rutil +package require rlink + +namespace eval rbtest { + # + # Test labo with fifo + # + proc test_labo {} { + # + set errcnt 0 + rlc errcnt -clear + # + rlc log "rbtest::test_labo - init: clear cntl, data, and fifo" + rlc exec -init te.cntl [regbld rbtest::INIT fifo data cntl] + # + #------------------------------------------------------------------------- + rlc log " test 1: check that sucessfull blk's do not abort chain" + + # use data reg to monitor labo aborts + rlc exec \ + -wreg te.data 0x0000 + + set blk0 {0x1111 0x2222} + set blk1 {0x3333 0x4444} + set blk {0x1111 0x2222 0x3333 0x4444} + rlc exec \ + -wblk te.fifo $blk0 \ + -labo -edata 0 \ + -wblk te.fifo $blk1 \ + -labo -edata 0 \ + -rblk te.fifo 4 -edata $blk \ + -labo -edata 0 \ + -wreg te.data 0x0001 + + # no labo above, so 0x01 written to data ! + rlc exec \ + -rreg te.data -edata 0x0001 + + # + #------------------------------------------------------------------------- + rlc log " test 2: check that failed rblk aborts chain" + + rlc exec \ + -wblk te.fifo $blk0 \ + -labo -edata 0 \ + -wblk te.fifo $blk1 \ + -labo -edata 0 \ + -wreg te.data 0x0010 \ + -rblk te.fifo 6 -edata $blk -edone 4 -estaterr \ + -labo -edata 1 \ + -wreg te.data 0x0011 \ + -rreg te.data -edata 0xffff \ + -wreg te.data 0x0012 + + # last labo aborted, so 0x10 written, but not 0x11 or 0x12 + rlc exec \ + -rreg te.data -edata 0x0010 + + # + #------------------------------------------------------------------------- + rlc log " test 3: check that failed wblk aborts chain" + + set blk {} + for { set i 0 } { $i < 17 } { incr i } { + lappend blk [expr {$i | ( $i << 8 ) }] + } + rlc exec \ + -wreg te.data 0x0020 \ + -wblk te.fifo $blk -edone 16 -estaterr \ + -labo -edata 1 \ + -wreg te.data 0x0021 \ + -rreg te.data -edata 0xffff \ + -wreg te.data 0x0022 + + # last labo aborted, so 0x20 written, but not 0x21 + rlc exec \ + -rreg te.data -edata 0x0020 + + # + #------------------------------------------------------------------------- + rlc log " test 4a: check that babo state kept over clists" + + rlc exec \ + -wreg te.data 0x0030 \ + -labo -edata 1 \ + -wreg te.data 0x0031 + + # no blk done, so labo state sicks, so 0x30 written, but not 0x31 + rlc exec \ + -rreg te.data -edata 0x0030 + + # + #------------------------------------------------------------------------- + rlc log " test 4b: check that babo readable from RLSTAT" + + # babo still set + set babomsk [regbld rlink::RLSTAT babo] + rlc exec \ + -rreg $rlink::ADDR_RLSTAT -edata $babomsk $babomsk + + # + #------------------------------------------------------------------------- + rlc log " test 4c: check that babo reset by successful rblk" + + rlc exec \ + -wreg te.data 0x0040 \ + -rblk te.fifo 8 -edata [lrange $blk 0 7] \ + -rreg $rlink::ADDR_RLSTAT -edata 0x0 $babomsk \ + -rblk te.fifo 8 -edata [lrange $blk 8 15] \ + -rreg $rlink::ADDR_RLSTAT -edata 0x0 $babomsk \ + -rblk te.fifo 8 -edone 0 -estaterr \ + -rreg $rlink::ADDR_RLSTAT -edata $babomsk $babomsk \ + -labo -edata 1 \ + -wreg te.data 0x0041 + + # last rblk failed again so 0x40 written, but not 0x41 + rlc exec \ + -rreg te.data -edata 0x0040 + + # + #------------------------------------------------------------------------- + rlc log " test 4d: check that babo reset by successful wblk" + + set blk2 {0x5555 0x6666} + rlc exec \ + -wblk te.fifo $blk2 \ + -rreg $rlink::ADDR_RLSTAT -edata 0x0 $babomsk + + # + #------------------------------------------------------------------------- + rlc log " test 5: check commands between blk and labo are accepted" + + # there are two words in fifo from previous test + rlc exec \ + -wreg te.data 0x0050 \ + -rblk te.fifo 4 -edata $blk2 -edone 2 -estaterr \ + -rreg $rlink::ADDR_RLSTAT -edata $babomsk $babomsk \ + -wreg te.data 0x0051 \ + -labo -edata 1 \ + -wreg te.data 0x0052 + + # last rblk failed so 0x50 written, also 0x51, but not 0x52 + rlc exec \ + -rreg te.data -edata 0x0051 + + # + #------------------------------------------------------------------------- + rlc log "rbtest::test_fifo - cleanup: clear cntl, data, and fifo" + rlc exec -init te.cntl [regbld rbtest::INIT fifo data cntl] + # + incr errcnt [rlc errcnt -clear] + return $errcnt + } +} diff --git a/tools/tcl/rbtest/util.tcl b/tools/tcl/rbtest/util.tcl index 10ac18dc..eaf94839 100644 --- a/tools/tcl/rbtest/util.tcl +++ b/tools/tcl/rbtest/util.tcl @@ -1,4 +1,4 @@ -# $Id: util.tcl 617 2014-12-21 14:18:53Z mueller $ +# $Id: util.tcl 661 2015-04-03 18:28:41Z mueller $ # # Copyright 2011-2014 by Walter F.J. Mueller # @@ -58,13 +58,13 @@ namespace eval rbtest { # restore te.cntl proc nbusymax {} { - set esdmsk [regbld rlink::STAT {stat -1} attn] - rlc exec -estatdef 0 $esdmsk \ + set esdmsk [regbld rlink::STAT rbtout rbnak rberr] + rlc exec \ -rreg te.cntl sav_cntl \ -wreg te.cntl [regbld rbtest::CNTL {nbusy -1}] \ -rreg te.data -estat [regbld rlink::STAT rbtout] $esdmsk \ -rreg te.ncyc ncyc - rlc exec -estatdef 0 $esdmsk \ + rlc exec \ -wreg te.cntl $sav_cntl return [expr {$ncyc - 1}] } @@ -72,10 +72,7 @@ namespace eval rbtest { # probe: determine rbd_tester environment (max nbusy, stat and attn wiring) # proc probe {} { - set esdval 0x00 - set esdmsk [regbld rlink::STAT {stat -1}] - set esdmsktout [regbld rlink::STAT {stat -1} rbtout] - set esdmskattn [regbld rlink::STAT {stat -1} attn] + set esdmsktout [regbld rlink::STAT rbnak rberr] set rbusy {} set rstat {} set rattn {} @@ -90,9 +87,9 @@ namespace eval rbtest { set nbusy [expr {$nbusy0 + $j}] set valc [regbld rbtest::CNTL [list nbusy $nbusy]] rlc exec \ - -wreg te.cntl $valc -estat $esdval $esdmsk\ - -wreg te.data 0x0000 statwr -estat $esdval $esdmsktout \ - -rreg te.data dummy statrd -estat $esdval $esdmsktout + -wreg te.cntl $valc \ + -wreg te.data 0x0000 statwr -estat 0x0 $esdmsktout \ + -rreg te.data dummy statrd -estat 0x0 $esdmsktout if {[llength $wrerr] == 0 && [regget rlink::STAT(rbnak) $statwr] != 0} { lappend wrerr $i $j $nbusy } @@ -107,7 +104,7 @@ namespace eval rbtest { # probe stat wiring # for {set i 0} { $i < 4 } {incr i} { - rlc exec -estatdef $esdval $esdmsk \ + rlc exec \ -wreg te.stat [expr {1 << $i}] \ -rreg te.data dummy statrd lappend rstat [list $i [regget rlink::STAT(stat) $statrd]] @@ -118,7 +115,7 @@ namespace eval rbtest { # rlc exec -attn for {set i 0} { $i < 16 } {incr i} { - rlc exec -estatdef $esdval $esdmskattn \ + rlc exec \ -wreg te.attn [expr {1 << $i}] \ -attn attnpat lappend rattn [list $i $attnpat] diff --git a/tools/tcl/rlink/util.tcl b/tools/tcl/rlink/util.tcl index edc8ed53..0ba08af9 100644 --- a/tools/tcl/rlink/util.tcl +++ b/tools/tcl/rlink/util.tcl @@ -1,4 +1,4 @@ -# $Id: util.tcl 617 2014-12-21 14:18:53Z mueller $ +# $Id: util.tcl 661 2015-04-03 18:28:41Z mueller $ # # Copyright 2011-2014 by Walter F.J. Mueller # @@ -27,9 +27,11 @@ package require rutil 1.0 namespace eval rlink { regdsc STAT {stat 7 4} {attn 3} {rbtout 2} {rbnak 1} {rberr 0} + variable STAT_DEFMASK [regbld rlink::STAT rbtout rbnak rberr] + regdsc RLCNTL {anena 15} {atoena 14} {atoval 7 8} regdsc RLSTAT {lcmd 15 8} {babo 7} {rbsize 2 3} - # + # 'pseudo register', describes 3rd word in return list element for -rlist regdsc FLAGS {vol 16} \ {chkdata 13} {chkstat 12} \ diff --git a/tools/tcl/rutil/util.tcl b/tools/tcl/rutil/util.tcl index 00f65734..61b47b9f 100644 --- a/tools/tcl/rutil/util.tcl +++ b/tools/tcl/rutil/util.tcl @@ -1,6 +1,6 @@ -# $Id: util.tcl 619 2014-12-23 13:17:41Z mueller $ +# $Id: util.tcl 661 2015-04-03 18:28:41Z mueller $ # -# Copyright 2011-2014 by Walter F.J. Mueller +# Copyright 2011-2015 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-03-28 660 1,0,4 add com8 and com16 # 2014-12-23 619 1.0.3 regget: add check for unknown field descriptor # 2014-07-12 569 1.0.2 add sxt16 and sxt32 # 2013-05-09 517 1.0.1 add optlist2arr @@ -202,6 +203,7 @@ namespace eval rutil { } return $rval } + # # errcnt2txt: returns "PASS" if 0 and "FAIL" otherwise --------------------- # @@ -209,6 +211,7 @@ namespace eval rutil { if {$errcnt} {return "FAIL"} return "PASS" } + # # sxt16: 16 bit sign extend ------------------------------------------------ # @@ -229,6 +232,20 @@ namespace eval rutil { return $val } + # + # com8: 8 bit complement --------------------------------------------------- + # + proc com8 {val} { + return [expr (~$val) & 0xff] + } + + # + # com16: 16 bit complement ------------------------------------------------ + # + proc com16 {val} { + return [expr (~$val) & 0xffff] + } + # # ! export reg... procs to global scope ------------------------------------ # diff --git a/tools/tcl/rw11/tbench.tcl b/tools/tcl/rw11/tbench.tcl index c995ea1f..86ca8fa2 100644 --- a/tools/tcl/rw11/tbench.tcl +++ b/tools/tcl/rw11/tbench.tcl @@ -1,6 +1,6 @@ -# $Id: tbench.tcl 607 2014-11-30 20:02:48Z mueller $ +# $Id: tbench.tcl 676 2015-05-09 16:31:54Z mueller $ # -# Copyright 2013-2014 by Walter F.J. Mueller +# Copyright 2013-2015 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2015-05-09 676 2.1 use 'rlc log -bare' instead of 'puts' # 2014-11-30 607 2.0 use new rlink v4 iface # 2013-04-26 510 1.0 Initial version (extracted from util.tcl) # @@ -43,7 +44,7 @@ namespace eval rw11 { set fh [open "$::env(RETROBASE)/tools/tbench/$fname"] while {[gets $fh line] >= 0} { if {[string match "#*" $line]} { - if {[string match "##*" $line]} { puts $line } + if {[string match "##*" $line]} { rlc log -bare $line } } elseif {[string match "@*" $line]} { incr errcnt [tbench_list $line] } else { @@ -54,7 +55,7 @@ namespace eval rw11 { } else { incr errcnt [tbench_step $lname] } - puts [format "%s: %s" $lname [rutil::errcnt2txt $errcnt]] + rlc log -bare [format "%s: %s" $lname [rutil::errcnt2txt $errcnt]] return $errcnt } @@ -66,7 +67,7 @@ namespace eval rw11 { set cpu cpu0 source "$::env(RETROBASE)/tools/tbench/$fname" set errcnt [rlc errcnt] - puts [format "%s: %s" $fname [rutil::errcnt2txt $errcnt]] + rlc log -bare [format "%s: %s" $fname [rutil::errcnt2txt $errcnt]] return $errcnt } diff --git a/tools/tcl/rw11/util.tcl b/tools/tcl/rw11/util.tcl index d408df35..ac547693 100644 --- a/tools/tcl/rw11/util.tcl +++ b/tools/tcl/rw11/util.tcl @@ -1,4 +1,4 @@ -# $Id: util.tcl 632 2015-01-11 12:30:03Z mueller $ +# $Id: util.tcl 675 2015-05-08 21:05:08Z mueller $ # # Copyright 2013-2015 by Walter F.J. Mueller # @@ -13,7 +13,10 @@ # # Revision History: # Date Rev Version Comment -# 2015-01-09 632 1.2.3 setup_sys: use rlc set; setup_sys: add rl11 +# 2015-05-08 675 1.3.2 w11a start/stop/suspend overhaul +# 2015-03-28 660 1.3.1 add setup_cntl +# 2015-03-21 659 1.3 setup_sys: add RPRM (later renamed to RHRP) +# 2015-01-09 632 1.2.3 setup_sys: use rlc set; setup_sys: add RL11 # 2014-07-26 575 1.2.2 run_pdpcp: add tout argument # 2014-06-27 565 1.2.1 temporarily hide RL11 # 2014-06-08 561 1.2 setup_sys: add RL11 @@ -31,7 +34,17 @@ package require rwxxtpp namespace eval rw11 { # - # setup_cpu: create w11 cpu system + # setup register descriptions for rw11 ------------------------------------- + # + # rlink stat usage for rw11 + regdsc STAT {cmderr 7} {cmdmerr 6} {cpususp 5} {cpugo 4} \ + {attn 3} {rbtout 2} {rbnak 1} {rberr 0} + + # check cmderr and rb(tout|nak|err) + variable STAT_DEFMASK [regbld rw11::STAT cmderr rbtout rbnak rberr] + + # + # setup_cpu: create w11 cpu system ----------------------------------------- # proc setup_cpu {} { rlc set baseaddr 16 @@ -39,12 +52,12 @@ namespace eval rw11 { rlc set basestat 2 rlink::setup; # basic rlink defs rw11 rlw rls w11a 1; # create 1 w11a cpu - cpu0 cp -reset; # reset CPU + cpu0 cp -creset; # reset CPU return "" } # - # setup_sys: create full system + # setup_sys: create full system -------------------------------------------- # proc setup_sys {} { if {[info commands rlw] eq ""} { @@ -54,6 +67,7 @@ namespace eval rw11 { cpu0 add dl11 -base 0176500 -lam 2 cpu0 add rk11 cpu0 add rl11 + cpu0 add rhrp cpu0 add lp11 cpu0 add pc11 rlw start @@ -61,7 +75,7 @@ namespace eval rw11 { } # - # setup_tt: setup terminals + # setup_tt: setup terminals ------------------------------------------------ # proc setup_tt {{cpu "cpu0"} {optlist {}}} { # process and check options @@ -108,7 +122,7 @@ namespace eval rw11 { } # - # setup_ostr: setup Ostream device (currently lp or pp) + # setup_ostr: setup Ostream device (currently lp or pp) -------------------- # proc setup_ostr {cpu unit optlist} { # process and check options @@ -135,7 +149,7 @@ namespace eval rw11 { } # - # setup_lp: setup printer + # setup_lp: setup printer -------------------------------------------------- # proc setup_lp {{cpu "cpu0"} {optlist {}}} { # process and check options @@ -146,7 +160,7 @@ namespace eval rw11 { } } # - # setup_pp: setup paper puncher + # setup_pp: setup paper puncher -------------------------------------------- # proc setup_pp {{cpu "cpu0"} {optlist {}}} { # process and check options @@ -158,7 +172,7 @@ namespace eval rw11 { } # - # run_pdpcp: execute pdpcp type command file + # run_pdpcp: execute pdpcp type command file ------------------------------- # proc run_pdpcp {fname {tout 10.} {cpu "cpu0"}} { rlc errcnt -clear @@ -171,4 +185,23 @@ namespace eval rw11 { return $errcnt } + # + # setup_cntl: setup a controller (used for I/O test benches) --------------- + # + proc setup_cntl {cpu ctype cname} { + if {![rlw get started]} { # start rlw, if needed + rlw start + rls server -stop + } + + set ccmd ${cpu}${cname}; # build controller command + if {[info commands $ccmd] eq ""} { # create controller, if needed + $cpu add $ctype + } + if {![$ccmd get started]} { # start it, if needed + $ccmd start + } + return "" + } + } diff --git a/tools/tcl/setup_packages b/tools/tcl/setup_packages index bc38976a..801c7dca 100755 --- a/tools/tcl/setup_packages +++ b/tools/tcl/setup_packages @@ -1,5 +1,5 @@ #! /usr/bin/env tclshcpp -# $Id: setup_packages 601 2014-11-07 22:44:43Z mueller $ +# $Id: setup_packages 668 2015-04-25 14:31:19Z mueller $ # pkg_mkIndex -verbose ../lib \ librlinktpp.so \ @@ -7,14 +7,17 @@ pkg_mkIndex -verbose ../lib \ librutiltpp.so \ librwxxtpp.so # -pkg_mkIndex -verbose rutil *.tcl -pkg_mkIndex -verbose rlink *.tcl -pkg_mkIndex -verbose rbtest *.tcl -pkg_mkIndex -verbose rbmoni *.tcl -pkg_mkIndex -verbose rbbram *.tcl -pkg_mkIndex -verbose rbs3hio *.tcl -pkg_mkIndex -verbose rbemon *.tcl +pkg_mkIndex -verbose rutil *.tcl +pkg_mkIndex -verbose rlink *.tcl +pkg_mkIndex -verbose rbtest *.tcl +pkg_mkIndex -verbose rbmoni *.tcl +pkg_mkIndex -verbose rbbram *.tcl +pkg_mkIndex -verbose rbs3hio *.tcl +pkg_mkIndex -verbose rbemon *.tcl # -pkg_mkIndex -verbose rw11 *.tcl +pkg_mkIndex -verbose rw11 *.tcl +# +pkg_mkIndex -verbose ibd_ibmon *.tcl +pkg_mkIndex -verbose ibd_rhrp *.tcl # pkg_mkIndex -verbose tst_rlink *.tcl