From 4a64a63c4ce0fe2ff37c2febb799f6d0ceed24f2 Mon Sep 17 00:00:00 2001 From: wfjm Date: Sat, 23 Feb 2019 09:37:19 +0100 Subject: [PATCH] rbd_tester: use fifo_simple_dram --- rtl/vlib/rbus/rbd_tester.vbom | 2 +- rtl/vlib/rbus/rbd_tester.vhd | 28 +++++++++++++++------------- rtl/vlib/rlink/tb/tb_rlink_stim.dat | 15 ++++++++------- tools/tcl/rbtest/test_fifo.tcl | 18 +++++++++++------- tools/tcl/rbtest/test_labo.tcl | 9 +++++---- 5 files changed, 40 insertions(+), 32 deletions(-) diff --git a/rtl/vlib/rbus/rbd_tester.vbom b/rtl/vlib/rbus/rbd_tester.vbom index aed140df..8657a60c 100644 --- a/rtl/vlib/rbus/rbd_tester.vbom +++ b/rtl/vlib/rbus/rbd_tester.vbom @@ -3,6 +3,6 @@ ../memlib/memlib.vhd rblib.vhd # components -../memlib/fifo_1c_dram_raw.vbom +../memlib/fifo_simple_dram.vbom # design rbd_tester.vhd diff --git a/rtl/vlib/rbus/rbd_tester.vhd b/rtl/vlib/rbus/rbd_tester.vhd index ce318e64..0c611ce0 100644 --- a/rtl/vlib/rbus/rbd_tester.vhd +++ b/rtl/vlib/rbus/rbd_tester.vhd @@ -1,6 +1,6 @@ --- $Id: rbd_tester.vhd 984 2018-01-02 20:56:27Z mueller $ +-- $Id: rbd_tester.vhd 1109 2019-02-09 13:36:41Z mueller $ -- --- Copyright 2010-2014 by Walter F.J. Mueller +-- Copyright 2010-2019 by Walter F.J. Mueller -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free @@ -15,12 +15,12 @@ -- Module Name: rbd_tester - syn -- Description: rbus dev: rbus tester -- --- Dependencies: memlib/fifo_1c_dram_raw +-- Dependencies: memlib/fifo_simple_dram -- -- Test bench: rlink/tb/tb_rlink (used as test target) -- -- Target Devices: generic --- Tool versions: xst 12.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 +-- Tool versions: xst 12.1-14.7; viv 2014.4-2017.2; ghdl 0.29-0.35 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri @@ -30,6 +30,7 @@ -- -- Revision History: -- Date Rev Version Comment +-- 2019-02-09 1109 4.2 use fifo_simple_dram (instead of _1c_dram_raw) -- 2014-09-05 591 4.1 use new iface with 8 regs -- 2014-08-30 589 4.0 use new rlink v4 iface and 4 bit STAT -- 2014-08-15 583 3.5 rb_mreq addr now 16 bit @@ -127,7 +128,7 @@ architecture syn of rbd_tester is signal N_REGS : regs_type := regs_init; signal FIFO_RESET : slbit := '0'; - signal FIFO_RE : slbit := '0'; + signal FIFO_CE : slbit := '0'; signal FIFO_WE : slbit := '0'; signal FIFO_EMPTY : slbit := '0'; signal FIFO_FULL : slbit := '0'; @@ -136,20 +137,20 @@ architecture syn of rbd_tester is begin - FIFO : fifo_1c_dram_raw + FIFO : fifo_simple_dram generic map ( AWIDTH => awidth, DWIDTH => 16) port map ( CLK => CLK, RESET => FIFO_RESET, - RE => FIFO_RE, + CE => FIFO_CE, WE => FIFO_WE, DI => RB_MREQ.din, DO => FIFO_DO, - SIZE => FIFO_SIZE, EMPTY => FIFO_EMPTY, - FULL => FIFO_FULL + FULL => FIFO_FULL, + SIZE => FIFO_SIZE ); proc_regs: process (CLK) @@ -172,7 +173,7 @@ begin variable irb_dout : slv16 := (others=>'0'); variable irbena : slbit := '0'; variable irblam : slv16 := (others=>'0'); - variable ififo_re : slbit := '0'; + variable ififo_ce : slbit := '0'; variable ififo_we : slbit := '0'; variable ififo_reset : slbit := '0'; variable isbusy : slbit := '0'; @@ -189,7 +190,7 @@ begin irbena := RB_MREQ.re or RB_MREQ.we; - ififo_re := '0'; + ififo_ce := '0'; ififo_we := '0'; ififo_reset := '0'; @@ -274,13 +275,14 @@ begin if FIFO_EMPTY = '1' then irb_err := '1'; else - ififo_re := '1'; + ififo_ce := '1'; end if; end if; if RB_MREQ.we='1' and isbusy='0' then if FIFO_FULL = '1' then irb_err := '1'; else + ififo_ce := '1'; ififo_we := '1'; end if; end if; @@ -350,7 +352,7 @@ begin N_REGS <= n; - FIFO_RE <= ififo_re; + FIFO_CE <= ififo_ce; FIFO_WE <= ififo_we; FIFO_RESET <= ififo_reset; diff --git a/rtl/vlib/rlink/tb/tb_rlink_stim.dat b/rtl/vlib/rlink/tb/tb_rlink_stim.dat index 07f15e1c..83c49ae5 100644 --- a/rtl/vlib/rlink/tb/tb_rlink_stim.dat +++ b/rtl/vlib/rlink/tb/tb_rlink_stim.dat @@ -1,7 +1,8 @@ -# $Id: tb_rlink_stim.dat 892 2017-05-01 17:57:34Z mueller $ +# $Id: tb_rlink_stim.dat 1109 2019-02-09 13:36:41Z mueller $ # # Revision History: # Date Rev Version Comment +# 2019-02-09 1109 4.2 adapt to fifo_simple (full at 15 writes) # 2017-05-01 892 4.1 start section B (error aborts) and C (retransmit) # 2014-12-21 617 4.0.1 rlink signals now tout and nak on separate stat bits # 2014-10-12 596 4.0 rewritten for rlink v4 @@ -389,12 +390,12 @@ C Test A4.4: wblk, rblk (with fifo, -> rberr response when fifo full) sop .dclr .dseq 18 x"4400" -- seq(18,4400) -wblkd 0 x"ffe6" 16 00000001 -- fifo := .... {err=1,dc=16} +wblkd 0 x"ffe6" 15 00000001 -- fifo := .... {err=1,dc=15} .dclr -.dseq 16 x"4400" -- seq(16,4400) +.dseq 15 x"4400" -- seq(15,4400) .dwrd x"0055" -- 1st lsb from rbus .dwrd x"0000" -- rest will be 0 from abort states -rblkd 1 x"ffe6" 16 00000001 -- lnak >? .... {err=1,dc=16) +rblkd 1 x"ffe6" 15 00000001 -- lnak >? .... {err=1,dc=15) eop .iowt 10 # @@ -508,7 +509,7 @@ sop .dclr .dseq 18 x"4400" -- seq(18,4400) init 0 x"ffe0" x"0007" 00000000 -- clear all -wblkd 1 x"ffe6" 16 00000001 -- fifo := .... {err=1,dc=16} +wblkd 1 x"ffe6" 15 00000001 -- fifo := .... {err=1,dc=15} rreg 2 x"fffe" x"0b81" 00000000 -- stat >? 0b81 (see above) labo 3 x"01" 00000000 wreg 4 x"ffe4" x"0101" 00000000 -- data := 0101 @@ -525,10 +526,10 @@ eop C aborted rblk, labo, wreg(data),rreg(dinc) sop .dclr -.dseq 16 x"4400" -- seq(16,4400) +.dseq 15 x"4400" -- seq(15,4400) .dwrd x"0055" -- 1st lsb from rbus .dwrd x"0000" -- rest will be 0 from abort states -rblkd 1 x"ffe6" 16 00000001 -- lnak >? .... {err=1,dc=16) +rblkd 1 x"ffe6" 15 00000001 -- lnak >? .... {err=1,dc=15) rreg 2 x"fffe" x"0981" 00000000 -- stat >? 0981 (see above) labo 3 x"01" 00000000 wreg 4 x"ffe4" x"0101" 00000000 -- data := 0101 diff --git a/tools/tcl/rbtest/test_fifo.tcl b/tools/tcl/rbtest/test_fifo.tcl index e88ad74b..869b52ce 100644 --- a/tools/tcl/rbtest/test_fifo.tcl +++ b/tools/tcl/rbtest/test_fifo.tcl @@ -1,6 +1,6 @@ -# $Id: test_fifo.tcl 985 2018-01-03 08:59:40Z mueller $ +# $Id: test_fifo.tcl 1109 2019-02-09 13:36:41Z mueller $ # -# Copyright 2011-2015 by Walter F.J. Mueller +# Copyright 2011-2019 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2019-02-09 1109 2.2 adapt to fifo_simple (full at 15 writes) # 2015-04-03 661 2.1 drop estatdef; use estaterr # 2014-11-09 603 2.0 use rlink v4 address layout and iface # 2011-03-27 374 1.0 Initial version @@ -74,14 +75,14 @@ namespace eval rbtest { -rblk te.fifo 4 -edata $blk -edone 3 -estaterr # # - rlc log " test 3b: fifo write error (write 17, read 16)" + rlc log " test 3b: fifo write error (write 17, read 15)" set blk {} for { set i 0 } { $i < 17 } { incr i } { lappend blk [expr {$i | ( $i << 8 ) }] } rlc exec \ - -wblk te.fifo $blk -edone 16 -estaterr \ - -rblk te.fifo 16 -edata [lrange $blk 0 15] -edone 16 + -wblk te.fifo $blk -edone 15 -estaterr \ + -rblk te.fifo 15 -edata [lrange $blk 0 14] -edone 15 # #------------------------------------------------------------------------- rlc log " test 4a: verify that init 100 clears fifo and not cntl&data" @@ -117,9 +118,12 @@ namespace eval rbtest { set bcode [expr {32 * $i + 2 * $j}] lappend blk [expr {( $bcode << 8 ) | ( $bcode + 1 )}] } + # write/read in two chunks of 8 words because fifo holds only 15 words rlc exec \ - -wblk te.fifo $blk \ - -rblk te.fifo [llength $blk] -edata $blk + -wblk te.fifo [lrange $blk 0 7] \ + -rblk te.fifo 8 -edata [lrange $blk 0 7] \ + -wblk te.fifo [lrange $blk 8 15] \ + -rblk te.fifo 8 -edata [lrange $blk 8 15] } # #------------------------------------------------------------------------- diff --git a/tools/tcl/rbtest/test_labo.tcl b/tools/tcl/rbtest/test_labo.tcl index 16a0ddf7..ad86bd64 100644 --- a/tools/tcl/rbtest/test_labo.tcl +++ b/tools/tcl/rbtest/test_labo.tcl @@ -1,6 +1,6 @@ -# $Id: test_labo.tcl 985 2018-01-03 08:59:40Z mueller $ +# $Id: test_labo.tcl 1109 2019-02-09 13:36:41Z mueller $ # -# Copyright 2015- by Walter F.J. Mueller +# Copyright 2015-2019 by Walter F.J. Mueller # # This program is free software; you may redistribute and/or modify it under # the terms of the GNU General Public License as published by the Free @@ -13,6 +13,7 @@ # # Revision History: # Date Rev Version Comment +# 2019-02-09 1109 1.1 adapt to fifo_simple (full at 15 writes) # 2015-04-03 662 1.0 Initial version # @@ -87,7 +88,7 @@ namespace eval rbtest { } rlc exec \ -wreg te.data 0x0020 \ - -wblk te.fifo $blk -edone 16 -estaterr \ + -wblk te.fifo $blk -edone 15 -estaterr \ -labo -edata 1 \ -wreg te.data 0x0021 \ -rreg te.data -edata 0xffff \ @@ -127,7 +128,7 @@ namespace eval rbtest { -wreg te.data 0x0040 \ -rblk te.fifo 8 -edata [lrange $blk 0 7] \ -rreg $rlink::ADDR_RLSTAT -edata 0x0 $babomsk \ - -rblk te.fifo 8 -edata [lrange $blk 8 15] \ + -rblk te.fifo 7 -edata [lrange $blk 8 14] \ -rreg $rlink::ADDR_RLSTAT -edata 0x0 $babomsk \ -rblk te.fifo 8 -edone 0 -estaterr \ -rreg $rlink::ADDR_RLSTAT -edata $babomsk $babomsk \