diff --git a/Makefile b/Makefile index bc7b0fec..604d5b44 100644 --- a/Makefile +++ b/Makefile @@ -1,4 +1,4 @@ -# $Id: Makefile 1176 2019-06-30 07:16:06Z mueller $ +# $Id: Makefile 1201 2019-08-10 16:51:22Z mueller $ # SPDX-License-Identifier: GPL-3.0-or-later # Copyright 2011-2019 by Walter F.J. Mueller # @@ -8,6 +8,7 @@ # # Revision History: # Date Rev Version Comment +# 2019-08-07 1201 1.2.12 drop nexys4, add nexys4d # 2019-01-10 1111 1.2.11 drop w11a/arty_bram # 2019-01-02 1101 1.2.10 add tst_{mig,sram}/arty; add w11a/arty # 2018-10-12 1055 1.2.9 use setup_package_filt @@ -70,12 +71,13 @@ SYN_viv += rtl/sys_gen/tst_snhumanio/basys3 SYN_viv += rtl/sys_gen/tst_rlink/basys3 SYN_viv += rtl/sys_gen/w11a/basys3 -# Nexys4 ------------------------------------- -SYN_viv += rtl/sys_gen/tst_rlink/nexys4 -SYN_viv += rtl/sys_gen/tst_serloop/nexys4 -SYN_viv += rtl/sys_gen/tst_snhumanio/nexys4 -SYN_viv += rtl/sys_gen/tst_sram/nexys4 -SYN_viv += rtl/sys_gen/w11a/nexys4 +# Nexys4d ------------------------------------ +SYN_viv += rtl/sys_gen/tst_rlink/nexys4d +SYN_viv += rtl/sys_gen/tst_serloop/nexys4d +SYN_viv += rtl/sys_gen/tst_snhumanio/nexys4d +SYN_viv += rtl/sys_gen/tst_sram/nexys4d +SYN_viv += rtl/sys_gen/w11a/nexys4d +SYN_viv += rtl/sys_gen/w11a/nexys4d_bram # Arty --------------------------------------- SYN_viv += rtl/sys_gen/tst_mig/arty @@ -130,11 +132,12 @@ SIM_viv += rtl/sys_gen/tst_rlink/basys3/tb #SIM_viv += rtl/sys_gen/tst_serloop/basys3/tb SIM_viv += rtl/sys_gen/w11a/basys3/tb -# Nexys4 ------------------------------------- -SIM_viv += rtl/sys_gen/tst_rlink/nexys4/tb -SIM_viv += rtl/sys_gen/tst_serloop/nexys4/tb -SIM_viv += rtl/sys_gen/tst_sram/nexys4/tb -SIM_viv += rtl/sys_gen/w11a/nexys4/tb +# Nexys4d ------------------------------------ +SIM_viv += rtl/sys_gen/tst_rlink/nexys4d/tb +SIM_viv += rtl/sys_gen/tst_serloop/nexys4d/tb +SIM_viv += rtl/sys_gen/tst_sram/nexys4d/tb +SIM_viv += rtl/sys_gen/w11a/nexys4d/tb +SIM_viv += rtl/sys_gen/w11a/nexys4d_bram/tb # Arty --------------------------------------- SIM_viv += rtl/sys_gen/tst_mig/arty/tb diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md index 8d346bdd..597f8abe 100644 --- a/doc/CHANGELOG.md +++ b/doc/CHANGELOG.md @@ -27,6 +27,7 @@ The full set of tests is only run for tagged releases. ### Summary - automate oskit download and container file setup - automate testing of oskits +- get Nexys A7 board working and fully integrated ### New features - new tools @@ -34,6 +35,16 @@ The full set of tests is only run for tagged releases. - oskit/\*/\*_setup: scripts for oskit download and container file setup - ostest: automation of oskit tests +### Changes +- firmware changes + - nexys4d/mig_a.prj: InputClk 100 MHz + - tst_mig/nexys4d/sys_tst_mig_n4d: use 100 MHz MIG SYS_CLK; add clock monitor + - tst_sram/nexys4d/sys_tst_sram_n4d: use 100 MHz MIG SYS_CLK + - w11a/nexys4d/sys_w11a_n4d: use 100 MHz MIG SYS_CLK + +### Bug Fixes + - nexys4d/mig_a.prj: BUGFIX: SysResetPolarity ACTIVE HIGH + --- ## 2019-07-27: [w11a_V0.79](https://github.com/wfjm/w11/releases/tag/w11a_V0.79) - rev 1197(wfjm) diff --git a/rtl/bplib/arty/migui_arty_gsim.vhd b/rtl/bplib/arty/migui_arty_gsim.vhd index 6f79e154..c3942432 100644 --- a/rtl/bplib/arty/migui_arty_gsim.vhd +++ b/rtl/bplib/arty/migui_arty_gsim.vhd @@ -1,4 +1,4 @@ --- $Id: migui_arty_gsim.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: migui_arty_gsim.vhd 1201 2019-08-10 16:51:22Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2018- by Walter F.J. Mueller -- @@ -76,13 +76,22 @@ architecture sim of migui_arty is begin + -- On Arty we have + -- SYS_CLK_I 166.6 Mhz + -- controller 333.3 MHz + -- UI_CLK 83.3 MHz (4:1) + -- therefore for simulation + -- f_vco 1000 MHz + -- --> mul 6 (f_vco/SYS_CLK) + -- --> div 12 (f_vco/UI_CLK) + MIG_SIM : migui_core_gsim generic map ( BAWIDTH => mig_bawidth, MAWIDTH => mig_mawidth, SAWIDTH => 24, - CLKMUI_MUL => 7, - CLKMUI_DIV => 14) + CLKMUI_MUL => 6, + CLKMUI_DIV => 12) port map ( SYS_CLK => SYS_CLK_I, SYS_RST => SYS_RST, diff --git a/rtl/bplib/nexys4d/mig_a.prj b/rtl/bplib/nexys4d/mig_a.prj index 6c62cfe7..f6acfd03 100644 --- a/rtl/bplib/nexys4d/mig_a.prj +++ b/rtl/bplib/nexys4d/mig_a.prj @@ -1,6 +1,6 @@ - + - + migui_nexys4d 1 1 @@ -9,20 +9,20 @@ ON Disabled xc7a100t-csg324/-1 - 4.0 + 4.2 No Buffer No Buffer - ACTIVE LOW + ACTIVE HIGH FALSE 1 50 Ohms 0 - + DDR2_SDRAM/Components/MT47H64M16HR-25E 3333 1.8V 4:1 - 150.015 + 100.01 0 1200 1.000 @@ -43,78 +43,78 @@ 3 ROW_BANK_COLUMN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - + + + - + - 8 - Sequential - 5 - Normal - No - Fast exit - 5 - Enable-Normal - Fullstrength - Enable - 1 - 50ohms - 0 - OCD Exit - Enable - Disable - Enable + 8 + Sequential + 5 + Normal + No + Fast exit + 5 + Enable-Normal + Fullstrength + Enable + 1 + 50ohms + 0 + OCD Exit + Enable + Disable + Enable NATIVE diff --git a/rtl/bplib/nexys4d/migui_nexys4d_gsim.vhd b/rtl/bplib/nexys4d/migui_nexys4d_gsim.vhd index 84a32cb6..5b02636d 100644 --- a/rtl/bplib/nexys4d/migui_nexys4d_gsim.vhd +++ b/rtl/bplib/nexys4d/migui_nexys4d_gsim.vhd @@ -1,4 +1,4 @@ --- $Id: migui_nexys4d_gsim.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: migui_nexys4d_gsim.vhd 1201 2019-08-10 16:51:22Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2018- by Walter F.J. Mueller -- @@ -74,13 +74,22 @@ architecture sim of migui_nexys4d is begin + -- On Nexys4 we have + -- SYS_CLK_I 100 Mhz + -- controller 300 MHz + -- UI_CLK 75 MHz (4:1) + -- therefore for simulation + -- f_vco 1200 MHz + -- --> mul 12 (f_vco/SYS_CLK) + -- --> div 16 (f_vco/UI_CLK) + MIG_SIM : migui_core_gsim generic map ( BAWIDTH => mig_bawidth, MAWIDTH => mig_mawidth, SAWIDTH => 24, - CLKMUI_MUL => 7, - CLKMUI_DIV => 14) + CLKMUI_MUL => 12, + CLKMUI_DIV => 16) port map ( SYS_CLK => SYS_CLK_I, SYS_RST => SYS_RST, diff --git a/rtl/bplib/nexys4d/nexys4d_pins.xdc b/rtl/bplib/nexys4d/nexys4d_pins.xdc index 941478ac..c6735729 100644 --- a/rtl/bplib/nexys4d/nexys4d_pins.xdc +++ b/rtl/bplib/nexys4d/nexys4d_pins.xdc @@ -1,9 +1,9 @@ # -*- tcl -*- -# $Id: nexys4d_pins.xdc 1190 2019-07-13 17:05:39Z mueller $ +# $Id: nexys4d_pins.xdc 1201 2019-08-10 16:51:22Z mueller $ # SPDX-License-Identifier: GPL-3.0-or-later -# Copyright 2017-2018 by Walter F.J. Mueller +# Copyright 2017-2019 by Walter F.J. Mueller # -# Nexys 4DDR core functionality +# Nexys4 DDR or Nexys A7-100 core functionality # - Configuration setup # - config voltage # - enable bitstream timestamp @@ -11,6 +11,8 @@ # - USB UART # - human I/O (switches, buttons, leds, display) # +# Note 2019-08-07: checked against Nexys A7 pin-out (is identical) +# # Revision History: # Date Rev Version Comment # 2018-12-30 1099 1.1 BUFFIX: Fix faulty IO voltage for I_SWI[8,9] diff --git a/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vhd b/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vhd index a56b7844..f32af33a 100644 --- a/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vhd +++ b/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_mig_n4d.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_mig_n4d.vhd 1201 2019-08-10 16:51:22Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2018-2019 by Walter F.J. Mueller -- @@ -20,18 +20,49 @@ -- Test bench: tb/tb_tst_mig_n4d -- -- Target Devices: generic --- Tool versions: viv 2017.2-2018.3; ghdl 0.34-0.35 +-- Tool versions: viv 2017.2-2019.1; ghdl 0.34-0.35 -- -- Synthesized (viv): -- Date Rev viv Target flop lutl lutm bram slic +-- 2019-08-10 1201 2019.1 xc7a100t-1l 4217 4173 440 1 1709 +clkmon -- 2019-02-02 1108 2018.3 xc7a100t-1l 4106 4145 440 1 1689 -- 2019-02-02 1108 2017.2 xc7a100t-1l 4097 4310 440 1 1767 -- 2019-01-02 1101 2017.2 xc7a100t-1l 4097 4310 457 1 1767 -- -- Revision History: -- Date Rev Version Comment +-- 2019-08-10 1201 1.1 use 100 MHz MIG SYS_CLK; add clock monitor -- 2018-12-30 1099 1.0 Initial version ------------------------------------------------------------------------------ +-- +-- Usage of Nexys 4 Switches, Buttons, LEDs +-- +-- SWI -- unused -- +-- +-- BTN +-- (4) ce -- unused -- +-- (3) le issue MIG_SYS_RST +-- (2) do light LED(12:15) +-- (1) ri light LED(8:11) +-- (0) up light LED(4:7) +-- +-- LEDs +-- (15) I_BTN(2) or R_FLG_UI_CLK (MIG UI clock monitor 75 MHz) +-- (14) I_BTN(2) or R_FLG_CLKREF (CLKREF clock monitor 200 MHz) +-- (13) I_BTN(2) or R_FLG_CLKSER (CLKSER clock monitor 120 MHz) +-- (12) I_BTN(2) or R_FLG_XX_CLK (sysclk clock monitor 80 MHz) +-- (11) I_BTN(1) or not APP_WDF_RDY +-- (10) I_BTN(1) or not APP_RDY +-- (8:9) I_BTN(1) +-- (7) I_BTN(0) or not MIG_INIT_CALIB_COMPLETE +-- (6) I_BTN(0) or MIG_UI_CLK_SYNC_RST +-- (5) I_BTN(0) +-- (4) I_BTN(0) or not LOCKED +-- (3) not SER_MONI.txok (shows tx back pressure) +-- (2) SER_MONI.txact (shows tx activity) +-- (1) not SER_MONI.rxok (shows rx back pressure) +-- (0) SER_MONI.rxact (shows rx activity) + library ieee; use ieee.std_logic_1164.all; @@ -101,7 +132,6 @@ architecture syn of sys_tst_mig_n4d is signal CLKS : slbit := '0'; signal CES_MSEC : slbit := '0'; - signal CLKMIG : slbit := '0'; signal CLKREF : slbit := '0'; signal LOCKED : slbit := '0'; -- raw LOCKED @@ -155,9 +185,15 @@ architecture syn of sys_tst_mig_n4d is signal MIG_SYS_RST : slbit := '0'; signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK - - signal R_DIMCNT : slv2 := (others=>'0'); - signal R_DIMFLG : slbit := '0'; + + signal R_CNT_UI_CLK : slv(25 downto 0) := (others=>'0'); + signal R_CNT_CLKREF : slv(26 downto 0) := (others=>'0'); + signal R_CNT_CLKSER : slv(25 downto 0) := (others=>'0'); + signal R_CNT_XX_CLK : slv(25 downto 0) := (others=>'0'); + signal R_FLG_UI_CLK : slbit := '0'; + signal R_FLG_CLKREF : slbit := '0'; + signal R_FLG_CLKSER : slbit := '0'; + signal R_FLG_XX_CLK : slbit := '0'; constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx @@ -195,7 +231,7 @@ begin CLK1_MSECDIV => 1000, CLK23_VCODIV => 1, CLK23_VCOMUL => 12, -- vco 1200 MHz - CLK2_OUTDIV => 8, -- mig sys 150.0 MHz + CLK2_OUTDIV => 12, -- mig sys 100.0 MHz (unused) CLK3_OUTDIV => 6, -- mig ref 200.0 MHz CLK23_GENTYPE => "PLL") port map ( @@ -206,7 +242,7 @@ begin CLK1 => CLKS, CE1_USEC => open, CE1_MSEC => CES_MSEC, - CLK2 => CLKMIG, + CLK2 => open, CLK3 => CLKREF, LOCKED => LOCKED ); @@ -243,7 +279,7 @@ begin CDC_CLKMIG_LOCKED : cdc_signal_s1_as port map ( - CLKO => CLKMIG, + CLKO => CLK100_BUF, DI => LOCKED, DO => LOCKED_CLKMIG ); @@ -369,7 +405,7 @@ begin UI_CLK => CLK, UI_CLK_SYNC_RST => MIG_UI_CLK_SYNC_RST, INIT_CALIB_COMPLETE => MIG_INIT_CALIB_COMPLETE, - SYS_CLK_I => CLKMIG, + SYS_CLK_I => CLK100_BUF, CLK_REF_I => CLKREF, DEVICE_TEMP_I => XADC_TEMP, SYS_RST => MIG_SYS_RST @@ -406,45 +442,103 @@ begin RB_SRES_OR => RB_SRES ); - proc_dim: process (CLKMIG) + proc_mon_ui_clk: process (CLK, I_BTN(3)) begin - if rising_edge(CLKMIG) then - R_DIMCNT <= slv(unsigned(R_DIMCNT) + 1); - if unsigned(R_DIMCNT) = 0 then - R_DIMFLG <= '1'; + if I_BTN(3) = '1' then + R_FLG_UI_CLK <= '1'; + R_CNT_UI_CLK <= (others=>'0'); + end if; + if rising_edge(CLK) then + if unsigned(R_CNT_UI_CLK) = 37500000-1 then + R_FLG_UI_CLK <= not R_FLG_UI_CLK; + R_CNT_UI_CLK <= (others=>'0'); else - R_DIMFLG <= '0'; + R_CNT_UI_CLK <= slv(unsigned(R_CNT_UI_CLK) + 1); end if; end if; - end process proc_dim; + end process proc_mon_ui_clk; + + proc_mon_clkref: process (CLKREF, I_BTN(3)) + begin + + if I_BTN(3) = '1' then + R_FLG_CLKREF <= '1'; + R_CNT_CLKREF <= (others=>'0'); + end if; + if rising_edge(CLKREF) then + if unsigned(R_CNT_CLKREF) = 100000000-1 then + R_FLG_CLKREF <= not R_FLG_CLKREF; + R_CNT_CLKREF <= (others=>'0'); + else + R_CNT_CLKREF <= slv(unsigned(R_CNT_CLKREF) + 1); + end if; + end if; + + end process proc_mon_clkref; + + proc_mon_clkser: process (CLKS, I_BTN(3)) + begin + + if I_BTN(3) = '1' then + R_FLG_CLKSER <= '1'; + R_CNT_CLKSER <= (others=>'0'); + end if; + if rising_edge(CLKS) then + if unsigned(R_CNT_CLKSER) = 60000000-1 then + R_FLG_CLKSER <= not R_FLG_CLKSER; + R_CNT_CLKSER <= (others=>'0'); + else + R_CNT_CLKSER <= slv(unsigned(R_CNT_CLKSER) + 1); + end if; + end if; + + end process proc_mon_clkser; + + proc_mon_xx_clk: process (XX_CLK, I_BTN(3)) + begin + + if I_BTN(3) = '1' then + R_FLG_XX_CLK <= '1'; + R_CNT_XX_CLK <= (others=>'0'); + end if; + if rising_edge(XX_CLK) then + if unsigned(R_CNT_XX_CLK) = 40000000-1 then + R_FLG_XX_CLK <= not R_FLG_XX_CLK; + R_CNT_XX_CLK <= (others=>'0'); + else + R_CNT_XX_CLK <= slv(unsigned(R_CNT_XX_CLK) + 1); + end if; + end if; + + end process proc_mon_xx_clk; RB_LAM(0) <= RB_LAM_TST; -- LED group(0:3): rlink traffic O_LED(0) <= SER_MONI.rxact; - O_LED(1) <= SER_MONI.txact; - O_LED(2) <= '0'; - O_LED(3) <= '0'; + O_LED(1) <= not SER_MONI.rxok; + O_LED(2) <= SER_MONI.txact; + O_LED(3) <= not SER_MONI.txok; -- LED group(4:7) serious error conditions - O_LED(4) <= R_DIMFLG and (I_BTN(0) or not LOCKED); - O_LED(5) <= R_DIMFLG and (I_BTN(0)); - O_LED(6) <= R_DIMFLG and (I_BTN(0) or MIG_UI_CLK_SYNC_RST); - O_LED(7) <= R_DIMFLG and (I_BTN(0) or not MIG_INIT_CALIB_COMPLETE); + O_LED(4) <= I_BTN(0) or not LOCKED; + O_LED(5) <= I_BTN(0); + O_LED(6) <= I_BTN(0) or MIG_UI_CLK_SYNC_RST; + O_LED(7) <= I_BTN(0) or not MIG_INIT_CALIB_COMPLETE; - -- green LED for activity - O_LED(8) <= R_DIMFLG and (I_BTN(1)); - O_LED(9) <= R_DIMFLG and (I_BTN(1)); - O_LED(10) <= R_DIMFLG and (I_BTN(1) or not APP_RDY); - O_LED(11) <= R_DIMFLG and (I_BTN(1) or not APP_WDF_RDY); + -- LED group(8:11) for activity + O_LED(8) <= I_BTN(1); + O_LED(9) <= I_BTN(1); + O_LED(10) <= I_BTN(1) or not APP_RDY; + O_LED(11) <= I_BTN(1) or not APP_WDF_RDY; - -- blue LED currently unused - O_LED(12) <= R_DIMFLG and (I_BTN(2)); - O_LED(13) <= R_DIMFLG and (I_BTN(2)); - O_LED(14) <= R_DIMFLG and (I_BTN(2)); - O_LED(15) <= R_DIMFLG and (I_BTN(2)); + -- LED group(12:15) for clock monitoring + O_LED(12) <= I_BTN(2) or R_FLG_XX_CLK; + O_LED(13) <= I_BTN(2) or R_FLG_CLKSER; + O_LED(14) <= I_BTN(2) or R_FLG_CLKREF; + O_LED(15) <= I_BTN(2) or R_FLG_UI_CLK; -- RGB LEDs unused O_RGBLED0 <= (others=>'0'); diff --git a/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vmfset b/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vmfset index 8b456fe2..a074d99f 100644 --- a/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vmfset +++ b/rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vmfset @@ -1,7 +1,8 @@ -# $Id: sys_tst_mig_n4d.vmfset 1108 2019-02-02 23:04:38Z mueller $ +# $Id: sys_tst_mig_n4d.vmfset 1201 2019-08-10 16:51:22Z mueller $ # # Validated code/tool version combinations -# Date rev viv +# Date rev viv +# 2019-08-10 1201 2019.1 # 2019-02-02 1108 2017.2 # 2019-02-02 1108 2018.3 # @@ -18,7 +19,6 @@ I [Designutils 20-1567] # generic # port driven by constant -------------------------------------- # not all LEDs used # OK 2018-12-30 -i [Synth 8-3917] O_LED[(2|3)] i [Synth 8-3917] O_RGBLED0[\d] i [Synth 8-3917] O_RGBLED1[\d] # 7 segment display unused # OK 2018-12-30 diff --git a/rtl/sys_gen/tst_mig/nexys4d/tb/tbrun.yml b/rtl/sys_gen/tst_mig/nexys4d/tb/tbrun.yml index e713e0d6..3b151d23 100644 --- a/rtl/sys_gen/tst_mig/nexys4d/tb/tbrun.yml +++ b/rtl/sys_gen/tst_mig/nexys4d/tb/tbrun.yml @@ -1,13 +1,14 @@ -# $Id: tbrun.yml 1099 2018-12-31 09:07:36Z mueller $ +# $Id: tbrun.yml 1201 2019-08-10 16:51:22Z mueller $ # # Revision History: # Date Rev Version Comment +# 2019-08-10 1201 1.0.1 add n4d to default # 2018-12-23 1092 1.0 Initial version # - default: mode: ${viv_modes} # -- tag: [viv, sys_tst_mig, n4d, base] +- tag: [default, viv, sys_tst_mig, n4d, base] test: | tbrun_tbwrri --lsuf base --pack tst_mig tb_tst_mig_n4d${ms} \ tst_mig::setup tst_mig::test_all diff --git a/rtl/sys_gen/tst_rlink/nexys4/tb/tbrun.yml b/rtl/sys_gen/tst_rlink/nexys4/tb/tbrun.yml index 1595da7c..78cfe22b 100644 --- a/rtl/sys_gen/tst_rlink/nexys4/tb/tbrun.yml +++ b/rtl/sys_gen/tst_rlink/nexys4/tb/tbrun.yml @@ -1,18 +1,19 @@ -# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $ +# $Id: tbrun.yml 1201 2019-08-10 16:51:22Z mueller $ # # Revision History: # Date Rev Version Comment +# 2019-08-10 1201 1.0.1 remove n4 from default # 2016-08-21 799 1.0 Initial version # - default: mode: ${viv_modes} # -- tag: [default, viv, sys_tst_rlink, n4, base] +- tag: [viv, sys_tst_rlink, n4, base] test: | tbrun_tbwrri --lsuf base --pack tst_rlink tb_tst_rlink_n4${ms} \ "tst_rlink::setup" "tst_rlink::test_all" # -- tag: [default, viv, sys_tst_rlink, n4, emon] +- tag: [viv, sys_tst_rlink, n4, emon] test: | tbrun_tbwrri --lsuf emon --pack tst_rlink tb_tst_rlink_n4${ms} \ "tst_rlink::setup" "tst_rlink::test_all_emon" diff --git a/rtl/sys_gen/tst_rlink/nexys4d/tb/tbrun.yml b/rtl/sys_gen/tst_rlink/nexys4d/tb/tbrun.yml index 89d38676..e1a1cb2c 100644 --- a/rtl/sys_gen/tst_rlink/nexys4d/tb/tbrun.yml +++ b/rtl/sys_gen/tst_rlink/nexys4d/tb/tbrun.yml @@ -1,18 +1,19 @@ -# $Id: tbrun.yml 838 2017-01-04 20:57:57Z mueller $ +# $Id: tbrun.yml 1201 2019-08-10 16:51:22Z mueller $ # # Revision History: # Date Rev Version Comment +# 2019-08-10 1201 1.0.1 add n4d to default # 2017-01-04 838 1.0 Initial version # - default: mode: ${viv_modes} # -- tag: [viv, sys_tst_rlink, n4d, base] +- tag: [default, viv, sys_tst_rlink, n4d, base] test: | tbrun_tbwrri --lsuf base --pack tst_rlink tb_tst_rlink_n4d${ms} \ "tst_rlink::setup" "tst_rlink::test_all" # -- tag: [viv, sys_tst_rlink, n4d, emon] +- tag: [default, viv, sys_tst_rlink, n4d, emon] test: | tbrun_tbwrri --lsuf emon --pack tst_rlink tb_tst_rlink_n4d${ms} \ "tst_rlink::setup" "tst_rlink::test_all_emon" diff --git a/rtl/sys_gen/tst_serloop/nexys4/tb/tbrun.yml b/rtl/sys_gen/tst_serloop/nexys4/tb/tbrun.yml index 05cf84e0..b0ec0f33 100644 --- a/rtl/sys_gen/tst_serloop/nexys4/tb/tbrun.yml +++ b/rtl/sys_gen/tst_serloop/nexys4/tb/tbrun.yml @@ -1,16 +1,17 @@ -# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $ +# $Id: tbrun.yml 1201 2019-08-10 16:51:22Z mueller $ # # Revision History: # Date Rev Version Comment +# 2019-08-10 1201 1.0.1 remove n4 from default # 2016-08-21 799 1.0 Initial version # - default: mode: ${viv_modes} # -- tag: [default, viv, sys_tst_serloop1, n4] +- tag: [viv, sys_tst_serloop1, n4] test: | tbrun_tbw tb_tst_serloop1_n4${ms} -- tag: [default, viv, sys_tst_serloop2, n4] +- tag: [viv, sys_tst_serloop2, n4] test: | tbrun_tbw tb_tst_serloop2_n4${ms} diff --git a/rtl/sys_gen/tst_serloop/nexys4d/tb/tbrun.yml b/rtl/sys_gen/tst_serloop/nexys4d/tb/tbrun.yml index d78b56a2..ac36fac1 100644 --- a/rtl/sys_gen/tst_serloop/nexys4d/tb/tbrun.yml +++ b/rtl/sys_gen/tst_serloop/nexys4d/tb/tbrun.yml @@ -1,16 +1,17 @@ -# $Id: tbrun.yml 838 2017-01-04 20:57:57Z mueller $ +# $Id: tbrun.yml 1201 2019-08-10 16:51:22Z mueller $ # # Revision History: # Date Rev Version Comment +# 2019-08-10 1201 1.0.1 add n4d to default # 2016-08-21 799 1.0 Initial version # - default: mode: ${viv_modes} # -- tag: [viv, sys_tst_serloop1, n4d] +- tag: [default, viv, sys_tst_serloop1, n4d] test: | tbrun_tbw tb_tst_serloop1_n4d${ms} -- tag: [viv, sys_tst_serloop2, n4d] +- tag: [default, viv, sys_tst_serloop2, n4d] test: | tbrun_tbw tb_tst_serloop2_n4d${ms} diff --git a/rtl/sys_gen/tst_sram/nexys4/tb/tbrun.yml b/rtl/sys_gen/tst_sram/nexys4/tb/tbrun.yml index 1b051ada..bbb0d42f 100644 --- a/rtl/sys_gen/tst_sram/nexys4/tb/tbrun.yml +++ b/rtl/sys_gen/tst_sram/nexys4/tb/tbrun.yml @@ -1,18 +1,19 @@ -# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $ +# $Id: tbrun.yml 1201 2019-08-10 16:51:22Z mueller $ # # Revision History: # Date Rev Version Comment +# 2019-08-10 1201 1.0.1 remove n4 from default # 2016-08-21 799 1.0 Initial version # - default: mode: ${viv_modes} # -- tag: [default, viv, sys_tst_sram, n4, base] +- tag: [viv, sys_tst_sram, n4, base] test: | tbrun_tbwrri --lsuf base --pack tst_sram tb_tst_sram_n4${ms} \ tst_sram::setup tst_sram::test_all -- tag: [default, viv, sys_tst_sram, n4, stress] +- tag: [viv, sys_tst_sram, n4, stress] test: | tbrun_tbwrri --lsuf stress --pack tst_sram tb_tst_sram_n4${ms} \ tst_sram::setup tst_sram::test_sim diff --git a/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vhd b/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vhd index e4102bb0..ff26b797 100644 --- a/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vhd +++ b/rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vhd @@ -1,4 +1,4 @@ --- $Id: sys_tst_sram_n4d.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_tst_sram_n4d.vhd 1201 2019-08-10 16:51:22Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2018-2019 by Walter F.J. Mueller -- @@ -20,16 +20,18 @@ -- Test bench: tb/tb_tst_sram_n4d -- -- Target Devices: generic --- Tool versions: viv 2017.2-2018.3; ghdl 0.34-0.35 +-- Tool versions: viv 2017.2-2019.1; ghdl 0.34-0.35 -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic +-- 2019-08-10 1201 2019.1 xc7a100t-1 4409 4606 656 5 1875 -- 2019-02-02 1108 2018.3 xc7a100t-1 4408 4606 656 5 1895 -- 2019-02-02 1108 2017.2 xc7a100t-1 4403 4900 657 5 1983 -- 2019-01-02 1101 2017.2 xc7a100t-1 4403 4900 640 5 1983 -- -- Revision History: -- Date Rev Version Comment +-- 2019-08-10 1201 1.1 use 100 MHz MIG SYS_CLK -- 2019-01-02 1101 1.0 Initial version -- 2018-12-30 1099 0.1 First draft (derived from sys_tst_sram_n4/arty) ------------------------------------------------------------------------------ @@ -100,11 +102,10 @@ architecture syn of sys_tst_sram_n4d is signal CLKS : slbit := '0'; signal CES_MSEC : slbit := '0'; - signal CLKMIG : slbit := '0'; signal CLKREF : slbit := '0'; - signal LOCKED : slbit := '0'; -- raw LOCKED - signal LOCKED_CLK : slbit := '0'; -- sync'ed to CLKMIG + signal LOCKED : slbit := '0'; -- raw LOCKED + signal LOCKED_CLKMIG : slbit := '0'; -- sync'ed to CLKMIG signal GBL_RESET : slbit := '0'; signal MEM_RESET : slbit := '0'; @@ -184,7 +185,7 @@ begin CLK1_MSECDIV => 1000, CLK23_VCODIV => 1, CLK23_VCOMUL => 12, -- vco 1200 MHz - CLK2_OUTDIV => 8, -- mig sys 150.0 MHz + CLK2_OUTDIV => 12, -- mig sys 100.0 MHz (unused) CLK3_OUTDIV => 6, -- mig ref 200.0 MHz CLK23_GENTYPE => "PLL") port map ( @@ -195,16 +196,16 @@ begin CLK1 => CLKS, CE1_USEC => open, CE1_MSEC => CES_MSEC, - CLK2 => CLKMIG, + CLK2 => open, CLK3 => CLKREF, LOCKED => LOCKED ); - CDC_CLK_LOCKED : cdc_signal_s1_as + CDC_CLKMIG_LOCKED : cdc_signal_s1_as port map ( - CLKO => CLKMIG, + CLKO => CLK100_BUF, DI => LOCKED, - DO => LOCKED_CLK + DO => LOCKED_CLKMIG ); IOB_RS232 : bp_rs232_4line_iob @@ -308,7 +309,7 @@ begin MEM_ADDR(19 downto 18) <= (others=>'0'); --?? FIXME ?? allow AWIDTH=20 - MEM_RESET <= not LOCKED_CLK or MEM_RESET_RRI; + MEM_RESET <= not LOCKED_CLKMIG or MEM_RESET_RRI; MEMCTL: sramif_mig_nexys4d -- SRAM to MIG iface ----------------- port map ( @@ -325,7 +326,7 @@ begin BE => MEM_BE, DI => MEM_DI, DO => MEM_DO, - CLKMIG => CLKMIG, + CLKMIG => CLK100_BUF, CLKREF => CLKREF, TEMP => XADC_TEMP, MONI => MIG_MONI, diff --git a/rtl/sys_gen/tst_sram/nexys4d/tb/tbrun.yml b/rtl/sys_gen/tst_sram/nexys4d/tb/tbrun.yml index ba67e590..151b1095 100644 --- a/rtl/sys_gen/tst_sram/nexys4d/tb/tbrun.yml +++ b/rtl/sys_gen/tst_sram/nexys4d/tb/tbrun.yml @@ -1,18 +1,19 @@ -# $Id: tbrun.yml 1099 2018-12-31 09:07:36Z mueller $ +# $Id: tbrun.yml 1201 2019-08-10 16:51:22Z mueller $ # # Revision History: # Date Rev Version Comment +# 2019-08-10 1201 1.0.1 add n4d to default # 2018-12-30 1099 1.0 Initial version # - default: mode: ${viv_modes} # -- tag: [viv, sys_tst_sram, n4d, base] +- tag: [default, viv, sys_tst_sram, n4d, base] test: | tbrun_tbwrri --lsuf base --pack tst_sram tb_tst_sram_n4d${ms} \ tst_sram::setup tst_sram::test_all -- tag: [viv, sys_tst_sram, n4d, stress] +- tag: [default, viv, sys_tst_sram, n4d, stress] test: | tbrun_tbwrri --lsuf stress --pack tst_sram tb_tst_sram_n4d${ms} \ tst_sram::setup tst_sram::test_sim diff --git a/rtl/sys_gen/w11a/nexys4/tb/tbrun.yml b/rtl/sys_gen/w11a/nexys4/tb/tbrun.yml index 44ed1466..5d60db84 100644 --- a/rtl/sys_gen/w11a/nexys4/tb/tbrun.yml +++ b/rtl/sys_gen/w11a/nexys4/tb/tbrun.yml @@ -1,7 +1,8 @@ -# $Id: tbrun.yml 916 2017-06-25 13:30:07Z mueller $ +# $Id: tbrun.yml 1201 2019-08-10 16:51:22Z mueller $ # # Revision History: # Date Rev Version Comment +# 2019-08-10 1201 1.2.1 remove n4 from default # 2017-06-25 916 1.2 retire mem70,mem70_n2 - now in tbcpu # 2016-09-18 809 1.0.1 use 60 sec tout for run_pdpcp tb_pdp11core_stim # 2016-08-21 799 1.0 Initial version @@ -9,23 +10,23 @@ - default: mode: ${viv_modes} # -- tag: [default, viv, sys_w11a, n4, stim1] +- tag: [viv, sys_w11a, n4, stim1] test: | tbrun_tbwrri --lsuf stim1 tb_w11a_n4${ms} \ "rlink::run_rri ../../../../w11a/tb/tb_rlink_tba_pdp11core_stim.dat" -- tag: [default, viv, sys_w11a, n4, stim2] +- tag: [viv, sys_w11a, n4, stim2] test: | tbrun_tbwrri --lsuf stim2 --pack rw11 tb_w11a_n4${ms} \ "rw11::setup_cpu" \ "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat 60." -- tag: [default, viv, sys_w11a, n4, tbcpu] +- tag: [viv, sys_w11a, n4, tbcpu] test: | tbrun_tbwrri --lsuf tbcpu --pack rw11 tb_w11a_n4${ms} \ "rw11::setup_cpu" "rw11::tbench @cpu_all.dat" -- tag: [default, viv, sys_w11a, n4, tbdev] +- tag: [viv, sys_w11a, n4, tbdev] test: | tbrun_tbwrri --lsuf tbdev --pack rw11 tb_w11a_n4${ms} \ "rw11::setup_cpu" "rw11::tbench @dev_all.dat" diff --git a/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vhd b/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vhd index 47ba9376..b4926f8f 100644 --- a/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vhd +++ b/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vhd @@ -1,4 +1,4 @@ --- $Id: sys_w11a_n4d.vhd 1181 2019-07-08 17:00:50Z mueller $ +-- $Id: sys_w11a_n4d.vhd 1201 2019-08-10 16:51:22Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2019- by Walter F.J. Mueller -- @@ -27,12 +27,14 @@ -- -- Synthesized: -- Date Rev viv Target flop lutl lutm bram slic MHz +-- 2019-08-10 1201 2019.1 xc7a100t-1 6850 10258 901 17.5 3563 80 -- 2019-05-19 1150 2017.2 xc7a100t-1 6811 10322 901 17.5 3496 80 +dz11 -- 2019-02-02 1108 2018.3 xc7a100t-1 6558 9537 814 17.0 3443 80 -- 2019-02-02 1108 2017.2 xc7a100t-1 6538 9496 798 17.0 3308 80 -- -- Revision History: -- Date Rev Version Comment +-- 2019-08-10 1201 1.1 use 100 MHz MIG SYS_CLK -- 2019-01-02 1101 1.0 Initial version (derived from sys_w11a_n4 and arty) ------------------------------------------------------------------------------ -- @@ -152,7 +154,6 @@ architecture syn of sys_w11a_n4d is signal CLKS : slbit := '0'; signal CES_MSEC : slbit := '0'; - signal CLKMIG : slbit := '0'; signal CLKREF : slbit := '0'; signal LOCKED : slbit := '0'; -- raw LOCKED @@ -257,7 +258,7 @@ begin CLK1_MSECDIV => 1000, CLK23_VCODIV => 1, CLK23_VCOMUL => 12, -- vco 1000 MHz - CLK2_OUTDIV => 8, -- mig sys 150.0 MHz + CLK2_OUTDIV => 12, -- mig sys 100.0 MHz (unused) CLK3_OUTDIV => 6, -- mig ref 200.0 MHz CLK23_GENTYPE => "PLL") port map ( @@ -268,7 +269,7 @@ begin CLK1 => CLKS, CE1_USEC => open, CE1_MSEC => CES_MSEC, - CLK2 => CLKMIG, + CLK2 => open, CLK3 => CLKREF, LOCKED => LOCKED ); @@ -402,7 +403,7 @@ begin BE => MEM_BE, DI => MEM_DI, DO => MEM_DO, - CLKMIG => CLKMIG, + CLKMIG => CLK100_BUF, CLKREF => CLKREF, TEMP => XADC_TEMP, MONI => MIG_MONI, diff --git a/rtl/sys_gen/w11a/nexys4d/tb/tbrun.yml b/rtl/sys_gen/w11a/nexys4d/tb/tbrun.yml index 3166d2fc..abbd2641 100644 --- a/rtl/sys_gen/w11a/nexys4d/tb/tbrun.yml +++ b/rtl/sys_gen/w11a/nexys4d/tb/tbrun.yml @@ -1,29 +1,30 @@ -# $Id: tbrun.yml 1103 2019-01-04 13:18:54Z mueller $ +# $Id: tbrun.yml 1201 2019-08-10 16:51:22Z mueller $ # # Revision History: # Date Rev Version Comment +# 2019-08-10 1201 1.0.1 add n4d to default # 2019-01-02 1101 1.0 Initial version # - default: mode: ${viv_modes} # -- tag: [viv, sys_w11a, n4d, stim1] +- tag: [default, viv, sys_w11a, n4d, stim1] test: | tbrun_tbwrri --lsuf stim1 tb_w11a_n4d${ms} \ "rlink::run_rri ../../../../w11a/tb/tb_rlink_tba_pdp11core_stim.dat" -- tag: [viv, sys_w11a, n4d, stim2] +- tag: [default, viv, sys_w11a, n4d, stim2] test: | tbrun_tbwrri --lsuf stim2 --pack rw11 tb_w11a_n4d${ms} \ "rw11::setup_cpu" \ "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat 60." -- tag: [viv, sys_w11a, n4d, tbcpu] +- tag: [default, viv, sys_w11a, n4d, tbcpu] test: | tbrun_tbwrri --lsuf tbcpu --pack rw11 tb_w11a_n4d${ms} \ "rw11::setup_cpu" "rw11::tbench @cpu_all.dat" -- tag: [viv, sys_w11a, n4d, tbdev] +- tag: [default, viv, sys_w11a, n4d, tbdev] test: | tbrun_tbwrri --lsuf tbdev --pack rw11 tb_w11a_n4d${ms} \ "rw11::setup_cpu" "rw11::tbench @dev_all.dat" diff --git a/tools/exptest/sys/sys_w11a_arty_setup.tcl b/tools/exptest/sys/sys_w11a_arty_setup.tcl index 45043cb6..20d0a86e 100644 --- a/tools/exptest/sys/sys_w11a_arty_setup.tcl +++ b/tools/exptest/sys/sys_w11a_arty_setup.tcl @@ -1,4 +1,4 @@ -# $Id: sys_w11a_arty_setup.tcl 1193 2019-07-14 08:36:20Z mueller $ +# $Id: sys_w11a_arty_setup.tcl 1201 2019-08-10 16:51:22Z mueller $ # SPDX-License-Identifier: GPL-3.0-or-later # Copyright 2019- by Walter F.J. Mueller # @@ -12,5 +12,6 @@ # set ::genv(rri_opt) "-tuD,12M,break,xon" set ::genv(sys_path) "rtl/sys_gen/w11a/arty" +set ::genv(memsize) 3840 source ostest_bigmem_setup.tcl source mcode_setup.tcl diff --git a/tools/exptest/sys/sys_w11a_br_arty_setup.tcl b/tools/exptest/sys/sys_w11a_br_arty_setup.tcl new file mode 100644 index 00000000..85505680 --- /dev/null +++ b/tools/exptest/sys/sys_w11a_br_arty_setup.tcl @@ -0,0 +1,15 @@ +# $Id: sys_w11a_br_arty_setup.tcl 1201 2019-08-10 16:51:22Z mueller $ +# SPDX-License-Identifier: GPL-3.0-or-later +# Copyright 2019- by Walter F.J. Mueller +# +# Revision History: +# Date Rev Version Comment +# 2019-08-08 1201 1.0 Initial version +#--- +# setup for sys_w11a_br_arty +# +set ::genv(rri_opt) "-tuD,12M,break,xon" +set ::genv(sys_path) "rtl/sys_gen/w11a/arty" +set ::genv(memsize) 176 +source ostest_minmem_setup.tcl +source mcode_setup.tcl diff --git a/tools/exptest/sys/sys_w11a_br_n4d_setup.tcl b/tools/exptest/sys/sys_w11a_br_n4d_setup.tcl new file mode 100644 index 00000000..6e07d07b --- /dev/null +++ b/tools/exptest/sys/sys_w11a_br_n4d_setup.tcl @@ -0,0 +1,15 @@ +# $Id: sys_w11a_br_n4d_setup.tcl 1201 2019-08-10 16:51:22Z mueller $ +# SPDX-License-Identifier: GPL-3.0-or-later +# Copyright 2019- by Walter F.J. Mueller +# +# Revision History: +# Date Rev Version Comment +# 2019-08-08 1201 1.0 Initial version +#--- +# setup for sys_w11a_br_n4d +# +set ::genv(rri_opt) "-tuD,12M,break,cts" +set ::genv(sys_path) "rtl/sys_gen/w11a/nexys4d_bram" +set ::genv(memsize) 512 +source ostest_midmem_setup.tcl +source mcode_setup.tcl diff --git a/tools/exptest/sys/sys_w11a_n4d_setup.tcl b/tools/exptest/sys/sys_w11a_n4d_setup.tcl new file mode 100644 index 00000000..4041f9d3 --- /dev/null +++ b/tools/exptest/sys/sys_w11a_n4d_setup.tcl @@ -0,0 +1,15 @@ +# $Id: sys_w11a_n4d_setup.tcl 1201 2019-08-10 16:51:22Z mueller $ +# SPDX-License-Identifier: GPL-3.0-or-later +# Copyright 2019- by Walter F.J. Mueller +# +# Revision History: +# Date Rev Version Comment +# 2019-08-08 1201 1.0 Initial version +#--- +# setup for sys_w11a_n4d +# +set ::genv(rri_opt) "-tuD,12M,break,cts" +set ::genv(sys_path) "rtl/sys_gen/w11a/nexys4d" +set ::genv(memsize) 3840 +source ostest_bigmem_setup.tcl +source mcode_setup.tcl