diff --git a/rtl/w11a/tb/tb_pdp11core_stim.dat b/rtl/w11a/tb/tb_pdp11core_stim.dat index 4fb78584..244a3ef3 100644 --- a/rtl/w11a/tb/tb_pdp11core_stim.dat +++ b/rtl/w11a/tb/tb_pdp11core_stim.dat @@ -1,4 +1,4 @@ -# $Id: tb_pdp11core_stim.dat 1254 2022-07-13 06:16:19Z mueller $ +# $Id: tb_pdp11core_stim.dat 1257 2022-07-16 21:49:08Z mueller $ # SPDX-License-Identifier: GPL-3.0-or-later # Copyright 2007-2016 by Walter F.J. Mueller # @@ -5282,6 +5282,7 @@ rr4 d=013076 -- ! r4=13076 # C test 44.5: JMP R : traps to 10 {44,45,70;J11} or 4 {all others} C Note: J11 doc is wrong, 11/70 traps 10, not 4, as stated +# ==> tested now with cpu_badinst_nofpp.mac:A1.1 # wal 177766 -- clear CPUERR wm 000000 -- @@ -6993,7 +6994,7 @@ brm 12 d=001111 -- ! d=000010 -- ! xor 110000,011000 -> n1z0v0c0; 101000 d=101000 -- ! - d=000004 -- ! xor 110000,110000 -> n1z0v0c0; 000000 + d=000004 -- ! xor 110000,110000 -> n0z1v0c0; 000000 d=000000 -- ! #-------- C Exec test 46.16wrc1: XOR - reg, C=1 @@ -7026,7 +7027,7 @@ brm 12 d=001111 -- ! d=000011 -- ! xor 110000,011000 -> n1z0v0c1; 101000 d=101000 -- ! - d=000005 -- ! xor 110000,110000 -> n1z0v0c1; 000000 + d=000005 -- ! xor 110000,110000 -> n0z1v0c1; 000000 d=000000 -- ! #-------- C Exec test 46.17wr: CMP - reg @@ -8601,6 +8602,7 @@ brm 13 d=000000 -- ! halt ; #----------------------------------------------------------------------------- C Setup code 50 [base 13500] (check that all reserved instructions trap to 10) +# ==> now tested with cpu_badinst_nofpp.mac # wal 013500 -- code (to be single stepped...) bwm 17 diff --git a/tools/tcode/cpu_all.dat b/tools/tcode/cpu_all.dat index 63f85453..d655e944 100644 --- a/tools/tcode/cpu_all.dat +++ b/tools/tcode/cpu_all.dat @@ -1,7 +1,8 @@ -# $Id: cpu_all.dat 1254 2022-07-13 06:16:19Z mueller $ +# $Id: cpu_all.dat 1257 2022-07-16 21:49:08Z mueller $ # ## steering file for all cpu tests # cpu_basics.mac cpu_eis.mac +cpu_badinst_nofpp.mac cpu_selftest.mac diff --git a/tools/tcode/cpu_badinst_nofpp.mac b/tools/tcode/cpu_badinst_nofpp.mac new file mode 100644 index 00000000..738dafd4 --- /dev/null +++ b/tools/tcode/cpu_badinst_nofpp.mac @@ -0,0 +1,156 @@ +; $Id: cpu_badinst_nofpp.mac 1257 2022-07-16 21:49:08Z mueller $ +; SPDX-License-Identifier: GPL-3.0-or-later +; Copyright 2022- by Walter F.J. Mueller +; +; Revision History: +; Date Rev Version Comment +; 2015-07-16 1257 1.0 Initial version +; +; Test that invalid instructions trap (including fpp) +; + .include |lib/tcode_std_base.mac| +; +; Section A: verify that invalid instructions trap =========================== + jmp ta0101 +; +vh.exp: inc trpcnt + add #2,(sp) + rti +trpcnt: .word 0 +; +; Test A1.1 -- jsr,jmp +++++++++++++++++++++++++++++++++++++++++++++++ +; check that the following instructions trap to 10 (rit) +; jsr to register +; jmp to register +; Note: 44,45,70 and J11 trap to 10, all other trap to 4 +; +ta0101: mov #vh.exp,v..rit ; setup rit handler + clr trpcnt +; + jsr pc,r0 + halt + jsr pc,r5 + halt + jmp r0 + halt + jmp r5 + halt +; + mov #v..rit+2,v..rit ; restore rit catcher + cmp trpcnt,#4. + beq .+4 + halt +; +9999$: iot ; end of test A1.1 +; +; Test A1.2 -- halt ++++++++++++++++++++++++++++++++++++++++++++++++++ +; check that the following instructions trap to 4 (iit) +; halt in supervisor and user mode +; +ta0102: mov #vh.exp,v..iit ; setup iit handler + clr trpcnt +; + mov #cp.cms,cp.psw ; supervisor mode + halt ; instruction under test + nop ; skipped by vh.exp + mov #cp.cmu,cp.psw ; user mode + halt ; instruction under test + nop ; skipped by vh.exp + clr cp.psw ; back to kernel mode +; + mov #v..iit+2,v..iit ; restore iit catcher + cmp trpcnt,#2. + beq .+4 + halt +; +9999$: iot ; end of test A1.2 +; +; Test A1.3 -- reserved (except fpp) +++++++++++++++++++++++++++++++++ +; check that reserved instruction code trap to 10 (rit) +; +ta0103: mov #vh.exp,v..rit ; setup iit handler + clr trpcnt +; + .word 000007 ; 000007 {MFPT in 11/44, J11} + halt + .word 000010 ; 000010-000077 + halt + .word 000077 + halt + .word 000210 ; 000210-000227 + halt + .word 000227 + halt + .word 007000 ; 007000-007077 {CSM in 11/44, J11} + halt + .word 007077 + halt + .word 007100 ; 007100-007177 + halt + .word 007177 + halt + .word 007200 ; 007200-007277 {TSTSET in J11} + halt + .word 007277 + halt + .word 007300 ; 007300-007377 {WRTLCK in J11} + halt + .word 007377 + halt + .word 007400 ; 007400-007777 + halt + .word 007777 + halt + .word 075000 ; 075000-075777 + halt + .word 075777 + halt + .word 076000 ; 076000-076177 {CIS} + halt + .word 076177 + halt + .word 076200 ; 076200-076777 + halt + .word 076777 + halt + .word 106400 ; 106400-106477 {MTPS, on 11/34A, J11} + halt + .word 106477 + halt + .word 106700 ; 106700-106777 {MFPS, on 11/34A, J11} + halt + .word 106777 + halt + .word 107000 ; 107000-107777 + halt + .word 107777 + halt +; + mov #v..rit+2,v..rit ; restore iit catcher + cmp trpcnt,#27. + beq .+4 + halt +; +9999$: iot ; end of test A1.3 +; +; Test A1.4 -- reserved (nofpp) ++++++++++++++++++++++++++++++++++++++ +; check that fpp instructions code trap to 10 (rit) +; +ta0104: mov #vh.exp,v..rit ; setup iit handler + clr trpcnt +; + .word 170000 ; 170000-177777 + halt + .word 177777 + halt +; + mov #v..rit+2,v..rit ; restore iit catcher + cmp trpcnt,#2. + beq .+4 + halt +; +9999$: iot ; end of test A1.4 +; +; END OF ALL TESTS - loop closure -------------------------------------------- +; + jmp loop