diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md
index eae1080c..2b0ce465 100644
--- a/doc/CHANGELOG.md
+++ b/doc/CHANGELOG.md
@@ -23,6 +23,14 @@ The HEAD version shows the current development. No guarantees that
software or firmware builds or that the documentation is consistent.
The full set of tests is only run for tagged releases.
+### Summary
+- use vivado 2019.1 as default
+
+### Changes
+- firmware changes
+ - sys_w11a_arty: down-rate to 72 MHz, viv 2019.1 fails with 75 MHz
+ - sys_w11a_*.vmfset: add new rule for vivado 2019.1
+
---
## 2019-06-01: [w11a_V0.78](https://github.com/wfjm/w11/releases/tag/w11a_V0.78) - rev 1158(wfjm)
diff --git a/rtl/sys_gen/w11a/arty/sys_conf.vhd b/rtl/sys_gen/w11a/arty/sys_conf.vhd
index 165670de..5baea680 100644
--- a/rtl/sys_gen/w11a/arty/sys_conf.vhd
+++ b/rtl/sys_gen/w11a/arty/sys_conf.vhd
@@ -1,4 +1,4 @@
--- $Id: sys_conf.vhd 1142 2019-04-28 19:27:57Z mueller $
+-- $Id: sys_conf.vhd 1159 2019-06-06 19:15:50Z mueller $
--
-- Copyright 2018-2019 by Walter F.J. Mueller
--
@@ -19,6 +19,7 @@
-- Tool versions: viv 2017.2-2018.3; ghdl 0.34-0.35
-- Revision History:
-- Date Rev Version Comment
+-- 2019-06-05 1159 1.1.2 down-rate to 72 MHz, viv 2019.1 fails with 75 MHz
-- 2019-04-28 1142 1.1.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.1 use typ for DL,PC,LP; add dz11,ibtst
-- 2019-01-27 1108 1.0.1 down-rate to 75 MHz, viv 2018.3 fails with 80 MHz
@@ -33,9 +34,9 @@ use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
- constant sys_conf_clksys_vcodivide : positive := 1;
- constant sys_conf_clksys_vcomultiply : positive := 9; -- vco 900 MHz
- constant sys_conf_clksys_outdivide : positive := 12; -- sys 75 MHz
+ constant sys_conf_clksys_vcodivide : positive := 5;
+ constant sys_conf_clksys_vcomultiply : positive := 54; -- vco 1080 MHz
+ constant sys_conf_clksys_outdivide : positive := 15; -- sys 72 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
diff --git a/rtl/sys_gen/w11a/arty/sys_w11a_arty.vmfset b/rtl/sys_gen/w11a/arty/sys_w11a_arty.vmfset
index 1f9172fd..a39ced70 100644
--- a/rtl/sys_gen/w11a/arty/sys_w11a_arty.vmfset
+++ b/rtl/sys_gen/w11a/arty/sys_w11a_arty.vmfset
@@ -1,7 +1,8 @@
-# $Id: sys_w11a_arty.vmfset 1108 2019-02-02 23:04:38Z mueller $
+# $Id: sys_w11a_arty.vmfset 1159 2019-06-06 19:15:50Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
+# 2019-06-05 1159 2019.1
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
@@ -117,3 +118,6 @@ i [DRC REQP-1709] PLLE2_ADV
# --> DSP multiplier is not pipelined, ok # OK 2018-12-28
i [DRC DPOP-1] PREG Output pipelining
i [DRC DPOP-2] MREG Output pipelining
+# indicated in many Artix-7 w11a, but not in arty
+#{2019.1:}
+#i [DRC DPIP-1] Input pipelining
diff --git a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vmfset b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vmfset
index 5ab9986c..f16d76da 100644
--- a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vmfset
+++ b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vmfset
@@ -1,7 +1,8 @@
-# $Id: sys_w11a_br_arty.vmfset 1108 2019-02-02 23:04:38Z mueller $
+# $Id: sys_w11a_br_arty.vmfset 1159 2019-06-06 19:15:50Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
+# 2019-06-05 1159 2019.1
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
@@ -120,3 +121,5 @@ I [Physopt 32-742] # BRAM Flop Optimization
# --> DSP multiplier is not pipelined, ok # OK 2018-12-22
i [DRC DPOP-1] PREG Output pipelining
i [DRC DPOP-2] MREG Output pipelining
+{2019.1:}
+i [DRC DPIP-1] Input pipelining
diff --git a/rtl/sys_gen/w11a/artys7/sys_w11a_as7.vmfset b/rtl/sys_gen/w11a/artys7/sys_w11a_as7.vmfset
index 1154ba99..07e2166b 100644
--- a/rtl/sys_gen/w11a/artys7/sys_w11a_as7.vmfset
+++ b/rtl/sys_gen/w11a/artys7/sys_w11a_as7.vmfset
@@ -1,4 +1,4 @@
-# $Id: sys_w11a_as7.vmfset 1108 2019-02-02 23:04:38Z mueller $
+# $Id: sys_w11a_as7.vmfset 1159 2019-06-06 19:15:50Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
@@ -80,6 +80,8 @@ I [Physopt 32-742] # BRAM Flop Optimization
# see https://www.xilinx.com/support/answers/64180.html # OK 2019-01-12
i [DRC REQP-1709] PLLE2_ADV
# --> DSP multiplier is not pipelined, ok # OK 2018-12-22
-# indicated everywhere, but not in as7 ??
+# DRC DPOP-1 indicated in Artix-7 designs, but not in Spartan-7 as7 ??
#i [DRC DPOP-1] PREG Output pipelining
#i [DRC DPOP-2] MREG Output pipelining
+{2019.1:}
+i [DRC DPIP-1] Input pipelining
diff --git a/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vmfset b/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vmfset
index 0e2111de..e6e6e6c6 100644
--- a/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vmfset
+++ b/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vmfset
@@ -1,7 +1,8 @@
-# $Id: sys_w11a_br_as7.vmfset 1108 2019-02-02 23:04:38Z mueller $
+# $Id: sys_w11a_br_as7.vmfset 1159 2019-06-06 19:15:50Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
+# 2019-06-05 1159 2019.1
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
@@ -118,3 +119,5 @@ I [Physopt 32-742] # BRAM Flop Optimization
# indicated everywhere, but not in as7 ??
#i [DRC DPOP-1] PREG Output pipelining
#i [DRC DPOP-2] MREG Output pipelining
+{2019.1:}
+i [DRC DPIP-1] Input pipelining
diff --git a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset
index 2e725542..34a931e3 100644
--- a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset
+++ b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset
@@ -1,7 +1,8 @@
-# $Id: sys_w11a_b3.vmfset 1108 2019-02-02 23:04:38Z mueller $
+# $Id: sys_w11a_b3.vmfset 1159 2019-06-06 19:15:50Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
+# 2019-06-05 1159 2019.1
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
@@ -114,3 +115,5 @@ I [Physopt 32-742] # BRAM Flop Optimization
# --> DSP multiplier is not pipelined, ok # OK 2018-12-22
i [DRC DPOP-1] PREG Output pipelining
i [DRC DPOP-2] MREG Output pipelining
+{2019.1:}
+i [DRC DPIP-1] Input pipelining
diff --git a/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vmfset b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vmfset
index 29d9f145..9728db06 100644
--- a/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vmfset
+++ b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vmfset
@@ -1,7 +1,8 @@
-# $Id: sys_w11a_c7.vmfset 1108 2019-02-02 23:04:38Z mueller $
+# $Id: sys_w11a_c7.vmfset 1159 2019-06-06 19:15:50Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
+# 2019-06-05 1159 2019.1
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
@@ -123,3 +124,5 @@ I [Physopt 32-742] # BRAM Flop Optimization
# --> DSP multiplier is not pipelined, ok # OK 2018-12-22
i [DRC DPOP-1] PREG Output pipelining
i [DRC DPOP-2] MREG Output pipelining
+{2019.1:}
+i [DRC DPIP-1] Input pipelining
diff --git a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vmfset b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vmfset
index 3bfec2cd..fe27f3bb 100644
--- a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vmfset
+++ b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vmfset
@@ -1,7 +1,8 @@
-# $Id: sys_w11a_n4.vmfset 1108 2019-02-02 23:04:38Z mueller $
+# $Id: sys_w11a_n4.vmfset 1159 2019-06-06 19:15:50Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
+# 2019-06-05 1159 2019.1
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
@@ -116,3 +117,5 @@ I [Physopt 32-742] # BRAM Flop Optimization
# --> DSP multiplier is not pipelined, ok # OK 2018-12-22
i [DRC DPOP-1] PREG Output pipelining
i [DRC DPOP-2] MREG Output pipelining
+{2019.1:}
+i [DRC DPIP-1] Input pipelining
diff --git a/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vmfset b/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vmfset
index ffcf523c..baba12b9 100644
--- a/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vmfset
+++ b/rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vmfset
@@ -1,7 +1,8 @@
-# $Id: sys_w11a_n4d.vmfset 1108 2019-02-02 23:04:38Z mueller $
+# $Id: sys_w11a_n4d.vmfset 1159 2019-06-06 19:15:50Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
+# 2019-06-05 1159 2019.1
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
@@ -107,3 +108,5 @@ i [DRC REQP-1709] PLLE2_ADV
# --> DSP multiplier is not pipelined, ok # OK 2019-01-02
i [DRC DPOP-1] PREG Output pipelining
i [DRC DPOP-2] MREG Output pipelining
+{2019.1:}
+i [DRC DPIP-1] Input pipelining