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Code Issues Releases Wiki Activity

fixes for Vivado 2016.3 and 2016.4

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- Vivado is used with -fsm_extraction one_hot. Starting with Vivado 2016.3
  this triggers fsm recognition and re-coding of two gray counter modules.
  This not only defeats the purpose of the gray coded counter, it also
  caused some constraints to fail. Added attributes to prevent fsm extraction
- the logic of `connect_hw_server` and `get_hw_servers` changed after Vivado
  2015.1. The `make <design>.vconfig` command worked up to Vivado 2016.2 due
  to some recovery mechanism, and finally broke with 2016.3. Fixed the
  call to `get_hw_servers`.
This commit is contained in:
Walter F.J. Mueller
2017-01-07 18:25:21 +01:00
parent 7a3298a42d
commit 646caf5f20
4 changed files with 31 additions and 14 deletions
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9
doc/CHANGELOG.md
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@@ -11,16 +11,17 @@
---
## HEAD <a name="head"></a>
### Proviso
_The HEAD version is shows the current development. No guarantees that
_The HEAD version shows the current development. No guarantees that
software or firmware builds or that the documentation is consistent.
The full set of tests is only run for releases._
The full set of tests is only run for tagged releases._
### Summary
- [w11 shell](../tools/tcl/rw11/shell.tcl) re-organized abd expanded,
- fixes for Vivado 2016.4
- added **preliminary** support for Nexys4 DDR board
- [w11 shell](../tools/tcl/rw11/shell.tcl) re-organized and expanded,
now default in [ti_w11](../tools/bin/ti_w11)
- `CPUERR` cleared with cpu reset (see [ECO-029](ECO-029-cpuerr_creset.md))
- `PS` initialized now with `000000` (see [ECO-028](ECO-028-ps_init.md))
- added **preliminary** and **FPGA untested** support for nexys4 DDR
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